- linaro-toolchain - lists.linaro.org

by Richard Sandiford

== This week == * Wrote a fix for 809768. Accepted upstream. * Looked at upstream PR 49742 (the failures seen with predictive commoning). Accepted upstream. * More shrink-wrap review. * Sent auto-inc-dec changes out for comments. Got some good private feedback (in the sense of being positive, and having good suggestions). * Sent a related define_bypass patch out for review. * Started looking at sms-and-memory-dependencies. == Next week == * Deal with auto-inc-dec suggestions. * More SMS.

15 years

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eglibc bug, multiple regressions on oneiric

by Mounir Bsaibes

Is there anyone handling this bug? https://bugs.launchpad.net/ubuntu/+source/eglibc/+bug/775849 Mounir -- Mounir Bsaibes Project Manager Follow Linaro.org: facebook.com/pages/Linaro/155974581091106 http://twitter.com/#!/linaroorg http://www.linaro.org/linaro-blog <http://www.linaro.org/linaro-blog>

15 years

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Linaro GCC 4.6 and 4.5 2011.07 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the release of both Linaro GCC 4.6 and Linaro GCC 4.5. Linaro GCC 4.6 is the fifth release in the 4.6 series. Based off the latest GCC 4.6.1+svn175677, it adds new optimisations and vectoriser improvements. Interesting changes include: * Updates to 4.6.1+r175677 * Improves support for vector shifts by a constant * Improves handling of memory dependencies in the SMS optimisation * Improved vectorisation of widening multiplies by keeping the operands smaller for longer * Improves the peeling of potentially misaligned vectorised loops * Improved vectorisation of signed and unsigned widening multiplies by a constant * Merges the new upstream Cortex-A5 tuning Fixes: * LP: #721531: Don't optimise out testing of the Thumb mode bit on function pointers * LP: #723185: ICE in reload_cse_simplify_operands when compiling with -marm -mfpu=neon * LP: #744754: ICE in *neon_movoi when using NEON intrinsics * LP: #791327: ICE due to using the stack pointer in RSB instructions * LP: #797748: ICE building SPEC2006 403.gcc emit-rtl.c * LP: #803232: ICE on code that uses vld4q_s16() NEON intrinsic * LP: #809435: Omit building the target libiberty when building a cross compiler * LP: #807573: ICE in *truncsisf2_vfp: Could not find a spill register * PR 49385: Ensure at least one of the operands is a register in thumb2_movhi_insn * Fixes an EABI unwinding bug that improves interoperability with armcc * Fixes a DWARF 2 problem exposed through shrinkwrap. * Fixes a bug in __builtin_isgreaterequal Known issues: * Building Python 2.7 with -mfpu=neon exposes a bug in vmov.i64 in binutils 2.20.51. Please use 2.21 or later. Linaro GCC 4.5 2011.07 is the twelfth release in the 4.5 series. Based off the latest GCC 4.5.3+svn175676, the release is focused on maintenance. Interesting changes in 4.5 include: * Updates to 4.5.3+r175676 Fixes: * LP: #721531: Don't optimise out testing of the Thumb mode bit on function pointers * LP: #723185: ICE in reload_cse_simplify_operands when compiling with -marm -mfpu=neon * LP: #744754: ICE in *neon_movoi when using NEON intrinsics * LP: #797748: ICE building SPEC2006 403.gcc emit-rtl.c * LP: #803232: ICE on code that uses vld4q_s16() NEON intrinsic * Fixes a DWARF 2 problem exposed through shrinkwrap. The source tarball is available from: https://launchpad.net/gcc-linaro/+milestone/4.6-2011.07 https://launchpad.net/gcc-linaro/+milestone/4.5-2011.07 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? inquire at support(a)linaro.org -- Michael

15 years

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[ACTIVITY] July 17-21

by Ira Rosen

Hi, - I finally submitted the over-widening patch, but Richard Guenther thought that this optimization should be done for scalars as well, and he is now working on this himself. - Some auto-vectorizer fixes Ira

15 years

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Returned mail: see transcript for details

by suparna＠in.ibm.com

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15 years

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Linaro QEMU 2011.07 released

by Peter Maydell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2011.07. Linaro QEMU 2011.07-0 is the latest monthly release of qemu-linaro. Based off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes and enhancements. This month's release is primarily minor improvements: - Fixes a compile failure on ia64 hosts - syscall 369 (prlimit64) implemented in linux-user mode - Fixes an ELF loader bug that caused problems with binaries generated by the Google Go compiler Plus of course new upstream fixes and improvements. Known issues: - The beagle and beaglexm models still do not support USB networking - Very recent Linaro omap3 hwpacks (20110716 and later) do not boot on the beagle model; this is caused by an x-loader bug (LP:813407) The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2011.07 Binary builds of this qemu-linaro release are being prepared and will be available shortly for users of Ubuntu. Packages will be in the linaro-maintainers tools ppa: https://launchpad.net/~linaro-maintainers/+archive/tools/ More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

15 years

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Appologies

by Andrew Stubbs

Hi All, Apologies for missing the stand-up call today. I've been having technical difficulties at my end. :( I think they're resolved now ... maybe. Andrew

15 years

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[ACTIVITY] weekly status

by Ken Werner

Hi, * continued to look into #809768 (ICE when building bionic's libm) * created some toolchain and android builds for verification purposes * libunwind * discussions with Michael and Uli on how to proceed (thanks!) * started to work on libunwind-ptrace * also look for .debug_frame info if there is no .eh_frame info for the given IP * mimics the behaviour of the reworked local unwinding * Attended an IBM internal class on Wednesday Note: I'm off for two days (21-22) and back on Monday. Regards Ken

15 years

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Branch is open

by Michael Hope

Hi there. The 2011.07 release has been spun and is testing up well. The 4.5 and 4.6 branches are now open so feel free to commit any approved patches. -- Michael

15 years

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[Activity] Week ending July 15th 2011

by Ramana Radhakrishnan

== GCC == === Progress === * Identified particular patterns that have issues with scheduler descriptions in A8 and A9 . Fixes to be benchmarked next. * Spent sometime on the new tree-reassoc work but SPEC2k failed for some of the neon configurations. Needs investigation. * T2 perf call. * Looked at libquantum bits with Revital. * BRANCH_COST benchmarking now complete for T2 . Same is running for ARM state. * Some patch review and bugzilla triaging upstream. === Plans === * ivopts patch for RichardS to try out - related to the excessive moves between integer and VFP unit. * BRANCH_COST further results. * Submit scheduler patches upstream after benchmarking. Meetings: * 1-1s * TCWG calls Absences. * 1st Aug - 5th August - Linaro sprint. * 8th - 9th August -Internal training. * 29th Aug - Sept. 2 - Holiday booked and approved. * 31st Oct - 4th Nov - Linaro Summit Orlando - Travel to be booked.

15 years

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[ACTIVITY] 11th - 17th July

by Andrew Stubbs

Continued responding to review comments on my widening multiply patches. Wrote large parts of most of the patches to fix bugs and tidy them up. The result is that all but patch 1 are now approved. Pushed the patches to Launchpad for final testing. Monitored the test status of my thumb2 constants patch, but it still hasn't returned any results. It seems Michael has been having some problems with his systems. Went back to looking at merging patches to 4.6. It's only really the hard ones left. Many are blocked on work that needs to be done by somebody else. Pinged Tom and Bernd to find out the status of their ones - all are stuck on the back burner. ---- Upstream patched requiring review: * NEON scheduling patch http://gcc.gnu.org/ml/gcc-patches/2011-02/msg01431.html * Widening Multiplies 1/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08721.html

15 years

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[ACTIVITY] weekly status

by Revital Eres

- Tracked the problematic file which contains the loop that causing bootstrap failure with SMS flags on ARM machine. It is not caused by SMS but rather due to doloop optimization which is applied when SMS flags are set. Now working on locating the exact loop and producing a testcase to reproduce the error. - Looking into Spec2006/libquantum benchmark - it has hot loop with conditional store which suppress SMS as it is only applied on single basic-block loops. If-conversion can not be done (replacing the store with conditional move and then a store) because in order to do that we need to prove that there is a store to the same location in each iteration of the loop; and it is not the case in this loop. Apparently, when running with crotex-a8 flag cond_exe statement is generated for the store but that's happening only after register allocation pass which is applied after SMS (IIUC,moving the generation of cond_exe before RA is not trivial http://gcc.gnu.org/ml/gcc/2000-05/msg00079.html) So, I'm looking into teaching SMS to handle conditional statements based on technique presented in [1]. This change is not trivial so I'm going to estimate the potential of applying SMS on the loop at first stage. [1] M. Lam, "Software pipelining: an effective scheduling technique for VLIW machines"

15 years

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[ACTIVITY] Jul 11 - Jul 14

by Ulrich Weigand

== GDB == * Tested GDB 7.2.91 prerelease on ARM; everything looking good. * Created a set of patches to prepare for Linaro GDB 7.3 series; verified release process on top of a current 7.3 snapshot. * Committed three mainline patches to fix shared library remote test problems (#804387). * Reviewed Yao's latest Thumb-2 displaced stepping patch. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

15 years

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[ACTIVITY} 2011-07-15

by David Gilbert

== String routines == * Sent a patch to libc-ports with modified configure scripts to add subdirectories for architecture specific ARM code, and the memchr.S from cortex-strings. == 64 bit atomics == * Working through comments on my patches and the set of discussions about the kernel interface for the helper case - not really sure which way that's going to go. == QEmu == * Looking at how tracing works, considering adding tracing to sd card code to help track down some of the sd card issues. Dave

15 years

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[ACTIVITY] report week 28

by Peter Maydell

RAG: Red: Amber: OMAP3 patch upstreaming is slower progress than hoped Green: Current Milestones: || || Planned || Estimate || Actual || ||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || || Historical Milestones: ||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 || ||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a || ||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 || ||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 || ||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 || == linaro-qemu-11.11 == * initial testing of linaro-qemu preparatory to next week's release == upstream-omap3-patches == * finished nand and onenand cleanup, sent 12-patch series upstream == gsoc-support == * mid-term evaluations == other == * discussion with other qemu developers about shortcomings / improvements to the device/bus model (qdev) * sent patch to fix compile error on ia64 hosts * patch review, etc Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences: 1-5 August: Linaro sprint 1111 15-19 August: KVM Forum and LinuxCon NA, Vancouver

15 years

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Fixed the unnecessary union initialisers that were causing ICEs with -g. This turned out to be a lot more work than Richard's one-liner suggested. :-) * Backported Chung-Lin's arm_legitimize_reload_address patch to 4.5. * Backported the smallest_mode_for_size patch to 4.5 and 4.6. * Patch review. * Found an off-by-one error in the vectoriser that caused it to think that contiguous memory regions overlapped. Unfortunately, this meant that a lot of my microbenchmarks were using the fallback ARM code instead of the nice-looking NEON code that I could see in the asm. * A bit more work on auto inc/dec. It tested regression-free for all default languages. Ran some more benchmarks and posted the results. == Next week == * Bugs and auto inc/dec. Richard

15 years

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[ACTIVITY] weekly status

by Ken Werner

Hi, * analyzed/tested toolchain issues the Linaro Android folks are facing * libquadmath disabled due to configure test fail of the target libiberty (#809435) * fix will be in 11.07 release * ICE when building bionic's libm (#809768) * not reproducible with a "plain" Linaro GCC * non upstreamable workaround in place (prevents the ICE but degrades the DWARF quality) * binary toolchain at http://people.linaro.org/~kwerner/ * libunwind * localunwrework branch now on git.linaro.org Note: I'll take two days off at the end of next week (21-22). Regards Ken

15 years

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[ACTIVITY] 11th - 15th July

by Asa Sandahl

Achieved: * Set up networking on the Panda board, ssh to the board from my laptop works fine. * Downloaded the benchmarks (SPEC2000 and EEMBC) and built them for x86. I now have a basic understanding of what the benchmarks do and how to run them. * For EEMBC I used the -m32 flag for building on my 64 bit installation. * For the SPEC2000 I used the Linaro configuration file and enabled the portability flags for a 64-bit host. Played around with different "runspec" actions and options. Building and running individual test cases as well as the full test suites. Finally I did a reportable run for all benchmarks. It took several hours and in the end I got a result for my laptop. Next step: * Cross-compile EEMBC and SPEC2000. I will try linaro-gcc and the cross compiler that comes with Natty. Best Regards Åsa

15 years

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[ACTIVITY] July 11-14

by Ira Rosen

Hi, - merged over-widened multiply patch to gcc-linaro-4.6 (now vectorized rgbyiqv should be about as good as its scalar version) - continued working on over-widened shifts and bit operations Ira

15 years

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Error: selected processor does not support requested special purpose register

by mins.lin＠globalunichip.com

Hi, I used Linaro cross-toolchain version 4.5 (gcc-4.5-arm-linux-gnueabi) to compile linux-linaro-11.05 for beagle board, but got the following error messages: ---- AS arch/arm/boot/compressed/head.o arch/arm/boot/compressed/head.S: Assembler messages: arch/arm/boot/compressed/head.S:127: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr' arch/arm/boot/compressed/head.S:134: Error: selected processor does not support requested special purpose register -- `mrs r2,cpsr' arch/arm/boot/compressed/head.S:136: Error: selected processor does not support requested special purpose register -- `msr cpsr_c,r2' make[2]: *** [arch/arm/boot/compressed/head.o] Error 1 make[1]: *** [arch/arm/boot/compressed/vmlinux] Error 2 make: *** [uImage] Error 2 ---- The .config file I used for kernel build is "config-2.6.38-1003-linaro-omap" which is from hwpack_linaro-omap3-x11-base_20110526-5_armel_supported.tar.gz My host development platform is 64-bit Ubuntu 10.04.2 LTS (Linux ubuntu 2.6.32-32-generic #62-Ubuntu SMP Wed Apr 20 21:52:38 UTC 2011 x86_64 GNU/Linux). Is this a known bug, or did I miss anything else ? Thanks. --------------------------------- Email Confidentiality Notice ------------------------------------------ If you are not the intended recipient for this CONFIDENTIAL E-mail, please delete it immediately without keeping or distributing any copy and notify the sender. ----------------------------------------------------------------------------------------------------------------------

15 years

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[Activity] Week ending July 8th .

by Ramana Radhakrishnan

== GCC == === Progress === * Panda board up again with apparently no change with software on it. Not sure what caused the difference today ! Now chugging along with SPEC2k. * Back on to BRANCH_COST . SPEC2k now running fully whence panda board was restored. * Submitted cleaned up neon shift immediates patch for merging. * On merge request review in Linaro this week. * Backported arith_shiftsi patch to 4.6 branch upstream. (done) * Identified particular patterns that have issues with scheduler descriptions in A8 and A9 . Working on fixes. === Plans === * Submit one_cmpldi2 patch for neon upstream. * Finish the scheduler patches. * Investigate A8 vs A9 regressions. * Look at EPILOGUE_USES and coremark . not sure why it regresses in performance yet. Meetings: * 1-1s * TCWG calls Absences. * 1st Aug - 5th August - Linaro sprint. * 8th - 9th August - Internal training. * 29th Aug - Sept. 2 - Vacation.

15 years

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[ACTIVITY] 4th - 8th July

by Andrew Stubbs

Completed the merge of FSF GCC 4.5 & 4.6 to Linaro GCC. There were a few extra test failure in the i686 testing for both toolchains, but x86_64 and arm were clean, so it seems likely to be an environmental issue (in particular, some of the failures were linker crashes). Posted an update to my widening multiplies patch 3. This one hopefully addressed the issues found by Richard Guenther. Also tested an posted updates to my other patches that had their context changed. Richard picked more holes in my patch, and also reviewed patches 4, 5 and 6. 4 & 5 only have minor issues so far, and 6 has actually been approved! :) Rewrote patch 3 yet again following review. Richard has now modified the VRP pass to make the widening pass's job simpler, so I don't need it to do as much. Also rebaslined the whole patch set; Bernd's recent patch has introduced some conflicts. Found (some of?) the bugs that broke my thumb2 constants patch. Pushed the updated patch to Launchpad for testing. Updated a lot of the patch tracker data. Half day Thursday. ---- Upstream patched requiring review: * NEON scheduling patch http://gcc.gnu.org/ml/gcc-patches/2011-02/msg01431.html * Widening Multiplies 1/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08721.html * Widening Multiplies 2/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08723.html * Widening Multiplies 3/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08724.html * Widening Multiplies 4/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08725.html * Widening Multiplies 5/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08726.html * Widening Multiplies 7/7 http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg08728.html

15 years

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[ACTIVITY] weekly status

by Ken Werner

Hi, * fixed a bug where libunwind could segfault when unwinding through a shared library using the ARM specific unwind tables * discussed the libuwind internals with Uli (thanks!) and concluded that the best way to implement remote unwinding for ARM is to integrate the support for the ARM.exidx* directly into the DWARF code * otherwise the user visible remote API needs to be extended for ARM only which seems to be a bad idea * requires to re-implement the existent ARM code (both local and remote) * will also benefit from libunwind's (dwarf) caching mechanism * started to re-implement the ARM code Regards Ken

15 years

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[ACTIVITY] Weekly status

by Revital Eres

- Continue Spec2006 analysis: Looking into SMS opportunities in SPEC2006/462.libquantum. - Looking into recent bootstrap failure with SMS flags on ARM -- it seems to be related to do-loop optimization.

15 years, 1 month

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Generating ancilliary sections with gas (fwd)

by Nicolas Pitre

Hello Michael, We do have more and more instances of the following issues turning up in the kernel requiring toolchain assistance to solve the problem properly. Could you or someone from your team follow this up please? ---------- Forwarded message ---------- Date: Tue, 1 Feb 2011 12:16:48 +0000 From: Dave Martin <dave.martin(a)linaro.org> To: binutils(a)sourceware.org Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org> Subject: Generating ancilliary sections with gas Hi all, Every now and again I come across a situation where it would be really useful to be able to query the assembler state during assembly: for example, to query and do something based on the current section name. This makes it possible to write generic macros to do certain things which otherwise require manual maintenance, or complex and fragile external preprocessing. Below, I give a real-world example of the problem, and sketch out a possible solution. What do people think of this approach? Does anyone have any better ideas on how to solve this? Cheers ---Dave EXAMPLE An example is the generation of custom ancilliary sections. Suppose you want to write macros which record fixup information. Currently, there's no way to put each fixup in an appropriately named section automatically within gas. Tellingly, gas has had to grow the ability to do this internally at least for ARM, since the exception handling information in .ARM.ex{idx,tab}* must go in sections with names based on the associated section name. However, this ancillary section generation support is neither flexible nor exposed to the user. By putting fixups in sections whose names are based on the name of the section they refer to, selective link-time discard of the fixups (and hence the code referenced by the fixups) will work; otherwise it doesn't. This would help avoid a situation where we have to keep dead code in the kernel because custom fixups are applied to it: at run-time, the code gets fixed up, then is thrown away. The fixups can't be selectively discarded because they are all in the same section: we seem have to no good way to separate them out into separate sections appropriately. For context, see: http://www.spinics.net/lists/arm-kernel/msg112268.html PROPOSAL To solve the problem of generating custom ancillary sections during assembly, here's a simple proposal: introducing a new kind of macro argument can make aspects of the assembler state available to macros in a flexible way, with only minimal implementation required. Basically, the macro qualifier field could be used to identify arguments which are filled in by the assembler with information about the assembly state, rather than being filled in by the invoker of the macro: e.g.: .macro mymacro name:req, flags, secname:current_section /* ... */ .pushsection "\secname\name", "\flags" /* ... */ .popsection .endm /* ... */ mymacro .ancillary, "a" During expansion, \name and \flags are expanded as normal. But \secname is substituted instead with the current section name, so the macro expansion would look like this: /* ... */ .pushsection ".text.ancillary", "a" /* ... */ .popsection Without the special :current_section argument, it doesn't appear possible to implement a macro such as mymacro in a generic way. This surely isn't the only way to achieve the goal, and it's probably not the best way, but it does have some desirable features. Principally, while a new pseudo-op(s) could have been defined to append text to the current section name, etc., allowing the current section name to be appear as a macro parameter avoids prejudicing the way the text is used. So there should never be a need to introduce additional pseudo-ops to do things with the current section name: with this patch, the user can always implement their own macro to do the desired thing. This gets the desired behaviour and maximum flexibility, while keeping the implementation in gas very simple. Also, using the macro expansion system in this way allows the caller a free choice of macro parameter names, and so pretty much guarantees that existing code won't get broken by the change. Because my hack is currently simplistic, it has shortcomings: in particular, it's not desirable to parse an argument from the invocation line at all to fill a :current_section argument. Currently, an argument is read in if present, but its value is ignored and the current section name pasted in at macro expansion time instead. However, that should be straightforward to fix with a bit more code. Of course, there's no reason only to expose the current section name in this way. Any aspect of the the assembler state (current subsection, current section flags, current instruction set, current macro mode, etc.) could be made available in a similar way. USAGE EXAMPLE AND PATCH Note that the specific implementation described here is intended to be illustrative, rather than complete or final. binutils$ cat <<EOF >tst.s .macro push_ancillary_section name:req, flags, csec:current_section .pushsection "\name\csec", "\flags" .endm .macro register_fixup _register_fixup 100\@ .endm .macro _register_fixup label:req \label : push_ancillary_section .fixup, "a" .long \label\(b) .popsection .endm .long 1 register_fixup .long 2 .data .long 3 register_fixup .long 4 .long 5 register_fixup .long 6 EOF binutils$ gas/as-new -ahlms -o tst.o tst.s ARM GAS tst.s page 1 1 .macro push_ancillary_section name:req, flags, csec:current_section 2 .pushsection "\name\csec", "\flags" 3 .endm 4 5 .macro register_fixup 6 _register_fixup 100\@ 7 .endm 8 9 .macro _register_fixup label:req 10 \label : 11 push_ancillary_section .fixup, "a" 12 .long \label\(b) 13 .popsection 14 .endm 15 16 0000 01000000 .long 1 17 register_fixup 17 > _register_fixup 1000 17 >> 1000: 17 >> push_ancillary_section .fixup,"a" 17 >>> .pushsection ".fixup.text","a" 17 0000 04000000 >> .long 1000b 17 >> .popsection 18 0004 02000000 .long 2 19 20 .data 21 0000 03000000 .long 3 22 register_fixup 22 > _register_fixup 1003 22 >> 1003: 22 >> push_ancillary_section .fixup,"a" 22 >>> .pushsection ".fixup.data","a" 22 0000 04000000 >> .long 1003b 22 >> .popsection 23 0004 04000000 .long 4 24 0008 05000000 .long 5 25 register_fixup 25 > _register_fixup 1006 25 >> 1006: 25 >> push_ancillary_section .fixup,"a" 25 >>> .pushsection ".fixup.data","a" 25 0004 0C000000 >> .long 1006b 25 >> .popsection 26 000c 06000000 .long 6 ARM GAS tst.s page 2 NO DEFINED SYMBOLS NO UNDEFINED SYMBOLS binutils$ arm-linux-gnueabi-objdump -rs tst.o tst.o: file format elf32-littlearm RELOCATION RECORDS FOR [.fixup.text]: OFFSET TYPE VALUE 00000000 R_ARM_ABS32 .text RELOCATION RECORDS FOR [.fixup.data]: OFFSET TYPE VALUE 00000000 R_ARM_ABS32 .data 00000004 R_ARM_ABS32 .data Contents of section .text: 0000 01000000 02000000 ........ Contents of section .data: 0000 03000000 04000000 05000000 06000000 ................ Contents of section .fixup.text: 0000 04000000 .... Contents of section .fixup.data: 0000 04000000 0c000000 ........ Contents of section .ARM.attributes: 0000 41150000 00616561 62690001 0b000000 A....aeabi...... 0010 08010901 2c01 ....,. diff --git a/gas/macro.c b/gas/macro.c index e392883..95c4de1 100644 --- a/gas/macro.c +++ b/gas/macro.c @@ -516,6 +516,8 @@ do_formals (macro_entry *macro, int idx, sb *in) formal->type = FORMAL_REQUIRED; else if (strcmp (qual.ptr, "vararg") == 0) formal->type = FORMAL_VARARG; + else if (strcmp (qual.ptr, "current_section") == 0) + formal->type = FORMAL_CURRENT_SECTION; else as_bad_where (macro->file, macro->line, @@ -540,6 +542,15 @@ do_formals (macro_entry *macro, int idx, sb *in) name, macro->name); } + else if (formal->type == FORMAL_CURRENT_SECTION) + { + sb_reset (&formal->def); + as_warn_where (macro->file, + macro->line, + _("Pointless default value for current_section parameter `%s' in macro `%s'"), + name, + macro->name); + } } /* Add to macro's hash table. */ @@ -734,7 +745,11 @@ sub_actual (int start, sb *in, sb *t, struct hash_control *formal_hash, ptr = (formal_entry *) hash_find (formal_hash, sb_terminate (t)); if (ptr) { - if (ptr->actual.len) + if (ptr->type == FORMAL_CURRENT_SECTION) + { + sb_add_string (out, segment_name (now_seg)); + } + else if (ptr->actual.len) { sb_add_sb (out, &ptr->actual); } diff --git a/gas/macro.h b/gas/macro.h index edc1b6b..ea6cabb 100644 --- a/gas/macro.h +++ b/gas/macro.h @@ -38,7 +38,8 @@ enum formal_type { FORMAL_OPTIONAL, FORMAL_REQUIRED, - FORMAL_VARARG + FORMAL_VARARG, + FORMAL_CURRENT_SECTION, }; /* Describe the formal arguments to a macro. */ _______________________________________________ linaro-toolchain mailing list linaro-toolchain(a)lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain

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