Hi,
* PR 49087 - fixed
* PR 49038 - opened by Richard - fixed on 4.7, to be backported to 4.5 and 4.6
* working on widening multiplication for unsigned types and constants
(the signed case works fine)
Ira
Posted a new patch for 16 -> 64 bit multiply and accumulate:
http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg05794.html
Pushed the same patch to a Launchpad branch for testing.
Pinged my addw/subw patch as a review didn't seem forthcoming.
Worked on a canonical form for HImode to DImode multiple-and-accumulate.
The problem isn't too hard to fix, but it's hard to do it in a nice way.
Attended Nathan S's reorg call. Followed up by talking to Nathan F about
what he's been working on with Wind River. Read up on the Wiki.
Looked at why the ARM smlal{tb,bt,tt} instructions are not generated.
I've added the proper patterns, but combine doesn't match them, and I've
run out of time this week to check why.
----
Upstream patched requiring review:
* NEON scheduling patch
http://gcc.gnu.org/ml/gcc-patches/2011-02/msg01431.html
* ARM Thumb2 addw/subw support.
http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg03783.html
* Multiply and accumulate:
http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg05794.html
== Last week ==
* Took Monday off, flew back to Taiwan on Tues., got home Wed. night.
* LP:689887, ICE in get_arm_condition_code(). Finally have some new
progress on this. Found my code was rejecting DImode comparisons,
causing uses of __aeabi_lcmp, etc. in expanded RTL. While this still
does not fully explain a bootstrap fail, it may be related, and it's
good I found this here rather then scratch heads on performance
regressions later... :)
* LP:771903: invalid ubfx asm produced by GCC. Mostly got down to the
bottom of this. This bug is rather well hidden, first avoided due to
some inlining heuristic changes after FSF 4.5 was branched (hence 4.6
and trunk doesn't show on the testcase), then hidden again later by
-ftree-bit-ccp. Was able to reproduce on mainline trunk after some
changes to testcase and options. Will send patch later.
* Talked with Ramana on IRC and mail about the '+' constraint modifiers
in the VFP fmul/fdiv patterns. Mostly concluded that these are typos,
and should be fixed.
== This week ==
* Continue with issues.
Hi there. The next two weeks is where we take the technical topics
from the TSC and the discussions had during the summit and turn them
into the concrete engineering blueprints for this cycle. I've created
a page at:
https://wiki.linaro.org/MichaelHope/Sandbox/1111Blueprints
listing all of the TRs. Could you please have a look through these,
find any with your name on them, and fill in the wiki page. I've put
more notes on the page itself. Some of the topics may warrant
specifications.
Let me know if you have questions on what the topics actually mean.
-- Michael
* Profiling SPEC 2k6 still; about 3/4 of the latrace files are
generated but it's taking some hand holding with some of them
(e.g. finding one that makes millions of calls to a library function
that we're not interested in but generates a huge log, and hence
needs it excluding).
* Working through the ones that I have with analysis scripts and
writing the interesting things up.
* Submitted ARM test suite fix for latrace (unsigned characterism)
* Verified Richard's binutils fix in natty-proposed fixed the vtk FTBFS
* Blueprint for 64bit sync primitives.
Dave
Hi,
* started to measure the overhead of -funwind-tables
* libunwind text size increase < 5%
* firefox4 is still building... :)
* found a small glitch when cross compiling the binutils deb package
* made a small patch, talked with doko, fix upstream
* installed android on the pandaboard
https://wiki.linaro.org/KenWerner/Sandbox/AndroidOnPanda
* setup an android development environment on my thinkpad
Regards
Ken
RAG:
Red:
Amber:
Green: 1105 work item status 100% complete
Current Milestones:
| Planned | Estimate | Actual |
qemu-linaro 2011-05 | 2011-05-19 | 2011-05-19 | n/a |
close out 1105 blueprints | 2011-05-28 | 2011-05-28 | 201--05-19 |
complete 1111 planning | 2011-05-28 | 2011-05-28 | |
Historical Milestones:
finish qemu-cont-integration | 2011-01-25 | 2011-01-25 | handed off |
first qemu-linaro release | 2011-02-08 | 2011-02-08 | 2011-02-08 |
qemu-linaro 2011-03 | 2011-03-08 | 2011-03-08 | 2011-03-08 |
qemu-linaro 2011-04 | 2011-04-21 | 2011-04-21 | 2011-04-21 |
== merge-correctness-fixes ==
* last few work items for this blueprint either completed or postponed
[For the record, postponed work:
setting Cortex A8r2 device ID etc regs -- moved to omap3 upstreaming
trustzone -- may get its own blueprint this cycle
VCVT fp exception flags -- postponed as rather tricky and an
obscure corner case that is unlikely to be noticed by users]
== other ==
* tracked down bug with QEMU loading of Google Go produced ELF files,
submitted patch
* talked to our local trustzone expert, very useful
* reworked and resent FPSCR exception flags patches based on review
comments
* reviewed a patch for setting IFSR right for BKPT
* more planning effort
* sent patch to suppress SD card model warnings generated when Linux
probes to see if it's an SDIO card
* redid the "check for unused -nic options" patch as it turned out to
cause regressions with NICs created via -device.
Meetings: toolchain, standup, 1-2-1
Current qemu patch status is tracked here:
https://wiki.linaro.org/PeterMaydell/QemuPatchStatus
Absences:
(maybe) 15-16 August: QEMU/KVM strand at LinuxCon NA, Vancouver
[LinuxCon proper follows on 17-19th]
== This week ==
* Spent almost all the week on GCC's auto inc/dec pass. I first
continued with the incremental "clean ups" and recoding that I'd
started during free time at Budapest, with the idea of bolting the new
optimisations on top of that. However, in the end, I decided it would
be better to rewrite the pass entirely, using a different approach.
I've now got an early prototype of that rewrite, and it seems to be
working as expected on the test cases I've tried so far. I'm running
a regression test over the weekend, although TBH, I expect it to fail
at this stage.
* Tested the fix for vzip, vunz and vtrn. Went well, so I'll submit
next week.
* Blueprints.
== Next week ==
* More auto inc/dec:
* Round off some known rough edges in the prototype.
* Fix bugs.
* Run benchmarks.
* Run code comparison tests (diffing assembly code), both on ARM and
on other targets of interest.
Richard
The Linaro Toolchain Working Group is pleased to announce the release
of Linaro GDB 7.2.
Linaro GDB 7.2 2011.05-0 is the sixth release in the 7.2 series. Based
off the latest GDB 7.2, it includes a number of ARM-focused bug fixes.
This release fixes:
* LP: #615972 Neon registers missing in core files
* LP: #615978 Failure to software single-step into signal handler
* LP: #615996 gdb.cp/templates.exp failures
The source tarball is available at:
https://launchpad.net/gdb-linaro/+milestone/7.2-2011.05-0
More information on Linaro GDB is available at:
https://launchpad.net/gdb-linaro
-- Michael
Can somebody please explain how development happens regarding qemu-linaro ?
I've taken a look here [0] and If I'm not mistaken, there's no code in the
repo. I can see a lot of blueprints, but I don't understand how work is
being done regarding those blueprints or when will it be done! Oh, and what
exactly is the 'qemu-linaro' tarball in the repo ?
I'm not sure how newbie this question is, but please bear with me. :D
Thanks in advance.
[0] https://launchpad.net/qemu-linaro
--
Karim Allah Ahmed.
LinkedIn <http://eg.linkedin.com/pub/karim-allah-ahmed/13/829/550/>
Hello,
* Sent 5 SMS related patches for review upstream.
* Backported two SMS patches from mainline to gcc-linaro and
gcc-linaro/4.6 (fixes for unfreed memory)
Thanks,
Revital
Hi,
* committed a patch that supports reductions in SLP (upstream)
* continued analyzing benchmarks: ffmpeg, EEMBC telecom, office, networking
* started to look into implementation of reverse accesses for Neon
* blueprints
Ira
The Linaro Toolchain Working Group is pleased to announce the release
of both Linaro GCC 4.5 and Linaro GCC 4.6.
Linaro GCC 4.5 2011.05 is the tenth release in the 4.5 series. Based
off the latest
GCC 4.5.3+svn173417, it adds new optimisations, much improved support
for strided load/stores, and fixes for many of the issues found in the
last month.
Interesting changes in 4.5 include:
* Updates to 4.5.3+r173417
* Performance improvements in NEON strided loads and stores
* Performance improvements targeted at EEMBC CoreMark
* Precompiled header support on recent Linux kernels
Fixes:
* LP: #660156: Heap randomisation causes PCH testsuite failures
* LP: #784375: vset_lane_u8 intrinsic generates wrong lane number
* LP: #759409: Profiled bootstrap fails in FSF GCC 4.5
* LP: #723086: Test regressions in the Fortran test suite
The strided load/store improvements allow both NEON intrinsics and the
vectoriser to efficiently access values that occur at every n'th
address, such as all of the red values in a RGB image or all of the
left channel samples in a interleaved audio array. Previous versions of GCC
would unpack the values onto the stack instead of using the registers
directly.
The CoreMark improvements improve the code generation for the hot
functions in benchmark. This release is now on par with Linaro GCC
4.4 and significantly ahead of other FSF or Linaro 4.5 based
compilers. This fixes the long-standing problems of ARMv5 being
faster than ARMv7 and 4.4 based compilers being faster than 4.5 based
ones.
Linaro GCC 4.6 is the third release in the 4.6 series. Based off the
latest GCC 4.6.0+svn173480, it adds new optimisations, vectoriser
improvements, and continues with the merge of many ARM-focused
changes.
Interesting changes include:
* Updates to 4.6.0+r173417
* Brings forward more of the performance improvements from Linaro GCC 4.5
* Adds support for swing-modulo scheduling
* Fixes precompiled header support on recent Linux kernels
* Changes the default NEON vector size to quads
* Adds auto-detection of the best vector size
* Adds vectorisation improvements due to better if-conversion
Fixes:
* LP: #714921: Uses an unreasonable amount of memory to compile QEMU on armel
* LP: #723086: Test regressions in the Fortran test suite
The source tarball is available from:
https://launchpad.net/gcc-linaro/+milestone/4.5-2011.05-0https://launchpad.net/gcc-linaro/+milestone/4.6-2011.05-0
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? inquire at support(a)linaro.org
-- Michael
Hi All,
This is based upon gcc version 4.5.3 (20110221 pre-release)
Any help appreciated
This shows a bug in the Linaro gcc compiler with the Arm NEON
vset_lane intrinsic
Note in the objdump that the vmov.8 instruction that places the
value in the vector for the non-q version uses 1 where it should use
2 and 3:
18: ee410bb0 vmov.8 d17[1], r0
1c: ee420bb0 vmov.8 d18[1], r0
20: ee400b90 vmov.8 d16[0], r0
3c: ee440bb0 vmov.8 d20[1], r0
For the q version the vmov.8 instructions are correct:
40: ee420bf0 vmov.8 d18[3], r0
54: ee420bd0 vmov.8 d18[2], r0
64: ee400b90 vmov.8 d16[0], r0
70: ee420bb0 vmov.8 d18[1], r0
/* Source code */
#include <arm_neon.h>
static uint8x8_t vec[5]
static uint8x16_t qvec[5];
void set(uint8_t value)
{
vec[1] = vset_lane_u8(value, vec[0], 3);
vec[2] = vset_lane_u8(value, vec[0], 2);
vec[3] = vset_lane_u8(value, vec[0], 1);
vec[4] = vset_lane_u8(value, vec[0], 0);
qvec[1] = vsetq_lane_u8(value, qvec[0], 3);
qvec[2] = vsetq_lane_u8(value, qvec[0], 2);
qvec[3] = vsetq_lane_u8(value, qvec[0], 1);
qvec[4] = vsetq_lane_u8(value, qvec[0], 0);
}
Thx
Lee
Hi there. The 2011.05 release has been spun and is testing up well.
The 4.5 and 4.6 branches are now open so feel free to commit any
approved patches.
-- Michael
Progress:
* Attended LDS from 9th -14th May.
Plans:
* Look at Thumb2 performance blueprint and break it down.
* Investigate more headroom for SPEC2k starting this week.
* Thumb2 performance call this week.
Meetings:
* 1-1s
* T2 performance.
Hello,
- Attended Linaro@UDS.
- SMS patches to support ARM do-loop pattern got approved in mainline
and merged into gcc-linaro 4.6 and 4.5.
- Sent merge request for two patches in trunk. (SMS_fixes_for_unfreed_memory)
- Implemented an optimization for the stage-count and now testing it.
Thanks,
Revital
== Last week ==
* At Linaro@UDS; I am still typing this in Budapest. Sparingly did some
work between sessions.
* PR42017, ARM LR register not being used. Discussed the patch with
Richard Sandiford at LDS. Re-tested a bit and about to resend a revised
patch according to his suggestion.
* LP:748138, redirect_jump() ICE. Committed patch to CS stable and
trunk. Submitted merge request to Linaro 4.5 branch.
* LP:689887. Got some suggestions from Revital on how to debug the
bootstrap failure caused by my patch, will look into applying it.
== This week ==
* Taking Monday off, I'll be flying back to Taiwan on Tuesday.
* Continue with issues after getting home.
RAG:
Red:
Amber:
Green: 1105 work item status 99% complete with 2 weeks to go
Current Milestones:
| Planned | Estimate | Actual |
qemu-linaro 2011-05 | 2011-05-19 | 2011-05-19 | n/a |
close out 1105 blueprints | 2011-05-28 | 2011-05-28 | |
complete 1111 planning | 2011-05-28 | 2011-05-28 | |
Historical Milestones:
finish qemu-cont-integration | 2011-01-25 | 2011-01-25 | handed off |
first qemu-linaro release | 2011-02-08 | 2011-02-08 | 2011-02-08 |
qemu-linaro 2011-03 | 2011-03-08 | 2011-03-08 | 2011-03-08 |
qemu-linaro 2011-04 | 2011-04-21 | 2011-04-21 | 2011-04-21 |
== merge-correctness-fixes ==
* some of my pending patches have been applied; a number of others are
still under discussion or need further work/testing
== other ==
* We won't be making a qemu-linaro 2011-05 release, since there are no
changes since the 2011-04 release (due to a combination of the Easter
holiday and UDS week).
* Attended UDS
* almost all 1105 work items either complete or confirmed postponed
to next cycle
* Good progress on fleshing out blueprints for next cycle:
https://wiki.linaro.org/PeterMaydell/Qemu1111
Current qemu patch status is tracked here:
https://wiki.linaro.org/PeterMaydell/QemuPatchStatus
Absences:
(maybe) 15-16 August: QEMU/KVM strand at LinuxCon NA, Vancouver
[LinuxCon proper follows on 17-19th]
Last week, Ramana pointed me at an upstream bug report about the
inefficient code that GCC generates for vzip, vuzp and vtrn:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48941
It was filed not longer after the Neon seminar at the summit;
I'm not sure whether that was a coincidence or not.
I attached a patch to the bug last week and will test it this week.
However, a cut-down version shows up another problem that isn't related
specifically to intrinsics. Given:
#include <arm_neon.h>
void foo (float32x4x2_t *__restrict dst, float32x4_t *__restrict src, int n)
{
while (n--)
{
dst[0] = vzipq_f32 (src[0], src[1]);
dst[1] = vzipq_f32 (src[2], src[3]);
dst += 2;
src += 4;
}
}
GCC produces:
cmp r2, #0
bxeq lr
.L3:
vldmia r1, {d16-d17}
vldr d18, [r1, #16]
vldr d19, [r1, #24]
vldr d20, [r1, #32]
vldr d21, [r1, #40]
vldr d22, [r1, #48]
vldr d23, [r1, #56]
add r3, r0, #32
vzip.32 q8, q9
vzip.32 q10, q11
subs r2, r2, #1
vstmia r0, {d16-d19}
add r1, r1, #64
vstmia r3, {d20-d23}
add r0, r0, #64
bne .L3
bx lr
We're missing many auto-increment opportunities here. I think this
is due to the limitations of GCC's auto-inc-dec pass rather than to
a problem in the ARM port itself. I think there are two main areas
for improvement:
- The pass only tries to use auto-incs in cases where there is a
separate addition and memory access. It doesn't try to handle
cases where there are two consecutive memory accesses of the
form *base and *(base + size), even if the address costs make
it clear that post-increments would be a win.
- The pass uses a backward scan rather than a forward scan,
which makes it harder to spot chains of more than two accesses.
FWIW, I've got fairly specific ideas about how to do this.
Unfortunately, the pass is in need of some TLC before it's
easy to make changes. So in terms of work items, how about:
1. Clean up the auto-inc pass so that it's easier to modify
2. Investigate improvements to the pass
3. Submit the changes upstream
4. Backport the changes to the Linaro branches
I wrote some patches for (1) last week.
I'd estimate it's about 2 weeks' work for (1) and (2). (3) and (4)
would hopefully be background tasks. The aim would be for something
like:
.L3:
vldmia r1!, {d16-d17}
vldmia r1!, {d18-d19}
vldmia r1!, {d20-d21}
vldmia r1!, {d22-d23}
vzip.32 q8, q9
vzip.32 q10, q11
subs r2, r2, #1
vstmia r0!, {d16-d19}
vstmia r0!, {d20-d23}
bne .L3
bx lr
This should help with auto-vectorised code, as well as normal core code.
(Combining the vldmias and vstmias is a different topic. The fact that
this particular example could be implemented using one load and one
store is to some extent coincidental.)
Richard
== String routines ==
* Gave up on perf on silverbell and redid it on ursa2; now have a
full set of perf figures and have updated the workload report to show
the spec
binaries that use significant time in libc and the routines they spend
it in; a handful of tests spend very significant amounts of time in
libm.
* Have ltrace results from about 75% of spec - some of the others
are fighting a bit
* Optimised the non-neon memcpy; it's now quite respectable except
in one or two cases (2 byte misaligned, and for some odd reason source
offset
by 8 bytes, destination by 12 is way down on any other combination)
(Current result graphs here
https://wiki.linaro.org/Internal/People/DaveGilbert?action=AttachFile&do=ge…
)
Dave
Hi,
* continued looking into ffmpeg/libavcodec:
- dcadsp.c - the inner loop contains reverse accesses which are not
supported on Neon. I think we can handle them using vrev and vswp.
- a lot of loops have unknown memory stride. I am exploring a
possibility of a combination of scalar loads and vmov into a vector
register, but it is probably too expensive.
* looking into telecom/conven
Ira
