- linaro-toolchain - lists.linaro.org

by Peter Maydell

Progress (combines two weeks): * UM-2 [QEMU upstream maintainership] - investigated various failures of avocado tests on s390x host. These are at least four different unrelated endianness bugs in different device, board or CPU models. Sent out a set of patches fixing at most of these. - TCWG / Arm syncup meeting - Linaro Connect - caught up on code review and sent a target-arm pull request - sent patch fixing a bug where our PNG screenshots have the pixel colour channels in the wrong order - while I had a conversation from Connect fresh in my mind, went back and re-looked at the page-table-walk bug with handling the NSW/SW bits that I sent patches for a couple of weeks ago. Re-did the code to consistently handle these bits in the right place and sent out another version of the patchset - reviewed a very large patchset from RTH that changes how TCG handles atomic accesses so we can implement FEAT_LSE2 - investigated a bug report about a regression with AArch32 EL1 under an AArch64 EL2; wrote patch -- PMM

2 years, 7 months

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[ACTIVITY] Report for week #16

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Reviewed a bunch of Gerrit requests for our CI scripts. - Learning Jenkins job builder syntax and working on a job definition to run fast_check_{gcc,gdb} jobs on Gerrit review requests for jenkins-scripts and ABE. - Changed CI scripts to save ABE and component testsuite logs when the ABE build or check step fails. This should help debug a case where a GDB CI job failed due to (probably) a corruption of the gdb.sum testsuite result file. # Misc - Some preparations for the trip to Linaro Connect. -- Thiago

2 years, 7 months

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[ACTIVITY] report week ending 21 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out v3 of the 'deprecate singlestep option' patchset - sorted out the draft QEMU Summit invite list and invitation text - spent some time trying to understand how the imx SoCs arrange their ethernet controllers and PHYs so I can review a patchset - sent patch fixing minor configure nit where it wasn't honouring --cross-prefix for the ObjC compiler - got the 8.0 release out of the door and handed over merge handling to rth - sent some patchsets updating a few old .txt files to reStructuredText - still thinking about our page-table-walk code -- I'm not convinced it's doing the right thing with NSW/SW bits, even after last week's patchset... -- PMM

2 years, 7 months

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[ACTIVITY] Report for week #15

by Thiago Jung Bauermann

Hello, # TCWG Infrastructure - Fixed problem in ABE with MinGW build of GDB's master branch. - Fixed problem in upstream GDB with MinGW build of GDB's master branch. - Analysed backlog of failed check_gdb jobs. - A couple of "misbisected" commits, including one pointing to a glibc commit. - One detected regression also noticed by Christophe, and fixed by the community. - One Arm failure that passes on QEMU TCG. - Reviewed a number of Gerrit requests about improving ABE and CI scripts. -- Thiago

2 years, 8 months

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[ACTIVITY] week ending Apr. 16 2023

by Alex Bennée

Project Orko ============ Generic vhost-user-device ([ORKO-19]) ===================================== - posted [PATCH 00/12] virtio: add vhost-user-generic and reduce copy and paste Message-Id: <20230414160433.2096866-1-alex.bennee(a)linaro.org> - sent [pull req for gpio simulated device support] [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> [pull req for gpio simulated device support] <https://github.com/rust-vmm/vhost-device/pull/313> Enable Arm Architecture in QEMU =============================== QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] softmmu/vl: fix typo for PHASE_MACHINE_INITIALIZED Message-Id: <20230413090310.1197548-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [QEMU][PATCH] gitlab-ci.d/crossbuilds: Drop the '--disable-tcg' configuration for xen Message-Id: <20230411210422.24255-1-vikram.garhwal(a)amd.com> [RFC 0/1] add support of `--initrd` for ELF-ARM kernels Message-Id: <20230414073432.36000-1-slankes(a)eonerc.rwth-aachen.de> [PATCH 0/2] accel/tcg/plugin: host insn size for plugin Message-Id: <20230406022751.757980-1-fei2.wu(a)intel.com> Other ===== Absences ======== - Easter holidays Current Review Queue ==================== TODO [PATCH for-8.1 0/3] Make softmmu/qtest.c target independent Message-Id: <20230411183418.1640500-1-thuth(a)redhat.com> ======================================================================================================================= TODO [QEMU][PATCH v6 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230411224746.16152-1-vikram.garhwal(a)amd.com> ==================================================================================================================================== TODO [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Message-Id: <20230223204342.1093632-1-richard.henderson(a)linaro.org> ========================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 8 months

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[ACTIVITY] report week ending 14 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] * trying to get a release out of the door -- due among other things to the Easter holiday weekend, rc4 is a bit late and has rather more changes than I would prefer * more triaging of Coverity issues * sent a few trivial bug fix patches * started reviewing and queueing arm patches for 8.1 * investigated a FEAT_SEL2 bug that showed up with some proposed changes to TF-A/Hafnium. The architecture and QEMU's code are pretty hairy in this area but I think I have identified the correct fix... -- PMM

2 years, 8 months

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LLVM bots down for extended period

by Aaron Ballman

Hello! I noticed that some of the build bots in the LLVM build lab have been down for an extended period of time. I tried emailing the Linaro Toolchain Working Group address as they're listed as the admin for the machine, but I've not heard a response in a week. Renato mentioned you might be a good person to contact instead. The following bot(s) appear to have been down for multiple weeks: https://lab.llvm.org/buildbot/#/builders/clang-armv7-global-isel https://lab.llvm.org/buildbot/#/builders/clang-native-arm-lnt-perf https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vla-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls-2stage https://lab.llvm.org/buildbot/#/builders/clang-aarch64-sve-vls https://lab.llvm.org/buildbot/#/builders/clang-armv7-vfpv3-full-2stage https://lab.llvm.org/buildbot/#/builders/clang-thumbv7-full-2stage Do you have plans to bring the bots back online? If not, that's okay -- just let me know and I can remove the bots from the lab for you. Thank you! ~Aaron

2 years, 8 months

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[ACTIVITY] Report for week #14

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI - Submitted to GDB mailing list and committed patches fixing the gdb.asm/asm-source.exp regression found by the check_gdb job. Turned out to be a small bug in the stabs debug format support. - Committed Gerrit review request disabling Python on MinGW cross builds. [GNU-767] Support changing SVE vector length in remote debugging - Investigating a follow-up question Simon asked during review of the patch series fixing a corner case when reading auxv from multi-threaded inferiors. -- Thiago

2 years, 8 months

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[ACTIVITY] report week ending 6 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] * rc3 this week * reworked my "deprecate the misleading -singlestep option" patchset to deal with review feedback, sent out v2 * KVM Forum programme committee work * investigated a regression where the mps3-an547 board asserts on startup; for 8.0 we will just revert the change that introduced the failure, since it was only an optimization * some triage of Coverity issue reports; sent some patches for some easy ones, queried original code submitter for others -- PMM

2 years, 8 months

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[TCWG CI] 602.gcc_s fails to run after llvmorg-17-init-4880-gf242291f59bf

by Maxim Kuvyrkov

Hi Alexandros, Linaro benchmarking CI flagged this patch. After it clang seems to miscompile 602.gcc_s from SPEC CPU2017 for "-O3 -flto" on aarch64-linux-gnu. Also, it appears that 600.perlbench_s slows down by 9%. Could you investigate, please? Let me know if you need any assistance in reproducing the problem. Our Benchmarking CI is still in active development, and there are false positives, but this report seems to be legit [1]. Kind regards, [1] https://ci.linaro.org/job/tcwg_bmk-code_speed-cpu2017speed--llvm-aarch64-ma… -- Maxim Kuvyrkov https://www.linaro.org

2 years, 8 months

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[ACTIVITY] Report for week #13

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI - Committed ABE change suggested by Maxim to mention failures that cause additional testsuite runs. - Tried to update Python MinGW build to 3.x, but it's a rabbit hole. Proposing to disable Python support when cross-building GDB with MinGW instead. - First regression detected by the tcwg_gnu_native_check_gdb CI job reported upstream¹. Started investigating it. [GNU-767] Support changing SVE vector length in remote debugging - Created a testcase to exercise the corner case mentioned by Pedro. Found out that GDB is also susceptible to it. Fixed both GDB and gdbserver. Posted patch series upstream². -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/871ql6dhf4.fsf@linaro.org/ ² https://inbox.sourceware.org/gdb-patches/20230331034432.3037148-1-thiago.ba…

2 years, 8 months

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[ACTIVITY] week ending Apr. 2 2023

by Alex Bennée

Project Orko ============ - more card generation for GPU tasks - started on virtio-gpu blog post - posted [RFC PATCH] tests/avocado: Test Xen guest support under KVM Message-Id: <20230324160719.1790792-1-alex.bennee(a)linaro.org> [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Generic vhost-user-device ([ORKO-19]) ===================================== - got an initial working [branch for generic and rng] [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH 00/10] accel/tcg: refactor the cpu-exec loop Message-Id: <20230320101035.2214196-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] more misc fixes for 8.0 (tests, gdbstub, meta, docs) Message-Id: <20230330101141.30199-1-alex.bennee(a)linaro.org> - preparing for next week's GSoC assessments [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [1/1] ======================= [PATCH v2 0/3] Enable avocado testing for Xen guests Message-Id: <20230308111952.2728440-1-dwmw2(a)infradead.org> Other ===== Absences ======== - Travelling Weds afternoon Current Review Queue ==================== TODO [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Message-Id: <20230223204342.1093632-1-richard.henderson(a)linaro.org> ========================================================================================================================== TODO [RFC QEMU PATCH 00/18] Add VirtIO GPU and Passthrough GPU support on Xen Message-Id: <20230312092244.451465-1-ray.huang(a)amd.com> ==================================================================================================================================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 8 months

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[ACTIVITY] report week ending 31 Mar

by Peter Maydell

Progress (short week, holiday and recovering from covid...): * UM-2 [QEMU upstream maintainership] * 8.0 release related work rumbles on * debugged and fixed a regression caused by my work on HSTR_EL2 traps * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] * implemented FEAT_PAN3 (and fixed a minor bug in syndrome reporting that I noticed in the process) -- PMM

2 years, 8 months

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[ACTIVITY] Report for week #12

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Enabled gdb.gdb/unittest.exp in fast_check_gdb job. It should be stable now that tcwg-jade-02's kernel has been upgraded. - Enabled bisections for check_gdb jobs. - Implemented Maxim's idea to handle GDB testsuite's tests that can FAIL but are silent when they pass (i.e., the "gdb_test -nopass" statements). [GNU-767] Support changing SVE vector length in remote debugging - Back in February I upstreamed a couple of preparation patches and Pedro noticed an unintended change in behaviour that can affect a corner case, so I am working on a fix for that now. -- Thiago

2 years, 8 months

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[ACTIVITY] Report for week #11

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Finished implementing ABE's support for rerunning failed tests using Maxim's idea of leveraging validate_failures.py to determine which tests need to be rerun. Submitted v3 and v4 versions, and committed v4. - Investigated why tcwg-abet-tested jobs have been failing in the CI. Found out that Jenkins sets a bogus core.hooksPath in the git repo config. Submitted and merged a gerrit request fixing the problem. - Investigated why cross-build gdbserver needs GMP and MPFR (and is thus failing to build) in tcwg-gnu-build jobs. Submitted Gerrit review request to fix it. - Started looking into why re-enabling GDB testsuite parallelism makes it run fewer tests. -- Thiago

2 years, 9 months

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[ACTIVITY] report week ending 17 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - went through and made estimates for a pile of JIRA tasks relating to implementing features we're missing to get to ARMv9.4 - diagnosed why --enable-werror wasn't affecting warnings from the kerneldoc docs generator, and sent a patch fixing it - some bug triage, looking for issues that ought to be fixed for 8.0 - fixed a division-by-zero bug in the cadence UART model - fixed a documentation markup mistake that made the docs look odd - investigating/fixing some more CI failures - minor bits of travel/conference related admin -- PMM

2 years, 9 months

1
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[ACTIVITY] Report for week #10

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Submitted and merged a couple of review requests removing obsolete CI jobs related to release automation and release regression detection - Finished version of scripts that have most of the logic for rerunning testsuites in ABE. Submitted as a review request. Addressed review comments and submitted v2. - Maxim found out a way to simplify the logic of determining whether a new testsuite run is warranted by using validate_failures.py, which I'm now implementing. -- Thiago

2 years, 9 months

1
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[ACTIVITY] week ending Mar. 12 2023

by Alex Bennée

Project Orko ============ - various syncs and lining up for resources [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Enable Arm Architecture in QEMU =============================== - bunch of sync meetings with various partners and members QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/30] gdbstub refactor for smaller build Message-Id: <20230307212139.883112-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] tweaks and fixes for 8.0-rc1 (tests, plugins, docs) Message-Id: <20230310103123.2118519-1-alex.bennee(a)linaro.org> - posted [PULL 0/5] gitdm updates Message-Id: <20230310155726.2222233-1-alex.bennee(a)linaro.org> - posted [PATCH v2 00/10] gitdm metadata updates Message-Id: <20230310180332.2274827-1-alex.bennee(a)linaro.org> - posted [kvm-unit-tests PATCH v10 0/7] MTTCG sanity tests for ARM Message-Id: <20230307112845.452053-1-alex.bennee(a)linaro.org> - various GSoC and Outreachy wranglings Completed Reviews [6/6] ======================= [PATCH v2] TCG plugin API extension to read guest memory content by an address Message-Id: <5c50db42136d4a908b261c66b132b043(a)yadro.com> [PATCH] plugin: fix clearing of plugin_mem_cbs before TB exit Message-Id: <20230222043204.941336-1-cota(a)braap.org> [PATCH 0/8] Inter-plugin interactions with QPP Message-Id: <20221213213757.4123265-1-fasano(a)mit.edu> [PATCH v4.5 00/29] gdbstub/next: re-organise and split build Message-Id: <20230303025805.625589-1-richard.henderson(a)linaro.org> [PATCH 0/3] softfloat: FloatRelation cleanups Message-Id: <20220401132240.79730-1-richard.henderson(a)linaro.org> [PATCH v2 0/3] Enable avocado testing for Xen guests Message-Id: <20230308111952.2728440-1-dwmw2(a)infradead.org> Absences ======== - Away on Tuesday Current Review Queue ==================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== TODO [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Message-Id: <20230226220650.1480786-1-smostafa(a)google.com> ====================================================================================================================== TODO [RFC PATCH] hw: arm: Support direct boot for Linux/arm64 EFI zboot images Message-Id: <20230223105308.559632-1-ardb(a)kernel.org> =================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 9 months

1
0
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[ACTIVITY] report week ending Mar 10

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Softfreeze was this Tuesday; lots of wrangling of pull requests - Code review; last arm pullreq before softfreeze - various admin type bits and pieces -- PMM

2 years, 9 months

1
0
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[ACTIVITY] Report for week #9

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Moved most of logic to rerun failed tests from tcwg_gnu-build.sh to Abe and a new script based on the sum file parser of compare_dg_tests.pl. The new script creates a "merged" sum file from all the runs. Currently changing Abe to make use of it. - Did a few cleanups in compare_dg_tests.pl as I was going through its code. Also added KFAIL status support to it, which the GDB testsuite needs. - Removed a few obsolete CI jobs which came out of the woodwork when I merged the compare_dg_tests.pl cleanups. -- Thiago

2 years, 9 months

1
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[ACTIVITY] week ending Mar. 5 2023

by Alex Bennée

Project Orko ============ - did [launch presentation] for SOAFEE and LEDGE SC [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Enable Arm Architecture in QEMU =============================== - bunch of planning for FEAT_GCS, see [QEMU-517] and related - spoke to Lauterbach on behalf of QC, gave pointers on debug [QEMU-517] <https://linaro.atlassian.net/browse/QEMU-517> FEAT_RME, CCA Realms ([QEMU-466]) ================================= - did a bit of review of rth's precursor patches [QEMU-466] <https://linaro.atlassian.net/browse/QEMU-466> QEMU Upstream Work ([UM-2]) =========================== - finished up [MR for using locally built QEMU in TuxRun] - posted [PATCH v4 00/26] gdbstub/next: re-organise and split build Message-Id: <20230302190846.2593720-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/24] testing updates (gitlab, cirrus, docker, avocado, windows) Message-Id: <20230301151604.1948813-1-alex.bennee(a)linaro.org> - these help address the CI minutes we are burning through monthly now [UM-2] <https://linaro.atlassian.net/browse/UM-2> [testing/next] <https://github.com/stsquad/qemu/tree/testing/next> [MR for using locally built QEMU in TuxRun] <https://gitlab.com/Linaro/tuxrun/-/merge_requests/179> Completed Reviews [6/6] ======================= [PATCH v2 0/4] Fix deadlock when dying because of a signal Message-Id: <20230213125238.331881-1-iii(a)linux.ibm.com> [PATCH 0/8] hw/arm: Cleanups around QOM style Message-Id: <20230220115114.25237-1-philmd(a)linaro.org> [PATCH v2 00/24] hw/ide: QOM/QDev housekeeping Message-Id: <20230220091358.17038-1-philmd(a)linaro.org> [PATCH v2] gdbstub: move update guest debug to accel ops Message-Id: <20230207131721.49233-1-mads(a)ynddal.dk> [PATCH 0/5] iotests: make meson aware of individual I/O tests Message-Id: <20230302184606.418541-1-berrange(a)redhat.com> [PATCH v2] TCG plugin API extension to read guest memory content by an address Message-Id: <5c50db42136d4a908b261c66b132b043(a)yadro.com> Other ===== Absences ======== Current Review Queue ==================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== TODO [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Message-Id: <20230226220650.1480786-1-smostafa(a)google.com> ====================================================================================================================== TODO [PATCH v2 00/28] tcg: Simplify temporary usage Message-Id: <20230222232715.15034-1-richard.henderson(a)linaro.org> ==================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 9 months

1
0
0 0

[TCWG CI] Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC

by ci_notify＠linaro.org

Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC: Results changed to -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 from -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-17-init-3240-g02828abd0845 commit for tcwg_aosp-code_size-surfaceflinger: commit 02828abd084536bb758d65043e9747dc2f0e990c Author: Sanjay Patel <spatel(a)rotateright.com> Date: Fri Feb 24 12:05:14 2023 -0500 [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC * oriole-master ** Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC: ** https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Bad build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Good build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Reproduce current build: <cut> mkdir -p investigate-llvm-02828abd084536bb758d65043e9747dc2f0e990c cd investigate-llvm-02828abd084536bb758d65043e9747dc2f0e990c # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 02828abd084536bb758d65043e9747dc2f0e990c Author: Sanjay Patel <spatel(a)rotateright.com> Date: Fri Feb 24 12:05:14 2023 -0500 [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC --- .../Transforms/InstCombine/vec_demanded_elts.ll | 317 ++++++++++++++++++++- 1 file changed, 313 insertions(+), 4 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll index e18865f9b95f..0f33eb58f080 100644 --- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -2,6 +2,9 @@ ; RUN: opt < %s -passes=instcombine -S | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +declare void @use(<2 x i4>) +declare void @use_fp(<2 x float>) + define i32 @test2(float %f) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[T5:%.*]] = fmul float [[F:%.*]], [[F]] @@ -76,8 +79,8 @@ define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind { define <2 x float> @test_fptrunc(double %f) { ; CHECK-LABEL: @test_fptrunc( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[F:%.*]], i64 0 -; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float> -; CHECK-NEXT: ret <2 x float> [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float> +; CHECK-NEXT: ret <2 x float> [[RET]] ; %t9 = insertelement <4 x double> undef, double %f, i32 0 %t10 = insertelement <4 x double> %t9, double 0.000000e+00, i32 1 @@ -91,8 +94,8 @@ define <2 x float> @test_fptrunc(double %f) { define <2 x double> @test_fpext(float %f) { ; CHECK-LABEL: @test_fpext( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[F:%.*]], i64 0 -; CHECK-NEXT: [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double> -; CHECK-NEXT: ret <2 x double> [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double> +; CHECK-NEXT: ret <2 x double> [[RET]] ; %t9 = insertelement <4 x float> undef, float %f, i32 0 %t10 = insertelement <4 x float> %t9, float 0.000000e+00, i32 1 @@ -842,3 +845,309 @@ define <8 x i4> @ins_of_ext_undef_elts_propagation2(<8 x i4> %v, <8 x i4> %v2, i %i21 = shufflevector <8 x i4> %i20, <8 x i4> %v, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15> ret <8 x i4> %i21 } + +define void @common_binop_demand_via_splat_op0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define void @common_binop_demand_via_splat_op1(<2 x i4> %p, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op1( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_X_YSHUF:%.*]] = mul <2 x i4> [[X]], [[YSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_X_YSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_x_yshuf = mul <2 x i4> %x, %yshuf + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_x_yshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 1, i4 2>, [[Q:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = mul <2 x i4> [[Y]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 1, i4 2>, %q ; thwart complexity-based canonicalization + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = mul <2 x i4> %y, %xshuf + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op1_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_splat_op1_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 2, i4 3>, [[Q:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = mul <2 x i4> [[YSHUF]], [[X]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 2, i4 3>, %q ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = mul <2 x i4> %yshuf, %x + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_wrong_commute(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_wrong_commute( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = sub <2 x i4> [[Y:%.*]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = sub <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = sub <2 x i4> %y, %xshuf + %b_xy = sub <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_not_dominated1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_not_dominated1( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %b_xy = mul <2 x i4> %x, %y + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define void @common_binop_demand_via_splat_op0_not_dominated2(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_not_dominated2( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define i4 @common_binop_demand_via_extelt_op0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define float @common_binop_demand_via_extelt_op1(<2 x float> %p, <2 x float> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op1( +; CHECK-NEXT: [[X:%.*]] = fsub <2 x float> <float 0.000000e+00, float 1.000000e+00>, [[P:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_X_YSHUF:%.*]] = fdiv <2 x float> [[X]], [[YSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = fdiv <2 x float> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x float> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use_fp(<2 x float> [[B_X_YSHUF]]) +; CHECK-NEXT: ret float [[B_XY0]] +; + %x = fsub <2 x float> <float 0.0, float 1.0>, %p ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x float> %y, <2 x float> poison, <2 x i32> zeroinitializer + %b_x_yshuf = fdiv <2 x float> %x, %yshuf + %b_xy = fdiv <2 x float> %x, %y + %b_xy0 = extractelement <2 x float> %b_xy, i32 0 + call void @use_fp(<2 x float> %b_x_yshuf) + ret float %b_xy0 +} + +define float @common_binop_demand_via_extelt_op0_commute(<2 x float> %p, <2 x float> %q) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_commute( +; CHECK-NEXT: [[X:%.*]] = fsub <2 x float> <float 0.000000e+00, float 1.000000e+00>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = fsub <2 x float> <float 3.000000e+00, float 2.000000e+00>, [[Q:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = fmul nnan <2 x float> [[Y]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = fmul ninf <2 x float> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x float> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use_fp(<2 x float> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret float [[B_XY0]] +; + %x = fsub <2 x float> <float 0.0, float 1.0>, %p ; thwart complexity-based canonicalization + %y = fsub <2 x float> <float 3.0, float 2.0>, %q ; thwart complexity-based canonicalization + %xshuf = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer + %b_y_xshuf = fmul nnan <2 x float> %y, %xshuf + %b_xy = fmul ninf <2 x float> %x, %y + %b_xy0 = extractelement <2 x float> %b_xy, i32 0 + call void @use_fp(<2 x float> %b_y_xshuf) + ret float %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op1_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op1_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 2, i4 3>, [[Q:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = or <2 x i4> [[YSHUF]], [[X]] +; CHECK-NEXT: [[B_XY:%.*]] = or <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 2, i4 3>, %q ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = or <2 x i4> %yshuf, %x + %b_xy = or <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_y_xshuf) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_wrong_commute(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_wrong_commute( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = sub <2 x i4> [[Y:%.*]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = sub <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = sub <2 x i4> %y, %xshuf + %b_xy = sub <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_y_xshuf) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_not_dominated1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_not_dominated1( +; CHECK-NEXT: [[B_XY:%.*]] = xor <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = xor <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %b_xy = xor <2 x i4> %x, %y + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = xor <2 x i4> %xshuf, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_not_dominated2(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_not_dominated2( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %b_xy = mul <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_mismatch_elt0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_mismatch_elt0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> <i32 1, i32 1> +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> <i32 1, i32 1> + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_mismatch_elt1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_mismatch_elt1( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 1 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 1 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} </cut>

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[TCWG CI] Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage

by ci_notify＠linaro.org

Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage: Results changed to -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 from -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-17-init-3239-g025952b00e0d commit for tcwg_aosp-code_size-surfaceflinger: commit 025952b00e0d5392d31387a4ed4e1d342003a37a Author: Simon Pilgrim <llvm-dev(a)redking.me.uk> Date: Sun Feb 26 15:19:46 2023 +0000 [X86] Add PR46472 bitselect test coverage As noted on Issue #45817 we didn't have scalar coverage for this * oriole-master ** Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage: ** https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Bad build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Good build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Reproduce current build: <cut> mkdir -p investigate-llvm-025952b00e0d5392d31387a4ed4e1d342003a37a cd investigate-llvm-025952b00e0d5392d31387a4ed4e1d342003a37a # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 025952b00e0d5392d31387a4ed4e1d342003a37a Author: Simon Pilgrim <llvm-dev(a)redking.me.uk> Date: Sun Feb 26 15:19:46 2023 +0000 [X86] Add PR46472 bitselect test coverage As noted on Issue #45817 we didn't have scalar coverage for this --- llvm/test/CodeGen/X86/bitselect.ll | 202 +++++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/llvm/test/CodeGen/X86/bitselect.ll b/llvm/test/CodeGen/X86/bitselect.ll new file mode 100644 index 000000000000..5f1f6bd83a9a --- /dev/null +++ b/llvm/test/CodeGen/X86/bitselect.ll @@ -0,0 +1,202 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-bmi | FileCheck %s --check-prefixes=X64,X64-NOBMI +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefixes=X64,X64-BMI + +; PR46472 +; bitselect(a,b,m) == or(and(a,not(m)),and(b,m)) +; bitselect(a,b,m) == xor(and(xor(a,b),m),a) + +define i8 @bitselect_i8(i8 %a, i8 %b, i8 %m) nounwind { +; X86-LABEL: bitselect_i8: +; X86: # %bb.0: +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorb %cl, %al +; X86-NEXT: andb {{[0-9]+}}(%esp), %al +; X86-NEXT: xorb %cl, %al +; X86-NEXT: retl +; +; X64-LABEL: bitselect_i8: +; X64: # %bb.0: +; X64-NEXT: andl %edx, %esi +; X64-NEXT: movl %edx, %eax +; X64-NEXT: notb %al +; X64-NEXT: andb %dil, %al +; X64-NEXT: orb %sil, %al +; X64-NEXT: retq + %not = xor i8 %m, -1 + %ma = and i8 %a, %not + %mb = and i8 %b, %m + %or = or i8 %ma, %mb + ret i8 %or +} + +define i16 @bitselect_i16(i16 %a, i16 %b, i16 %m) nounwind { +; X86-LABEL: bitselect_i16: +; X86: # %bb.0: +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorw %ax, %cx +; X86-NEXT: andw {{[0-9]+}}(%esp), %cx +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i16: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %eax +; X64-NOBMI-NEXT: andl %edx, %esi +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: orl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i16: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnl %edi, %edx, %eax +; X64-BMI-NEXT: andl %edx, %esi +; X64-BMI-NEXT: orl %esi, %eax +; X64-BMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-BMI-NEXT: retq + %not = xor i16 %m, -1 + %ma = and i16 %a, %not + %mb = and i16 %b, %m + %or = or i16 %ma, %mb + ret i16 %or +} + +define i32 @bitselect_i32(i32 %a, i32 %b, i32 %m) nounwind { +; X86-LABEL: bitselect_i32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i32: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: xorl %edi, %eax +; X64-NOBMI-NEXT: andl %edx, %eax +; X64-NOBMI-NEXT: xorl %edi, %eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i32: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnl %edi, %edx, %eax +; X64-BMI-NEXT: andl %edx, %esi +; X64-BMI-NEXT: orl %esi, %eax +; X64-BMI-NEXT: retq + %not = xor i32 %m, -1 + %ma = and i32 %a, %not + %mb = and i32 %b, %m + %or = or i32 %ma, %mb + ret i32 %or +} + +define i64 @bitselect_i64(i64 %a, i64 %b, i64 %m) nounwind { +; X86-LABEL: bitselect_i64: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: xorl %esi, %edx +; X86-NEXT: andl {{[0-9]+}}(%esp), %edx +; X86-NEXT: xorl %esi, %edx +; X86-NEXT: popl %esi +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i64: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rsi, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: andq %rdx, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i64: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnq %rdi, %rdx, %rax +; X64-BMI-NEXT: andq %rdx, %rsi +; X64-BMI-NEXT: orq %rsi, %rax +; X64-BMI-NEXT: retq + %not = xor i64 %m, -1 + %ma = and i64 %a, %not + %mb = and i64 %b, %m + %or = or i64 %ma, %mb + ret i64 %or +} + +define i128 @bitselect_i128(i128 %a, i128 %b, i128 %m) nounwind { +; X86-LABEL: bitselect_i128: +; X86: # %bb.0: +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorl %edi, %ecx +; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorl %edi, %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: xorl %ebx, %edi +; X86-NEXT: andl {{[0-9]+}}(%esp), %edi +; X86-NEXT: xorl %ebx, %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: xorl %esi, %ebx +; X86-NEXT: andl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: xorl %esi, %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: andl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: movl %esi, 12(%eax) +; X86-NEXT: movl %ebx, 8(%eax) +; X86-NEXT: movl %edi, 4(%eax) +; X86-NEXT: movl %ecx, (%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: retl $4 +; +; X64-NOBMI-LABEL: bitselect_i128: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rdx, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: andq %r8, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: xorq %rsi, %rcx +; X64-NOBMI-NEXT: andq %r9, %rcx +; X64-NOBMI-NEXT: xorq %rsi, %rcx +; X64-NOBMI-NEXT: movq %rcx, %rdx +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i128: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnq %rsi, %r9, %rsi +; X64-BMI-NEXT: andnq %rdi, %r8, %rax +; X64-BMI-NEXT: andq %r9, %rcx +; X64-BMI-NEXT: orq %rcx, %rsi +; X64-BMI-NEXT: andq %r8, %rdx +; X64-BMI-NEXT: orq %rdx, %rax +; X64-BMI-NEXT: movq %rsi, %rdx +; X64-BMI-NEXT: retq + %not = xor i128 %m, -1 + %ma = and i128 %a, %not + %mb = and i128 %b, %m + %or = or i128 %ma, %mb + ret i128 %or +} </cut>

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[ACTIVITY] Report for week #8

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilize GDB testsuite results in the CI - Cleaned up change in tcwg_gnu-build.sh that reruns failed tests and created Gerrit review request¹. - Based on Laurent's and Maxim's suggestions, decided to put the code which retries the failed tests in Abe, so now I'm working on that. -- Thiago ¹ https://review.linaro.org/c/toolchain/jenkins-scripts/+/43265

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[ACTIVITY] report week ending 24 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Code review: big FEAT_LSE2 support series, 8.3 pointer auth, gdbstub support for M-profile sysregs, another round of FEAT_RME, and more - discussions about how to handle the fact that QEMU has run out of gitlab CI minutes, and some tweaking of my scripts to work around the lack of minutes -- PMM

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