- linaro-toolchain - lists.linaro.org

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- the usual release cycle work. Looks relatively quiet this time around. -- taking the opportunity to try to catch up on some of the for-8.0 code review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] -- started thinking about how to implement FEAT_FGT. Looking at the code where this ought to go, I found a minor bug with how we implement the existing HSTR_EL2 traps, and a case where we trap AArch32 ATS12NSO* with the wrong syndrome. -- PMM

2 years, 7 months

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[ACTIVITY] Report for week #45

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Working on v2 of the gdbserver patches improving SVE support. Tested new code for regressions in different systems and configurations and found none. Preparing new version of the patches for upstream submission. Will likely post them early next week. -- Thiago

2 years, 7 months

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[ACTIVITY] week ending Nov. 13 2022

by Alex Bennée

Project Stratos =============== - finished [blog post for virtio-camera] - did a review of [virtio-loopback] [blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> [virtio-loopback] <https://git.virtualopensystems.com/virtio-loopback> vhost-device maintainer effort ([UM-196]) - review work Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - hackbox2 upgrade follow-up - health check content Completed Reviews [7/7] ======================= [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-1-richard.henderson(a)linaro.org> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH] Run docker probe only if docker or podman are available Message-Id: <20221030083510.310584-1-sw(a)weilnetz.de> [PULL 3/3] linux-test (tests/tcg/multiarch/linux-test.c) add check Message-Id: <1626902375-7002-4-git-send-email-tsimpson(a)quicinc.com> [PATCH v5 00/18] tests/qtest: Enable running qtest on Windows Message-Id: <20221006151927.2079583-3-bmeng.cn(a)gmail.com> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH RFC 0/1] tcg: add perfmap and jitdump Message-Id: <20221012051846.1432050-1-iii(a)linux.ibm.com> Absences ======== Current Review Queue ==================== TODO [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Message-Id: <20221111074101.2069454-1-richard.henderson(a)linaro.org> ===================================================================================================================================== TODO [PATCH v3 0/7] memory: prevent dma-reentracy issues Message-Id: <20221028191648.964076-1-alxndr(a)bu.edu> =========================================================================================================== TODO [QEMU][PATCH v2 0/5] Introduce Xilinx Versal CANFD Message-Id: <20221022054746.28217-1-vikram.garhwal(a)amd.com> ================================================================================================================== -- Alex Bennée

2 years, 7 months

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[ACTIVITY] report week ending 10 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- identified another piece of the reset mechanics that can be tractably cleaned up: I think we should be able to get everything (effectively) moved over to the 3-phase reset system -- sent out various for-8.0 patchsets that convert devices that were using device_class_set_parent_reset(), since getting rid of that function is step 1 of that cleanup -- code review etc -- PMM

2 years, 7 months

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[ACTIVITY] Report for week #44

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Confirmed that gdbserver doesn't send a new XML target description over the wire when the vector length changes, so there's no impact of these patches on the amount of remote protocol traffic, which was a concern for GDB maintainers. - Started doing some up code cleanup and regression tests to prepare for submitting v2 of the patches. # [GNU-796] Stabilise GDB testsuite results in the CI - Committed Gerrit change request adding the new CI job¹ to run fast subset of GDB tests, which also has stable results. The list of tests comes from Sourceware's builder project. -- Thiago ¹ https://ci.linaro.org/view/tcwg_gnu_native/job/tcwg_gnu_native_fast_check_g…

2 years, 7 months

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[ACTIVITY] report week ending 4 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- investigated and thought a bit more about a race condition involving display devices. I know think I understand the problem but the best idea I could come up with for a solution is pretty painful... (Still hoping for feedback on whether I've missed something.) -- collated and sent out a pull request with various bug fixes for rc0 -- sent some more reset-cleanup patches (these will be for 8.0) -- PMM

2 years, 7 months

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Virt meeting 2022-11-01

by Richard Henderson

Hi guys, I will attempt to join today, but we've been finding that connectivity is dependent on the number of rain drops and/or hail in between here and the mast. So I'm not overly hopeful for later this evening. Status report: - Fixed a failure in my x86 TARGET_TB_PCREL patches, which caused non-booting of some images (in today's tcg PR). - Revised the TCGv_i128 patch set (not yet posted). - Lots of work on accel/tcg/{cputlb,user-exec}.c, to honor atomicity requirements of FEAT_LSE2. Next up: Adding qemu_ld/st helpers and patterns for i128. r~

2 years, 8 months

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[ACTIVITY] Report for week #43

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. Started checking changes for regressions. -- Thiago

2 years, 8 months

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[ACTIVITY] report week ending 28 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Cross-checked our boot.c code against the kernel's booting.rst, and sent patch fixing a few EL3 config bits we weren't setting - Sent out the minutes from QEMU Summit * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - Wrote and sent out patches to implement the extra traps required for FEAT_EVT -- PMM

2 years, 8 months

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[ACTIVITY] Report for week #42

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilise GDB testsuite results in the CI - Reworked and committed Gerrit change request for jenkins-scripts adding a new CI job definition in tcwg_gnu-build.sh. - Also reworked and committed another one to the same script adding a default manifest file if one isn't specified on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Implemented Luis' suggestion of assuming that if ptrace can't read the SVE state, then SVE is disabled (which is what gdbserver does before my patches). It turns out that the only situation where this happens, gdbserver doesn't actually care about the target description. - Started exploring/implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. As Luis suggests, it may simplify the code. -- Thiago

2 years, 8 months

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[ACTIVITY] week ending Oct. 23 2022

by Alex Bennée

Project Stratos =============== - wrote a [draft blog post for virtio-camera] [draft blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> vhost-device maintainer effort ([UM-196]) - review work [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: don't process FCSE translations on physical TLBs Message-Id: <20221021172338.2782240-1-alex.bennee(a)linaro.org> - posted [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: protect execlog's last_exec expansion Message-Id: <20221021164028.2757262-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: enable debug on CONFIG_DEBUG_TCG Message-Id: <20221021155146.2729598-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [4/4] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits Message-Id: <20221020123506.26363-1-ani(a)anisinha.ca> Other ===== - reviews and appraisals - members operational meeting - QEMU plans Absences ======== Current Review Queue ==================== TODO [PATCH 00/31] tcg: Support for Int128 with helpers Message-Id: <20221020115242.2301066-1-richard.henderson(a)linaro.org> ========================================================================================================================== TODO [PATCH v8 0/9] target/arm: pc-relative translation blocks Message-Id: <20221020030641.2066807-1-richard.henderson(a)linaro.org> ================================================================================================================================= TODO [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> ============================================================================================================================ -- Alex Bennée

2 years, 8 months

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[ACTIVITY] report week ending 21 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Spent a couple of days investigating a long-standing intermittent test case failure booting a kernel on the raspberry pi. This turned out to be caused by two linked bugs: - the test framework unhelpfully disconnects immediately from the guest serial console when the test ends, rather than staying connected until the QEMU process exits to capture all the output - QEMU's socket chardev loses data when the remote end closes the connection if the guest UART hasn't read all of it So the test was failing because the guest sometimes only saw the 'h' of the final 'halt' command the test sent... - Investigated and fixed a regression caused by some of last week's reset patches. (Turns out the patch to fix it had been sent back in 2021 but we accidentally dropped it on the floor. Oops.) thanks -- PMM

2 years, 8 months

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[ACTIVITY] Report for week #41

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued incorporating suggestions from Luis' review of the patches. Working on a few regressions I introduced in the process. # [GNU-796] Stabilise GDB testsuite results in the CI - Started addressing Maxim's comments to my change requests for jenkins-scripts. -- Thiago

2 years, 8 months

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[ACTIVITY] week ending Oct. 16 2022

by Alex Bennée

Project Stratos =============== - virtio-camera discussion and prep vhost-device maintainer effort ([UM-196]) - more review, vsock merged \o/ [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - more leadership committee work - more member engagement on CCA/RME - posted [PATCH v1 0/4] testing/next hotfix (revert bios build, mingw) Message-Id: <20221011113417.794841-1-alex.bennee(a)linaro.org> - posted [PULL 0/1] testing: revert pc-bios build patch Message-Id: <20221011192858.956078-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/7] testing/next (configure, RUNC, win32|64) Message-Id: <20221013154705.1846261-1-alex.bennee(a)linaro.org> - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [2/2] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> Other ===== - reviews and appraisals - other admin Absences ======== - day off ill Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== -- Alex Bennée

2 years, 8 months

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[ACTIVITY] report week ending 14 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Started looking again at QEMU's rather messy set of reset related APIs. Dug out the half-a-plan I wrote up a long time back and refreshed my memory of what I was hoping we might be able to do. - As an initial step, wrote some patches to get rid of uses of several deprecated reset-related functions so that I only have to think about one set of functions and not two... -- PMM

2 years, 8 months

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[TCWG CI] Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses

by ci_notify＠linaro.org

Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 624 # First few build errors in logs: # 00:01:42 mm/slub.c:4428:5: error: virtual use of statement not up to date # 00:01:42 mm/slub.c:4428:5: internal compiler error: verify_ssa failed # 00:01:43 make[2]: *** [scripts/Makefile.build:250: mm/slub.o] Error 1 # 00:01:44 make[1]: *** [scripts/Makefile.build:500: mm] Error 2 # 00:01:56 make: *** [Makefile:1990: .] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 629 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-3219-g25413fdb2ac commit for tcwg_kernel: commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. * gnu-master-aarch64-next-allnoconfig ** Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Reproduce current build: <cut> mkdir -p investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 cd investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. --- gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c | 40 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c | 44 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c | 45 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c | 39 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c | 42 +++ gcc/tree-if-conv.cc | 313 ++++++++++++++++++-- gcc/tree-vect-data-refs.cc | 3 +- gcc/tree-vect-patterns.cc | 330 +++++++++++++++++++++- 14 files changed, 1079 insertions(+), 31 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c new file mode 100644 index 00000000000..01cf34fb444 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c @@ -0,0 +1,40 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define ELT0 {0} +#define ELT1 {1} +#define ELT2 {2} +#define ELT3 {3} +#define N 32 +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].i; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c new file mode 100644 index 00000000000..1a4a1579c14 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 0} +#define ELT1 {0x7FFFFFFFUL, 1} +#define ELT2 {0x7FFFFFFFUL, 2} +#define ELT3 {0x7FFFFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c new file mode 100644 index 00000000000..849f4a017e1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c @@ -0,0 +1,44 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" +#include <stdbool.h> + +extern void abort(void); + +typedef struct { + int c; + int b; + bool a : 1; + int d : 31; +} struct_t; + +#define N 16 +#define ELT_F { 0xFFFFFFFF, 0xFFFFFFFF, 0, 0x7FFFFFFF } +#define ELT_T { 0xFFFFFFFF, 0xFFFFFFFF, 1, 0x7FFFFFFF } + +struct_t vect_false[N] = { ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +struct_t vect_true[N] = { ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +int main (void) +{ + unsigned ret = 0; + for (unsigned i = 0; i < N; i++) + { + ret |= vect_false[i].a; + } + if (ret) + abort (); + + for (unsigned i = 0; i < N; i++) + { + ret |= vect_true[i].a; + } + if (!ret) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c new file mode 100644 index 00000000000..5bc9c412e96 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c @@ -0,0 +1,45 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 3, 0} +#define ELT1 {0x7FFFFFFFUL, 3, 1} +#define ELT2 {0x7FFFFFFFUL, 3, 2} +#define ELT3 {0x7FFFFFFFUL, 3, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c new file mode 100644 index 00000000000..1dc24d3eded --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 9; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c new file mode 100644 index 00000000000..7d24c299758 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 8; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c new file mode 100644 index 00000000000..19683d277b1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c @@ -0,0 +1,39 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].i = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].i != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c new file mode 100644 index 00000000000..d550dd35ab7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c new file mode 100644 index 00000000000..3303d2610ff --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c new file mode 100644 index 00000000000..fae6ea3557d --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 9; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c new file mode 100644 index 00000000000..99360c2967b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 8; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc index bac29fb5574..e468a4659fa 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -91,6 +91,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-pass.h" #include "ssa.h" #include "expmed.h" +#include "expr.h" #include "optabs-query.h" #include "gimple-pretty-print.h" #include "alias.h" @@ -123,6 +124,9 @@ along with GCC; see the file COPYING3. If not see #include "tree-vectorizer.h" #include "tree-eh.h" +/* For lang_hooks.types.type_for_mode. */ +#include "langhooks.h" + /* Only handle PHIs with no more arguments unless we are asked to by simd pragma. */ #define MAX_PHI_ARG_NUM \ @@ -145,6 +149,12 @@ static bool need_to_rewrite_undefined; before phi_convertible_by_degenerating_args. */ static bool any_complicated_phi; +/* True if we have bitfield accesses we can lower. */ +static bool need_to_lower_bitfields; + +/* True if there is any ifcvting to be done. */ +static bool need_to_ifcvt; + /* Hash for struct innermost_loop_behavior. It depends on the user to free the memory. */ @@ -1411,15 +1421,6 @@ if_convertible_loop_p_1 (class loop *loop, vec<data_reference_p> *refs) calculate_dominance_info (CDI_DOMINATORS); - /* Allow statements that can be handled during if-conversion. */ - ifc_bbs = get_loop_body_in_if_conv_order (loop); - if (!ifc_bbs) - { - if (dump_file && (dump_flags & TDF_DETAILS)) - fprintf (dump_file, "Irreducible loop\n"); - return false; - } - for (i = 0; i < loop->num_nodes; i++) { basic_block bb = ifc_bbs[i]; @@ -2899,18 +2900,22 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) class loop *new_loop; gimple *g; gimple_stmt_iterator gsi; - unsigned int save_length; + unsigned int save_length = 0; g = gimple_build_call_internal (IFN_LOOP_VECTORIZED, 2, build_int_cst (integer_type_node, loop->num), integer_zero_node); gimple_call_set_lhs (g, cond); - /* Save BB->aux around loop_version as that uses the same field. */ - save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; - void **saved_preds = XALLOCAVEC (void *, save_length); - for (unsigned i = 0; i < save_length; i++) - saved_preds[i] = ifc_bbs[i]->aux; + void **saved_preds = NULL; + if (any_complicated_phi || need_to_predicate) + { + /* Save BB->aux around loop_version as that uses the same field. */ + save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; + saved_preds = XALLOCAVEC (void *, save_length); + for (unsigned i = 0; i < save_length; i++) + saved_preds[i] = ifc_bbs[i]->aux; + } initialize_original_copy_tables (); /* At this point we invalidate porfile confistency until IFN_LOOP_VECTORIZED @@ -2922,8 +2927,9 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) profile_probability::always (), true); free_original_copy_tables (); - for (unsigned i = 0; i < save_length; i++) - ifc_bbs[i]->aux = saved_preds[i]; + if (any_complicated_phi || need_to_predicate) + for (unsigned i = 0; i < save_length; i++) + ifc_bbs[i]->aux = saved_preds[i]; if (new_loop == NULL) return NULL; @@ -2999,7 +3005,7 @@ ifcvt_split_critical_edges (class loop *loop, bool aggressive_if_conv) auto_vec<edge> critical_edges; /* Loop is not well formed. */ - if (num <= 2 || loop->inner || !single_exit (loop)) + if (loop->inner) return false; body = get_loop_body (loop); @@ -3260,6 +3266,201 @@ ifcvt_hoist_invariants (class loop *loop, edge pe) free (body); } +/* Returns the DECL_FIELD_BIT_OFFSET of the bitfield accesse in stmt iff its + type mode is not BLKmode. If BITPOS is not NULL it will hold the poly_int64 + value of the DECL_FIELD_BIT_OFFSET of the bitfield access and STRUCT_EXPR, + if not NULL, will hold the tree representing the base struct of this + bitfield. */ + +static tree +get_bitfield_rep (gassign *stmt, bool write, tree *bitpos, + tree *struct_expr) +{ + tree comp_ref = write ? gimple_assign_lhs (stmt) + : gimple_assign_rhs1 (stmt); + + tree field_decl = TREE_OPERAND (comp_ref, 1); + tree rep_decl = DECL_BIT_FIELD_REPRESENTATIVE (field_decl); + + /* Bail out if the representative is BLKmode as we will not be able to + vectorize this. */ + if (TYPE_MODE (TREE_TYPE (rep_decl)) == E_BLKmode) + return NULL_TREE; + + /* Bail out if the DECL_SIZE of the field_decl isn't the same as the BF's + precision. */ + unsigned HOST_WIDE_INT bf_prec + = TYPE_PRECISION (TREE_TYPE (gimple_assign_lhs (stmt))); + if (compare_tree_int (DECL_SIZE (field_decl), bf_prec) != 0) + return NULL_TREE; + + if (struct_expr) + *struct_expr = TREE_OPERAND (comp_ref, 0); + + if (bitpos) + *bitpos + = fold_build2 (MINUS_EXPR, bitsizetype, + DECL_FIELD_BIT_OFFSET (field_decl), + DECL_FIELD_BIT_OFFSET (rep_decl)); + + return rep_decl; + +} + +/* Lowers the bitfield described by DATA. + For a write like: + + struct.bf = _1; + + lower to: + + __ifc_1 = struct.<representative>; + __ifc_2 = BIT_INSERT_EXPR (__ifc_1, _1, bitpos); + struct.<representative> = __ifc_2; + + For a read: + + _1 = struct.bf; + + lower to: + + __ifc_1 = struct.<representative>; + _1 = BIT_FIELD_REF (__ifc_1, bitsize, bitpos); + + where representative is a legal load that contains the bitfield value, + bitsize is the size of the bitfield and bitpos the offset to the start of + the bitfield within the representative. */ + +static void +lower_bitfield (gassign *stmt, bool write) +{ + tree struct_expr; + tree bitpos; + tree rep_decl = get_bitfield_rep (stmt, write, &bitpos, &struct_expr); + tree rep_type = TREE_TYPE (rep_decl); + tree bf_type = TREE_TYPE (gimple_assign_lhs (stmt)); + + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Lowering:\n"); + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + fprintf (dump_file, "to:\n"); + } + + /* REP_COMP_REF is a COMPONENT_REF for the representative. NEW_VAL is it's + defining SSA_NAME. */ + tree rep_comp_ref = build3 (COMPONENT_REF, rep_type, struct_expr, rep_decl, + NULL_TREE); + tree new_val = ifc_temp_var (rep_type, rep_comp_ref, &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + if (write) + { + new_val = ifc_temp_var (rep_type, + build3 (BIT_INSERT_EXPR, rep_type, new_val, + unshare_expr (gimple_assign_rhs1 (stmt)), + bitpos), &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + gimple *new_stmt = gimple_build_assign (unshare_expr (rep_comp_ref), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + else + { + tree bfr = build3 (BIT_FIELD_REF, bf_type, new_val, + build_int_cst (bitsizetype, TYPE_PRECISION (bf_type)), + bitpos); + new_val = ifc_temp_var (bf_type, bfr, &gsi); + + gimple *new_stmt = gimple_build_assign (gimple_assign_lhs (stmt), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + + gsi_remove (&gsi, true); +} + +/* Return TRUE if there are bitfields to lower in this LOOP. Fill TO_LOWER + with data structures representing these bitfields. */ + +static bool +bitfields_to_lower_p (class loop *loop, + vec <gassign *> &reads_to_lower, + vec <gassign *> &writes_to_lower) +{ + gimple_stmt_iterator gsi; + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Analyzing loop %d for bitfields:\n", loop->num); + } + + for (unsigned i = 0; i < loop->num_nodes; ++i) + { + basic_block bb = ifc_bbs[i]; + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) + { + gassign *stmt = dyn_cast<gassign*> (gsi_stmt (gsi)); + if (!stmt) + continue; + + tree op = gimple_assign_lhs (stmt); + bool write = TREE_CODE (op) == COMPONENT_REF; + + if (!write) + op = gimple_assign_rhs1 (stmt); + + if (TREE_CODE (op) != COMPONENT_REF) + continue; + + if (DECL_BIT_FIELD_TYPE (TREE_OPERAND (op, 1))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + + if (!INTEGRAL_TYPE_P (TREE_TYPE (op))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NO OK to lower," + " field type is not Integral.\n"); + return false; + } + + if (!get_bitfield_rep (stmt, write, NULL, NULL)) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NOT OK to lower," + " representative is BLKmode.\n"); + return false; + } + + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\tBitfield OK to lower.\n"); + if (write) + writes_to_lower.safe_push (stmt); + else + reads_to_lower.safe_push (stmt); + } + } + } + return !reads_to_lower.is_empty () || !writes_to_lower.is_empty (); +} + + /* If-convert LOOP when it is legal. For the moment this pass has no profitability analysis. Returns non-zero todo flags when something changed. */ @@ -3270,12 +3471,16 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) unsigned int todo = 0; bool aggressive_if_conv; class loop *rloop; + auto_vec <gassign *, 4> reads_to_lower; + auto_vec <gassign *, 4> writes_to_lower; bitmap exit_bbs; edge pe; again: rloop = NULL; ifc_bbs = NULL; + need_to_lower_bitfields = false; + need_to_ifcvt = false; need_to_predicate = false; need_to_rewrite_undefined = false; any_complicated_phi = false; @@ -3291,16 +3496,42 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) aggressive_if_conv = true; } - if (!ifcvt_split_critical_edges (loop, aggressive_if_conv)) + if (!single_exit (loop)) goto cleanup; - if (!if_convertible_loop_p (loop) - || !dbg_cnt (if_conversion_tree)) + /* If there are more than two BBs in the loop then there is at least one if + to convert. */ + if (loop->num_nodes > 2 + && !ifcvt_split_critical_edges (loop, aggressive_if_conv)) goto cleanup; - if ((need_to_predicate || any_complicated_phi) - && ((!flag_tree_loop_vectorize && !loop->force_vectorize) - || loop->dont_vectorize)) + ifc_bbs = get_loop_body_in_if_conv_order (loop); + if (!ifc_bbs) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "Irreducible loop\n"); + goto cleanup; + } + + if (loop->num_nodes > 2) + { + need_to_ifcvt = true; + + if (!if_convertible_loop_p (loop) || !dbg_cnt (if_conversion_tree)) + goto cleanup; + + if ((need_to_predicate || any_complicated_phi) + && ((!flag_tree_loop_vectorize && !loop->force_vectorize) + || loop->dont_vectorize)) + goto cleanup; + } + + if ((flag_tree_loop_vectorize || loop->force_vectorize) + && !loop->dont_vectorize) + need_to_lower_bitfields = bitfields_to_lower_p (loop, reads_to_lower, + writes_to_lower); + + if (!need_to_ifcvt && !need_to_lower_bitfields) goto cleanup; /* The edge to insert invariant stmts on. */ @@ -3311,7 +3542,8 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) Either version this loop, or if the pattern is right for outer-loop vectorization, version the outer loop. In the latter case we will still if-convert the original inner loop. */ - if (need_to_predicate + if (need_to_lower_bitfields + || need_to_predicate || any_complicated_phi || flag_tree_loop_if_convert != 1) { @@ -3351,10 +3583,31 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) pe = single_pred_edge (gimple_bb (preds->last ())); } - /* Now all statements are if-convertible. Combine all the basic - blocks into one huge basic block doing the if-conversion - on-the-fly. */ - combine_blocks (loop); + if (need_to_lower_bitfields) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "-------------------------\n"); + fprintf (dump_file, "Start lowering bitfields\n"); + } + while (!reads_to_lower.is_empty ()) + lower_bitfield (reads_to_lower.pop (), false); + while (!writes_to_lower.is_empty ()) + lower_bitfield (writes_to_lower.pop (), true); + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Done lowering bitfields\n"); + fprintf (dump_file, "-------------------------\n"); + } + } + if (need_to_ifcvt) + { + /* Now all statements are if-convertible. Combine all the basic + blocks into one huge basic block doing the if-conversion + on-the-fly. */ + combine_blocks (loop); + } </cut>

2 years, 8 months

1
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[ACTIVITY] Report for weeks #37, #39 and #40

by Thiago Jung Bauermann

Hello, I haven't sent a report since week #36. For that reason, this report covers three weeks. # [GNU-796] Stabilise GDB testsuite results in the CI - Implemented CI job to run fast GDB tests based on the list from Sourceware's builder. Submitted Gerrit change requests for jenkins-scripts and ci/job/configs. - Posted Gerrit change request for jenkins-scripts with an improvement to tcwg_gnu-build.sh to use a default path for the artifacts file if one isn't given on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Started incorporating suggestions from Luis' review of the patches. # Community participation - Reviewed mailing list patch “[PATCH v3] gdb/arm: Handle lazy FPU register stacking” - Attended GNU Tools Cauldron 2022. -- Thiago

2 years, 8 months

1
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[ACTIVITY] week ending Oct. 9 2022

by Alex Bennée

Project Stratos =============== [UM-196] <https://linaro.atlassian.net/browse/UM-196> vhost-device maintainer effort ([UM-196]) - [review of vhost-sock for vhost-device] [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/54] testing, gdbstub, plugin and gitdm updates Message-Id: <20221004130138.2299307-1-alex.bennee(a)linaro.org> - took 3 attempts [PULL v3 00/52] testing, gdbstub, plugin and gitdm updates Message-Id: <20221006105556.3319342-1-alex.bennee(a)linaro.org> - leadership committee work - member engagement on CCA/RME [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH 00/20] Cross compilation changes for 7.2 Message-Id: <20220825222745.38779-13-pbonzini(a)redhat.com> [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Message-Id: <20221004141051.110653-4-richard.henderson(a)linaro.org> [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> Other ===== - reviews and appraisals Absences ======== Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org> =========================================================================================================================================================================== -- Alex Bennée

2 years, 8 months

1
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[ACTIVITY] report week ending Oct 7

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - miscellaneous upstream patch review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - sent out patchset implementing FEAT_GTG - sent out patch implementing FEAT_E0PD - code review of RTH's FEAT_HAFDBS patchset -- PMM

2 years, 8 months

1
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[ACTIVITY] report week ending 30 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out patch which adds a retry-on-EINTR loop to KVM_CREATE_VM ioctls - wrote up the draft of the minutes for the QEMU Summit for review - more code review and pullrequest collation (notably the Arm v8R support patchset) * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - read up on the remaining unimplemented features under this epic; closed out one we'd already implemented, and wrote up enough detail on the others to be happy with putting them all into the current sprint (they're all small features) - started looking at FEAT_GTG thanks -- PMM

2 years, 9 months

1
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[ACTIVITY] week ending Sep. 25 2022

by Alex Bennée

Project Stratos =============== - held poll for next meeting - started planning for virtio-camera/sensor QEMU Upstream Work ([UM-2]) =========================== - posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id: <CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com> - sadly one patch had to be reverted as it exposed another race - posted [PATCH v1 00/10] plugins/next (disas, monitor, docs, execlog) Message-Id: <20220921160801.1490125-6-alex.bennee(a)linaro.org> - posted [PULL 00/30] testing updates (docker, avocado, deprecate 32bit BE MIPS) Message-Id: <20220920171533.1098094-4-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Update docs - mention -d plugin - document features of tests/plugin plugins - clean up command lines to drop builddir KVM Forum ========= - Attended KVM forum, gave a talk, helper with another Completed Reviews [3/3] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> [RFC PATCH v2] gdbstub: only send stop-reply packets when allowed to Message-Id: <ba99db564c3aeb1812bdfbc9116849092334482f.1661362557.git.quic_mathbern(a)quicinc.com> [RFC 0/4] Support interactions between TCG plugins Message-Id: <20220901182734.2987337-1-fasano(a)mit.edu> Absences ======== Current Review Queue ==================== TODO [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [PATCH 00/51] tests/qtest: Enable running qtest on Windows Message-Id: <20220824094029.1634519-1-bmeng.cn(a)gmail.com> ======================================================================================================================== TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org> ======================================================================================================================================= -- Alex Bennée

2 years, 9 months

1
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[ACTIVITY] report week ending 23 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - attended KVM Forum - catching up with code review, email, etc... - sent out an Arm pullreq now 7.2 has opened up for development * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - diagnosed a regression caused by the recent FEAT_PMUv3p5 changes and sent out a fix KVM Forum trip highlights: * it was good to be able to meet people face-to-face again after several years * Cloud use of Arm hardware has now got to the point where big cloud companies are working through performance issues and then coming to present about it; e.g. Google did a talk about perf issues during migration on an Ampere Altra setup. The solutions seem to be a mix of "apply the lessons and fixes we already went through with x86" and "architecture fixes coming down the pipe" (in this case FEAT_TLBIRANGE and FEAT_BBM). * lots of Google talks about pKVM (using hypervisor hardware on Android to improve security). In fact lots of Google all over -- apparently they've made a big push to do more upstream kernel work and as a result a large chunk of the kernel KVM commits come from them... * talk from Xilinx (now with AMD) about doing co-simulation of QEMU and RTL -- basically (with the aid of a lot of non-upstream stuff) having QEMU talk to a SystemC environment so you can have eg an emulated ethernet card in FPGA that plugs into a QEMU VM. This kind of thing is a use-case which historically upstream have not really been interested in addressing. * Which brings me to the BoF session on emulation, perhaps the most interesting bit of the conference for me. There was a lot of discussion about whether QEMU might move closer to what I call the "bag of lego bricks" paradigm, where it provides device models and users might be able to configure it at runtime to stitch them together, perhaps adding out-of-tree devices of their own. There is clearly interest in this (eg from attendees from Xilinx and Qualcomm); the sticking point is that from upstream's perspective this seems like "you should do this thing that will benefit us and not you". My take is that whether this goes anywhere will depend on whether those who would like this are prepared to coordinate together to present themselves as a group who are willing to dig in to the necessary upstream refactoring and cleanup that would be a precondition for having something like this be anywhere near supportable, i.e. that they're a group who will come and help rather than merely consume... * There was also a shorter discussion in the BoF about the idea of "heterogenous CPU emulation", eg one QEMU model with both Arm and Microblaze CPUs. This is not conceptually controversial, it's just a lot of work. It seemed like maybe a few folk now care enough to have a go at it. -- PMM

2 years, 9 months

1
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[ACTIVITY] Report for week #36

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Made a few last-minute adjustments to the code and fixed a couple of regressions on x86_64-linux. Re-ran regression tests on x86_64-linux and aarch64-linux. Wrote cover letter and descriptions for all the patches. - Finally posted the patch series upstream¹. # [GNU-796] Stabilize GDB testsuite results in the Linaro CI - Started working on this issue. Currently adding a new CI job to run the same small subset of GDB testcases that Sourceware's buildbot runs. This subset runs quickly and has stable results so the job will be a good canary to check that the CI infrastructure is working correctly. -- Thiago ¹https://inbox.sourceware.org/gdb-patches/20220908064151.3959930-1-thiago.b…

2 years, 9 months

1
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[ACTIVITY] Report for week #35

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Cleaned up code for upstream submission, and divided it into patches. A couple of the patches affect other architectures and OSes, so made sure the code builds on as many combinations I can test, and now doing final regression testing on some of them. I'm hoping to finally send the patches upstream early next week. -- Thiago

2 years, 10 months

1
0
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[ACTIVITY] Report for week #34

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished fixing regressions in my changes to gdbserver for debugging an inferior which changes the SVE length. - Started cleaning up code for upstream submission and dividing it into patches. # Community participation - Reviewed mailing list patches: - [PATCH,v3] [aarch64] Fix removal of non-address bits for PAuth - [PATCH 1/2] gdb: Fix deleted thread when issuing next command - [PATCH 2/2] gdb: Improve the resuming of the stepped thread -- Thiago

2 years, 10 months

1
0
0 0

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