== Last week ==
* Finished the patch that I was working on last week to use memory operands
rather than register operands in neon.md. Submitted upstream:
http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01996.html
Among other things, this allows the intrinsics to use post-modified
addresses.
* Submitted patches to make the number of rtl generator arguments
(as opposed to insn operands) available to the expand-time code:
http://gcc.gnu.org/ml/gcc-patches/2011-03/msg02227.htmlhttp://gcc.gnu.org/ml/gcc-patches/2011-03/msg02228.htmlhttp://gcc.gnu.org/ml/gcc-patches/2011-03/msg02229.html
This is part of the tree-rtl expansion "cleanups" that I've been
doing in preparation for the vectoriser work.
* More discussion about the handling of type modes vs. per-function
target switching. I've think we've agreed what the right approach is,
although it's probably outside the scope of this project. The discussion
was still useful because it meant I could submit & defend the next patch.
* Submitted a patch to use non-BLK modes for arrays of vectors
(like uint32x2x2_t & co. in arm_neon.h);
http://gcc.gnu.org/ml/gcc-patches/2011-03/msg02192.html
This avoids that stack spilling that was discussed during the week.
Richard Guenther seemed happy with the patch in principle, but
understandably wanted to see how the optabs stuff worked out first.
Also, the testcase he asked me to try exposed another instance of:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46329
so that needs to be fixed first.
* Started writing & testing a fix for that PR (46329).
== This week ==
* Finish fix for PR46329.
* More vld & vst stuff.
Richard
== Last week ==
* PR48250 / CS Issue #9845 / Launchpad #723185. Unaligned DImode reload
under NEON. Went back and forth with Richard Earnshaw on gcc-patches for
most of the week. The issues should finally be clear, and I think it
would be better to modify the significant parts of
arm_legitimize_reload_address() to do the right thing rather than just
fixing the bug. I have a new patch done over the weekend, though it
still shows a few regressions after some testing. I hope this gets done
by this week...
* PR48325 / Launchpad #744754, another NEON ICE in postreload. This
appears to be the IA/DB modes for VLDM/VSTM for NEON struct modes were
not enabled. This ICE actually does not happen currently on upstream
trunk, but sent patch anyways. Pending review.
* Spent some time on Launchpad #736661 (C++ ICE in expr.c), and looked
at upstream testsuite regressions of gcc.dg/pr17957.c and
gcc.dg/torture/pr47975.c under -mfpu=neon (ICE on OImode const0_rtx
assignment).
* Call with Ramana on ARM optimization work.
== This week ==
* Get PR48250/Launchpad #723185 nailed.
* Other pending GCC issues.
* TW Public Holiday, Mon. and Tue. (Apr.4-5)
The Bazaar team have been working on improving the performance of bzr
on the gcc-linaro tree. Here's how long the steps take on my machine
with the current 2.4 development version:
Update tip before branching:
bzr pull 20.4 s (no revisions)
Make the branch:
bzr branch --hardlink 4.5 optspace 26.8 s
Do some work and commit it:
...change two files
bzr status 1:05
(again) bzr status 1.7 s
bzr commit . 3.6 s
Push the changes up:
bzr push lp:~michaelh1/gcc-linaro/optspace 3:47 ~9 MB (~40 kB/s
which is saturating my uplink)
Later, the merge master pulls the branch down and merges:
bzr branch --no-tree lp:~michaelh1/gcc-linaro/optspace 36 s ~900 k
bzr merge ../optspace 3:26
The bzr status and bzr commit are quite good. I've asked them to look
into bzr merge.
-- Michael
Hi All,
After downloading linaro toolchain by apt-get in ubuntu, I compiled
the uboot for ARM1136 SoC with -march=armv5 option. And it can compile
successfully. Then I let the uboot run on target boards and system
failed due to "undefined instructions". Checked linaro toolchain
options, it is:
#arm-linux-gnueabi-gcc -v
Using built-in specs.
COLLECT_GCC=arm-linux-gnueabi-gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabi/4.5.2/lto-wrapper
Target: arm-linux-gnueabi
Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro
4.5.2-5ubuntu2~ppa1'
--with-bugurl=file:///usr/share/doc/gcc-4.5/README.Bugs
--enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr
--program-suffix=-4.5 --enable-shared --enable-multiarch
--enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib
--without-included-gettext --enable-threads=posix
--with-gxx-include-dir=/usr/arm-linux-gnueabi/include/c++/4.5.2
--libdir=/usr/lib --enable-nls --enable-clocale=gnu
--enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin
--enable-gold --enable-ld=default --with-plugin-ld=ld.gold
--enable-objc-gc --disable-sjlj-exceptions --with-arch=armv7-a
--with-float=softfp --with-fpu=vfpv3-d16 --with-mode=thumb
--disable-werror --enable-checking=release
--program-prefix=arm-linux-gnueabi-
--includedir=/usr/arm-linux-gnueabi/include --build=x86_64-linux-gnu
--host=x86_64-linux-gnu --target=arm-linux-gnueabi
--with-headers=/usr/arm-linux-gnueabi/include
--with-libs=/usr/arm-linux-gnueabi/lib
Thread model: posix
gcc version 4.5.2 (Ubuntu/Linaro 4.5.2-5ubuntu2~ppa1)
The imporant options are "--with-arch=armv7-a --with-float=softfp
--with-fpu=vfpv3-d16". I just want to ask whether these options stop
arm-linux-gnueabi-gcc to support old arch? If so, according to gcc
documents at http://gcc.gnu.org/install/configure.html,
"
--with-cpu=cpu
--with-cpu-32=cpu
--with-cpu-64=cpu
Specify which cpu variant the compiler should generate code for by
default. cpu will be used as the default value of the -mcpu= switch.
This option is only supported on some targets, including ARM, i386,
M68k, PowerPC, and SPARC. The --with-cpu-32 and --with-cpu-64 options
specify separate default CPUs for 32-bit and 64-bit modes; these
options are only supported for i386, x86-64 and PowerPC.
--with-schedule=cpu
--with-arch=cpu
--with-arch-32=cpu
--with-arch-64=cpu
--with-tune=cpu
--with-tune-32=cpu
--with-tune-64=cpu
--with-abi=abi
--with-fpu=type
--with-float=type
These configure options provide default values for the
-mschedule=, -march=, -mtune=, -mabi=, and -mfpu= options and for
-mhard-float or -msoft-float. As with --with-cpu, which switches will
be accepted and acceptable values of the arguments depend on the
target.
"
There are only default values for later compiling. Users should be
able to swith to other values by setting other options. But why did
arm-linux-gnueabi-gcc still build "undefined instructions" to arm1136
with "arch=armv5"? In fact arm1136 is armv6.
Then i compiled a toolchain for linaro gcc-linaro-4.4-2011.02-0 codes
by myself, the options are simple:
#arm-none-linux-gnueabi-gcc -v
Using built-in specs.
Target: arm-none-linux-gnueabi
Configured with: ../gcc-linaro-4.4-2011.02-0/configure
--target=arm-none-linux-gnueabi
--prefix=/home/vmuser/development/toolchain/build-toolchain/tools
--enable-languages=c,c++ --disable-libgomp
Thread model: posix
gcc version 4.4.5 (Linaro GCC 4.4-2011.02-0)
Then I compiled uboot by this toolchain again, the uboot can work.
Then why can the toolchain compiled by myself support more arch? And
what performance is lost in my compiling?
Thanks
Barry
== GCC ==
Progress:
* Investigated excessive VFP moves . Partially investigating ways forward.
* Polished up my divmodsi4 patch. Discussed it during the call.
Looking for ways to do it properly at the tree level.
* Got Panda board on Friday.
* Off on Wednesday.
* Conversations with Revital and Chung-Lin. Need to sync up with
Andrew next week.
* Found an issue with binutils and Neon and this is now LP:747837
Plans:
* Continue looking at excessive VFP moves.
* Finish working through Thumb2 speed tickets.
* Set up new Panda board.
* Conversation with Andrew sometime this week.
Meetings:
* 1-1s
* Linaro toolchain meeting
Absences:
* April 15 – 26 -> Booked Holiday.
* May 9-14 - LDS Budapest
== GDB ==
* Committed patch to fix single-stepping across bad ARM/Thumb boundary
(bug #667309) to mainline and Linaro GDB.
* Committed patch to fix accessing "fpscr" register to mainline.
* Ongoing work to fix single-stepping over signal handlers (bug #615978).
Posted yet another updated patch to gdb-patches for comments.
* Implemented patch to support NEON registers in core files (bug #615972).
* Investigated failure to disable address space randomization
(bug #616001).
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi,
== pandaboard ==
* noticed that hw perf events are not working on 2.6.38-1001-linaro-omap
* it seems that the omap kernel has not configured its PMU properly
* perf_event_open syscall returns ENODEV
* started discussion with agreen (#744458)
* noticed that natty puts its glibc into a multilib path
* prevents linaro gcc (and upstream) from being built
== libunwind ==
* created a generic and local variant of the extbl parser
* ran the test suite a few times using different unwind methods
* started to look into the test suite failures
* started to fix a couple of the failures on ARM
Regards
Ken
RAG:
Red:
Amber:
Green: the aircon has been fixed; blessed quiet again
Current Milestones:
| Planned | Estimate | Actual |
qemu-linaro 2011-04 | 2011-04-21 | 2011-04-21 | |
Historical Milestones:
finish qemu-cont-integration | 2011-01-25 | 2011-01-25 | handed off |
first qemu-linaro release | 2011-02-08 | 2011-02-08 | 2011-02-08 |
qemu-linaro 2011-03 | 2011-03-08 | 2011-03-08 | 2011-03-08 |
== maintain-beagle-models ==
* the board-ram-limits patchset has been expanded significantly to
address upstream suggestions; it now includes a lot of refactoring
of sun4m (sparc) board code to use the new generic max-ram
functionality instead of a sun4m-specific bit of code. Unfortunately
there is still some pushback upstream on the grounds that a simple
max-ram limit doesn't cater for complicated NUMA situations :-(
== merge-correctness-fixes ==
* working on moving implementation of VLD/VST "multiple structures" forms
into qemu helper functions; the current implementation is correct but
can expand to hundreds of TCG ops which is well beyond the maximum
permitted value, so could potentially overrun a TCG buffer
== other ==
* wrote up some technical/engineering input into what we ought to be
doing with qemu next cycle
* review of a patch by Dmitry Eremin-Solenikov adding ARMv4/v4T support
* some review of s390 TCG patches (not because we have a direct interest
in s390 but as part of being a good citizen upstream)
* sent a pull request for some neon patches that had been on the list
a few weeks; hopefully this will help drain the patch pipeline
* meetings: toolchain, standup, pdsw-tools
Current qemu patch status is tracked here:
https://wiki.linaro.org/PeterMaydell/QemuPatchStatus
Absences:
Holiday: 22 Apr - 2 May
9-13 May: UDS, Budapest
(maybe) ~17-19 August: QEMU/KVM strand at LinuxCon NA, Vancouver
Hello,
* Submitted merge requests for SMS patch to gcc-linaro and gcc-linaro/4.6.
* Testing SMS patch which extends the current implementation to
consider loops that contain
instructions with REG_INC_NOTE.
* Filed PRs 48336 48380 for recent fails of trunk on ARM.
* Had a chat with Ramana about the DENbench benchmarks, directions and findings.
* Filed PR 745743 in linaro gcc-bugzilla
Thanks,
Revital
Hi,
* continued bringing patches upstream
- auto-detection of vector size - committed
- changing default vector size to 128 - submitted and testing the
final version
- if-conversion improvement - submitted and now testing the final version
* gcc-linaro-4.6
- submitted a merge request for store sink patch (this patch is
already upstream)
Ira
For reference. We know that the NEON intrinsics in GCC have issues.
I came across this page:
http://hilbert-space.de/?p=22
which has a colour to greyscale conversion done using intrinsics.
gcc-linaro-4.5-2011.03-0 does poorly through saving intermediate
values on the stack. The core of the loop is:
.L3:
mov ip, r4
vld3.8 {d16-d18}, [r6]
vstmia r4, {d16-d18}
ldmia ip!, {r0, r1, r2, r3}
mov sl, r9
adds r7, r7, #1
adds r6, r6, #24
stmia sl!, {r0, r1, r2, r3}
fldd d16, [sp, #24]
fldd d18, [sp, #32]
ldmia ip, {r0, r1}
vmull.u8 q8, d16, d19
stmia sl, {r0, r1}
vmlal.u8 q8, d18, d20
fldd d18, [sp, #40]
vmlal.u8 q8, d18, d21
vshrn.i16 d16, q8, #8
vst1.8 {d16}, [r5]
adds r5, r5, #8
cmp r8, r7
bgt .L3
llvm-2.9~svn128540 does much better:
vld3.8 {d20, d21, d22}, [r1]!
add r3, r3, #1
cmp r3, r2
vmull.u8 q12, d21, d16
vmlal.u8 q12, d20, d17
vmlal.u8 q12, d22, d18
vshrn.i16 d19, q12, #8
vst1.8 {d19}, [r0]!
blt .LBB0_1
and may actually be better than the had-written assembler on Nils's
page due to scheduling the loop comparison earlier.
Richard S, were you looking into this?
-- Michael
Hi there. A reminder that today's call has shifted due to the
European daylight savings change. It's now at 0800 UTC which is 9 am
in the UK, 10 am in central Europe, and 10 am in Israel.
-- Michael
== Last week ==
* PR46934: Thumb-1 ICE, small fix in the "casesi" jump-table expand
code. Quickly approved and committed upstream.
* Enhance XOR patch for gcc/simplify-rtx.c. Updated comments and
committed upstream.
* PR48250 / CS Issue #9845 / Launchpad #723185. Unaligned DImode reload
under NEON. Submitted patch upstream, but still need to do some more
verification that older pre-ARMv5TE cases are safe. Should complete this
week.
* Working on a type of ICE seen currently on upstream trunk, a few
testcases failing under '-O3 -g'. It seems VTA related, but also might
have something to do with register elimination not fully done for
(var_location (entry_value ...)) expressions, leaving [afp+#num] memory
addresses existing in debug insns after reload. Still investigating.
* Launchpad #689887, ICE in get_arm_condition_code(). Pushed a merge
request to Linaro 4.5 for this patch. Also another LP#742961 appeared as
another case of this ICE...
* Still working on (what I think should be) the last of the CoreMark
ARMv6 regressions. The problem is to combine uxtb+cmp into ands #255.
This could be done by adding (set (cc) (compare (zero_extend...)))
patterns, implemented by ands assembly, but still looking if this can be
done (probably more elegantly) by something like CANONICALIZE_COMPARISON
(replacing compare operands) in the ARM backend.
* Launchpad #736007, ICE immed_double_const under -mfpu=neon -g. Some
discussion on gcc-patches about this, still unclear on what should be
done...
== This week ==
* Push forward on above issues.
Committed Dan's RVCT interoperation patch, both upstream and to Linaro
GCC 4.6.
Adjusted Benrd's "Discourage NEON on Cortex-A8" patch following Richard
Earnshaw's comments, and reposted upstream. The new version was
approved, and committed. I've also submitted a merge proposal to Linaro
GCC 4.6.
Dropped Tom's patch for marking smalls strings read-only. This
optimization seems to have no visible effect for ARM in GCC 4.6. I'll
leave it it to Tom to forward-port, if it's still meaningful for MIPS.
Julian has committed the patch for lp:675347, so I've submitted merge
requests to both Linaro GCC 4.5 and 4.6.
Bernd has posted the shrink wrapping patches upstream. I've posted this
info in all the relevant Linaro tracking tickets.
Talked Revital Eres through the Bazaar/Launchpad merge request system.
Tried to understand why GCC 4.6 does not use multiply-and-accumulate
efficiently, when used with 64-bit values. It seems that the compiler
sometimes uses (subreg:SI (reg:DI ...)) and sometimes just uses a plain
(reg:SI ..) and those don't combine to give useful patterns, but I
haven't got to the bottom of it yet.
Tested an FSF GCC 4.6 snapshot from the 23rd. All well, so I've merged
it to the Linaro GCC 4.6 branch.
* Future Absence
Away Monday 28th to Friday 1st April.
----
Upstream patched requiring review:
* Thumb2 constants:
http://gcc.gnu.org/ml/gcc-patches/2010-12/msg00652.html
* ARM EABI half-precision functions
http://gcc.gnu.org/ml/gcc-patches/2011-02/msg00874.html
* ARM Thumb2 Spill Likely tweak
http://gcc.gnu.org/ml/gcc-patches/2011-02/msg00880.html
* NEON scheduling patch
http://gcc.gnu.org/ml/gcc-patches/2011-02/msg01431.html
Hi,
== libunwind ==
* modified the extbtl-parser to operate on the DWARF model directly
* this adds support for unwinding call stacks with mixed (DWARF and extbl)
frames on ARM
* did a few other fixes and cleanups
* posted the patches on the libunwind ml
* set up a tree on git.linaro.org
* attended a class on friday
Regards
Ken
== GDB ==
* Completed glibc patch to add ARM unwind tables to system call stubs
(bug #684218), patch committed upstream and backported to Ubuntu glibc.
* Posted kernel patch to fixes GDB inferior calls while stopped in a
restartable system call (bug #615974); waiting for review.
* Ongoing work to fix single-stepping over signal handlers (bug #615978).
* Implemented patch to fix single-stepping across bad ARM/Thumb boundary
(bug #667309); posted to mailing list for comments.
* Contributed two fixes for valgrind on ARM (to enable running GDB under
valgrind); both now accepted mainline.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
== This week ==
* Moved the discussion about the RTL and gimple representation of
strided loads/stores to the gcc@ list. Got some good feedback:
http://gcc.gnu.org/ml/gcc/2011-03/msg00322.html
* Started a subdiscussion about the handling of modes:
http://gcc.gnu.org/ml/gcc/2011-03/msg00342.html
This is a tricky one. I'll add more fuel to the fire next week.
* Committed two GCC patches to clean up the expand interface.
Dealt with the fallout (some expected, but unfortunately some not).
* Submitted two of the patches to improve code generation for
strided load/store intrinsics:
http://gcc.gnu.org/ml/gcc-patches/2011-03/msg01631.htmlhttp://gcc.gnu.org/ml/gcc-patches/2011-03/msg01634.html
* Spent a lot of the week reworking the way the load/store intrinsics
are handled, to fix both correctness and performance bugs. The new
rtl patterns should have the right form for the vectoriser.
Made what feels like good progress, but it's not complete yet.
* Sent separate R_ARM_IRELATIVE patch to glibc, after feedback from
glibc-ports.
* Booked flight and hotel for Budapest summit.
* Pinged unreviewed patches.
== Next week ==
* More intrinsics improvements. I think these are necessary to get good
code out of the vectoriser too.
Richard
== String routines ==
* Wrote a thumb optimised strchr
- As expected it's got nice performance for longer runs but at
sizes <16 bytes it's slower, and a lot of the strchr
calls are very short, so it's probably not of benefit in most cases
( https://wiki.linaro.org/WorkingGroups/ToolChain/Benchmarks/InitialStrchr?ac…
)
* Wrote a neon-memcpy
- As previously found with memset, it performs well on A8 but
poorly on A9 - it does however do the case where
the source/destination isn't aligned quite well even on A9 ; the vld1
unaligned case works with relatively little penalty.
(it performs comparably to the Bionic implementation - mine is a
bit faster on shorter calls, Bionic is better
on longer uses - I think that's because they've got some careful use
of preloads where I have so far got none).
I'm on holiday up to and including 5th April.
Dave
== GCC ==
Progress:
* Investigated excessive VFP moves . Investigating ways forward.
* Went through some of the test results with 4.6 RC2 upstream - looking
through test results etc.
* Setup SPEC2k6 cross on my Linaro machine.
* Waiting for my new Panda board sometime next week.
* Some small bug fixes upstream. Need to rework a couple of
documentation patches after review.
Plans:
* Continue looking at excessive VFP moves.
* Continue to look at some patches upstream.
* Finish working through Thumb2 speed tickets.
* Set up new Panda board.
* Start looking at DENBench results and identify
potential speed up areas.
Meetings:
* 1-1s
* Linaro toolchain meeting
Absences:
* March 30th (maybe): WC Cricket Semi-final. (Ind v Pak)
* April 15 – 26 -> Booked Holiday.
* May 9-14 - LDS Budapest
RAG:
Red:
Amber:
Green:
Current Milestones:
| Planned | Estimate | Actual |
qemu-linaro 2011-04 | 2011-04-21 | 2011-04-21 | |
Historical Milestones:
finish qemu-cont-integration | 2011-01-25 | 2011-01-25 | handed off |
first qemu-linaro release | 2011-02-08 | 2011-02-08 | 2011-02-08 |
qemu-linaro 2011-03 | 2011-03-08 | 2011-03-08 | 2011-03-08 |
== maintain-beagle-models ==
* benchmarking/testing of the TCG locking fix: oddly benchmarks
seem to come out with less slowdown (1% or less) than a system
mode bootup/shutdown. (I used scimark and dhrystone. scimark
is the same speed, which is to be expected because we spend all
our time doing floating point emulation. I was expecting a bigger
perf hit on dhrystone, though.)
* submitted patches to make qemu fail cleanly if you ask for more RAM
than a board supports
== merge-correctness-fixes ==
* tested the Neon element load/store instructions; wrote patches to
fix UNDEF handling (which are blocked waiting for the patch pipeline
to be drained) and confirmed there aren't any other bugs.
There is a meego patch to use helper functions for multi-element
load/store which is apparently to avoid overflowing a TCG buffer:
need to test and upstream this.
* investigated android qemu tree for any missing correctness fixes:
looking through the changelog I think we have fixes upstream for
everything that was fixed in the android tree.
== other ==
* patch: fix versatilepb/realview handling of multiple nic options
* patch: better diagnosis of more nics requested than board supports
[this is needed to get the vexpress patch committed]
* reviewed a patch to add ARMv4/v4T support to qemu
(mostly consists of making sure we UNDEF in the right places)
* meetings: toolchain, standup, pdsw-tools, 1-2-1
Current qemu patch status is tracked here:
https://wiki.linaro.org/PeterMaydell/QemuPatchStatus
Absences:
Holiday: 22 Apr - 2 May
9-13 May: UDS, Budapest
(maybe) ~17-19 August: QEMU/KVM strand at LinuxCon NA, Vancouver
Hello,
Implemented a patch to apply SMS in the presence of instructions with
REG_INC_NOTE. (this occurs in telecom/autocor thus SMS needs to be run
with -fno-auto-inc-dec
flag to be applied)
Sent a merge request to gcc-linaro for the SMS patches.
Thanks to Andrew Stubbs for his help.
https://code.launchpad.net/~eres/gcc-linaro/SMS_doloop_for_ARM
I intend to send a request to gcc-linaro.4.6 as well.
Thanks,
Revital
Hi,
* resubmitted and committed store sink patch to trunk, I'll commit it
to gcc-linaro-4.6 next week
* submitted autodetection of vector size patch to gcc-patches, I'l
commit it next week
* started testing a patch that makes mvectorize-with-neon-quad the default
* DenBench: found some more cases where vectorization of strided
accesses using vzip/vuzp causes degradation. Since Richard is making a
lot of progress with vlsd/vst, I think it doesn't make sense to spend
too much time on vzip/vuzp, and I am going to run DenBench without
this patch.
Ira
Philipp Kern <trash(a)philkern.de> writes:
> On 2011-03-23, Goswin von Brederlow <goswin-v-b(a)web.de> wrote:
>> Also does the testing transition consider the Built-Using? If I specify
>> 'Built-Using: gcc-4.5 (= 4.5.2-5)' will the package be blocked from
>> entering testing until gcc-4.5 (= 4.5.2-5) has entered and block gcc-4.5
>> (= 4.5.2-5) from being replaced from testing?
>
> It doesn't need to. All we want is compliance on the archive side so that the
> sources are not expired away, as long as that binary is carried in a suite.
> No need to involve britney at that point.
>
> Kind regards
> Philipp Kern
Not quite. For ia32-libs it would be nice if ia32-libs could be blocked
from testing as long as the source packages it includes aren't in
testing. Currently that is solved by building against testing in the
first palce. But that is something we can live with.
As a side note the debian-cd package needs to also consider Built-Using
when creating source images. Will the Sources.gz file list multiple
entries for a source if multiple versions are relevant?
MfG
Goswin
