[TCWG CI] Regression caused by gcc: tree-optimization/102570 - teach VN about internal functions
by ci_notify＠linaro.org
[TCWG CI] Regression caused by gcc: tree-optimization/102570 - teach VN about internal functions:
commit 55a3be2f5255d69e740d61b2c5aaba1ccbc643b8
Author: Richard Biener <rguenther(a)suse.de>
tree-optimization/102570 - teach VN about internal functions
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
18360
# First few build errors in logs:
# 00:01:21 ./include/linux/arm-smccc.h:460:40: error: ‘res.a0’ is used uninitialized [-Werror=uninitialized]
# 00:01:21 ./include/linux/arm-smccc.h:460:40: error: ‘res.a0’ is used uninitialized [-Werror=uninitialized]
# 00:01:21 ./include/linux/arm-smccc.h:460:40: error: ‘res.a0’ is used uninitialized [-Werror=uninitialized]
# 00:01:21 make[2]: *** [scripts/Makefile.build:288: arch/arm64/hyperv/hv_core.o] Error 1
# 00:01:22 crypto/asymmetric_keys/asymmetric_type.c:481:15: error: ‘restrict_method’ is used uninitialized [-Werror=uninitialized]
# 00:01:22 make[2]: *** [scripts/Makefile.build:288: crypto/asymmetric_keys/asymmetric_type.o] Error 1
# 00:01:22 ./include/trace/perf.h:38:25: error: ‘entry’ is used uninitialized [-Werror=uninitialized]
# 00:01:22 ./include/trace/perf.h:44:13: error: ‘__entry_size’ is used uninitialized [-Werror=uninitialized]
# 00:01:23 security/keys/encrypted-keys/encrypted.c:660:19: error: ‘mkey’ is used uninitialized [-Werror=uninitialized]
# 00:01:23 security/keys/encrypted-keys/encrypted.c:905:19: error: ‘epayload’ is used uninitialized [-Werror=uninitialized]
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
21404
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_kernel/gnu-master-aarch64-next-allmodconfig
First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Reproduce builds:
<cut>
mkdir investigate-gcc-55a3be2f5255d69e740d61b2c5aaba1ccbc643b8
cd investigate-gcc-55a3be2f5255d69e740d61b2c5aaba1ccbc643b8
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach 55a3be2f5255d69e740d61b2c5aaba1ccbc643b8
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 22d34a2a50651d01669b6fbcdb9677c18d2197c5
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 55a3be2f5255d69e740d61b2c5aaba1ccbc643b8
Author: Richard Biener <rguenther(a)suse.de>
Date: Mon Oct 4 10:57:45 2021 +0200
tree-optimization/102570 - teach VN about internal functions
We're now using internal functions for a lot of stuff but there's
still missing VN support out of laziness. The following instantiates
support and adds testcases for FRE and PRE (hoisting).
2021-10-04 Richard Biener <rguenther(a)suse.de>
PR tree-optimization/102570
* tree-ssa-sccvn.h (vn_reference_op_struct): Document
we are using clique for the internal function code.
* tree-ssa-sccvn.c (vn_reference_op_eq): Compare the
internal function code.
(print_vn_reference_ops): Print the internal function code.
(vn_reference_op_compute_hash): Hash it.
(copy_reference_ops_from_call): Record it.
(visit_stmt): Remove the restriction around internal function
calls.
(fully_constant_vn_reference_p): Use fold_const_call and handle
internal functions.
(vn_reference_eq): Compare call return types.
* tree-ssa-pre.c (create_expression_by_pieces): Handle
generating calls to internal functions.
(compute_avail): Remove the restriction around internal function
calls.
* gcc.dg/tree-ssa/ssa-fre-96.c: New testcase.
* gcc.dg/tree-ssa/ssa-pre-33.c: Likewise.
---
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-96.c | 14 +++++
gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-33.c | 15 +++++
gcc/tree-ssa-pre.c | 27 +++++----
gcc/tree-ssa-sccvn.c | 91 ++++++++++++++++++------------
gcc/tree-ssa-sccvn.h | 3 +-
5 files changed, 103 insertions(+), 47 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-96.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-96.c
new file mode 100644
index 00000000000..fd1d5713b5f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-96.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-tree-fre1" } */
+
+_Bool f1(unsigned x, unsigned y, unsigned *res)
+{
+ _Bool t = __builtin_add_overflow(x, y, res);
+ unsigned res1;
+ _Bool t1 = __builtin_add_overflow(x, y, &res1);
+ *res -= res1;
+ return t==t1;
+}
+
+/* { dg-final { scan-tree-dump-times "ADD_OVERFLOW" 1 "fre1" } } */
+/* { dg-final { scan-tree-dump "return 1;" "fre1" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-33.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-33.c
new file mode 100644
index 00000000000..3b3bd629bc2
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-pre-33.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-pre" } */
+
+_Bool f1(unsigned x, unsigned y, unsigned *res, int flag, _Bool *t)
+{
+ if (flag)
+ *t = __builtin_add_overflow(x, y, res);
+ unsigned res1;
+ _Bool t1 = __builtin_add_overflow(x, y, &res1);
+ *res -= res1;
+ return *t==t1;
+}
+
+/* We should hoist the .ADD_OVERFLOW to before the check. */
+/* { dg-final { scan-tree-dump-times "ADD_OVERFLOW" 1 "pre" } } */
diff --git a/gcc/tree-ssa-pre.c b/gcc/tree-ssa-pre.c
index 08755847f66..1cc1aae694f 100644
--- a/gcc/tree-ssa-pre.c
+++ b/gcc/tree-ssa-pre.c
@@ -2855,9 +2855,13 @@ create_expression_by_pieces (basic_block block, pre_expr expr,
unsigned int operand = 1;
vn_reference_op_t currop = &ref->operands[0];
tree sc = NULL_TREE;
- tree fn = find_or_generate_expression (block, currop->op0, stmts);
- if (!fn)
- return NULL_TREE;
+ tree fn = NULL_TREE;
+ if (currop->op0)
+ {
+ fn = find_or_generate_expression (block, currop->op0, stmts);
+ if (!fn)
+ return NULL_TREE;
+ }
if (currop->op1)
{
sc = find_or_generate_expression (block, currop->op1, stmts);
@@ -2873,12 +2877,19 @@ create_expression_by_pieces (basic_block block, pre_expr expr,
return NULL_TREE;
args.quick_push (arg);
}
- gcall *call = gimple_build_call_vec (fn, args);
+ gcall *call;
+ if (currop->op0)
+ {
+ call = gimple_build_call_vec (fn, args);
+ gimple_call_set_fntype (call, currop->type);
+ }
+ else
+ call = gimple_build_call_internal_vec ((internal_fn)currop->clique,
+ args);
gimple_set_location (call, expr->loc);
- gimple_call_set_fntype (call, currop->type);
if (sc)
gimple_call_set_chain (call, sc);
- tree forcedname = make_ssa_name (TREE_TYPE (currop->type));
+ tree forcedname = make_ssa_name (ref->type);
gimple_call_set_lhs (call, forcedname);
/* There's no CCP pass after PRE which would re-compute alignment
information so make sure we re-materialize this here. */
@@ -4004,10 +4015,6 @@ compute_avail (function *fun)
vn_reference_s ref1;
pre_expr result = NULL;
- /* We can value number only calls to real functions. */
- if (gimple_call_internal_p (stmt))
- continue;
-
vn_reference_lookup_call (as_a <gcall *> (stmt), &ref, &ref1);
/* There is no point to PRE a call without a value. */
if (!ref || !ref->result)
diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c
index 416a5252144..0d942218279 100644
--- a/gcc/tree-ssa-sccvn.c
+++ b/gcc/tree-ssa-sccvn.c
@@ -70,6 +70,7 @@ along with GCC; see the file COPYING3. If not see
#include "tree-scalar-evolution.h"
#include "tree-ssa-loop-niter.h"
#include "builtins.h"
+#include "fold-const-call.h"
#include "tree-ssa-sccvn.h"
/* This algorithm is based on the SCC algorithm presented by Keith
@@ -212,7 +213,8 @@ vn_reference_op_eq (const void *p1, const void *p2)
TYPE_MAIN_VARIANT (vro2->type))))
&& expressions_equal_p (vro1->op0, vro2->op0)
&& expressions_equal_p (vro1->op1, vro2->op1)
- && expressions_equal_p (vro1->op2, vro2->op2));
+ && expressions_equal_p (vro1->op2, vro2->op2)
+ && (vro1->opcode != CALL_EXPR || vro1->clique == vro2->clique));
}
/* Free a reference operation structure VP. */
@@ -264,15 +266,18 @@ print_vn_reference_ops (FILE *outfile, const vec<vn_reference_op_s> ops)
&& TREE_CODE_CLASS (vro->opcode) != tcc_declaration)
{
fprintf (outfile, "%s", get_tree_code_name (vro->opcode));
- if (vro->op0)
+ if (vro->op0 || vro->opcode == CALL_EXPR)
{
fprintf (outfile, "<");
closebrace = true;
}
}
- if (vro->op0)
+ if (vro->op0 || vro->opcode == CALL_EXPR)
{
- print_generic_expr (outfile, vro->op0);
+ if (!vro->op0)
+ fprintf (outfile, internal_fn_name ((internal_fn)vro->clique));
+ else
+ print_generic_expr (outfile, vro->op0);
if (vro->op1)
{
fprintf (outfile, ",");
@@ -684,6 +689,8 @@ static void
vn_reference_op_compute_hash (const vn_reference_op_t vro1, inchash::hash &hstate)
{
hstate.add_int (vro1->opcode);
+ if (vro1->opcode == CALL_EXPR && !vro1->op0)
+ hstate.add_int (vro1->clique);
if (vro1->op0)
inchash::add_expr (vro1->op0, hstate);
if (vro1->op1)
@@ -769,11 +776,16 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2)
if (vr1->type != vr2->type)
return false;
}
+ else if (vr1->type == vr2->type)
+ ;
else if (COMPLETE_TYPE_P (vr1->type) != COMPLETE_TYPE_P (vr2->type)
|| (COMPLETE_TYPE_P (vr1->type)
&& !expressions_equal_p (TYPE_SIZE (vr1->type),
TYPE_SIZE (vr2->type))))
return false;
+ else if (vr1->operands[0].opcode == CALL_EXPR
+ && !types_compatible_p (vr1->type, vr2->type))
+ return false;
else if (INTEGRAL_TYPE_P (vr1->type)
&& INTEGRAL_TYPE_P (vr2->type))
{
@@ -1270,6 +1282,8 @@ copy_reference_ops_from_call (gcall *call,
temp.type = gimple_call_fntype (call);
temp.opcode = CALL_EXPR;
temp.op0 = gimple_call_fn (call);
+ if (gimple_call_internal_p (call))
+ temp.clique = gimple_call_internal_fn (call);
temp.op1 = gimple_call_chain (call);
if (stmt_could_throw_p (cfun, call) && (lr = lookup_stmt_eh_lp (call)) > 0)
temp.op2 = size_int (lr);
@@ -1459,9 +1473,11 @@ fully_constant_vn_reference_p (vn_reference_t ref)
a call to a builtin function with at most two arguments. */
op = &operands[0];
if (op->opcode == CALL_EXPR
- && TREE_CODE (op->op0) == ADDR_EXPR
- && TREE_CODE (TREE_OPERAND (op->op0, 0)) == FUNCTION_DECL
- && fndecl_built_in_p (TREE_OPERAND (op->op0, 0))
+ && (!op->op0
+ || (TREE_CODE (op->op0) == ADDR_EXPR
+ && TREE_CODE (TREE_OPERAND (op->op0, 0)) == FUNCTION_DECL
+ && fndecl_built_in_p (TREE_OPERAND (op->op0, 0),
+ BUILT_IN_NORMAL)))
&& operands.length () >= 2
&& operands.length () <= 3)
{
@@ -1481,13 +1497,17 @@ fully_constant_vn_reference_p (vn_reference_t ref)
anyconst = true;
if (anyconst)
{
- tree folded = build_call_expr (TREE_OPERAND (op->op0, 0),
- arg1 ? 2 : 1,
- arg0->op0,
- arg1 ? arg1->op0 : NULL);
- if (folded
- && TREE_CODE (folded) == NOP_EXPR)
- folded = TREE_OPERAND (folded, 0);
+ combined_fn fn;
+ if (op->op0)
+ fn = as_combined_fn (DECL_FUNCTION_CODE
+ (TREE_OPERAND (op->op0, 0)));
+ else
+ fn = as_combined_fn ((internal_fn) op->clique);
+ tree folded;
+ if (arg1)
+ folded = fold_const_call (fn, ref->type, arg0->op0, arg1->op0);
+ else
+ folded = fold_const_call (fn, ref->type, arg0->op0);
if (folded
&& is_gimple_min_invariant (folded))
return folded;
@@ -5648,28 +5668,27 @@ visit_stmt (gimple *stmt, bool backedges_varying_p = false)
&& TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL)
extra_fnflags = flags_from_decl_or_type (TREE_OPERAND (fn, 0));
}
- if (!gimple_call_internal_p (call_stmt)
- && (/* Calls to the same function with the same vuse
- and the same operands do not necessarily return the same
- value, unless they're pure or const. */
- ((gimple_call_flags (call_stmt) | extra_fnflags)
- & (ECF_PURE | ECF_CONST))
- /* If calls have a vdef, subsequent calls won't have
- the same incoming vuse. So, if 2 calls with vdef have the
- same vuse, we know they're not subsequent.
- We can value number 2 calls to the same function with the
- same vuse and the same operands which are not subsequent
- the same, because there is no code in the program that can
- compare the 2 values... */
- || (gimple_vdef (call_stmt)
- /* ... unless the call returns a pointer which does
- not alias with anything else. In which case the
- information that the values are distinct are encoded
- in the IL. */
- && !(gimple_call_return_flags (call_stmt) & ERF_NOALIAS)
- /* Only perform the following when being called from PRE
- which embeds tail merging. */
- && default_vn_walk_kind == VN_WALK)))
+ if (/* Calls to the same function with the same vuse
+ and the same operands do not necessarily return the same
+ value, unless they're pure or const. */
+ ((gimple_call_flags (call_stmt) | extra_fnflags)
+ & (ECF_PURE | ECF_CONST))
+ /* If calls have a vdef, subsequent calls won't have
+ the same incoming vuse. So, if 2 calls with vdef have the
+ same vuse, we know they're not subsequent.
+ We can value number 2 calls to the same function with the
+ same vuse and the same operands which are not subsequent
+ the same, because there is no code in the program that can
+ compare the 2 values... */
+ || (gimple_vdef (call_stmt)
+ /* ... unless the call returns a pointer which does
+ not alias with anything else. In which case the
+ information that the values are distinct are encoded
+ in the IL. */
+ && !(gimple_call_return_flags (call_stmt) & ERF_NOALIAS)
+ /* Only perform the following when being called from PRE
+ which embeds tail merging. */
+ && default_vn_walk_kind == VN_WALK))
changed = visit_reference_op_call (lhs, call_stmt);
else
changed = defs_to_varying (call_stmt);
diff --git a/gcc/tree-ssa-sccvn.h b/gcc/tree-ssa-sccvn.h
index 96100596d2e..8a1b649c726 100644
--- a/gcc/tree-ssa-sccvn.h
+++ b/gcc/tree-ssa-sccvn.h
@@ -106,7 +106,8 @@ typedef const struct vn_phi_s *const_vn_phi_t;
typedef struct vn_reference_op_struct
{
ENUM_BITFIELD(tree_code) opcode : 16;
- /* Dependence info, used for [TARGET_]MEM_REF only. */
+ /* Dependence info, used for [TARGET_]MEM_REF only. For internal
+ function calls clique is also used for the internal function code. */
unsigned short clique;
unsigned short base;
unsigned reverse : 1;
</cut>
4 years
- 1
- 0
[TCWG CI] 464.h264ref slowed down by 6% after llvm: [SCEV] Infer flags from add/gep in any block
by ci_notify＠linaro.org
After llvm commit 0658bab870c89d81678f1f37aac0396ddd0913b3
Author: Philip Reames <listmail(a)philipreames.com>
[SCEV] Infer flags from add/gep in any block
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 6% from 11124 to 11783 perf samples
- 464.h264ref:[.] FastFullPelBlockMotionSearch slowed down by 41% from 1504 to 2116 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O2
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-0658bab870c89d81678f1f37aac0396ddd0913b3
cd investigate-llvm-0658bab870c89d81678f1f37aac0396ddd0913b3
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 0658bab870c89d81678f1f37aac0396ddd0913b3
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 2ced9a42be8aba4533225fdb8ed02fe6f50060b6
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 0658bab870c89d81678f1f37aac0396ddd0913b3
Author: Philip Reames <listmail(a)philipreames.com>
Date: Wed Oct 6 10:35:01 2021 -0700
[SCEV] Infer flags from add/gep in any block
This patch removes a compile time restriction from isSCEVExprNeverPoison. We've strengthened our ability to reason about flags on scopes other than addrecs, and this bailout prevents us from using it. The comment is also suspect as well in that we're in the middle of constructing a SCEV for I. As such, we're going to visit all operands *anyways*.
Differential Revision: https://reviews.llvm.org/D111186
---
llvm/lib/Analysis/ScalarEvolution.cpp | 10 ---------
.../Analysis/DependenceAnalysis/Preliminary.ll | 2 +-
.../Analysis/ScalarEvolution/flags-from-poison.ll | 8 +++----
.../SLPVectorizer/X86/consecutive-access.ll | 25 +++++++++-------------
4 files changed, 15 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 6683b1a5205c..4fb2266b6e89 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -6645,16 +6645,6 @@ bool ScalarEvolution::isGuaranteedToTransferExecutionTo(const Instruction *A,
bool ScalarEvolution::isSCEVExprNeverPoison(const Instruction *I) {
- // Here we check that I is in the header of the innermost loop containing I,
- // since we only deal with instructions in the loop header. The actual loop we
- // need to check later will come from an add recurrence, but getting that
- // requires computing the SCEV of the operands, which can be expensive. This
- // check we can do cheaply to rule out some cases early.
- Loop *InnermostContainingLoop = LI.getLoopFor(I->getParent());
- if (InnermostContainingLoop == nullptr ||
- InnermostContainingLoop->getHeader() != I->getParent())
- return false;
-
// Only proceed if we can prove that I does not yield poison.
if (!programUndefinedIfPoison(I))
return false;
diff --git a/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll b/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
index 0899f67d6914..91827f3231ba 100644
--- a/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
@@ -623,7 +623,7 @@ entry:
; CHECK-LABEL: p9
; CHECK: da analyze - none!
-; CHECK: da analyze - flow [|<]!
+; CHECK: da analyze - none!
; CHECK: da analyze - confused!
; CHECK: da analyze - none!
; CHECK: da analyze - confused!
diff --git a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
index f0bda26edb38..0423854bbc3b 100644
--- a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
+++ b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
@@ -1628,9 +1628,9 @@ define noundef i32 @add-basic(i32 %a, i32 %b) {
; CHECK-LABEL: 'add-basic'
; CHECK-NEXT: Classifying expressions for: @add-basic
; CHECK-NEXT: %res = add nuw nsw i32 %a, %b
-; CHECK-NEXT: --> (%a + %b) U: full-set S: full-set
+; CHECK-NEXT: --> (%a + %b)<nuw><nsw> U: full-set S: full-set
; CHECK-NEXT: %res2 = udiv i32 255, %res
-; CHECK-NEXT: --> (255 /u (%a + %b)) U: [0,256) S: [0,256)
+; CHECK-NEXT: --> (255 /u (%a + %b)<nuw><nsw>) U: [0,256) S: [0,256)
; CHECK-NEXT: Determining loop execution counts for: @add-basic
;
%res = add nuw nsw i32 %a, %b
@@ -1656,9 +1656,9 @@ define noundef i32 @mul-basic(i32 %a, i32 %b) {
; CHECK-LABEL: 'mul-basic'
; CHECK-NEXT: Classifying expressions for: @mul-basic
; CHECK-NEXT: %res = mul nuw nsw i32 %a, %b
-; CHECK-NEXT: --> (%a * %b) U: full-set S: full-set
+; CHECK-NEXT: --> (%a * %b)<nuw><nsw> U: full-set S: full-set
; CHECK-NEXT: %res2 = udiv i32 255, %res
-; CHECK-NEXT: --> (255 /u (%a * %b)) U: [0,256) S: [0,256)
+; CHECK-NEXT: --> (255 /u (%a * %b)<nuw><nsw>) U: [0,256) S: [0,256)
; CHECK-NEXT: Determining loop execution counts for: @mul-basic
;
%res = mul nuw nsw i32 %a, %b
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll b/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
index e4000b52c4a9..8f57fe6866bd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
@@ -8,10 +8,6 @@ target triple = "x86_64-apple-macosx10.9.0"
@C = common global [2000 x float] zeroinitializer, align 16
@D = common global [2000 x float] zeroinitializer, align 16
-; Currently SCEV isn't smart enough to figure out that accesses
-; A[3*i], A[3*i+1] and A[3*i+2] are consecutive, but in future
-; that would hopefully be fixed. For now, check that this isn't
-; vectorized.
; Function Attrs: nounwind ssp uwtable
define void @foo_3double(i32 %u) #0 {
; CHECK-LABEL: @foo_3double(
@@ -21,26 +17,25 @@ define void @foo_3double(i32 %u) #0 {
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[U]], 3
; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[MUL]] to i64
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 [[IDXPROM]]
-; CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[ARRAYIDX]], align 8
; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 [[IDXPROM]]
-; CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[ARRAYIDX4]], align 8
-; CHECK-NEXT: [[ADD5:%.*]] = fadd double [[TMP0]], [[TMP1]]
-; CHECK-NEXT: store double [[ADD5]], double* [[ARRAYIDX]], align 8
; CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[MUL]], 1
; CHECK-NEXT: [[IDXPROM12:%.*]] = sext i32 [[ADD11]] to i64
; CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 [[IDXPROM12]]
-; CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[ARRAYIDX13]], align 8
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast double* [[ARRAYIDX]] to <2 x double>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]], align 8
; CHECK-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 [[IDXPROM12]]
-; CHECK-NEXT: [[TMP3:%.*]] = load double, double* [[ARRAYIDX17]], align 8
-; CHECK-NEXT: [[ADD18:%.*]] = fadd double [[TMP2]], [[TMP3]]
-; CHECK-NEXT: store double [[ADD18]], double* [[ARRAYIDX13]], align 8
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[ARRAYIDX4]] to <2 x double>*
+; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, <2 x double>* [[TMP2]], align 8
+; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast double* [[ARRAYIDX]] to <2 x double>*
+; CHECK-NEXT: store <2 x double> [[TMP4]], <2 x double>* [[TMP5]], align 8
; CHECK-NEXT: [[ADD24:%.*]] = add nsw i32 [[MUL]], 2
; CHECK-NEXT: [[IDXPROM25:%.*]] = sext i32 [[ADD24]] to i64
; CHECK-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [2000 x double], [2000 x double]* @A, i32 0, i64 [[IDXPROM25]]
-; CHECK-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX26]], align 8
+; CHECK-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX26]], align 8
; CHECK-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2000 x double], [2000 x double]* @B, i32 0, i64 [[IDXPROM25]]
-; CHECK-NEXT: [[TMP5:%.*]] = load double, double* [[ARRAYIDX30]], align 8
-; CHECK-NEXT: [[ADD31:%.*]] = fadd double [[TMP4]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = load double, double* [[ARRAYIDX30]], align 8
+; CHECK-NEXT: [[ADD31:%.*]] = fadd double [[TMP6]], [[TMP7]]
; CHECK-NEXT: store double [[ADD31]], double* [[ARRAYIDX26]], align 8
; CHECK-NEXT: ret void
;
</cut>
4 years
- 1
- 0
[TCWG CI] 464.h264ref slowed down by 6% after llvm: [SCEV] Use full logic when infering flags on add and gep
by ci_notify＠linaro.org
After llvm commit d02db32644b7360bcda54cdf739fa42abe450fcd
Author: Philip Reames <listmail(a)philipreames.com>
[SCEV] Use full logic when infering flags on add and gep
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 6% from 10842 to 11545 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-d02db32644b7360bcda54cdf739fa42abe450fcd
cd investigate-llvm-d02db32644b7360bcda54cdf739fa42abe450fcd
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach d02db32644b7360bcda54cdf739fa42abe450fcd
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach f39978b84f1d3a1da6c32db48f64c8daae64b3ad
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit d02db32644b7360bcda54cdf739fa42abe450fcd
Author: Philip Reames <listmail(a)philipreames.com>
Date: Sun Oct 3 15:32:15 2021 -0700
[SCEV] Use full logic when infering flags on add and gep
This is a followon to D109845. With that landed, we will have fixed all known instances of pr51817, and can thus start inferring flags more aggressively with greatly reduced risk of miscompiles. This patch simply applies the same inference logic used in that patch to our other major flag inference path.
We can still do much better here (on both paths), but this is our first step.
Differential Revision: https://reviews.llvm.org/D111003
---
llvm/lib/Analysis/ScalarEvolution.cpp | 10 ++--------
.../Delinearization/multidim_ivs_and_integer_offsets_3d.ll | 2 +-
.../Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll | 2 +-
llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll | 4 ++--
llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll | 8 ++++----
llvm/test/Analysis/ScalarEvolution/load.ll | 2 +-
llvm/test/Analysis/ScalarEvolution/ptrtoint.ll | 2 +-
polly/test/IstAstInfo/simple-run-time-condition.ll | 2 +-
8 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 75cecbf48c08..70bf9aee6e0a 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -6657,14 +6657,8 @@ bool ScalarEvolution::isSCEVExprNeverPoison(const Instruction *I) {
// TODO: We can do better here in some cases.
if (!isSCEVable(Op->getType()))
return false;
- // TODO: the following two lines should be:
- // if (auto *DefI = getDefinedScopeRoot(getSCEV(Op)))
- // if (isGuaranteedToTransferExecutionTo(DefI, I))
- // We use the following instead for the purposes of seperating a bugfix
- // change from an optimization change. Once pr51817 is fully addressed,
- // we should unlock this power.
- if (auto *AddRecS = dyn_cast<SCEVAddRecExpr>(getSCEV(Op)))
- if (isGuaranteedToExecuteForEveryIteration(I, AddRecS->getLoop()))
+ if (auto *DefI = getDefinedScopeRoot(getSCEV(Op)))
+ if (isGuaranteedToTransferExecutionTo(DefI, I))
return true;
}
return false;
diff --git a/llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll b/llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
index 712a52927dcb..77982c786e6e 100644
--- a/llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
+++ b/llvm/test/Analysis/Delinearization/multidim_ivs_and_integer_offsets_3d.ll
@@ -11,7 +11,7 @@
; AddRec: {{{(56 + (8 * (-4 + (3 * %m)) * %o) + %A),+,(8 * %m * %o)}<%for.i>,+,(8 * %o)}<%for.j>,+,8}<%for.k>
; CHECK: Base offset: %A
; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of 8 bytes.
-; CHECK: ArrayRef[{3,+,1}<nuw><%for.i>][{-4,+,1}<nw><%for.j>][{7,+,1}<nuw><nsw><%for.k>]
+; CHECK: ArrayRef[{3,+,1}<nuw><%for.i>][{-4,+,1}<nsw><%for.j>][{7,+,1}<nuw><nsw><%for.k>]
define void @foo(i64 %n, i64 %m, i64 %o, double* %A) {
entry:
diff --git a/llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll b/llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
index e3fdb0642211..8ecd498ea211 100644
--- a/llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
+++ b/llvm/test/Analysis/Delinearization/multidim_ivs_and_parameteric_offsets_3d.ll
@@ -11,7 +11,7 @@
; AddRec: {{{((8 * ((((%m * %p) + %q) * %o) + %r)) + %A),+,(8 * %m * %o)}<%for.i>,+,(8 * %o)}<%for.j>,+,8}<%for.k>
; CHECK: Base offset: %A
; CHECK: ArrayDecl[UnknownSize][%m][%o] with elements of 8 bytes.
-; CHECK: ArrayRef[{%p,+,1}<nw><%for.i>][{%q,+,1}<nw><%for.j>][{%r,+,1}<nsw><%for.k>]
+; CHECK: ArrayRef[{%p,+,1}<nw><%for.i>][{%q,+,1}<nsw><%for.j>][{%r,+,1}<nsw><%for.k>]
define void @foo(i64 %n, i64 %m, i64 %o, double* %A, i64 %p, i64 %q, i64 %r) {
entry:
diff --git a/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll b/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
index 821513199546..1f1515435e1a 100644
--- a/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
+++ b/llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
@@ -11,8 +11,8 @@ target triple = "powerpc64le-unknown-linux-gnu"
; }
; }
-; CHECK-DAG: Loop 'for.i' has cost = 20300
-; CHECK-DAG: Loop 'for.j' has cost = 700
+; CHECK-DAG: Loop 'for.i' has cost = 20600
+; CHECK-DAG: Loop 'for.j' has cost = 800
define void @foo(i64 %n, i64 %m, i32* %A, i32* %B, i32* %C) {
entry:
diff --git a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
index c8d3137f8dc9..5ab24159c250 100644
--- a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
+++ b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll
@@ -273,9 +273,9 @@ define void @test-add-scope-bound-unkn-header(i32* %input, i32 %needle) {
; CHECK-NEXT: %offset = load i32, i32* %gep, align 4
; CHECK-NEXT: --> %offset U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: %i.next = add nuw i32 %i, %offset
-; CHECK-NEXT: --> (%offset + %i) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT: --> (%offset + %i)<nuw> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: %gep2 = getelementptr i32, i32* %input, i32 %i.next
-; CHECK-NEXT: --> ((4 * (sext i32 (%offset + %i) to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT: --> ((4 * (sext i32 (%offset + %i)<nuw> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-header
; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count.
; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count.
@@ -307,9 +307,9 @@ define void @test-add-scope-bound-unkn-header2(i32* %input, i32 %needle) {
; CHECK-NEXT: %offset = load i32, i32* %gep, align 4
; CHECK-NEXT: --> %offset U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: %i.next = add nuw i32 %i, %offset
-; CHECK-NEXT: --> (%offset + %i) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT: --> (%offset + %i)<nuw> U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: %gep2 = getelementptr i32, i32* %input, i32 %i.next
-; CHECK-NEXT: --> ((4 * (sext i32 (%offset + %i) to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
+; CHECK-NEXT: --> ((4 * (sext i32 (%offset + %i)<nuw> to i64))<nsw> + %input) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %loop: Variant }
; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-header2
; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count.
; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count.
diff --git a/llvm/test/Analysis/ScalarEvolution/load.ll b/llvm/test/Analysis/ScalarEvolution/load.ll
index c0d671342af7..e95a093b2a8b 100644
--- a/llvm/test/Analysis/ScalarEvolution/load.ll
+++ b/llvm/test/Analysis/ScalarEvolution/load.ll
@@ -73,7 +73,7 @@ define i32 @test2() nounwind uwtable readonly {
; CHECK-NEXT: %n.01 = phi %struct.ListNode* [ bitcast ({ %struct.ListNode*, i32, [4 x i8] }* @node5 to %struct.ListNode*), %entry ], [ %1, %for.body ]
; CHECK-NEXT: --> %n.01 U: full-set S: full-set Exits: @node1 LoopDispositions: { %for.body: Variant }
; CHECK-NEXT: %i = getelementptr inbounds %struct.ListNode, %struct.ListNode* %n.01, i64 0, i32 1
-; CHECK-NEXT: --> (4 + %n.01) U: full-set S: full-set Exits: (4 + @node1)<nuw><nsw> LoopDispositions: { %for.body: Variant }
+; CHECK-NEXT: --> (4 + %n.01)<nuw> U: [4,0) S: [4,0) Exits: (4 + @node1)<nuw><nsw> LoopDispositions: { %for.body: Variant }
; CHECK-NEXT: %0 = load i32, i32* %i, align 4
; CHECK-NEXT: --> %0 U: full-set S: full-set Exits: 0 LoopDispositions: { %for.body: Variant }
; CHECK-NEXT: %add = add nsw i32 %0, %sum.02
diff --git a/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll b/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
index 93d8782f373e..cb40ddda9369 100644
--- a/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
+++ b/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
@@ -502,7 +502,7 @@ define void @pr46786_c26_int(i32* %arg, i32* %arg1, i32* %arg2) {
; X32-NEXT: %i11 = ashr exact i64 %i10, 2
; X32-NEXT: --> %i11 U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: <<Unknown>> LoopDispositions: { %bb6: Variant }
; X32-NEXT: %i12 = getelementptr inbounds i32, i32* %arg2, i64 %i11
-; X32-NEXT: --> ((4 * (trunc i64 %i11 to i32)) + %arg2) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %bb6: Variant }
+; X32-NEXT: --> ((4 * (trunc i64 %i11 to i32))<nsw> + %arg2) U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %bb6: Variant }
; X32-NEXT: %i13 = load i32, i32* %i12, align 4
; X32-NEXT: --> %i13 U: full-set S: full-set Exits: <<Unknown>> LoopDispositions: { %bb6: Variant }
; X32-NEXT: %i14 = add nsw i32 %i13, %i8
diff --git a/polly/test/IstAstInfo/simple-run-time-condition.ll b/polly/test/IstAstInfo/simple-run-time-condition.ll
index aba5d9e34f50..0d167566291b 100644
--- a/polly/test/IstAstInfo/simple-run-time-condition.ll
+++ b/polly/test/IstAstInfo/simple-run-time-condition.ll
@@ -20,7 +20,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
; for the delinearization is simplified such that conditions that would not
; cause any code to be executed are not generated.
-; CHECK: if (((o >= 1 && q <= 0 && m + q >= 0) || (o <= 0 && m + q >= 100 && q <= 100)) && 0 == ((m >= 1 && n + p >= 9223372036854775809) || (o <= 0 && n >= 1 && m + q >= 9223372036854775909) || (o <= 0 && m >= 1 && n >= 1 && q <= -9223372036854775709)))
+; CHECK: if (((o >= 1 && q <= 0 && m + q >= 0) || (o <= 0 && m + q >= 100 && q <= 100)) && 0 == ((o <= 0 && n >= 1 && m + q >= 9223372036854775909) || (o <= 0 && m >= 1 && n >= 1 && q <= -9223372036854775709)))
; CHECK: if (o <= 0) {
; CHECK: for (int c0 = 0; c0 < n; c0 += 1)
</cut>
4 years
- 1
- 0
[TCWG CI] Regression caused by gcc: Enhance -Waddress to detect more suspicious expressions [PR102103].
by ci_notify＠linaro.org
[TCWG CI] Regression caused by gcc: Enhance -Waddress to detect more suspicious expressions [PR102103].:
commit 4dc7ce6fb3917958d1a6036d8acf2953b9c1b868
Author: Martin Sebor <msebor(a)redhat.com>
Enhance -Waddress to detect more suspicious expressions [PR102103].
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
21397
# First few build errors in logs:
# 00:02:12 sound/core/oss/mixer_oss.c:1035:21: error: ‘slot’ is used uninitialized [-Werror=uninitialized]
# 00:02:15 make[3]: *** [scripts/Makefile.build:288: sound/core/oss/mixer_oss.o] Error 1
# 00:02:15 sound/core/oss/pcm_oss.c:108:29: error: ‘t’ is used uninitialized [-Werror=uninitialized]
# 00:02:15 sound/core/oss/pcm_oss.c:2475:34: error: ‘setup’ is used uninitialized [-Werror=uninitialized]
# 00:02:15 sound/core/oss/pcm_oss.c:2985:51: error: ‘template’ is used uninitialized [-Werror=uninitialized]
# 00:02:15 sound/core/seq/oss/seq_oss_init.c:350:35: error: ‘qinfo’ is used uninitialized [-Werror=uninitialized]
# 00:02:15 sound/core/seq/oss/seq_oss_init.c:370:35: error: ‘qinfo’ is used uninitialized [-Werror=uninitialized]
# 00:02:16 make[4]: *** [scripts/Makefile.build:288: sound/core/seq/oss/seq_oss_init.o] Error 1
# 00:02:22 make[3]: *** [scripts/Makefile.build:288: sound/core/oss/pcm_oss.o] Error 1
# 00:02:28 make[3]: *** [scripts/Makefile.build:571: sound/core/seq/oss] Error 2
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
21403
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_kernel/gnu-master-aarch64-next-allmodconfig
First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al…
Reproduce builds:
<cut>
mkdir investigate-gcc-4dc7ce6fb3917958d1a6036d8acf2953b9c1b868
cd investigate-gcc-4dc7ce6fb3917958d1a6036d8acf2953b9c1b868
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-next-al… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach 4dc7ce6fb3917958d1a6036d8acf2953b9c1b868
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach f1710910087fb1f4a7706e9ce838163ffcbc50b4
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 4dc7ce6fb3917958d1a6036d8acf2953b9c1b868
Author: Martin Sebor <msebor(a)redhat.com>
Date: Fri Oct 1 11:50:25 2021 -0600
Enhance -Waddress to detect more suspicious expressions [PR102103].
Resolves:
PR c/102103 - missing warning comparing array address to null
gcc/ChangeLog:
PR c/102103
* doc/invoke.texi (-Waddress): Update.
* gengtype.c (write_types): Avoid -Waddress.
* poly-int.h (POLY_SET_COEFF): Avoid using null.
gcc/c-family/ChangeLog:
PR c/102103
* c-common.c (decl_with_nonnull_addr_p): Handle members.
Check and perform warning suppression.
(c_common_truthvalue_conversion): Enhance warning suppression.
gcc/c/ChangeLog:
PR c/102103
* c-typeck.c (maybe_warn_for_null_address): New function.
(build_binary_op): Call it.
gcc/cp/ChangeLog:
PR c/102103
* typeck.c (warn_for_null_address): Enhance.
(cp_build_binary_op): Call it also for member pointers.
gcc/fortran/ChangeLog:
PR c/102103
* array.c: Remove an unnecessary test.
* trans-array.c: Same.
gcc/testsuite/ChangeLog:
PR c/102103
* g++.dg/cpp0x/constexpr-array-ptr10.C: Suppress a valid warning.
* g++.dg/warn/Wreturn-local-addr-6.C: Correct a cast.
* gcc.dg/Waddress.c: Expect a warning.
* c-c++-common/Waddress-3.c: New test.
* c-c++-common/Waddress-4.c: New test.
* g++.dg/warn/Waddress-5.C: New test.
* g++.dg/warn/Waddress-6.C: New test.
* g++.dg/warn/pr101219.C: Expect a warning.
* gcc.dg/Waddress-3.c: New test.
---
gcc/c-family/c-common.c | 29 +++--
gcc/c/c-typeck.c | 140 ++++++++++++++++-----
gcc/cp/typeck.c | 94 ++++++++++++--
gcc/doc/invoke.texi | 48 +++++--
gcc/fortran/array.c | 2 +-
gcc/fortran/trans-array.c | 1 -
gcc/gengtype.c | 4 +-
gcc/poly-int.h | 4 +-
gcc/testsuite/c-c++-common/Waddress-3.c | 125 ++++++++++++++++++
gcc/testsuite/c-c++-common/Waddress-4.c | 106 ++++++++++++++++
gcc/testsuite/g++.dg/cpp0x/constexpr-array-ptr10.C | 5 +-
gcc/testsuite/g++.dg/warn/Waddress-5.C | 115 +++++++++++++++++
gcc/testsuite/g++.dg/warn/Waddress-6.C | 79 ++++++++++++
gcc/testsuite/g++.dg/warn/Wreturn-local-addr-6.C | 4 +-
gcc/testsuite/g++.dg/warn/pr101219.C | 4 +-
gcc/testsuite/gcc.dg/Waddress-3.c | 35 ++++++
gcc/testsuite/gcc.dg/Waddress.c | 2 +-
17 files changed, 722 insertions(+), 75 deletions(-)
diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c
index 5845c675e85..9d19e352725 100644
--- a/gcc/c-family/c-common.c
+++ b/gcc/c-family/c-common.c
@@ -3393,14 +3393,16 @@ c_wrap_maybe_const (tree expr, bool non_const)
return expr;
}
-/* Return whether EXPR is a declaration whose address can never be
- NULL. */
+/* Return whether EXPR is a declaration whose address can never be NULL.
+ The address of the first struct member could be NULL only if it were
+ accessed through a NULL pointer, and such an access would be invalid. */
bool
decl_with_nonnull_addr_p (const_tree expr)
{
return (DECL_P (expr)
- && (TREE_CODE (expr) == PARM_DECL
+ && (TREE_CODE (expr) == FIELD_DECL
+ || TREE_CODE (expr) == PARM_DECL
|| TREE_CODE (expr) == LABEL_DECL
|| !DECL_WEAK (expr)));
}
@@ -3488,13 +3490,17 @@ c_common_truthvalue_conversion (location_t location, tree expr)
case ADDR_EXPR:
{
tree inner = TREE_OPERAND (expr, 0);
- if (decl_with_nonnull_addr_p (inner))
+ if (decl_with_nonnull_addr_p (inner)
+ /* Check both EXPR and INNER for suppression. */
+ && !warning_suppressed_p (expr, OPT_Waddress)
+ && !warning_suppressed_p (inner, OPT_Waddress))
{
- /* Common Ada programmer's mistake. */
+ /* Common Ada programmer's mistake. */
warning_at (location,
OPT_Waddress,
"the address of %qD will always evaluate as %<true%>",
inner);
+ suppress_warning (inner, OPT_Waddress);
return truthvalue_true_node;
}
break;
@@ -3627,8 +3633,17 @@ c_common_truthvalue_conversion (location_t location, tree expr)
break;
/* If this isn't narrowing the argument, we can ignore it. */
if (TYPE_PRECISION (totype) >= TYPE_PRECISION (fromtype))
- return c_common_truthvalue_conversion (location,
- TREE_OPERAND (expr, 0));
+ {
+ tree op0 = TREE_OPERAND (expr, 0);
+ if ((TREE_CODE (fromtype) == POINTER_TYPE
+ && TREE_CODE (totype) == INTEGER_TYPE)
+ || warning_suppressed_p (expr, OPT_Waddress))
+ /* Suppress -Waddress for casts to intptr_t, propagating
+ any suppression from the enclosing expression to its
+ operand. */
+ suppress_warning (op0, OPT_Waddress);
+ return c_common_truthvalue_conversion (location, op0);
+ }
}
break;
diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c
index c74f876e667..33963d7555a 100644
--- a/gcc/c/c-typeck.c
+++ b/gcc/c/c-typeck.c
@@ -11554,6 +11554,110 @@ build_vec_cmp (tree_code code, tree type,
return build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
}
+/* Possibly warn about an address of OP never being NULL in a comparison
+ operation CODE involving null. */
+
+static void
+maybe_warn_for_null_address (location_t loc, tree op, tree_code code)
+{
+ if (!warn_address || warning_suppressed_p (op, OPT_Waddress))
+ return;
+
+ if (TREE_CODE (op) == NOP_EXPR)
+ {
+ /* Allow casts to intptr_t to suppress the warning. */
+ tree type = TREE_TYPE (op);
+ if (TREE_CODE (type) == INTEGER_TYPE)
+ return;
+ op = TREE_OPERAND (op, 0);
+ }
+
+ if (TREE_CODE (op) == POINTER_PLUS_EXPR)
+ {
+ /* Allow a cast to void* to suppress the warning. */
+ tree type = TREE_TYPE (TREE_TYPE (op));
+ if (VOID_TYPE_P (type))
+ return;
+
+ /* Adding any value to a null pointer, including zero, is undefined
+ in C. This includes the expression &p[0] where p is the null
+ pointer, although &p[0] will have been folded to p by this point
+ and so not diagnosed. */
+ if (code == EQ_EXPR)
+ warning_at (loc, OPT_Waddress,
+ "the comparison will always evaluate as %<false%> "
+ "for the pointer operand in %qE must not be NULL",
+ op);
+ else
+ warning_at (loc, OPT_Waddress,
+ "the comparison will always evaluate as %<true%> "
+ "for the pointer operand in %qE must not be NULL",
+ op);
+
+ return;
+ }
+
+ if (TREE_CODE (op) != ADDR_EXPR)
+ return;
+
+ op = TREE_OPERAND (op, 0);
+
+ if (TREE_CODE (op) == IMAGPART_EXPR
+ || TREE_CODE (op) == REALPART_EXPR)
+ {
+ /* The address of either complex part may not be null. */
+ if (code == EQ_EXPR)
+ warning_at (loc, OPT_Waddress,
+ "the comparison will always evaluate as %<false%> "
+ "for the address of %qE will never be NULL",
+ op);
+ else
+ warning_at (loc, OPT_Waddress,
+ "the comparison will always evaluate as %<true%> "
+ "for the address of %qE will never be NULL",
+ op);
+ return;
+ }
+
+ /* Set to true in the loop below if OP dereferences is operand.
+ In such a case the ultimate target need not be a decl for
+ the null [in]equality test to be constant. */
+ bool deref = false;
+
+ /* Get the outermost array or object, or member. */
+ while (handled_component_p (op))
+ {
+ if (TREE_CODE (op) == COMPONENT_REF)
+ {
+ /* Get the member (its address is never null). */
+ op = TREE_OPERAND (op, 1);
+ break;
+ }
+
+ /* Get the outer array/object to refer to in the warning. */
+ op = TREE_OPERAND (op, 0);
+ deref = true;
+ }
+
+ if ((!deref && !decl_with_nonnull_addr_p (op))
+ || from_macro_expansion_at (loc))
+ return;
+
+ if (code == EQ_EXPR)
+ warning_at (loc, OPT_Waddress,
+ "the comparison will always evaluate as %<false%> "
+ "for the address of %qE will never be NULL",
+ op);
+ else
+ warning_at (loc, OPT_Waddress,
+ "the comparison will always evaluate as %<true%> "
+ "for the address of %qE will never be NULL",
+ op);
+
+ if (DECL_P (op))
+ inform (DECL_SOURCE_LOCATION (op), "%qD declared here", op);
+}
+
/* Build a binary-operation expression without default conversions.
CODE is the kind of expression to build.
LOCATION is the operator's location.
@@ -12189,44 +12293,12 @@ build_binary_op (location_t location, enum tree_code code,
short_compare = 1;
else if (code0 == POINTER_TYPE && null_pointer_constant_p (orig_op1))
{
- if (TREE_CODE (op0) == ADDR_EXPR
- && decl_with_nonnull_addr_p (TREE_OPERAND (op0, 0))
- && !from_macro_expansion_at (location))
- {
- if (code == EQ_EXPR)
- warning_at (location,
- OPT_Waddress,
- "the comparison will always evaluate as %<false%> "
- "for the address of %qD will never be NULL",
- TREE_OPERAND (op0, 0));
- else
- warning_at (location,
- OPT_Waddress,
- "the comparison will always evaluate as %<true%> "
- "for the address of %qD will never be NULL",
- TREE_OPERAND (op0, 0));
- }
+ maybe_warn_for_null_address (location, op0, code);
result_type = type0;
}
else if (code1 == POINTER_TYPE && null_pointer_constant_p (orig_op0))
{
- if (TREE_CODE (op1) == ADDR_EXPR
- && decl_with_nonnull_addr_p (TREE_OPERAND (op1, 0))
- && !from_macro_expansion_at (location))
- {
- if (code == EQ_EXPR)
- warning_at (location,
- OPT_Waddress,
- "the comparison will always evaluate as %<false%> "
- "for the address of %qD will never be NULL",
- TREE_OPERAND (op1, 0));
- else
- warning_at (location,
- OPT_Waddress,
- "the comparison will always evaluate as %<true%> "
- "for the address of %qD will never be NULL",
- TREE_OPERAND (op1, 0));
- }
+ maybe_warn_for_null_address (location, op1, code);
result_type = type1;
}
else if (code0 == POINTER_TYPE && code1 == POINTER_TYPE)
diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c
index cd130f16a66..e880d34dcfe 100644
--- a/gcc/cp/typeck.c
+++ b/gcc/cp/typeck.c
@@ -4603,25 +4603,93 @@ warn_for_null_address (location_t location, tree op, tsubst_flags_t complain)
|| warning_suppressed_p (op, OPT_Waddress))
return;
+ if (TREE_CODE (op) == NON_DEPENDENT_EXPR)
+ op = TREE_OPERAND (op, 0);
+
tree cop = fold_for_warn (op);
- if (TREE_CODE (cop) == ADDR_EXPR
- && decl_with_nonnull_addr_p (TREE_OPERAND (cop, 0))
- && !warning_suppressed_p (cop, OPT_Waddress))
- warning_at (location, OPT_Waddress, "the address of %qD will never "
- "be NULL", TREE_OPERAND (cop, 0));
+ if (TREE_CODE (cop) == NON_LVALUE_EXPR)
+ /* Unwrap the expression for C++ 98. */
+ cop = TREE_OPERAND (cop, 0);
- if (CONVERT_EXPR_P (op)
+ if (TREE_CODE (cop) == PTRMEM_CST)
+ {
+ /* The address of a nonstatic data member is never null. */
+ warning_at (location, OPT_Waddress,
+ "the address %qE will never be NULL",
+ cop);
+ return;
+ }
+
+ if (TREE_CODE (cop) == NOP_EXPR)
+ {
+ /* Allow casts to intptr_t to suppress the warning. */
+ tree type = TREE_TYPE (cop);
+ if (TREE_CODE (type) == INTEGER_TYPE)
+ return;
+
+ STRIP_NOPS (cop);
+ }
+
+ bool warned = false;
+ if (TREE_CODE (cop) == ADDR_EXPR)
+ {
+ cop = TREE_OPERAND (cop, 0);
+
+ /* Set to true in the loop below if OP dereferences its operand.
+ In such a case the ultimate target need not be a decl for
+ the null [in]equality test to be necessarily constant. */
+ bool deref = false;
+
+ /* Get the outermost array or object, or member. */
+ while (handled_component_p (cop))
+ {
+ if (TREE_CODE (cop) == COMPONENT_REF)
+ {
+ /* Get the member (its address is never null). */
+ cop = TREE_OPERAND (cop, 1);
+ break;
+ }
+
+ /* Get the outer array/object to refer to in the warning. */
+ cop = TREE_OPERAND (cop, 0);
+ deref = true;
+ }
+
+ if ((!deref && !decl_with_nonnull_addr_p (cop))
+ || from_macro_expansion_at (location)
+ || warning_suppressed_p (cop, OPT_Waddress))
+ return;
+
+ warned = warning_at (location, OPT_Waddress,
+ "the address of %qD will never be NULL", cop);
+ op = cop;
+ }
+ else if (TREE_CODE (cop) == POINTER_PLUS_EXPR)
+ {
+ /* Adding zero to the null pointer is well-defined in C++. When
+ the offset is unknown (i.e., not a constant) warn anyway since
+ it's less likely that the pointer operand is null than not. */
+ tree off = TREE_OPERAND (cop, 1);
+ if (!integer_zerop (off)
+ && !warning_suppressed_p (cop, OPT_Waddress))
+ warning_at (location, OPT_Waddress, "comparing the result of pointer "
+ "addition %qE and NULL", cop);
+ return;
+ }
+ else if (CONVERT_EXPR_P (op)
&& TYPE_REF_P (TREE_TYPE (TREE_OPERAND (op, 0))))
{
- tree inner_op = op;
- STRIP_NOPS (inner_op);
+ STRIP_NOPS (op);
- if (DECL_P (inner_op))
- warning_at (location, OPT_Waddress,
- "the compiler can assume that the address of "
- "%qD will never be NULL", inner_op);
+ if (DECL_P (op))
+ warned = warning_at (location, OPT_Waddress,
+ "the compiler can assume that the address of "
+ "%qD will never be NULL", op);
}
+
+ if (warned && DECL_P (op))
+ inform (DECL_SOURCE_LOCATION (op), "%qD declared here", op);
}
/* Warn about [expr.arith.conv]/2: If one operand is of enumeration type and
@@ -5411,6 +5479,8 @@ cp_build_binary_op (const op_location_t &location,
op1 = cp_convert (TREE_TYPE (op0), op1, complain);
}
result_type = TREE_TYPE (op0);
+
+ warn_for_null_address (location, orig_op0, complain);
}
else if (TYPE_PTRMEMFUNC_P (type1) && null_ptr_cst_p (orig_op0))
return cp_build_binary_op (location, code, op1, op0, complain);
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 5f39b208049..d35114c0727 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -8551,17 +8551,43 @@ by @option{-Wall}.
@item -Waddress
@opindex Waddress
@opindex Wno-address
-Warn about suspicious uses of memory addresses. These include using
-the address of a function in a conditional expression, such as
-@code{void func(void); if (func)}, and comparisons against the memory
-address of a string literal, such as @code{if (x == "abc")}. Such
-uses typically indicate a programmer error: the address of a function
-always evaluates to true, so their use in a conditional usually
-indicate that the programmer forgot the parentheses in a function
-call; and comparisons against string literals result in unspecified
-behavior and are not portable in C, so they usually indicate that the
-programmer intended to use @code{strcmp}. This warning is enabled by
-@option{-Wall}.
+Warn about suspicious uses of address expressions. These include comparing
+the address of a function or a declared object to the null pointer constant
+such as in
+@smallexample
+void f (void);
+void g (void)
+@{
+ if (!func) // warning: expression evaluates to false
+ abort ();
+@}
+@end smallexample
+comparisons of a pointer to a string literal, such as in
+@smallexample
+void f (const char *x)
+@{
+ if (x == "abc") // warning: expression evaluates to false
+ puts ("equal");
+@}
+@end smallexample
+and tests of the results of pointer addition or subtraction for equality
+to null, such as in
+@smallexample
+void f (const int *p, int i)
+@{
+ return p + i == NULL;
+@}
+@end smallexample
+Such uses typically indicate a programmer error: the address of most
+functions and objects necessarily evaluates to true (the exception are
+weak symbols), so their use in a conditional might indicate missing
+parentheses in a function call or a missing dereference in an array
+expression. The subset of the warning for object pointers can be
+suppressed by casting the pointer operand to an integer type such
+as @code{inptr_t} or @code{uinptr_t}.
+Comparisons against string literals result in unspecified behavior
+and are not portable, and suggest the intent was to call @code{strcmp}.
+@option{-Waddress} warning is enabled by @option{-Wall}.
@item -Wno-address-of-packed-member
@opindex Waddress-of-packed-member
diff --git a/gcc/fortran/array.c b/gcc/fortran/array.c
index a4d1cb4c72d..6552eaf3b0c 100644
--- a/gcc/fortran/array.c
+++ b/gcc/fortran/array.c
@@ -2581,7 +2581,7 @@ gfc_array_dimen_size (gfc_expr *array, int dimen, mpz_t *result)
}
}
- if (array->shape && array->shape[dimen])
+ if (array->shape)
{
mpz_init_set (*result, array->shape[dimen]);
return true;
diff --git a/gcc/fortran/trans-array.c b/gcc/fortran/trans-array.c
index b8061f37772..e2f59e0823c 100644
--- a/gcc/fortran/trans-array.c
+++ b/gcc/fortran/trans-array.c
@@ -5104,7 +5104,6 @@ set_loop_bounds (gfc_loopinfo *loop)
if (info->shape)
{
- gcc_assert (info->shape[dim]);
/* The frontend has worked out the size for us. */
if (!loopspec[n]
|| !specinfo->shape
diff --git a/gcc/gengtype.c b/gcc/gengtype.c
index 31d4bf4e5d0..a77cfd92bfa 100644
--- a/gcc/gengtype.c
+++ b/gcc/gengtype.c
@@ -3685,8 +3685,8 @@ write_types (outf_p output_header, type_p structures,
output_mangled_typename (output_header, s);
oprintf (output_header, "(X) do { \\\n");
oprintf (output_header,
- " if (X != NULL) gt_%sx_%s (X);\\\n", wtd->prefix,
- s_id_for_tag);
+ " if ((intptr_t)(X) != 0) gt_%sx_%s (X);\\\n",
+ wtd->prefix, s_id_for_tag);
oprintf (output_header, " } while (0)\n");
for (opt = s->u.s.opt; opt; opt = opt->next)
diff --git a/gcc/poly-int.h b/gcc/poly-int.h
index f47f9e436a8..94e7b701f64 100644
--- a/gcc/poly-int.h
+++ b/gcc/poly-int.h
@@ -324,10 +324,10 @@ struct poly_result<T1, T2, 2>
routine can take the address of RES rather than the address of
a temporary.
- The dummy comparison against a null C * is just a way of checking
+ The dummy self-comparison against C * is just a way of checking
that C gives the right type. */
#define POLY_SET_COEFF(C, RES, I, VALUE) \
- ((void) (&(RES).coeffs[0] == (C *) 0), \
+ ((void) (&(RES).coeffs[0] == (C *) (void *) &(RES).coeffs[0]), \
wi::int_traits<C>::precision_type == wi::FLEXIBLE_PRECISION \
? (void) ((RES).coeffs[I] = VALUE) \
: (void) ((RES).coeffs[I].~C (), new (&(RES).coeffs[I]) C (VALUE)))
diff --git a/gcc/testsuite/c-c++-common/Waddress-3.c b/gcc/testsuite/c-c++-common/Waddress-3.c
new file mode 100644
index 00000000000..9a13a444045
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Waddress-3.c
@@ -0,0 +1,125 @@
+/* PR c/102103 - missing warning comparing array address to null
+ { dg-do compile }
+ { dg-options "-Wall" } */
+
+typedef __INTPTR_TYPE__ intptr_t;
+typedef __UINTPTR_TYPE__ uintptr_t;
+
+#ifndef __cplusplus
+# define bool _Bool
+#endif
+
+struct S { void *p, *a1[2], *a2[2][2]; } s, *p;
+
+extern const void *a1[2];
+extern void *a2[2][2], *ax[];
+
+void T (bool);
+
+void test_array_eq_0 (int i)
+{
+ // Verify that casts intptr_t suppress the warning.
+ T ((intptr_t)a1 == 0);
+ T ((uintptr_t)a1 == 0);
+ T (a1 == 0); // { dg-warning "-Waddress" }
+ T (0 == &a1); // { dg-warning "-Waddress" }
+ // Verify that casts to other pointer types don't suppress it.
+ T ((void *)a1 == 0); // { dg-warning "-Waddress" }
+ T ((char *)a1 == 0); // { dg-warning "-Waddress" }
+ T (a1[0] == 0);
+ T (0 == (intptr_t)&a1[0]);
+ T (0 == &a1[0]); // { dg-warning "-Waddress" }
+ T (a1[i] == 0);
+ T (0 == (uintptr_t)&a1[i]);
+ T (0 == &a1[i]); // { dg-warning "-Waddress" }
+
+ T ((intptr_t)a2 == 0);
+ T (a2 == 0); // { dg-warning "-Waddress" }
+ T (0 == &a2); // { dg-warning "-Waddress" }
+ T (a2[0] == 0); // { dg-warning "-Waddress" }
+ T (0 == &a1[0]); // { dg-warning "-Waddress" }
+ T (a2[i] == 0); // { dg-warning "-Waddress" }
+ T (0 == &a2[i]); // { dg-warning "-Waddress" }
+ T (a2[0][0] == 0);
+ T (0 == &a2[0][0]); // { dg-warning "-Waddress" }
+ T (&ax == 0); // { dg-warning "-Waddress" }
+ T (0 == &ax); // { dg-warning "-Waddress" }
+ T (&ax[0] == 0); // { dg-warning "-Waddress" }
+ T (0 == ax[0]);
+}
+
+
+void test_array_neq_0 (int i)
+{
+ // Verify that casts to intptr_t suppress the warning.
+ T ((uintptr_t)a1);
+
+ T (a1); // { dg-warning "-Waddress" }
+ T ((void *)a1); // { dg-warning "-Waddress" }
+ T (&a1 != 0); // { dg-warning "-Waddress" }
+ T (a1[0]);
+ T (&a1[0] != 0); // { dg-warning "-Waddress" }
+ T (a1[i]);
+ T (&a1[i] != 0); // { dg-warning "-Waddress" }
+
+ T ((intptr_t)a2);
+ T (a2); // { dg-warning "-Waddress" }
+ T ((void *)a2); // { dg-warning "-Waddress" }
+ T ((char *)a2); // { dg-warning "-Waddress" }
+ T (&a2 != 0); // { dg-warning "-Waddress" }
+ T (a2[0]); // { dg-warning "-Waddress" }
+ T (&a1[0] != 0); // { dg-warning "-Waddress" }
+ T (a2[i]); // { dg-warning "-Waddress" }
+ T (&a2[i] != 0); // { dg-warning "-Waddress" }
+ T (a2[0][0]);
+ T (&a2[0][0] != 0); // { dg-warning "-Waddress" }
+}
+
+
+void test_member_array_eq_0 (int i)
+{
+ // Verify that casts to intptr_t suppress the warning.
+ T ((intptr_t)s.a1 == 0);
+ T (s.a1 == 0); // { dg-warning "-Waddress" }
+ T (0 == &a1); // { dg-warning "-Waddress" }
+ T (s.a1[0] == 0);
+ T ((void*)s.a1); // { dg-warning "-Waddress" }
+ T (0 == &a1[0]); // { dg-warning "-Waddress" }
+ T (s.a1[i] == 0);
+ T (0 == &a1[i]); // { dg-warning "-Waddress" }
+
+ T ((uintptr_t)s.a2 == 0);
+ T (s.a2 == 0); // { dg-warning "-Waddress" }
+ T (0 == &a2); // { dg-warning "-Waddress" }
+ T ((void *)s.a2 == 0);// { dg-warning "-Waddress" }
+ T (s.a2[0] == 0); // { dg-warning "-Waddress" }
+ T (0 == &a1[0]); // { dg-warning "-Waddress" }
+ T (s.a2[i] == 0); // { dg-warning "-Waddress" }
+ T (0 == &a2[i]); // { dg-warning "-Waddress" }
+ T (s.a2[0][0] == 0);
+ T (0 == &a2[0][0]); // { dg-warning "-Waddress" }
+}
+
+
+void test_member_array_neq_0 (int i)
+{
+ // Verify that casts to intptr_t suppress the warning.
+ T ((uintptr_t)s.a1);
+ T (s.a1); // { dg-warning "-Waddress" }
+ T (&s.a1 != 0); // { dg-warning "-Waddress" }
+ T ((void *)&s.a1[0]); // { dg-warning "-Waddress" }
+ T (s.a1[0]);
+ T (&s.a1[0] != 0); // { dg-warning "-Waddress" }
+ T (s.a1[i]);
+ T (&s.a1[i] != 0); // { dg-warning "-Waddress" }
+
+ T ((intptr_t)s.a2);
+ T (s.a2); // { dg-warning "-Waddress" }
+ T (&s.a2 != 0); // { dg-warning "-Waddress" }
+ T (s.a2[0]); // { dg-warning "-Waddress" }
+ T (&s.a1[0] != 0); // { dg-warning "-Waddress" }
+ T (s.a2[i]); // { dg-warning "-Waddress" }
+ T (&s.a2[i] != 0); // { dg-warning "-Waddress" }
+ T (s.a2[0][0]);
+ T (&s.a2[0][0] != 0); // { dg-warning "-Waddress" }
+}
diff --git a/gcc/testsuite/c-c++-common/Waddress-4.c b/gcc/testsuite/c-c++-common/Waddress-4.c
new file mode 100644
index 00000000000..489a0cd717c
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Waddress-4.c
@@ -0,0 +1,106 @@
+/* PR c/102103 - missing warning comparing array address to null
+ { dg-do compile }
+ { dg-options "-Wall" } */
+
+typedef __INTPTR_TYPE__ intptr_t;
+typedef __INTPTR_TYPE__ uintptr_t;
+
+extern char *ax[], *a2[][2];
+
+void T (int);
+
+void test_ax_plus_eq_0 (int i)
+{
+ // Verify that casts to intptr_t suppress the warning.
+ T ((intptr_t)(ax + 0) == 0);
+ T ((uintptr_t)(ax + 1) == 0);
+
+ T (ax + 0 == 0); // { dg-warning "-Waddress" }
+ T (&ax[0] == 0); // { dg-warning "-Waddress" }
+ T (ax - 1 == 0); // { dg-warning "-Waddress" }
+ T (0 == &ax[-1]); // { dg-warning "-Waddress" }
+ T ((void *)(&ax[0] + 2) == 0); // { dg-warning "-Waddress" }
+ T (&ax[0] + 2 == 0); // { dg-warning "-Waddress" }
+ T (ax + 3 == 0); // { dg-warning "-Waddress" }
+ T (0 == &ax[-4]); // { dg-warning "-Waddress" }
+ T (ax - i == 0); // { dg-warning "-Waddress" }
+ T (&ax[i] == 0); // { dg-warning "-Waddress" }
+ T (0 == &ax[1] + i); // { dg-warning "-Waddress" }
+}
+
+void test_a2_plus_eq_0 (int i)
+{
+ // Verify that casts to intptr_t suppress the warning.
+ T ((intptr_t)(a2 + 0) == 0);
+ T ((uintptr_t)(a2 + 1) == 0);
+
+ T (a2 + 0 == 0); // { dg-warning "-Waddress" }
+ // Verify that a cast to another pointer type doesn't suppress it.
+ T ((void*)(a2 + 0) == 0); // { dg-warning "-Waddress" }
+ T ((char*)a2 + 1 == 0); // { dg-warning "-Waddress" }
+ T (&a2[0] == 0); // { dg-warning "-Waddress" }
+ T (a2 - 1 == 0); // { dg-warning "-Waddress" }
+ T (0 == &a2[-1]); // { dg-warning "-Waddress" }
+ T (a2 + 2 == 0); // { dg-warning "-Waddress" }
+ T (0 == &a2[-2]); // { dg-warning "-Waddress" }
+ T (a2 - i == 0); // { dg-warning "-Waddress" }
+ T (&a2[i] == 0); // { dg-warning "-Waddress" }
+}
+
+// Exercise a pointer.
+void test_p_plus_eq_0 (int *p, int i)
+{
+ /* P + 0 and equivalently &P[0] are invalid for a null P but they're
+ folded to p before the warning has a chance to trigger. */
+ T (p + 0 == 0); // { dg-warning "-Waddress" "pr102555" { xfail *-*-* } }
+ T (&p[0] == 0); // { dg-warning "-Waddress" "pr102555" { xfail *-*-* } }
+
+ T (p - 1 == 0); // { dg-warning "-Waddress" }
+ T (0 == &p[-1]); // { dg-warning "-Waddress" }
+ T (p + 2 == 0); // { dg-warning "-Waddress" }
+ T (0 == &p[-2]); // { dg-warning "-Waddress" }
+ T (p - i == 0); // { dg-warning "-Waddress" }
+ T (&p[i] == 0); // { dg-warning "-Waddress" }
+}
+
+// Exercise pointer to array.
+void test_pa_plus_eq_0 (int (*p)[], int (*p2)[][2], int i)
+{
+ // The array pointer may be null.
+ T (*p == 0);
+ /* &**P is equivalent to *P and might be the result od macro expansion.
+ Verify it doesn't cause a warning. */
+ T (&**p == 0);
+
+ /* *P + 0 is invalid but folded to *P before the warning has a chance
+ to trigger. */
+ T (*p + 0 == 0); // { dg-warning "-Waddress" "pr102555" { xfail *-*-* } }
+
+ T (&(*p)[0] == 0); // { dg-warning "-Waddress" }
+ T (*p - 1 == 0); // { dg-warning "-Waddress" }
+ T (0 == &(*p)[-1]); // { dg-warning "-Waddress" }
+ T (*p + 2 == 0); // { dg-warning "-Waddress" }
+ T (0 == &(*p)[-2]); // { dg-warning "-Waddress" }
+ T (*p - i == 0); // { dg-warning "-Waddress" }
+ T (&(*p)[i] == 0); // { dg-warning "-Waddress" }
+
+
+ /* Similar to the above but for a pointer to a two-dimensional array,
+ referring to the higher-level element (i.e., an array itself). */
+ T (*p2 == 0);
+ T (**p2 == 0); // { dg-warning "-Waddress" "pr102555" { xfail *-*-* } }
+ T (&**p2 == 0); // { dg-warning "-Waddress" "pr102555" { xfail *-*-* } }
+ T (&***p2 == 0); // { dg-warning "-Waddress" "pr102555" { xfail *-*-* } }
+ T (&**p2 == 0);
+
+ T (*p2 + 0 == 0); // { dg-warning "-Waddress" "pr102555" { xfail *-*-* } }
+ T (&(*p2)[0] == 0); // { dg-warning "-Waddress" }
+ T (&(*p2)[0][1] == 0); // { dg-warning "-Waddress" }
+ T (*p2 - 1 == 0); // { dg-warning "-Waddress" }
+ T (0 == &(*p2)[-1]); // { dg-warning "-Waddress" }
+ T (0 == &(*p2)[1][2]); // { dg-warning "-Waddress" }
+ T (*p2 + 2 == 0); // { dg-warning "-Waddress" }
+ T (0 == &(*p2)[-2]); // { dg-warning "-Waddress" }
+ T (*p2 - i == 0); // { dg-warning "-Waddress" }
+ T (&(*p2)[i] == 0); // { dg-warning "-Waddress" }
+}
diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-array-ptr10.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-array-ptr10.C
index 5224bb14234..63295230d51 100644
--- a/gcc/testsuite/g++.dg/cpp0x/constexpr-array-ptr10.C
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-array-ptr10.C
@@ -85,8 +85,11 @@ extern __attribute__ ((weak)) int i;
constexpr int *p1 = &i + 1;
#pragma GCC diagnostic push
+// Suppress warning: ordered comparison of pointer with integer zero.
#pragma GCC diagnostic ignored "-Wextra"
-// Suppress warning: ordered comparison of pointer with integer zero
+// Also suppress -Waddress for comparisons of constant addresses to
+// to null.
+#pragma GCC diagnostic ignored "-Waddress"
constexpr bool b0 = p1; // { dg-error "not a constant expression" }
constexpr bool b1 = p1 == 0; // { dg-error "not a constant expression" }
diff --git a/gcc/testsuite/g++.dg/warn/Waddress-5.C b/gcc/testsuite/g++.dg/warn/Waddress-5.C
new file mode 100644
index 00000000000..b1ad38a8112
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Waddress-5.C
@@ -0,0 +1,115 @@
+/* PR c/102103 - missing warning comparing array address to null
+ { dg-do compile }
+ { dg-options "-Wall" } */
+
+#if __cplusplus < 201103L
+# define nullptr __null
+#endif
+
+struct A
+{
+ void f ();
+ virtual void vf ();
+ virtual void pvf () = 0;
+
+ void sf ();
+
+ int *p;
+ int a[2];
+};
+
+void T (bool);
+
+void warn_memptr_if ()
+{
+ // Exercise warnings for addresses of nonstatic member functions.
+ if (&A::f == 0) // { dg-warning "the address '&A::f'" }
+ T (0);
+
+ if (&A::vf) // { dg-warning "-Waddress" }
+ T (0);
+
+ if (&A::pvf != 0) // { dg-warning "-Waddress" }
+ T (0);
+
+ // Exercise warnings for addresses of static member functions.
+ if (&A::sf == 0) // { dg-warning "-Waddress" }
+ T (0);
+
+ if (&A::sf) // { dg-warning "-Waddress" }
+ T (0);
+
+ // Exercise warnings for addresses of nonstatic data members.
+ if (&A::p == 0) // { dg-warning "the address '&A::p'" }
+ T (0);
+
+ if (&A::a == nullptr) // { dg-warning "-Waddress" }
+ T (0);
+}
+
+void warn_memptr_bool ()
+{
+ // Exercise warnings for addresses of nonstatic member functions.
+ T (&A::f == 0); // { dg-warning "-Waddress" }
+ T (&A::vf); // { dg-warning "-Waddress" }
+ T (&A::pvf != 0); // { dg-warning "-Waddress" }
+
+ // Exercise warnings for addresses of static member functions.
+ T (&A::sf == 0); // { dg-warning "-Waddress" }
+ T (&A::sf); // { dg-warning "-Waddress" }
+
+ // Exercise warnings for addresses of nonstatic data members.
+ T (&A::p == 0); // { dg-warning "-Waddress" }
+ T (&A::a == nullptr); // { dg-warning "-Waddress" }
+}
+
+
+/* Verify that no warnings are issued for a dependent expression in
+ a template. */
+
+template <int>
+struct B
+{
+ // This is why.
+ struct F { void* operator& () const { return 0; } } f;
+};
+
+template <class Type, int N>
+void nowarn_dependent (Type targ)
+{
+ T (&Type::x == 0);
+ T (&targ == 0);
+
+ Type tarr[1];
+ T (&tarr[0] == nullptr);
+
+ T (&B<N>::f == 0);
+
+ /* Like in the case above, the address-of operator could be a member
+ of B<N>::vf that returns zero. */
+ T (&B<N>::vf);
+ T (&B<N>::pvf != 0);
+ T (&B<N>::p == 0);
+ T (&B<N>::a == 0);
+}
+
+
+/* Verify that in an uninstantiated template warnings are not issued
+ for dependent expressions but are issued otherwise. */
+
+template <class Type>
+void warn_non_dependent (Type targ, Type *tptr, int i)
+{
+ /* The address of a pointer to a dependent type cannot be null but
+ the warning doesn't have a chance to see it. */
+ T (&tptr == 0); // { dg-warning "-Waddress" "pr102378" { xfail *-*-* } }
+ T (&i == 0); // { dg-warning "-Waddress" }
+
+ int iarr[1];
+ T (&iarr == 0); // { dg-warning "-Waddress" }
+ T (&*iarr != 0); // { dg-warning "-Waddress" "pr102378" { xfail *-*-* } }
+ T (&iarr[0] == 0); // { dg-warning "-Waddress" }
+
+ Type tarr[1];
+ T (&tarr == nullptr); // { dg-warning "-Waddress" "pr102378" { xfail *-*-* } }
+}
diff --git a/gcc/testsuite/g++.dg/warn/Waddress-6.C b/gcc/testsuite/g++.dg/warn/Waddress-6.C
new file mode 100644
index 00000000000..c22a83a0dd7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Waddress-6.C
@@ -0,0 +1,79 @@
+/* PR c/102103 - missing warning comparing array address to null
+ { dg-do compile }
+ Verify -Waddress for member arrays of structs and notes.
+ { dg-options "-Wall" } */
+
+#if __cplusplus < 201103L
+# define nullptr __null
+#endif
+
+void T (bool);
+
+struct A
+{
+ int n;
+ int ia[]; // { dg-message "'A::ia' declared here" }
+};
+
+struct B
+{
+ A a[3]; // { dg-message "'B::a' declared here" }
+};
+
+struct C
+{
+ B b[3]; // { dg-message "'C::b' declared here" }
+};
+
+struct D
+{
+ C c[3]; // { dg-message "'D::c' declared here" }
+};
+
+
+void test_waddress_1d ()
+{
+ D d[2]; // { dg-message "'d' declared here" }
+
+ T (d); // { dg-warning "address of 'd'" }
+ T (d == nullptr); // { dg-warning "address of 'd'" }
+ T (&d); // { dg-warning "address of 'd'" }
+ T (d->c); // { dg-warning "address of 'D::c'" }
+ T (d->c != nullptr); // { dg-warning "address of 'D::c'" }
+ T (d->c->b); // { dg-warning "address of 'C::b'" }
+ T (d->c[1].b->a); // { dg-warning "address of 'B::a'" }
+ T (d->c->b[2].a->ia); // { dg-warning "address of 'A::ia'" }
+
+ if (d->c->b[2].a[1].ia) // { dg-warning "address of 'A::ia'" }
+ T (0);
+
+ if (bool b = d->c->b[1].a) // { dg-warning "address of 'B::a'" }
+ T (b);
+
+ /* The following is represented as a declaration of P followed
+ by an if statement and so it isn't diagnosed. It's not clear
+ that it should be since the pointer is then used.
+ void *p = d->c->b[2].a;
+ if (p) ...
+ */
+ if (void *p = d->c->b[2].a) // { dg-warning "address of 'A::ia'" "" { xfail *-*-* } }
+ T (p);
+}
+
+
+void test_waddress_2d (int i)
+{
+ D d[2][3]; // { dg-message "'d' declared here" }
+
+ T (d); // { dg-warning "address of 'd'" }
+ T (d == nullptr); // { dg-warning "address of 'd'" }
+ T (&d); // { dg-warning "address of 'd'" }
+ T (*d); // { dg-warning "address of 'd'" }
+ T (d[1] != nullptr); // { dg-warning "address of 'd'" }
+ T (&d[1]->c); // { dg-warning "address of 'D::c'" }
+ T (d[1]->c); // { dg-warning "address of 'D::c'" }
+ T (d[1]->c == nullptr); // { dg-warning "address of 'D::c'" }
+ T (d[i]->c[1].b); // { dg-warning "address of 'C::b'" }
+ T ((*(d + i))->c->b->a); // { dg-warning "address of 'B::a'" }
+ T (d[1][2].c->b->a->ia); // { dg-warning "address of 'A::ia'" }
+}
</cut>
4 years
- 1
- 0
[TCWG CI] 458.sjeng grew in size by 4% after gcc: aarch64: Improve size heuristic for cpymem expansion
by ci_notify＠linaro.org
After gcc commit a459ee44c0a74b0df0485ed7a56683816c02aae9
Author: Kyrylo Tkachov <kyrylo.tkachov(a)arm.com>
aarch64: Improve size heuristic for cpymem expansion
the following benchmarks grew in size by more than 1%:
- 458.sjeng grew in size by 4% from 105780 to 109944 bytes
- 459.GemsFDTD grew in size by 2% from 247504 to 251468 bytes
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: GCC + Glibc + GNU Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -Os -flto
- Hardware: APM Mustang 8x X-Gene1
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_gnu_apm/gnu-master-aarch64-spec2k6-Os_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa…
Reproduce builds:
<cut>
mkdir investigate-gcc-a459ee44c0a74b0df0485ed7a56683816c02aae9
cd investigate-gcc-a459ee44c0a74b0df0485ed7a56683816c02aae9
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_apm-gnu-master-aa… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach a459ee44c0a74b0df0485ed7a56683816c02aae9
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 8f95e3c04d659d541ca4937b3df2f1175a1c5f05
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit a459ee44c0a74b0df0485ed7a56683816c02aae9
Author: Kyrylo Tkachov <kyrylo.tkachov(a)arm.com>
Date: Wed Sep 29 11:21:45 2021 +0100
aarch64: Improve size heuristic for cpymem expansion
Similar to my previous patch for setmem this one does the same for the cpymem expansion.
We count the number of ops emitted and compare it against the alternative of just calling
the library function when optimising for size.
For the code:
void
cpy_127 (char *out, char *in)
{
__builtin_memcpy (out, in, 127);
}
void
cpy_128 (char *out, char *in)
{
__builtin_memcpy (out, in, 128);
}
we now emit a call to memcpy (with an extra MOV-immediate instruction for the size) instead of:
cpy_127(char*, char*):
ldp q0, q1, [x1]
stp q0, q1, [x0]
ldp q0, q1, [x1, 32]
stp q0, q1, [x0, 32]
ldp q0, q1, [x1, 64]
stp q0, q1, [x0, 64]
ldr q0, [x1, 96]
str q0, [x0, 96]
ldr q0, [x1, 111]
str q0, [x0, 111]
ret
cpy_128(char*, char*):
ldp q0, q1, [x1]
stp q0, q1, [x0]
ldp q0, q1, [x1, 32]
stp q0, q1, [x0, 32]
ldp q0, q1, [x1, 64]
stp q0, q1, [x0, 64]
ldp q0, q1, [x1, 96]
stp q0, q1, [x0, 96]
ret
which is a clear code size win. Speed optimisation heuristics remain unchanged.
2021-09-29 Kyrylo Tkachov <kyrylo.tkachov(a)arm.com>
* config/aarch64/aarch64.c (aarch64_expand_cpymem): Count number of
emitted operations and adjust heuristic for code size.
2021-09-29 Kyrylo Tkachov <kyrylo.tkachov(a)arm.com>
* gcc.target/aarch64/cpymem-size.c: New test.
---
gcc/config/aarch64/aarch64.c | 36 ++++++++++++++++++--------
gcc/testsuite/gcc.target/aarch64/cpymem-size.c | 29 +++++++++++++++++++++
2 files changed, 54 insertions(+), 11 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ac17c1c88fb..a9a1800af53 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -23390,7 +23390,8 @@ aarch64_copy_one_block_and_progress_pointers (rtx *src, rtx *dst,
}
/* Expand cpymem, as if from a __builtin_memcpy. Return true if
- we succeed, otherwise return false. */
+ we succeed, otherwise return false, indicating that a libcall to
+ memcpy should be emitted. */
bool
aarch64_expand_cpymem (rtx *operands)
@@ -23407,11 +23408,13 @@ aarch64_expand_cpymem (rtx *operands)
unsigned HOST_WIDE_INT size = INTVAL (operands[2]);
- /* Inline up to 256 bytes when optimizing for speed. */
+ /* Try to inline up to 256 bytes. */
unsigned HOST_WIDE_INT max_copy_size = 256;
- if (optimize_function_for_size_p (cfun))
- max_copy_size = 128;
+ bool size_p = optimize_function_for_size_p (cfun);
+
+ if (size > max_copy_size)
+ return false;
int copy_bits = 256;
@@ -23421,13 +23424,14 @@ aarch64_expand_cpymem (rtx *operands)
|| !TARGET_SIMD
|| (aarch64_tune_params.extra_tuning_flags
& AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS))
- {
- copy_bits = 128;
- max_copy_size = max_copy_size / 2;
- }
+ copy_bits = 128;
- if (size > max_copy_size)
- return false;
+ /* Emit an inline load+store sequence and count the number of operations
+ involved. We use a simple count of just the loads and stores emitted
+ rather than rtx_insn count as all the pointer adjustments and reg copying
+ in this function will get optimized away later in the pipeline. */
+ start_sequence ();
+ unsigned nops = 0;
base = copy_to_mode_reg (Pmode, XEXP (dst, 0));
dst = adjust_automodify_address (dst, VOIDmode, base, 0);
@@ -23456,7 +23460,8 @@ aarch64_expand_cpymem (rtx *operands)
cur_mode = V4SImode;
aarch64_copy_one_block_and_progress_pointers (&src, &dst, cur_mode);
-
+ /* A single block copy is 1 load + 1 store. */
+ nops += 2;
n -= mode_bits;
/* Emit trailing copies using overlapping unaligned accesses - this is
@@ -23471,7 +23476,16 @@ aarch64_expand_cpymem (rtx *operands)
n = n_bits;
}
}
+ rtx_insn *seq = get_insns ();
+ end_sequence ();
+
+ /* A memcpy libcall in the worst case takes 3 instructions to prepare the
+ arguments + 1 for the call. */
+ unsigned libcall_cost = 4;
+ if (size_p && libcall_cost < nops)
+ return false;
+ emit_insn (seq);
return true;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/cpymem-size.c b/gcc/testsuite/gcc.target/aarch64/cpymem-size.c
new file mode 100644
index 00000000000..4d488b74301
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cpymem-size.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+#include <stdlib.h>
+
+/*
+** cpy_127:
+** mov x2, 127
+** b memcpy
+*/
+void
+cpy_127 (char *out, char *in)
+{
+ __builtin_memcpy (out, in, 127);
+}
+
+/*
+** cpy_128:
+** mov x2, 128
+** b memcpy
+*/
+void
+cpy_128 (char *out, char *in)
+{
+ __builtin_memcpy (out, in, 128);
+}
+
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
</cut>
4 years
- 2
- 2
[TCWG CI] Regression caused by gcc: [PR102546] X << Y being non-zero implies X is also non-zero.
by ci_notify＠linaro.org
[TCWG CI] Regression caused by gcc: [PR102546] X << Y being non-zero implies X is also non-zero.:
commit 5f9ccf17de7f7581412c6bffd4a37beca9a79836
Author: Aldy Hernandez <aldyh(a)redhat.com>
[PR102546] X << Y being non-zero implies X is also non-zero.
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
18603
# First few build errors in logs:
# 00:01:53 arch/arm/vfp/vfpdouble.c:1206:1: internal compiler error: in upper_bound, at value-range.h:531
# 00:01:53 arch/arm/vfp/vfpsingle.c:1246:1: internal compiler error: in upper_bound, at value-range.h:531
# 00:01:53 make[2]: *** [scripts/Makefile.build:271: arch/arm/vfp/vfpdouble.o] Error 1
# 00:01:54 make[2]: *** [scripts/Makefile.build:271: arch/arm/vfp/vfpsingle.o] Error 1
# 00:01:55 make[1]: *** [scripts/Makefile.build:514: arch/arm/vfp] Error 2
# 00:01:56 arch/arm/nwfpe/softfloat.c:3432:1: internal compiler error: in upper_bound, at value-range.h:531
# 00:01:57 make[2]: *** [scripts/Makefile.build:271: arch/arm/nwfpe/softfloat.o] Error 1
# 00:01:57 make[1]: *** [scripts/Makefile.build:514: arch/arm/nwfpe] Error 2
# 00:02:14 arch/arm/kernel/smp.c:857:1: internal compiler error: in upper_bound, at value-range.h:531
# 00:02:15 make[2]: *** [scripts/Makefile.build:271: arch/arm/kernel/smp.o] Error 1
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
19709
# linux build successful:
all
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_kernel/gnu-master-arm-stable-allyesconfig
First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-stable-ally…
Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-stable-ally…
Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-stable-ally…
Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-stable-ally…
Reproduce builds:
<cut>
mkdir investigate-gcc-5f9ccf17de7f7581412c6bffd4a37beca9a79836
cd investigate-gcc-5f9ccf17de7f7581412c6bffd4a37beca9a79836
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-stable-ally… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-stable-ally… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-stable-ally… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach 5f9ccf17de7f7581412c6bffd4a37beca9a79836
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 257d2890a769a8aa564d079170377e637e07acb1
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 5f9ccf17de7f7581412c6bffd4a37beca9a79836
Author: Aldy Hernandez <aldyh(a)redhat.com>
Date: Fri Oct 1 13:05:36 2021 +0200
[PR102546] X << Y being non-zero implies X is also non-zero.
This patch teaches this to range-ops.
Tested on x86-64 Linux.
gcc/ChangeLog:
PR tree-optimization/102546
* range-op.cc (operator_lshift::op1_range): Teach range-ops that
X << Y is non-zero implies X is also non-zero.
---
gcc/range-op.cc | 18 ++++++++++++++----
gcc/testsuite/gcc.dg/tree-ssa/pr102546.c | 23 +++++++++++++++++++++++
2 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/gcc/range-op.cc b/gcc/range-op.cc
index 5e37133026d..2baca4a197f 100644
--- a/gcc/range-op.cc
+++ b/gcc/range-op.cc
@@ -2078,6 +2078,12 @@ operator_lshift::op1_range (irange &r,
relation_kind rel ATTRIBUTE_UNUSED) const
{
tree shift_amount;
+
+ if (!lhs.contains_p (build_zero_cst (type)))
+ r.set_nonzero (type);
+ else
+ r.set_varying (type);
+
if (op2.singleton_p (&shift_amount))
{
wide_int shift = wi::to_wide (shift_amount);
@@ -2089,21 +2095,24 @@ operator_lshift::op1_range (irange &r,
return false;
if (shift == 0)
{
- r = lhs;
+ r.intersect (lhs);
return true;
}
// Work completely in unsigned mode to start.
tree utype = type;
+ int_range_max tmp_range;
if (TYPE_SIGN (type) == SIGNED)
{
int_range_max tmp = lhs;
utype = unsigned_type_for (type);
range_cast (tmp, utype);
- op_rshift.fold_range (r, utype, tmp, op2);
+ op_rshift.fold_range (tmp_range, utype, tmp, op2);
}
else
- op_rshift.fold_range (r, utype, lhs, op2);
+ op_rshift.fold_range (tmp_range, utype, lhs, op2);
+
+ r.intersect (tmp_range);
// Start with ranges which can produce the LHS by right shifting the
// result by the shift amount.
@@ -2128,7 +2137,8 @@ operator_lshift::op1_range (irange &r,
range_cast (r, type);
return true;
}
- return false;
+
+ return !r.varying_p ();
}
bool
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr102546.c b/gcc/testsuite/gcc.dg/tree-ssa/pr102546.c
new file mode 100644
index 00000000000..4bd98747732
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr102546.c
@@ -0,0 +1,23 @@
+// { dg-do compile }
+// { dg-options "-O3 -fdump-tree-optimized" }
+
+static int a;
+static char b, c, d;
+void bar(void);
+void foo(void);
+
+int main() {
+ int f = 0;
+ for (; f <= 5; f++) {
+ bar();
+ b = b && f;
+ d = f << f;
+ if (!(a >= d || f))
+ foo();
+ c = 1;
+ for (; c; c = 0)
+ ;
+ }
+}
+
+// { dg-final { scan-tree-dump-not "foo" "optimized" } }
</cut>
4 years
- 2
- 1
Re: [TCWG CI] 400.perlbench slowed down by 6% after llvm: [SimplifyCFG] Ignore free instructions when computing cost for folding branch to common dest
by Maxim Kuvyrkov
Hi Arthur,
Thanks for looking into this!
The flags to compile regexec.c were:
-O3 --target=aarch64-linux-gnu -fgnu89-inline
Clang was configured with (on x86_64-linux-gnu host):
cmake -G Ninja ../llvm/llvm '-DLLVM_ENABLE_PROJECTS=clang;lld' -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_ASSERTIONS=True -DCMAKE_INSTALL_PREFIX=../llvm-install -DLLVM_TARGETS_TO_BUILD=AArch64
Please let me know if the above doesn’t work for you.
Regards,
--
Maxim Kuvyrkov
https://www.linaro.org
> On 29 Sep 2021, at 20:47, Arthur Eubanks <aeubanks(a)google.com> wrote:
>
> Do you know the flags passed to Clang to compile the sources? I tried compiling the preprocessed sources but ran into the below, and couldn't find the flags in any of the logs.
>
> In file included from regexec.c:93:
> In file included from ./perl.h:384:
> In file included from /home/tcwg-buildslave/workspace/tcwg_bmk_0/abe/builds/destdir/x86_64-pc-linux-gnu/aarch64-linux-gnu/libc/usr/include/sys/types.h:144:
> /home/tcwg-buildslave/workspace/tcwg_bmk_0/llvm-install/lib/clang/14.0.0/include/stddef.h:46:27: error: typedef redefinition with different types ('unsigned long' vs 'unsigned long long')
> typedef long unsigned int size_t;
> ^
> 1 error generated.
>
>
>
> And yeah just moving the code around could cause major performance regressions, I've had other patches do the same for various benchmarks, there's not much we can do about that if that's actually the root cause. If I can compile the file I can check if the optimization actually created worse IR or not.
>
>
> On Wed, Sep 29, 2021 at 5:59 AM Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org> wrote:
> Hi Arthur,
>
> Pre-processed source is in the save-temps tarballs linked below; S_regmatch() is in regexec.i .
>
> The save-temps also have .s assembly file for before and after your patch, and the only code-gen difference is in S_reginclass() function — see the attached screenshot #1.
>
> Looking into profile of S_regmatch(), some of the extra cycles come from hot loop starting with “cbz w19,...” getting misaligned — before your patch it was starting at "2bce10", and after it starts at "2bce6c”.
>
> Maybe the added instructions in S_reginclass() pushed the loop in S_regmatch() in an unfortunate way?
>
> --
> Maxim Kuvyrkov
> https://www.linaro.org
>
>> On 27 Sep 2021, at 20:05, Arthur Eubanks <aeubanks(a)google.com> wrote:
>>
>> Could I get the source file with S_regmatch()?
>>
>> On Mon, Sep 27, 2021 at 6:07 AM Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org> wrote:
>> Hi Arthur,
>>
>> Your patch seems to be slowing down 400.perlbench by 6% — due to slow down of its hot function S_regmatch() by 14%.
>>
>> Could you take a look if this is easily fixable, please?
>>
>> Regards,
>>
>> --
>> Maxim Kuvyrkov
>> https://www.linaro.org
>>
>> > On 24 Sep 2021, at 15:07, ci_notify(a)linaro.org wrote:
>> >
>> > After llvm commit e7249e4acf3cf9438d6d9e02edecebd5b622a4dc
>> > Author: Arthur Eubanks <aeubanks(a)google.com>
>> >
>> > [SimplifyCFG] Ignore free instructions when computing cost for folding branch to common dest
>> >
>> > the following benchmarks slowed down by more than 2%:
>> > - 400.perlbench slowed down by 6% from 9730 to 10312 perf samples
>> > - 400.perlbench:[.] S_regmatch slowed down by 14% from 3660 to 4188 perf samples
>> >
>> > Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
>> >
>> > For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
>> > - First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
>> > - Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
>> > - Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
>> >
>> > Configuration:
>> > - Benchmark: SPEC CPU2006
>> > - Toolchain: Clang + Glibc + LLVM Linker
>> > - Version: all components were built from their tip of trunk
>> > - Target: aarch64-linux-gnu
>> > - Compiler flags: -O3
>> > - Hardware: NVidia TX1 4x Cortex-A57
>> >
>> > This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
>
> <2021-09-29_15-44-27.png><2021-09-29_15-53-20.png>
4 years
- 2
- 3
[TCWG CI] 456.hmmer slowed down by 5% after llvm: Revert "Allow rematerialization of virtual reg uses"
by ci_notify＠linaro.org
After llvm commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Revert "Allow rematerialization of virtual reg uses"
the following benchmarks slowed down by more than 2%:
- 456.hmmer slowed down by 5% from 7649 to 8028 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: arm-linux-gnueabihf
- Compiler flags: -O2 -flto -marm
- Hardware: NVidia TK1 4x Cortex-A15
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tk1/llvm-master-arm-spec2k6-O2_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
cd investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 08d7eec06e8cf5c15a96ce11f311f1480291a441
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Date: Fri Sep 24 09:53:51 2021 -0700
Revert "Allow rematerialization of virtual reg uses"
Reverted due to two distcint performance regression reports.
This reverts commit 92c1fd19abb15bc68b1127a26137a69e033cdb39.
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 12 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 9 +-
llvm/test/CodeGen/AMDGPU/remat-sop.mir | 60 -
llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll | 28 +-
llvm/test/CodeGen/ARM/funnel-shift-rot.ll | 32 +-
llvm/test/CodeGen/ARM/funnel-shift.ll | 30 +-
.../test/CodeGen/ARM/illegal-bitfield-loadstore.ll | 30 +-
llvm/test/CodeGen/ARM/neon-copy.ll | 10 +-
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 227 +-
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 206 +-
llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 95 +-
llvm/test/CodeGen/Mips/llvm-ir/sub.ll | 31 +-
llvm/test/CodeGen/Mips/tls.ll | 4 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 120 +-
llvm/test/CodeGen/RISCV/atomic-signext.ll | 24 +-
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 96 +-
llvm/test/CodeGen/RISCV/mul.ll | 72 +-
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll | 12 +-
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll | 270 +-
llvm/test/CodeGen/RISCV/rv32zbb.ll | 94 +-
llvm/test/CodeGen/RISCV/rv32zbp.ll | 262 +-
llvm/test/CodeGen/RISCV/rv32zbt.ll | 206 +-
.../CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll | 150 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 146 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 3584 ++++++++++----------
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 664 ++--
llvm/test/CodeGen/RISCV/shifts.ll | 308 +-
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 208 +-
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 190 +-
llvm/test/CodeGen/Thumb/dyn-stackalloc.ll | 7 +-
.../tail-pred-disabled-in-loloops.ll | 14 +-
.../LowOverheadLoops/varying-outer-2d-reduction.ll | 64 +-
.../CodeGen/Thumb2/LowOverheadLoops/while-loops.ll | 67 +-
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll | 30 +-
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll | 82 +-
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll | 98 +-
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll | 529 +--
llvm/test/CodeGen/X86/addcarry.ll | 20 +-
llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll | 12 +-
llvm/test/CodeGen/X86/dag-update-nodetomatch.ll | 17 +-
.../X86/delete-dead-instrs-with-live-uses.mir | 4 +-
llvm/test/CodeGen/X86/inalloca-invoke.ll | 2 +-
llvm/test/CodeGen/X86/licm-regpressure.ll | 28 +-
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 40 +-
llvm/test/CodeGen/X86/sdiv_fix.ll | 5 +-
45 files changed, 4093 insertions(+), 4106 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index a0c52e2f1a13..c394ac910be1 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -117,11 +117,10 @@ public:
const MachineFunction &MF) const;
/// Return true if the instruction is trivially rematerializable, meaning it
- /// has no side effects. Uses of constants and unallocatable physical
- /// registers are always trivial to rematerialize so that the instructions
- /// result is independent of the place in the function. Uses of virtual
- /// registers are allowed but it is caller's responsility to ensure these
- /// operands are valid at the point the instruction is beeing moved.
+ /// has no side effects and requires no operands that aren't always available.
+ /// This means the only allowed uses are constants and unallocatable physical
+ /// registers so that the instructions result is independent of the place
+ /// in the function.
bool isTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA = nullptr) const {
return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
@@ -141,7 +140,8 @@ protected:
/// set, this hook lets the target specify whether the instruction is actually
/// trivially rematerializable, taking into consideration its operands. This
/// predicate must return false if the instruction has any side effects other
- /// than producing a value.
+ /// than producing a value, or if it requres any address registers that are
+ /// not always available.
/// Requirements must be check as stated in isTriviallyReMaterializable() .
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA) const {
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index fe7d60e0b7e2..1eab8e7443a7 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -921,8 +921,7 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
const MachineRegisterInfo &MRI = MF.getRegInfo();
// Remat clients assume operand 0 is the defined register.
- if (!MI.getNumOperands() || !MI.getOperand(0).isReg() ||
- MI.getOperand(0).isTied())
+ if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
return false;
Register DefReg = MI.getOperand(0).getReg();
@@ -984,6 +983,12 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
// same virtual register, though.
if (MO.isDef() && Reg != DefReg)
return false;
+
+ // Don't allow any virtual-register uses. Rematting an instruction with
+ // virtual register uses would length the live ranges of the uses, which
+ // is not necessarily a good idea, certainly not "trivial".
+ if (MO.isUse())
+ return false;
}
// Everything checked out.
diff --git a/llvm/test/CodeGen/AMDGPU/remat-sop.mir b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
index c9915aaabfde..ed799bfca028 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-sop.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
@@ -51,66 +51,6 @@ body: |
S_NOP 0, implicit %2
S_ENDPGM 0
...
-# The liverange of %0 covers a point of rematerialization, source value is
-# availabe.
----
-name: test_remat_s_mov_b32_vreg_src_long_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_remat_s_mov_b32_vreg_src_long_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_NOP 0, implicit %0
- S_ENDPGM 0
-...
-# The liverange of %0 does not cover a point of rematerialization, source value is
-# unavailabe and we do not want to artificially extend the liverange.
----
-name: test_no_remat_s_mov_b32_vreg_src_short_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_no_remat_s_mov_b32_vreg_src_short_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.1, addrspace 5)
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.0, addrspace 5)
- ; GCN: renamable $sgpr0 = S_MOV_B32 killed renamable $sgpr0
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.1, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.0, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_ENDPGM 0
-...
---
name: test_remat_s_mov_b64
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
index 175a2069a441..a4243276c70a 100644
--- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
+++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
@@ -29,20 +29,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; ENABLE-NEXT: pophs {r11, pc}
; ENABLE-NEXT: .LBB0_3: @ %while.body.preheader
; ENABLE-NEXT: movw r12, :lower16:skip
-; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: sub r1, r1, #1
; ENABLE-NEXT: movt r12, :upper16:skip
; ENABLE-NEXT: .LBB0_4: @ %while.body
; ENABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; ENABLE-NEXT: ldrb r1, [r0]
-; ENABLE-NEXT: ldrb r1, [r12, r1]
-; ENABLE-NEXT: add r0, r0, r1
-; ENABLE-NEXT: sub r1, r3, #1
-; ENABLE-NEXT: cmp r1, r3
+; ENABLE-NEXT: ldrb r3, [r0]
+; ENABLE-NEXT: ldrb r3, [r12, r3]
+; ENABLE-NEXT: add r0, r0, r3
+; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: cmp r3, r1
; ENABLE-NEXT: bhs .LBB0_6
; ENABLE-NEXT: @ %bb.5: @ %while.body
; ENABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; ENABLE-NEXT: cmp r0, r2
-; ENABLE-NEXT: mov r3, r1
+; ENABLE-NEXT: mov r1, r3
; ENABLE-NEXT: blo .LBB0_4
; ENABLE-NEXT: .LBB0_6: @ %if.end29
; ENABLE-NEXT: pop {r11, pc}
@@ -119,20 +119,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; DISABLE-NEXT: pophs {r11, pc}
; DISABLE-NEXT: .LBB0_3: @ %while.body.preheader
; DISABLE-NEXT: movw r12, :lower16:skip
-; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: sub r1, r1, #1
; DISABLE-NEXT: movt r12, :upper16:skip
; DISABLE-NEXT: .LBB0_4: @ %while.body
; DISABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; DISABLE-NEXT: ldrb r1, [r0]
-; DISABLE-NEXT: ldrb r1, [r12, r1]
-; DISABLE-NEXT: add r0, r0, r1
-; DISABLE-NEXT: sub r1, r3, #1
-; DISABLE-NEXT: cmp r1, r3
+; DISABLE-NEXT: ldrb r3, [r0]
+; DISABLE-NEXT: ldrb r3, [r12, r3]
+; DISABLE-NEXT: add r0, r0, r3
+; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: cmp r3, r1
; DISABLE-NEXT: bhs .LBB0_6
; DISABLE-NEXT: @ %bb.5: @ %while.body
; DISABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; DISABLE-NEXT: cmp r0, r2
-; DISABLE-NEXT: mov r3, r1
+; DISABLE-NEXT: mov r1, r3
; DISABLE-NEXT: blo .LBB0_4
; DISABLE-NEXT: .LBB0_6: @ %if.end29
; DISABLE-NEXT: pop {r11, pc}
diff --git a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
index ea15fcc5c824..55157875d355 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
@@ -73,13 +73,13 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: push {r4, r5, r11, lr}
; SCALAR-NEXT: rsb r3, r2, #0
; SCALAR-NEXT: and r4, r2, #63
-; SCALAR-NEXT: and r12, r3, #63
-; SCALAR-NEXT: rsb r3, r12, #32
+; SCALAR-NEXT: and lr, r3, #63
+; SCALAR-NEXT: rsb r3, lr, #32
; SCALAR-NEXT: lsl r2, r0, r4
-; SCALAR-NEXT: lsr lr, r0, r12
-; SCALAR-NEXT: orr r3, lr, r1, lsl r3
-; SCALAR-NEXT: subs lr, r12, #32
-; SCALAR-NEXT: lsrpl r3, r1, lr
+; SCALAR-NEXT: lsr r12, r0, lr
+; SCALAR-NEXT: orr r3, r12, r1, lsl r3
+; SCALAR-NEXT: subs r12, lr, #32
+; SCALAR-NEXT: lsrpl r3, r1, r12
; SCALAR-NEXT: subs r5, r4, #32
; SCALAR-NEXT: movwpl r2, #0
; SCALAR-NEXT: cmp r5, #0
@@ -88,8 +88,8 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: lsr r3, r0, r3
; SCALAR-NEXT: orr r3, r3, r1, lsl r4
; SCALAR-NEXT: lslpl r3, r0, r5
-; SCALAR-NEXT: lsr r0, r1, r12
-; SCALAR-NEXT: cmp lr, #0
+; SCALAR-NEXT: lsr r0, r1, lr
+; SCALAR-NEXT: cmp r12, #0
; SCALAR-NEXT: movwpl r0, #0
; SCALAR-NEXT: orr r1, r3, r0
; SCALAR-NEXT: mov r0, r2
@@ -245,15 +245,15 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r11, lr}
; CHECK-NEXT: push {r4, r5, r11, lr}
-; CHECK-NEXT: and r12, r2, #63
+; CHECK-NEXT: and lr, r2, #63
; CHECK-NEXT: rsb r2, r2, #0
-; CHECK-NEXT: rsb r3, r12, #32
+; CHECK-NEXT: rsb r3, lr, #32
; CHECK-NEXT: and r4, r2, #63
-; CHECK-NEXT: lsr lr, r0, r12
-; CHECK-NEXT: orr r3, lr, r1, lsl r3
-; CHECK-NEXT: subs lr, r12, #32
+; CHECK-NEXT: lsr r12, r0, lr
+; CHECK-NEXT: orr r3, r12, r1, lsl r3
+; CHECK-NEXT: subs r12, lr, #32
; CHECK-NEXT: lsl r2, r0, r4
-; CHECK-NEXT: lsrpl r3, r1, lr
+; CHECK-NEXT: lsrpl r3, r1, r12
; CHECK-NEXT: subs r5, r4, #32
; CHECK-NEXT: movwpl r2, #0
; CHECK-NEXT: cmp r5, #0
@@ -262,8 +262,8 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-NEXT: lsr r3, r0, r3
; CHECK-NEXT: orr r3, r3, r1, lsl r4
; CHECK-NEXT: lslpl r3, r0, r5
-; CHECK-NEXT: lsr r0, r1, r12
-; CHECK-NEXT: cmp lr, #0
+; CHECK-NEXT: lsr r0, r1, lr
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r0, #0
; CHECK-NEXT: orr r1, r0, r3
; CHECK-NEXT: mov r0, r2
diff --git a/llvm/test/CodeGen/ARM/funnel-shift.ll b/llvm/test/CodeGen/ARM/funnel-shift.ll
index 6372f9be2ca3..54c93b493c98 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift.ll
@@ -224,31 +224,31 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: bl __aeabi_uldivmod
; CHECK-NEXT: add r0, r2, #27
-; CHECK-NEXT: lsl r2, r7, #27
-; CHECK-NEXT: and r12, r0, #63
; CHECK-NEXT: lsl r6, r6, #27
+; CHECK-NEXT: and r1, r0, #63
+; CHECK-NEXT: lsl r2, r7, #27
; CHECK-NEXT: orr r7, r6, r7, lsr #5
-; CHECK-NEXT: rsb r3, r12, #32
-; CHECK-NEXT: lsr r2, r2, r12
; CHECK-NEXT: mov r6, #63
-; CHECK-NEXT: orr r2, r2, r7, lsl r3
-; CHECK-NEXT: subs r3, r12, #32
+; CHECK-NEXT: rsb r3, r1, #32
+; CHECK-NEXT: lsr r2, r2, r1
+; CHECK-NEXT: subs r12, r1, #32
; CHECK-NEXT: bic r6, r6, r0
+; CHECK-NEXT: orr r2, r2, r7, lsl r3
; CHECK-NEXT: lsl r5, r9, #1
-; CHECK-NEXT: lsrpl r2, r7, r3
-; CHECK-NEXT: subs r1, r6, #32
+; CHECK-NEXT: lsrpl r2, r7, r12
; CHECK-NEXT: lsl r0, r5, r6
-; CHECK-NEXT: lsl r4, r8, #1
+; CHECK-NEXT: subs r4, r6, #32
+; CHECK-NEXT: lsl r3, r8, #1
; CHECK-NEXT: movwpl r0, #0
-; CHECK-NEXT: orr r4, r4, r9, lsr #31
+; CHECK-NEXT: orr r3, r3, r9, lsr #31
; CHECK-NEXT: orr r0, r0, r2
; CHECK-NEXT: rsb r2, r6, #32
-; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: lsr r1, r7, r1
; CHECK-NEXT: lsr r2, r5, r2
-; CHECK-NEXT: orr r2, r2, r4, lsl r6
-; CHECK-NEXT: lslpl r2, r5, r1
-; CHECK-NEXT: lsr r1, r7, r12
-; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: orr r2, r2, r3, lsl r6
+; CHECK-NEXT: lslpl r2, r5, r4
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r1, #0
; CHECK-NEXT: orr r1, r2, r1
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
diff --git a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
index 0a0bb62b0a09..2922e0ed5423 100644
--- a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
+++ b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
@@ -91,17 +91,17 @@ define void @i56_or(i56* %a) {
; BE-LABEL: i56_or:
; BE: @ %bb.0:
; BE-NEXT: mov r1, r0
+; BE-NEXT: ldr r12, [r0]
; BE-NEXT: ldrh r2, [r1, #4]!
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: orr r2, r3, r2, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: strb r12, [r1, #2]
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: strb r2, [r1, #2]
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
%aa = load i56, i56* %a
@@ -127,13 +127,13 @@ define void @i56_and_or(i56* %a) {
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: strb r2, [r1, #2]
; BE-NEXT: orr r2, r3, r12, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: ldr r12, [r0]
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
diff --git a/llvm/test/CodeGen/ARM/neon-copy.ll b/llvm/test/CodeGen/ARM/neon-copy.ll
index 46490efb6631..09a991da2e59 100644
--- a/llvm/test/CodeGen/ARM/neon-copy.ll
+++ b/llvm/test/CodeGen/ARM/neon-copy.ll
@@ -1340,16 +1340,16 @@ define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, sp, #8
; CHECK-NEXT: vmov.u16 r1, d0[1]
-; CHECK-NEXT: and r12, r0, #3
+; CHECK-NEXT: and r0, r0, #3
; CHECK-NEXT: vmov.u16 r2, d0[2]
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vmov.u16 r3, d0[3]
-; CHECK-NEXT: orr r0, r0, r12, lsl #1
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vmov.u16 r12, d0[3]
+; CHECK-NEXT: orr r0, r3, r0, lsl #1
; CHECK-NEXT: vst1.16 {d0[0]}, [r0:16]
; CHECK-NEXT: vldr d0, [sp]
; CHECK-NEXT: vmov.16 d0[1], r1
; CHECK-NEXT: vmov.16 d0[2], r2
-; CHECK-NEXT: vmov.16 d0[3], r3
+; CHECK-NEXT: vmov.16 d0[3], r12
; CHECK-NEXT: add sp, sp, #8
; CHECK-NEXT: bx lr
%tmp = extractelement <8 x i16> %x, i32 0
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index a125446b27c3..8be7100d368b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -766,85 +766,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: move $2, $6
-; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
-; MMR3-NEXT: srlv $3, $7, $16
-; MMR3-NEXT: not16 $6, $16
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sll16 $2, $2, 1
-; MMR3-NEXT: sllv $2, $2, $6
-; MMR3-NEXT: li16 $6, 64
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: srlv $4, $4, $16
-; MMR3-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
-; MMR3-NEXT: subu16 $7, $6, $16
+; MMR3-NEXT: srlv $4, $7, $16
+; MMR3-NEXT: not16 $3, $16
+; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sll16 $2, $6, 1
+; MMR3-NEXT: sllv $3, $2, $3
+; MMR3-NEXT: li16 $2, 64
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: srlv $6, $6, $16
+; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: subu16 $7, $2, $16
; MMR3-NEXT: sllv $9, $5, $7
-; MMR3-NEXT: andi16 $5, $7, 32
-; MMR3-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
-; MMR3-NEXT: andi16 $6, $16, 32
-; MMR3-NEXT: sw $6, 36($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $3, $9
+; MMR3-NEXT: andi16 $2, $7, 32
+; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $5, $16, 32
+; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
+; MMR3-NEXT: move $4, $9
; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $3, $17, $5
-; MMR3-NEXT: movn $2, $4, $6
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: lw $17, 0($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $4, $17, $4
-; MMR3-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $6, 1
-; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $3
-; MMR3-NEXT: addiu $3, $16, -64
-; MMR3-NEXT: srav $1, $6, $3
-; MMR3-NEXT: andi16 $3, $3, 32
-; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $3
-; MMR3-NEXT: sllv $3, $6, $7
-; MMR3-NEXT: sw $3, 4($sp) # 4-byte Folded Spill
-; MMR3-NEXT: not16 $3, $7
-; MMR3-NEXT: srl16 $4, $17, 1
-; MMR3-NEXT: srlv $3, $4, $3
+; MMR3-NEXT: movn $4, $17, $2
+; MMR3-NEXT: movn $3, $6, $5
+; MMR3-NEXT: addiu $2, $16, -64
+; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srlv $5, $5, $2
+; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $17, 1
+; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: not16 $5, $2
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $4
+; MMR3-NEXT: srav $1, $17, $2
+; MMR3-NEXT: andi16 $2, $2, 32
+; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $2
+; MMR3-NEXT: sllv $2, $17, $7
+; MMR3-NEXT: not16 $4, $7
+; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $6, $7, 1
+; MMR3-NEXT: srlv $6, $6, $4
; MMR3-NEXT: sltiu $10, $16, 64
-; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $5, $3, $10
+; MMR3-NEXT: or16 $6, $2
+; MMR3-NEXT: srlv $2, $7, $16
+; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
+; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sllv $3, $4, $3
; MMR3-NEXT: or16 $3, $2
-; MMR3-NEXT: srlv $2, $17, $16
-; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $7, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sllv $17, $7, $4
-; MMR3-NEXT: or16 $17, $2
-; MMR3-NEXT: srav $11, $6, $16
-; MMR3-NEXT: lw $2, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $17, $11, $2
-; MMR3-NEXT: sra $2, $6, 31
+; MMR3-NEXT: srav $11, $17, $16
+; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $11, $4
+; MMR3-NEXT: sra $2, $17, 31
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: movn $4, $17, $10
-; MMR3-NEXT: lw $6, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $9, $6
-; MMR3-NEXT: lw $6, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: lw $7, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $3
+; MMR3-NEXT: move $8, $2
+; MMR3-NEXT: movn $8, $3, $10
+; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $6, $9, $3
+; MMR3-NEXT: li16 $3, 0
+; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $7, $3, $4
+; MMR3-NEXT: or16 $7, $6
; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
; MMR3-NEXT: movn $1, $2, $3
; MMR3-NEXT: movn $1, $7, $10
; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $3, $16
-; MMR3-NEXT: movn $11, $2, $6
+; MMR3-NEXT: movn $11, $2, $4
; MMR3-NEXT: movn $2, $11, $10
-; MMR3-NEXT: move $3, $4
+; MMR3-NEXT: move $3, $8
; MMR3-NEXT: move $4, $1
; MMR3-NEXT: lwp $16, 40($sp)
; MMR3-NEXT: addiusp 48
@@ -858,80 +852,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
-; MMR6-NEXT: move $12, $7
+; MMR6-NEXT: move $1, $7
; MMR6-NEXT: lw $3, 44($sp)
; MMR6-NEXT: li16 $2, 64
-; MMR6-NEXT: subu16 $16, $2, $3
-; MMR6-NEXT: sllv $1, $5, $16
-; MMR6-NEXT: andi16 $2, $16, 32
-; MMR6-NEXT: selnez $8, $1, $2
-; MMR6-NEXT: sllv $9, $4, $16
-; MMR6-NEXT: not16 $16, $16
-; MMR6-NEXT: srl16 $17, $5, 1
-; MMR6-NEXT: srlv $10, $17, $16
-; MMR6-NEXT: or $9, $9, $10
-; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $8, $8, $9
-; MMR6-NEXT: srlv $9, $7, $3
-; MMR6-NEXT: not16 $7, $3
-; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill
+; MMR6-NEXT: subu16 $7, $2, $3
+; MMR6-NEXT: sllv $8, $5, $7
+; MMR6-NEXT: andi16 $2, $7, 32
+; MMR6-NEXT: selnez $9, $8, $2
+; MMR6-NEXT: sllv $10, $4, $7
+; MMR6-NEXT: not16 $7, $7
+; MMR6-NEXT: srl16 $16, $5, 1
+; MMR6-NEXT: srlv $7, $16, $7
+; MMR6-NEXT: or $7, $10, $7
+; MMR6-NEXT: seleqz $7, $7, $2
+; MMR6-NEXT: or $7, $9, $7
+; MMR6-NEXT: srlv $9, $1, $3
+; MMR6-NEXT: not16 $16, $3
+; MMR6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $17, $6, 1
-; MMR6-NEXT: sllv $10, $17, $7
+; MMR6-NEXT: sllv $10, $17, $16
; MMR6-NEXT: or $9, $10, $9
; MMR6-NEXT: andi16 $17, $3, 32
; MMR6-NEXT: seleqz $9, $9, $17
; MMR6-NEXT: srlv $10, $6, $3
; MMR6-NEXT: selnez $11, $10, $17
; MMR6-NEXT: seleqz $10, $10, $17
-; MMR6-NEXT: or $8, $10, $8
-; MMR6-NEXT: seleqz $1, $1, $2
-; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: or $10, $10, $7
+; MMR6-NEXT: seleqz $12, $8, $2
+; MMR6-NEXT: or $8, $11, $9
; MMR6-NEXT: addiu $2, $3, -64
-; MMR6-NEXT: srlv $10, $5, $2
+; MMR6-NEXT: srlv $9, $5, $2
; MMR6-NEXT: sll16 $7, $4, 1
; MMR6-NEXT: not16 $16, $2
; MMR6-NEXT: sllv $11, $7, $16
; MMR6-NEXT: sltiu $13, $3, 64
-; MMR6-NEXT: or $1, $9, $1
-; MMR6-NEXT: selnez $8, $8, $13
-; MMR6-NEXT: or $9, $11, $10
-; MMR6-NEXT: srav $10, $4, $2
+; MMR6-NEXT: or $8, $8, $12
+; MMR6-NEXT: selnez $10, $10, $13
+; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: srav $11, $4, $2
; MMR6-NEXT: andi16 $2, $2, 32
-; MMR6-NEXT: seleqz $11, $10, $2
+; MMR6-NEXT: seleqz $12, $11, $2
; MMR6-NEXT: sra $14, $4, 31
; MMR6-NEXT: selnez $15, $14, $2
; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $11, $15, $11
-; MMR6-NEXT: seleqz $11, $11, $13
-; MMR6-NEXT: selnez $2, $10, $2
-; MMR6-NEXT: seleqz $10, $14, $13
-; MMR6-NEXT: or $8, $8, $11
-; MMR6-NEXT: selnez $8, $8, $3
-; MMR6-NEXT: selnez $1, $1, $13
+; MMR6-NEXT: or $12, $15, $12
+; MMR6-NEXT: seleqz $12, $12, $13
+; MMR6-NEXT: selnez $2, $11, $2
+; MMR6-NEXT: seleqz $11, $14, $13
+; MMR6-NEXT: or $10, $10, $12
+; MMR6-NEXT: selnez $10, $10, $3
+; MMR6-NEXT: selnez $8, $8, $13
; MMR6-NEXT: or $2, $2, $9
; MMR6-NEXT: srav $9, $4, $3
; MMR6-NEXT: seleqz $4, $9, $17
-; MMR6-NEXT: selnez $11, $14, $17
-; MMR6-NEXT: or $4, $11, $4
-; MMR6-NEXT: selnez $11, $4, $13
+; MMR6-NEXT: selnez $12, $14, $17
+; MMR6-NEXT: or $4, $12, $4
+; MMR6-NEXT: selnez $12, $4, $13
; MMR6-NEXT: seleqz $2, $2, $13
; MMR6-NEXT: seleqz $4, $6, $3
-; MMR6-NEXT: seleqz $6, $12, $3
+; MMR6-NEXT: seleqz $1, $1, $3
+; MMR6-NEXT: or $2, $8, $2
+; MMR6-NEXT: selnez $2, $2, $3
; MMR6-NEXT: or $1, $1, $2
-; MMR6-NEXT: selnez $1, $1, $3
-; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: or $4, $4, $8
-; MMR6-NEXT: or $6, $11, $10
-; MMR6-NEXT: srlv $2, $5, $3
-; MMR6-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $3, $7, $3
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: seleqz $2, $2, $17
-; MMR6-NEXT: selnez $3, $9, $17
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: selnez $2, $2, $13
-; MMR6-NEXT: or $3, $2, $10
-; MMR6-NEXT: move $2, $6
+; MMR6-NEXT: or $4, $4, $10
+; MMR6-NEXT: or $2, $12, $11
+; MMR6-NEXT: srlv $3, $5, $3
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: sllv $5, $7, $5
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: seleqz $3, $3, $17
+; MMR6-NEXT: selnez $5, $9, $17
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: selnez $3, $3, $13
+; MMR6-NEXT: or $3, $3, $11
; MMR6-NEXT: move $5, $1
; MMR6-NEXT: lw $16, 8($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index e4b4b3ae1d0f..ed2bfc9fcf60 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -776,77 +776,76 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 68($sp)
; MMR3-NEXT: li16 $2, 64
-; MMR3-NEXT: subu16 $17, $2, $16
-; MMR3-NEXT: sllv $9, $5, $17
-; MMR3-NEXT: andi16 $3, $17, 32
+; MMR3-NEXT: subu16 $7, $2, $16
+; MMR3-NEXT: sllv $9, $5, $7
+; MMR3-NEXT: move $17, $5
+; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $3, $7, 32
; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MMR3-NEXT: li16 $2, 0
; MMR3-NEXT: move $4, $9
; MMR3-NEXT: movn $4, $2, $3
-; MMR3-NEXT: srlv $5, $7, $16
+; MMR3-NEXT: srlv $5, $8, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 16($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sllv $2, $2, $3
; MMR3-NEXT: or16 $2, $5
-; MMR3-NEXT: srlv $7, $6, $16
+; MMR3-NEXT: srlv $5, $6, $16
+; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MMR3-NEXT: andi16 $3, $16, 32
; MMR3-NEXT: sw $3, 12($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $2, $7, $3
+; MMR3-NEXT: movn $2, $5, $3
; MMR3-NEXT: addiu $3, $16, -64
; MMR3-NEXT: or16 $2, $4
-; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $3, $6, $3
-; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $3, 1
-; MMR3-NEXT: sw $4, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $4
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: srlv $1, $3, $4
-; MMR3-NEXT: andi16 $4, $4, 32
+; MMR3-NEXT: srlv $4, $17, $3
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $4
+; MMR3-NEXT: lw $4, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $4, 1
+; MMR3-NEXT: not16 $5, $3
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $17
+; MMR3-NEXT: srlv $1, $4, $3
+; MMR3-NEXT: andi16 $3, $3, 32
+; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $3
; MMR3-NEXT: sltiu $10, $16, 64
; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: sllv $2, $3, $17
-; MMR3-NEXT: not16 $3, $17
-; MMR3-NEXT: srl16 $4, $6, 1
+; MMR3-NEXT: sllv $2, $4, $7
+; MMR3-NEXT: not16 $3, $7
+; MMR3-NEXT: lw $7, 0($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $4, $7, 1
; MMR3-NEXT: srlv $4, $4, $3
; MMR3-NEXT: or16 $4, $2
-; MMR3-NEXT: srlv $2, $6, $16
+; MMR3-NEXT: srlv $2, $7, $16
; MMR3-NEXT: lw $3, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $6, 0($sp) # 4-byte Folded Reload
; MMR3-NEXT: sllv $3, $6, $3
; MMR3-NEXT: or16 $3, $2
; MMR3-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MMR3-NEXT: srlv $2, $2, $16
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $2, $6
+; MMR3-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $2, $17
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movz $3, $17, $10
-; MMR3-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $4, $9, $17
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $4
+; MMR3-NEXT: li16 $6, 0
+; MMR3-NEXT: movz $3, $6, $10
+; MMR3-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $4, $9, $7
+; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $6, $7, $17
+; MMR3-NEXT: or16 $6, $4
; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $1, $17, $4
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $1, $7, $10
+; MMR3-NEXT: movn $1, $7, $4
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $1, $6, $10
; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $4, $16
-; MMR3-NEXT: movn $2, $17, $6
+; MMR3-NEXT: movn $2, $7, $17
; MMR3-NEXT: li16 $4, 0
; MMR3-NEXT: movz $2, $4, $10
; MMR3-NEXT: move $4, $1
@@ -856,91 +855,98 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
;
; MMR6-LABEL: lshr_i128:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: addiu $sp, $sp, -24
-; MMR6-NEXT: .cfi_def_cfa_offset 24
-; MMR6-NEXT: sw $17, 20($sp) # 4-byte Folded Spill
-; MMR6-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
+; MMR6-NEXT: addiu $sp, $sp, -32
+; MMR6-NEXT: .cfi_def_cfa_offset 32
+; MMR6-NEXT: sw $17, 28($sp) # 4-byte Folded Spill
+; MMR6-NEXT: sw $16, 24($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
; MMR6-NEXT: move $1, $7
-; MMR6-NEXT: move $7, $4
-; MMR6-NEXT: lw $3, 52($sp)
+; MMR6-NEXT: move $7, $5
+; MMR6-NEXT: lw $3, 60($sp)
; MMR6-NEXT: srlv $2, $1, $3
-; MMR6-NEXT: not16 $16, $3
-; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
-; MMR6-NEXT: move $4, $6
-; MMR6-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $5, $3
+; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: move $17, $6
+; MMR6-NEXT: sw $6, 16($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $6, $6, 1
-; MMR6-NEXT: sllv $6, $6, $16
+; MMR6-NEXT: sllv $6, $6, $5
; MMR6-NEXT: or $8, $6, $2
-; MMR6-NEXT: addiu $6, $3, -64
-; MMR6-NEXT: srlv $9, $5, $6
-; MMR6-NEXT: sll16 $2, $7, 1
-; MMR6-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
-; MMR6-NEXT: not16 $16, $6
+; MMR6-NEXT: addiu $5, $3, -64
+; MMR6-NEXT: srlv $9, $7, $5
+; MMR6-NEXT: move $6, $4
+; MMR6-NEXT: sll16 $2, $4, 1
+; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $16, $5
; MMR6-NEXT: sllv $10, $2, $16
; MMR6-NEXT: andi16 $16, $3, 32
; MMR6-NEXT: seleqz $8, $8, $16
; MMR6-NEXT: or $9, $10, $9
-; MMR6-NEXT: srlv $10, $4, $3
+; MMR6-NEXT: srlv $10, $17, $3
; MMR6-NEXT: selnez $11, $10, $16
; MMR6-NEXT: li16 $17, 64
; MMR6-NEXT: subu16 $2, $17, $3
-; MMR6-NEXT: sllv $12, $5, $2
+; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: move $17, $7
; MMR6-NEXT: andi16 $4, $2, 32
-; MMR6-NEXT: andi16 $17, $6, 32
-; MMR6-NEXT: seleqz $9, $9, $17
+; MMR6-NEXT: andi16 $7, $5, 32
+; MMR6-NEXT: sw $7, 20($sp) # 4-byte Folded Spill
+; MMR6-NEXT: seleqz $9, $9, $7
; MMR6-NEXT: seleqz $13, $12, $4
; MMR6-NEXT: or $8, $11, $8
; MMR6-NEXT: selnez $11, $12, $4
-; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: sllv $12, $6, $2
+; MMR6-NEXT: move $7, $6
+; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: not16 $2, $2
-; MMR6-NEXT: srl16 $6, $5, 1
+; MMR6-NEXT: srl16 $6, $17, 1
; MMR6-NEXT: srlv $2, $6, $2
; MMR6-NEXT: or $2, $12, $2
; MMR6-NEXT: seleqz $2, $2, $4
-; MMR6-NEXT: addiu $4, $3, -64
-; MMR6-NEXT: srlv $4, $7, $4
-; MMR6-NEXT: or $12, $11, $2
-; MMR6-NEXT: or $6, $8, $13
-; MMR6-NEXT: srlv $5, $5, $3
-; MMR6-NEXT: selnez $8, $4, $17
-; MMR6-NEXT: sltiu $11, $3, 64
-; MMR6-NEXT: selnez $13, $6, $11
-; MMR6-NEXT: or $8, $8, $9
+; MMR6-NEXT: srlv $4, $7, $5
+; MMR6-NEXT: or $11, $11, $2
+; MMR6-NEXT: or $5, $8, $13
+; MMR6-NEXT: srlv $6, $17, $3
+; MMR6-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: selnez $7, $4, $2
+; MMR6-NEXT: sltiu $8, $3, 64
+; MMR6-NEXT: selnez $12, $5, $8
+; MMR6-NEXT: or $7, $7, $9
+; MMR6-NEXT: lw $5, 12($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $9, $6, $2
+; MMR6-NEXT: sllv $9, $2, $5
; MMR6-NEXT: seleqz $10, $10, $16
-; MMR6-NEXT: li16 $2, 0
-; MMR6-NEXT: or $10, $10, $12
-; MMR6-NEXT: or $9, $9, $5
-; MMR6-NEXT: seleqz $5, $8, $11
-; MMR6-NEXT: seleqz $8, $2, $11
-; MMR6-NEXT: srlv $7, $7, $3
-; MMR6-NEXT: seleqz $2, $7, $16
-; MMR6-NEXT: selnez $2, $2, $11
+; MMR6-NEXT: li16 $5, 0
+; MMR6-NEXT: or $10, $10, $11
+; MMR6-NEXT: or $6, $9, $6
+; MMR6-NEXT: seleqz $2, $7, $8
+; MMR6-NEXT: seleqz $7, $5, $8
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: srlv $9, $5, $3
+; MMR6-NEXT: seleqz $11, $9, $16
+; MMR6-NEXT: selnez $11, $11, $8
; MMR6-NEXT: seleqz $1, $1, $3
-; MMR6-NEXT: or $5, $13, $5
-; MMR6-NEXT: selnez $5, $5, $3
-; MMR6-NEXT: or $5, $1, $5
-; MMR6-NEXT: or $2, $8, $2
-; MMR6-NEXT: seleqz $1, $9, $16
-; MMR6-NEXT: selnez $6, $7, $16
-; MMR6-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
-; MMR6-NEXT: seleqz $7, $7, $3
-; MMR6-NEXT: selnez $9, $10, $11
-; MMR6-NEXT: seleqz $4, $4, $17
-; MMR6-NEXT: seleqz $4, $4, $11
-; MMR6-NEXT: or $4, $9, $4
+; MMR6-NEXT: or $2, $12, $2
+; MMR6-NEXT: selnez $2, $2, $3
+; MMR6-NEXT: or $5, $1, $2
+; MMR6-NEXT: or $2, $7, $11
+; MMR6-NEXT: seleqz $1, $6, $16
+; MMR6-NEXT: selnez $6, $9, $16
+; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $9, $16, $3
+; MMR6-NEXT: selnez $10, $10, $8
+; MMR6-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $4, $4, $16
+; MMR6-NEXT: seleqz $4, $4, $8
+; MMR6-NEXT: or $4, $10, $4
; MMR6-NEXT: selnez $3, $4, $3
-; MMR6-NEXT: or $4, $7, $3
+; MMR6-NEXT: or $4, $9, $3
; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: selnez $1, $1, $11
-; MMR6-NEXT: or $3, $8, $1
-; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR6-NEXT: addiu $sp, $sp, 24
+; MMR6-NEXT: selnez $1, $1, $8
+; MMR6-NEXT: or $3, $7, $1
+; MMR6-NEXT: lw $16, 24($sp) # 4-byte Folded Reload
+; MMR6-NEXT: lw $17, 28($sp) # 4-byte Folded Reload
+; MMR6-NEXT: addiu $sp, $sp, 32
; MMR6-NEXT: jrc $ra
</cut>
4 years
- 3
- 7
[ACTIVITY] report week ending 1 Oct
by Peter Maydell
Progress
* UM-2 [QEMU upstream maintainership]
+ Worked through my code-review backlog
+ Noticed that we never got round to making our emulated GICv3
support having redistributors in more than one contiguous region;
this prevents using more than 123 CPUs with the virt board. Sent
out a patchset which adds the necessary handling.
+ Generally trying to tie off loose ends pre-holiday :-)
-- PMM
4 years
- 1
- 0
[TCWG CI] Regression caused by linux:30f349097897c115345beabeecc5e710b479ff1e
by ci_notify＠linaro.org
Identified regression caused by *linux:30f349097897c115345beabeecc5e710b479ff1e*:
commit 30f349097897c115345beabeecc5e710b479ff1e
Merge: 9c566611ac5c f76c87e8c337
Author: Linus Torvalds <torvalds(a)linux-foundation.org>
Merge tag 'pm-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Results regressed to (for first_bad == 30f349097897c115345beabeecc5e710b479ff1e)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
21782
# First few build errors in logs:
from (for last_good == 9c566611ac5cc7b45af943632f7a9b1b6a642991)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
29893
# linux build successful:
all
This commit has regressed these CI configurations:
- tcwg_kernel/gnu-release-arm-mainline-allmodconfig
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-mainline-a…
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-mainline-a…
Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-mainline-a…
Reproduce builds:
<cut>
mkdir investigate-linux-30f349097897c115345beabeecc5e710b479ff1e
cd investigate-linux-30f349097897c115345beabeecc5e710b479ff1e
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-mainline-a… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-mainline-a… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-mainline-a… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /linux/ ./ ./bisect/baseline/
cd linux
# Reproduce first_bad build
git checkout --detach 30f349097897c115345beabeecc5e710b479ff1e
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 9c566611ac5cc7b45af943632f7a9b1b6a642991
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 30f349097897c115345beabeecc5e710b479ff1e
Merge: 9c566611ac5c f76c87e8c337
Author: Linus Torvalds <torvalds(a)linux-foundation.org>
Date: Wed Sep 8 16:38:25 2021 -0700
Merge tag 'pm-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull more power management updates from Rafael Wysocki:
"These are mostly ARM cpufreq driver updates, including one new
MediaTek driver that has just passed all of the reviews, with the
addition of a revert of a recent intel_pstate commit, some core
cpufreq changes and a DT-related update of the operating performance
points (OPP) support code.
Specifics:
- Add new cpufreq driver for the MediaTek MT6779 platform called
mediatek-hw along with corresponding DT bindings (Hector.Yuan).
- Add DCVS interrupt support to the qcom-cpufreq-hw driver (Thara
Gopinath).
- Make the qcom-cpufreq-hw driver set the dvfs_possible_from_any_cpu
policy flag (Taniya Das).
- Blocklist more Qualcomm platforms in cpufreq-dt-platdev (Bjorn
Andersson).
- Make the vexpress cpufreq driver set the CPUFREQ_IS_COOLING_DEV
flag (Viresh Kumar).
- Add new cpufreq driver callback to allow drivers to register with
the Energy Model in a consistent way and make several drivers use
it (Viresh Kumar).
- Change the remaining users of the .ready() cpufreq driver callback
to move the code from it elsewhere and drop it from the cpufreq
core (Viresh Kumar).
- Revert recent intel_pstate change adding HWP guaranteed performance
change notification support to it that led to problems, because the
notification in question is triggered prematurely on some systems
(Rafael Wysocki).
- Convert the OPP DT bindings to DT schema and clean them up while at
it (Rob Herring)"
* tag 'pm-5.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (23 commits)
Revert "cpufreq: intel_pstate: Process HWP Guaranteed change notification"
cpufreq: mediatek-hw: Add support for CPUFREQ HW
cpufreq: Add of_perf_domain_get_sharing_cpumask
dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW
cpufreq: Remove ready() callback
cpufreq: sh: Remove sh_cpufreq_cpu_ready()
cpufreq: acpi: Remove acpi_cpufreq_cpu_ready()
cpufreq: qcom-hw: Set dvfs_possible_from_any_cpu cpufreq driver flag
cpufreq: blocklist more Qualcomm platforms in cpufreq-dt-platdev
cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support
cpufreq: scmi: Use .register_em() to register with energy model
cpufreq: vexpress: Use .register_em() to register with energy model
cpufreq: scpi: Use .register_em() to register with energy model
dt-bindings: opp: Convert to DT schema
dt-bindings: Clean-up OPP binding node names in examples
ARM: dts: omap: Drop references to opp.txt
cpufreq: qcom-cpufreq-hw: Use .register_em() to register with energy model
cpufreq: omap: Use .register_em() to register with energy model
cpufreq: mediatek: Use .register_em() to register with energy model
cpufreq: imx6q: Use .register_em() to register with energy model
...
Documentation/cpu-freq/cpu-drivers.rst | 3 -
.../devicetree/bindings/cpufreq/cpufreq-dt.txt | 2 +-
.../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 70 +++
.../bindings/cpufreq/cpufreq-mediatek.txt | 2 +-
.../devicetree/bindings/cpufreq/cpufreq-st.txt | 6 +-
.../bindings/cpufreq/nvidia,tegra20-cpufreq.txt | 2 +-
.../devicetree/bindings/devfreq/rk3399_dmc.txt | 2 +-
.../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 +-
.../devicetree/bindings/gpu/arm,mali-midgard.yaml | 2 +-
.../bindings/interconnect/fsl,imx8m-noc.yaml | 4 +-
.../opp/allwinner,sun50i-h6-operating-points.yaml | 4 +
Documentation/devicetree/bindings/opp/opp-v1.yaml | 51 ++
.../devicetree/bindings/opp/opp-v2-base.yaml | 214 +++++++
Documentation/devicetree/bindings/opp/opp-v2.yaml | 475 ++++++++++++++++
Documentation/devicetree/bindings/opp/opp.txt | 622 ---------------------
Documentation/devicetree/bindings/opp/qcom-opp.txt | 2 +-
.../bindings/opp/ti-omap5-opp-supply.txt | 2 +-
.../devicetree/bindings/power/power-domain.yaml | 2 +-
.../translations/zh_CN/cpu-freq/cpu-drivers.rst | 2 -
arch/arm/boot/dts/omap34xx.dtsi | 1 -
arch/arm/boot/dts/omap36xx.dtsi | 1 -
drivers/base/arch_topology.c | 2 +
drivers/cpufreq/Kconfig.arm | 12 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/acpi-cpufreq.c | 14 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 4 +
drivers/cpufreq/cpufreq-dt.c | 3 +-
drivers/cpufreq/cpufreq.c | 17 +-
drivers/cpufreq/imx6q-cpufreq.c | 2 +-
drivers/cpufreq/intel_pstate.c | 39 --
drivers/cpufreq/mediatek-cpufreq-hw.c | 308 ++++++++++
drivers/cpufreq/mediatek-cpufreq.c | 3 +-
drivers/cpufreq/omap-cpufreq.c | 2 +-
drivers/cpufreq/qcom-cpufreq-hw.c | 151 ++++-
drivers/cpufreq/scmi-cpufreq.c | 65 ++-
drivers/cpufreq/scpi-cpufreq.c | 3 +-
drivers/cpufreq/sh-cpufreq.c | 11 -
drivers/cpufreq/vexpress-spc-cpufreq.c | 25 +-
include/linux/cpufreq.h | 75 ++-
39 files changed, 1441 insertions(+), 767 deletions(-)
</cut>
4 years
- 3
- 3
[TCWG CI] Regression caused by linux: scripts/gcc-plugins: consistently use HOSTCC
by ci_notify＠linaro.org
[TCWG CI] Regression caused by linux: scripts/gcc-plugins: consistently use HOSTCC:
commit e554fdf7141e9edc05e7ece258f45b471af87494
Author: Ross Burton <ross.burton(a)arm.com>
scripts/gcc-plugins: consistently use HOSTCC
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
21723
# First few build errors in logs:
# 00:02:07 drivers/char/ipmi/ipmi_msghandler.c:4880:1: error: the frame size of 1232 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
# 00:02:07 make[2]: *** [drivers/char/ipmi/ipmi_msghandler.o] Error 1
# 00:02:43 make[1]: *** [drivers/char/ipmi] Error 2
# 00:03:47 lib/crypto/curve25519-fiat32.c:864:1: error: the frame size of 1288 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
# 00:03:47 make[2]: *** [lib/crypto/curve25519-fiat32.o] Error 1
# 00:03:54 make[1]: *** [lib/crypto] Error 2
# 00:03:54 fs/reiserfs/namei.c:1646:1: error: the frame size of 1176 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
# 00:03:54 make[2]: *** [fs/reiserfs/namei.o] Error 1
# 00:04:32 drivers/tty/serial/8250/8250_aspeed_vuart.c:568:1: error: the frame size of 1048 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
# 00:04:32 make[4]: *** [drivers/tty/serial/8250/8250_aspeed_vuart.o] Error 1
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
29916
# linux build successful:
all
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_kernel/gnu-release-arm-next-allmodconfig
First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo…
Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo…
Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo…
Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo…
Reproduce builds:
<cut>
mkdir investigate-linux-e554fdf7141e9edc05e7ece258f45b471af87494
cd investigate-linux-e554fdf7141e9edc05e7ece258f45b471af87494
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /linux/ ./ ./bisect/baseline/
cd linux
# Reproduce first_bad build
git checkout --detach e554fdf7141e9edc05e7ece258f45b471af87494
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 86455276585996fe5b43972aa8f31afcbafabc40
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit e554fdf7141e9edc05e7ece258f45b471af87494
Author: Ross Burton <ross.burton(a)arm.com>
Date: Thu Sep 23 16:28:11 2021 +0100
scripts/gcc-plugins: consistently use HOSTCC
The GCC plugins are built using HOSTCC, but the path to the GCC plugins
headers is obtained using CC. This can lead to interesting failures if
the host compiler and cross compiler are different versions, and the
host compiler uses the cross headers.
Signed-off-by: Ross Burton <ross.burton(a)arm.com>
Signed-off-by: Kees Cook <keescook(a)chromium.org>
Link: https://lore.kernel.org/r/20210923152811.406516-1-ross.burton@arm.com
---
scripts/gcc-plugins/Kconfig | 2 +-
scripts/gcc-plugins/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/scripts/gcc-plugins/Kconfig b/scripts/gcc-plugins/Kconfig
index ab9eb4cbe33a..5dad6d780138 100644
--- a/scripts/gcc-plugins/Kconfig
+++ b/scripts/gcc-plugins/Kconfig
@@ -9,7 +9,7 @@ menuconfig GCC_PLUGINS
bool "GCC plugins"
depends on HAVE_GCC_PLUGINS
depends on CC_IS_GCC
- depends on $(success,test -e $(shell,$(CC) -print-file-name=plugin)/include/plugin-version.h)
+ depends on $(success,test -e $(shell,$(HOSTCC) -print-file-name=plugin)/include/plugin-version.h)
default y
help
GCC plugins are loadable modules that provide extra features to the
diff --git a/scripts/gcc-plugins/Makefile b/scripts/gcc-plugins/Makefile
index 1952d3bb80c6..6aac404344a6 100644
--- a/scripts/gcc-plugins/Makefile
+++ b/scripts/gcc-plugins/Makefile
@@ -19,7 +19,7 @@ targets += randomize_layout_seed.h randomize_layout_hash.h
always-y += $(GCC_PLUGIN)
-GCC_PLUGINS_DIR = $(shell $(CC) -print-file-name=plugin)
+GCC_PLUGINS_DIR = $(shell $(HOSTCXX) -print-file-name=plugin)
plugin_cxxflags = -Wp,-MMD,$(depfile) $(KBUILD_HOSTCXXFLAGS) -fPIC \
-include $(srctree)/include/linux/compiler-version.h \
</cut>
4 years
- 1
- 0
[CI-NOTIFY]: TCWG Bisect tcwg_kernel/llvm-release-aarch64-next-allnoconfig - Build # 10 - Successful!
by ci_notify＠linaro.org
Successfully identified regression in *linux* in CI configuration tcwg_kernel/llvm-release-aarch64-next-allnoconfig. So far, this commit has regressed CI configurations:
- tcwg_kernel/llvm-release-aarch64-next-allnoconfig
Culprit:
<cut>
commit 8633ef82f101c040427b57d4df7b706261420b94
Author: Javier Martinez Canillas <javierm(a)redhat.com>
Date: Fri Jun 25 15:13:59 2021 +0200
drivers/firmware: consolidate EFI framebuffer setup for all arches
The register_gop_device() function registers an "efi-framebuffer" platform
device to match against the efifb driver, to have an early framebuffer for
EFI platforms.
But there is already support to do exactly the same by the Generic System
Framebuffers (sysfb) driver. This used to be only for X86 but it has been
moved to drivers/firmware and could be reused by other architectures.
Also, besides supporting registering an "efi-framebuffer", this driver can
register a "simple-framebuffer" allowing to use the siple{fb,drm} drivers
on non-X86 EFI platforms. For example, on aarch64 these drivers can only
be used with DT and doesn't have code to register a "simple-frambuffer"
platform device when booting with EFI.
For these reasons, let's remove the register_gop_device() duplicated code
and instead move the platform specific logic that's there to sysfb driver.
Signed-off-by: Javier Martinez Canillas <javierm(a)redhat.com>
Acked-by: Borislav Petkov <bp(a)suse.de>
Acked-by: Daniel Vetter <daniel.vetter(a)ffwll.ch>
Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20210625131359.1804394-1-javi…
</cut>
Results regressed to (for first_bad == 8633ef82f101c040427b57d4df7b706261420b94)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_llvm:
-5
# build_abe qemu:
-2
# linux_n_obj:
600
# First few build errors in logs:
# 00:00:38 ld.lld: error: undefined symbol: screen_info
# 00:00:38 make: *** [vmlinux] Error 1
from (for last_good == d391c58271072d0b0fad93c82018d495b2633448)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_llvm:
-5
# build_abe qemu:
-2
# linux_n_obj:
601
# linux build successful:
all
# linux boot successful:
boot
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next…
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next…
Build top page/logs: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next…
Configuration details:
rr[linux_git]="https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git#ff11764…"
Reproduce builds:
<cut>
mkdir investigate-linux-8633ef82f101c040427b57d4df7b706261420b94
cd investigate-linux-8633ef82f101c040427b57d4df7b706261420b94
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /linux/ ./ ./bisect/baseline/
cd linux
# Reproduce first_bad build
git checkout --detach 8633ef82f101c040427b57d4df7b706261420b94
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach d391c58271072d0b0fad93c82018d495b2633448
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/…
Artifacts: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next…
Build log: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-release-aarch64-next…
Full commit (up to 1000 lines):
<cut>
commit 8633ef82f101c040427b57d4df7b706261420b94
Author: Javier Martinez Canillas <javierm(a)redhat.com>
Date: Fri Jun 25 15:13:59 2021 +0200
drivers/firmware: consolidate EFI framebuffer setup for all arches
The register_gop_device() function registers an "efi-framebuffer" platform
device to match against the efifb driver, to have an early framebuffer for
EFI platforms.
But there is already support to do exactly the same by the Generic System
Framebuffers (sysfb) driver. This used to be only for X86 but it has been
moved to drivers/firmware and could be reused by other architectures.
Also, besides supporting registering an "efi-framebuffer", this driver can
register a "simple-framebuffer" allowing to use the siple{fb,drm} drivers
on non-X86 EFI platforms. For example, on aarch64 these drivers can only
be used with DT and doesn't have code to register a "simple-frambuffer"
platform device when booting with EFI.
For these reasons, let's remove the register_gop_device() duplicated code
and instead move the platform specific logic that's there to sysfb driver.
Signed-off-by: Javier Martinez Canillas <javierm(a)redhat.com>
Acked-by: Borislav Petkov <bp(a)suse.de>
Acked-by: Daniel Vetter <daniel.vetter(a)ffwll.ch>
Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20210625131359.1804394-1-javi…
---
arch/arm/include/asm/efi.h | 5 +--
arch/arm64/include/asm/efi.h | 5 +--
arch/riscv/include/asm/efi.h | 5 +--
drivers/firmware/Kconfig | 8 ++--
drivers/firmware/Makefile | 2 +-
drivers/firmware/efi/efi-init.c | 90 ---------------------------------------
drivers/firmware/efi/sysfb_efi.c | 76 ++++++++++++++++++++++++++++++++-
drivers/firmware/sysfb.c | 35 ++++++++++-----
drivers/firmware/sysfb_simplefb.c | 31 ++++++++++----
drivers/gpu/drm/tiny/Kconfig | 4 +-
include/linux/sysfb.h | 26 +++++------
11 files changed, 143 insertions(+), 144 deletions(-)
diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h
index 9de7ab2ce05d..a6f3b179e8a9 100644
--- a/arch/arm/include/asm/efi.h
+++ b/arch/arm/include/asm/efi.h
@@ -17,6 +17,7 @@
#ifdef CONFIG_EFI
void efi_init(void);
+extern void efifb_setup_from_dmi(struct screen_info *si, const char *opt);
int efi_create_mapping(struct mm_struct *mm, efi_memory_desc_t *md);
int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md);
@@ -52,10 +53,6 @@ void efi_virtmap_unload(void);
struct screen_info *alloc_screen_info(void);
void free_screen_info(struct screen_info *si);
-static inline void efifb_setup_from_dmi(struct screen_info *si, const char *opt)
-{
-}
-
/*
* A reasonable upper bound for the uncompressed kernel size is 32 MBytes,
* so we will reserve that amount of memory. We have no easy way to tell what
diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h
index 3578aba9c608..42d673a011c8 100644
--- a/arch/arm64/include/asm/efi.h
+++ b/arch/arm64/include/asm/efi.h
@@ -14,6 +14,7 @@
#ifdef CONFIG_EFI
extern void efi_init(void);
+extern void efifb_setup_from_dmi(struct screen_info *si, const char *opt);
#else
#define efi_init()
#endif
@@ -85,10 +86,6 @@ static inline void free_screen_info(struct screen_info *si)
{
}
-static inline void efifb_setup_from_dmi(struct screen_info *si, const char *opt)
-{
-}
-
#define EFI_ALLOC_ALIGN SZ_64K
/*
diff --git a/arch/riscv/include/asm/efi.h b/arch/riscv/include/asm/efi.h
index 6d98cd999680..7a8f0d45b13a 100644
--- a/arch/riscv/include/asm/efi.h
+++ b/arch/riscv/include/asm/efi.h
@@ -13,6 +13,7 @@
#ifdef CONFIG_EFI
extern void efi_init(void);
+extern void efifb_setup_from_dmi(struct screen_info *si, const char *opt);
#else
#define efi_init()
#endif
@@ -39,10 +40,6 @@ static inline void free_screen_info(struct screen_info *si)
{
}
-static inline void efifb_setup_from_dmi(struct screen_info *si, const char *opt)
-{
-}
-
void efi_virtmap_load(void);
void efi_virtmap_unload(void);
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 71f3d97f0c39..af6719cc576b 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -254,9 +254,9 @@ config QCOM_SCM_DOWNLOAD_MODE_DEFAULT
config SYSFB
bool
default y
- depends on X86 || COMPILE_TEST
+ depends on X86 || ARM || ARM64 || RISCV || COMPILE_TEST
-config X86_SYSFB
+config SYSFB_SIMPLEFB
bool "Mark VGA/VBE/EFI FB as generic system framebuffer"
depends on SYSFB
help
@@ -264,10 +264,10 @@ config X86_SYSFB
bootloader or kernel can show basic video-output during boot for
user-guidance and debugging. Historically, x86 used the VESA BIOS
Extensions and EFI-framebuffers for this, which are mostly limited
- to x86.
+ to x86 BIOS or EFI systems.
This option, if enabled, marks VGA/VBE/EFI framebuffers as generic
framebuffers so the new generic system-framebuffer drivers can be
- used on x86. If the framebuffer is not compatible with the generic
+ used instead. If the framebuffer is not compatible with the generic
modes, it is advertised as fallback platform framebuffer so legacy
drivers like efifb, vesafb and uvesafb can pick it up.
If this option is not selected, all system framebuffers are always
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index ad78f78ffa8d..6ac637e422b9 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o
obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o
obj-$(CONFIG_SYSFB) += sysfb.o
-obj-$(CONFIG_X86_SYSFB) += sysfb_simplefb.o
+obj-$(CONFIG_SYSFB_SIMPLEFB) += sysfb_simplefb.o
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o
diff --git a/drivers/firmware/efi/efi-init.c b/drivers/firmware/efi/efi-init.c
index a552a08a1741..b19ce1a83f91 100644
--- a/drivers/firmware/efi/efi-init.c
+++ b/drivers/firmware/efi/efi-init.c
@@ -275,93 +275,3 @@ void __init efi_init(void)
}
#endif
}
-
-static bool efifb_overlaps_pci_range(const struct of_pci_range *range)
-{
- u64 fb_base = screen_info.lfb_base;
-
- if (screen_info.capabilities & VIDEO_CAPABILITY_64BIT_BASE)
- fb_base |= (u64)(unsigned long)screen_info.ext_lfb_base << 32;
-
- return fb_base >= range->cpu_addr &&
- fb_base < (range->cpu_addr + range->size);
-}
-
-static struct device_node *find_pci_overlap_node(void)
-{
- struct device_node *np;
-
- for_each_node_by_type(np, "pci") {
- struct of_pci_range_parser parser;
- struct of_pci_range range;
- int err;
-
- err = of_pci_range_parser_init(&parser, np);
- if (err) {
- pr_warn("of_pci_range_parser_init() failed: %d\n", err);
- continue;
- }
-
- for_each_of_pci_range(&parser, &range)
- if (efifb_overlaps_pci_range(&range))
- return np;
- }
- return NULL;
-}
-
-/*
- * If the efifb framebuffer is backed by a PCI graphics controller, we have
- * to ensure that this relation is expressed using a device link when
- * running in DT mode, or the probe order may be reversed, resulting in a
- * resource reservation conflict on the memory window that the efifb
- * framebuffer steals from the PCIe host bridge.
- */
-static int efifb_add_links(struct fwnode_handle *fwnode)
-{
- struct device_node *sup_np;
-
- sup_np = find_pci_overlap_node();
-
- /*
- * If there's no PCI graphics controller backing the efifb, we are
- * done here.
- */
- if (!sup_np)
- return 0;
-
- fwnode_link_add(fwnode, of_fwnode_handle(sup_np));
- of_node_put(sup_np);
-
- return 0;
-}
-
-static const struct fwnode_operations efifb_fwnode_ops = {
- .add_links = efifb_add_links,
-};
-
-static struct fwnode_handle efifb_fwnode;
-
-static int __init register_gop_device(void)
-{
- struct platform_device *pd;
- int err;
-
- if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI)
- return 0;
-
- pd = platform_device_alloc("efi-framebuffer", 0);
- if (!pd)
- return -ENOMEM;
-
- if (IS_ENABLED(CONFIG_PCI)) {
- fwnode_init(&efifb_fwnode, &efifb_fwnode_ops);
- pd->dev.fwnode = &efifb_fwnode;
- }
-
- err = platform_device_add_data(pd, &screen_info, sizeof(screen_info));
- if (err)
- return err;
-
- return platform_device_add(pd);
-}
-subsys_initcall(register_gop_device);
diff --git a/drivers/firmware/efi/sysfb_efi.c b/drivers/firmware/efi/sysfb_efi.c
index 9f035b15501c..f51865e1b876 100644
--- a/drivers/firmware/efi/sysfb_efi.c
+++ b/drivers/firmware/efi/sysfb_efi.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Generic System Framebuffers on x86
+ * Generic System Framebuffers
* Copyright (c) 2012-2013 David Herrmann <dh.herrmann(a)gmail.com>
*
* EFI Quirks Copyright (c) 2006 Edgar Hucek <gimli(a)dark-green.com>
@@ -19,7 +19,9 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mm.h>
+#include <linux/of_address.h>
#include <linux/pci.h>
+#include <linux/platform_device.h>
#include <linux/screen_info.h>
#include <linux/sysfb.h>
#include <video/vga.h>
@@ -267,7 +269,72 @@ static const struct dmi_system_id efifb_dmi_swap_width_height[] __initconst = {
{},
};
-__init void sysfb_apply_efi_quirks(void)
+static bool efifb_overlaps_pci_range(const struct of_pci_range *range)
+{
+ u64 fb_base = screen_info.lfb_base;
+
+ if (screen_info.capabilities & VIDEO_CAPABILITY_64BIT_BASE)
+ fb_base |= (u64)(unsigned long)screen_info.ext_lfb_base << 32;
+
+ return fb_base >= range->cpu_addr &&
+ fb_base < (range->cpu_addr + range->size);
+}
+
+static struct device_node *find_pci_overlap_node(void)
+{
+ struct device_node *np;
+
+ for_each_node_by_type(np, "pci") {
+ struct of_pci_range_parser parser;
+ struct of_pci_range range;
+ int err;
+
+ err = of_pci_range_parser_init(&parser, np);
+ if (err) {
+ pr_warn("of_pci_range_parser_init() failed: %d\n", err);
+ continue;
+ }
+
+ for_each_of_pci_range(&parser, &range)
+ if (efifb_overlaps_pci_range(&range))
+ return np;
+ }
+ return NULL;
+}
+
+/*
+ * If the efifb framebuffer is backed by a PCI graphics controller, we have
+ * to ensure that this relation is expressed using a device link when
+ * running in DT mode, or the probe order may be reversed, resulting in a
+ * resource reservation conflict on the memory window that the efifb
+ * framebuffer steals from the PCIe host bridge.
+ */
+static int efifb_add_links(struct fwnode_handle *fwnode)
+{
+ struct device_node *sup_np;
+
+ sup_np = find_pci_overlap_node();
+
+ /*
+ * If there's no PCI graphics controller backing the efifb, we are
+ * done here.
+ */
+ if (!sup_np)
+ return 0;
+
+ fwnode_link_add(fwnode, of_fwnode_handle(sup_np));
+ of_node_put(sup_np);
+
+ return 0;
+}
+
+static const struct fwnode_operations efifb_fwnode_ops = {
+ .add_links = efifb_add_links,
+};
+
+static struct fwnode_handle efifb_fwnode;
+
+__init void sysfb_apply_efi_quirks(struct platform_device *pd)
{
if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI ||
!(screen_info.capabilities & VIDEO_CAPABILITY_SKIP_QUIRKS))
@@ -281,4 +348,9 @@ __init void sysfb_apply_efi_quirks(void)
screen_info.lfb_height = temp;
screen_info.lfb_linelength = 4 * screen_info.lfb_width;
}
+
+ if (screen_info.orig_video_isVGA == VIDEO_TYPE_EFI && IS_ENABLED(CONFIG_PCI)) {
+ fwnode_init(&efifb_fwnode, &efifb_fwnode_ops);
+ pd->dev.fwnode = &efifb_fwnode;
+ }
}
diff --git a/drivers/firmware/sysfb.c b/drivers/firmware/sysfb.c
index 1337515963d5..2bfbb05f7d89 100644
--- a/drivers/firmware/sysfb.c
+++ b/drivers/firmware/sysfb.c
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Generic System Framebuffers on x86
+ * Generic System Framebuffers
* Copyright (c) 2012-2013 David Herrmann <dh.herrmann(a)gmail.com>
*/
/*
- * Simple-Framebuffer support for x86 systems
+ * Simple-Framebuffer support
* Create a platform-device for any available boot framebuffer. The
* simple-framebuffer platform device is already available on DT systems, so
* this module parses the global "screen_info" object and creates a suitable
@@ -16,12 +16,12 @@
* to pick these devices up without messing with simple-framebuffer drivers.
* The global "screen_info" is still valid at all times.
*
- * If CONFIG_X86_SYSFB is not selected, we never register "simple-framebuffer"
+ * If CONFIG_SYSFB_SIMPLEFB is not selected, never register "simple-framebuffer"
* platform devices, but only use legacy framebuffer devices for
* backwards compatibility.
*
* TODO: We set the dev_id field of all platform-devices to 0. This allows
- * other x86 OF/DT parsers to create such devices, too. However, they must
+ * other OF/DT parsers to create such devices, too. However, they must
* start at offset 1 for this to work.
*/
@@ -43,12 +43,10 @@ static __init int sysfb_init(void)
bool compatible;
int ret;
- sysfb_apply_efi_quirks();
-
/* try to create a simple-framebuffer device */
- compatible = parse_mode(si, &mode);
+ compatible = sysfb_parse_mode(si, &mode);
if (compatible) {
- ret = create_simplefb(si, &mode);
+ ret = sysfb_create_simplefb(si, &mode);
if (!ret)
return 0;
}
@@ -61,9 +59,24 @@ static __init int sysfb_init(void)
else
name = "platform-framebuffer";
- pd = platform_device_register_resndata(NULL, name, 0,
- NULL, 0, si, sizeof(*si));
- return PTR_ERR_OR_ZERO(pd);
+ pd = platform_device_alloc(name, 0);
+ if (!pd)
+ return -ENOMEM;
+
+ sysfb_apply_efi_quirks(pd);
+
+ ret = platform_device_add_data(pd, si, sizeof(*si));
+ if (ret)
+ goto err;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ platform_device_put(pd);
+ return ret;
}
/* must execute after PCI subsystem for EFI quirks */
diff --git a/drivers/firmware/sysfb_simplefb.c b/drivers/firmware/sysfb_simplefb.c
index df892444ea17..b86761904949 100644
--- a/drivers/firmware/sysfb_simplefb.c
+++ b/drivers/firmware/sysfb_simplefb.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Generic System Framebuffers on x86
+ * Generic System Framebuffers
* Copyright (c) 2012-2013 David Herrmann <dh.herrmann(a)gmail.com>
*/
@@ -23,9 +23,9 @@
static const char simplefb_resname[] = "BOOTFB";
static const struct simplefb_format formats[] = SIMPLEFB_FORMATS;
-/* try parsing x86 screen_info into a simple-framebuffer mode struct */
-__init bool parse_mode(const struct screen_info *si,
- struct simplefb_platform_data *mode)
+/* try parsing screen_info into a simple-framebuffer mode struct */
+__init bool sysfb_parse_mode(const struct screen_info *si,
+ struct simplefb_platform_data *mode)
{
const struct simplefb_format *f;
__u8 type;
@@ -57,13 +57,14 @@ __init bool parse_mode(const struct screen_info *si,
return false;
}
-__init int create_simplefb(const struct screen_info *si,
- const struct simplefb_platform_data *mode)
+__init int sysfb_create_simplefb(const struct screen_info *si,
+ const struct simplefb_platform_data *mode)
{
struct platform_device *pd;
struct resource res;
u64 base, size;
u32 length;
+ int ret;
/*
* If the 64BIT_BASE capability is set, ext_lfb_base will contain the
@@ -105,7 +106,19 @@ __init int create_simplefb(const struct screen_info *si,
if (res.end <= res.start)
return -EINVAL;
- pd = platform_device_register_resndata(NULL, "simple-framebuffer", 0,
- &res, 1, mode, sizeof(*mode));
- return PTR_ERR_OR_ZERO(pd);
+ pd = platform_device_alloc("simple-framebuffer", 0);
+ if (!pd)
+ return -ENOMEM;
+
+ sysfb_apply_efi_quirks(pd);
+
+ ret = platform_device_add_resources(pd, &res, 1);
+ if (ret)
+ return ret;
+
+ ret = platform_device_add_data(pd, mode, sizeof(*mode));
+ if (ret)
+ return ret;
+
+ return platform_device_add(pd);
}
diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index 5593128eeff9..d31be274a2bd 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -64,8 +64,8 @@ config DRM_SIMPLEDRM
buffer, size, and display format must be provided via device tree,
UEFI, VESA, etc.
- On x86 and compatible, you should also select CONFIG_X86_SYSFB to
- use UEFI and VESA framebuffers.
+ On x86 BIOS or UEFI systems, you should also select SYSFB_SIMPLEFB
+ to use UEFI and VESA framebuffers.
config TINYDRM_HX8357D
tristate "DRM support for HX8357D display panels"
diff --git a/include/linux/sysfb.h b/include/linux/sysfb.h
index 3e5355769dc3..b0dcfa26d07b 100644
--- a/include/linux/sysfb.h
+++ b/include/linux/sysfb.h
@@ -58,37 +58,37 @@ struct efifb_dmi_info {
#ifdef CONFIG_EFI
extern struct efifb_dmi_info efifb_dmi_list[];
-void sysfb_apply_efi_quirks(void);
+void sysfb_apply_efi_quirks(struct platform_device *pd);
#else /* CONFIG_EFI */
-static inline void sysfb_apply_efi_quirks(void)
+static inline void sysfb_apply_efi_quirks(struct platform_device *pd)
{
}
#endif /* CONFIG_EFI */
-#ifdef CONFIG_X86_SYSFB
+#ifdef CONFIG_SYSFB_SIMPLEFB
-bool parse_mode(const struct screen_info *si,
- struct simplefb_platform_data *mode);
-int create_simplefb(const struct screen_info *si,
- const struct simplefb_platform_data *mode);
+bool sysfb_parse_mode(const struct screen_info *si,
+ struct simplefb_platform_data *mode);
+int sysfb_create_simplefb(const struct screen_info *si,
+ const struct simplefb_platform_data *mode);
-#else /* CONFIG_X86_SYSFB */
+#else /* CONFIG_SYSFB_SIMPLE */
-static inline bool parse_mode(const struct screen_info *si,
- struct simplefb_platform_data *mode)
+static inline bool sysfb_parse_mode(const struct screen_info *si,
+ struct simplefb_platform_data *mode)
{
return false;
}
-static inline int create_simplefb(const struct screen_info *si,
- const struct simplefb_platform_data *mode)
+static inline int sysfb_create_simplefb(const struct screen_info *si,
+ const struct simplefb_platform_data *mode)
{
return -EINVAL;
}
-#endif /* CONFIG_X86_SYSFB */
+#endif /* CONFIG_SYSFB_SIMPLE */
#endif /* _LINUX_SYSFB_H */
</cut>
4 years
- 4
- 4
[TCWG CI] 400.perlbench slowed down by 6% after llvm: [SimplifyCFG] Ignore free instructions when computing cost for folding branch to common dest
by ci_notify＠linaro.org
After llvm commit e7249e4acf3cf9438d6d9e02edecebd5b622a4dc
Author: Arthur Eubanks <aeubanks(a)google.com>
[SimplifyCFG] Ignore free instructions when computing cost for folding branch to common dest
the following benchmarks slowed down by more than 2%:
- 400.perlbench slowed down by 6% from 9730 to 10312 perf samples
- 400.perlbench:[.] S_regmatch slowed down by 14% from 3660 to 4188 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-e7249e4acf3cf9438d6d9e02edecebd5b622a4dc
cd investigate-llvm-e7249e4acf3cf9438d6d9e02edecebd5b622a4dc
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach e7249e4acf3cf9438d6d9e02edecebd5b622a4dc
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 32a50078657dd8beead327a3478ede4e9d730432
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit e7249e4acf3cf9438d6d9e02edecebd5b622a4dc
Author: Arthur Eubanks <aeubanks(a)google.com>
Date: Fri Aug 27 12:32:59 2021 -0700
[SimplifyCFG] Ignore free instructions when computing cost for folding branch to common dest
When determining whether to fold branches to a common destination by
merging two blocks, SimplifyCFG will count the number of instructions to
be moved into the first basic block. However, there's no reason to count
free instructions like bitcasts and other similar instructions.
This resolves missed branch foldings with -fstrict-vtable-pointers in
llvm-test-suite's lambda benchmark.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D108837
---
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 17 ++++++-----
llvm/test/CodeGen/AArch64/csr-split.ll | 34 +++++++++++-----------
.../fold-branch-to-common-dest-free-cost.ll | 5 ++--
3 files changed, 29 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 2ff98b238de0..a3bd89e72af9 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -3258,13 +3258,16 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, DomTreeUpdater *DTU,
SawVectorOp |= isVectorOp(I);
// Account for the cost of duplicating this instruction into each
- // predecessor.
- NumBonusInsts += PredCount;
-
- // Early exits once we reach the limit.
- if (NumBonusInsts >
- BonusInstThreshold * BranchFoldToCommonDestVectorMultiplier)
- return false;
+ // predecessor. Ignore free instructions.
+ if (!TTI ||
+ TTI->getUserCost(&I, CostKind) != TargetTransformInfo::TCC_Free) {
+ NumBonusInsts += PredCount;
+
+ // Early exits once we reach the limit.
+ if (NumBonusInsts >
+ BonusInstThreshold * BranchFoldToCommonDestVectorMultiplier)
+ return false;
+ }
auto IsBCSSAUse = [BB, &I](Use &U) {
auto *UI = cast<Instruction>(U.getUser());
diff --git a/llvm/test/CodeGen/AArch64/csr-split.ll b/llvm/test/CodeGen/AArch64/csr-split.ll
index 1bee7f05acec..de85b4313433 100644
--- a/llvm/test/CodeGen/AArch64/csr-split.ll
+++ b/llvm/test/CodeGen/AArch64/csr-split.ll
@@ -82,22 +82,22 @@ define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: cbz x0, .LBB1_2
-; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: cbz x0, .LBB1_3
+; CHECK-NEXT: // %bb.1: // %entry
; CHECK-NEXT: adrp x8, a
; CHECK-NEXT: ldrsw x8, [x8, :lo12:a]
; CHECK-NEXT: mov x19, x0
; CHECK-NEXT: cmp x8, x0
-; CHECK-NEXT: b.eq .LBB1_3
-; CHECK-NEXT: .LBB1_2: // %return
-; CHECK-NEXT: mov w0, wzr
-; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
-; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB1_3: // %if.then2
+; CHECK-NEXT: b.ne .LBB1_3
+; CHECK-NEXT: // %bb.2: // %if.then2
; CHECK-NEXT: bl callVoid
; CHECK-NEXT: mov x0, x19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: b callNonVoid
+; CHECK-NEXT: .LBB1_3: // %return
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
;
; CHECK-APPLE-LABEL: test2:
; CHECK-APPLE: ; %bb.0: ; %entry
@@ -108,26 +108,26 @@ define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr {
; CHECK-APPLE-NEXT: .cfi_offset w29, -16
; CHECK-APPLE-NEXT: .cfi_offset w19, -24
; CHECK-APPLE-NEXT: .cfi_offset w20, -32
-; CHECK-APPLE-NEXT: cbz x0, LBB1_2
-; CHECK-APPLE-NEXT: ; %bb.1: ; %if.end
+; CHECK-APPLE-NEXT: cbz x0, LBB1_3
+; CHECK-APPLE-NEXT: ; %bb.1: ; %entry
; CHECK-APPLE-NEXT: Lloh2:
; CHECK-APPLE-NEXT: adrp x8, _a@PAGE
; CHECK-APPLE-NEXT: Lloh3:
; CHECK-APPLE-NEXT: ldrsw x8, [x8, _a@PAGEOFF]
; CHECK-APPLE-NEXT: mov x19, x0
; CHECK-APPLE-NEXT: cmp x8, x0
-; CHECK-APPLE-NEXT: b.eq LBB1_3
-; CHECK-APPLE-NEXT: LBB1_2: ; %return
-; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-APPLE-NEXT: mov w0, wzr
-; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
-; CHECK-APPLE-NEXT: ret
-; CHECK-APPLE-NEXT: LBB1_3: ; %if.then2
+; CHECK-APPLE-NEXT: b.ne LBB1_3
+; CHECK-APPLE-NEXT: ; %bb.2: ; %if.then2
; CHECK-APPLE-NEXT: bl _callVoid
; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-APPLE-NEXT: mov x0, x19
; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
; CHECK-APPLE-NEXT: b _callNonVoid
+; CHECK-APPLE-NEXT: LBB1_3: ; %return
+; CHECK-APPLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-APPLE-NEXT: mov w0, wzr
+; CHECK-APPLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
+; CHECK-APPLE-NEXT: ret
; CHECK-APPLE-NEXT: .loh AdrpLdr Lloh2, Lloh3
entry:
%tobool = icmp eq i32* %p1, null
diff --git a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-free-cost.ll b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-free-cost.ll
index ace2a5ed35ca..27df5ec44582 100644
--- a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-free-cost.ll
+++ b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-free-cost.ll
@@ -8,12 +8,11 @@ declare void @g2()
define void @f(i8* %a, i8* %b, i1 %c, i1 %d, i1 %e) {
; CHECK-LABEL: @f(
-; CHECK-NEXT: br i1 [[C:%.*]], label [[L1:%.*]], label [[L3:%.*]]
-; CHECK: l1:
; CHECK-NEXT: [[A1:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* [[A:%.*]])
; CHECK-NEXT: [[B1:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* [[B:%.*]])
; CHECK-NEXT: [[I:%.*]] = icmp eq i8* [[A1]], [[B1]]
-; CHECK-NEXT: br i1 [[I]], label [[L2:%.*]], label [[L3]]
+; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C:%.*]], i1 [[I]], i1 false
+; CHECK-NEXT: br i1 [[OR_COND]], label [[L2:%.*]], label [[L3:%.*]]
; CHECK: l2:
; CHECK-NEXT: call void @g1()
; CHECK-NEXT: br label [[RET:%.*]]
</cut>
4 years
- 3
- 4
[CI-NOTIFY]: TCWG Bisect tcwg_kernel/llvm-master-aarch64-next-allyesconfig - Build # 14 - Successful!
by ci_notify＠linaro.org
Successfully identified regression in *linux* in CI configuration tcwg_kernel/llvm-master-aarch64-next-allyesconfig. So far, this commit has regressed CI configurations:
- tcwg_kernel/llvm-master-aarch64-next-allyesconfig
Culprit:
<cut>
commit 3d463dd5023b5a58b3c37207d65eeb5acbac2be3
Author: Krzysztof Kozlowski <krzysztof.kozlowski(a)canonical.com>
Date: Thu Jul 29 12:40:19 2021 +0200
nfc: fdp: constify several pointers
Several functions do not modify pointed data so arguments and local
variables can be const for correctness and safety. This allows also
making file-scope nci_core_get_config_otp_ram_version array const.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)canonical.com>
Signed-off-by: David S. Miller <davem(a)davemloft.net>
</cut>
Results regressed to (for first_bad == 3d463dd5023b5a58b3c37207d65eeb5acbac2be3)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_llvm:
-5
# build_abe qemu:
-2
# linux_n_obj:
19928
# First few build errors in logs:
# 00:02:04 drivers/nfc/fdp/fdp.c:116:60: error: passing 'const char *' to parameter of type '__u8 *' (aka 'unsigned char *') discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
# 00:02:04 make[3]: *** [scripts/Makefile.build:271: drivers/nfc/fdp/fdp.o] Error 1
# 00:02:05 make[2]: *** [scripts/Makefile.build:514: drivers/nfc/fdp] Error 2
# 00:02:23 make[1]: *** [scripts/Makefile.build:514: drivers/nfc] Error 2
# 00:04:16 make: *** [Makefile:1842: drivers] Error 2
from (for last_good == c3e26b6dc1b4e3e8f57be4f004b1f2a410c5c468)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_llvm:
-5
# build_abe qemu:
-2
# linux_n_obj:
20000
# linux build successful:
all
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-…
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-…
Build top page/logs: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-…
Configuration details:
rr[linux_git]="https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git#cb16362…"
Reproduce builds:
<cut>
mkdir investigate-linux-3d463dd5023b5a58b3c37207d65eeb5acbac2be3
cd investigate-linux-3d463dd5023b5a58b3c37207d65eeb5acbac2be3
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /linux/ ./ ./bisect/baseline/
cd linux
# Reproduce first_bad build
git checkout --detach 3d463dd5023b5a58b3c37207d65eeb5acbac2be3
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach c3e26b6dc1b4e3e8f57be4f004b1f2a410c5c468
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/…
Artifacts: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-…
Build log: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-aarch64-next-…
Full commit (up to 1000 lines):
<cut>
commit 3d463dd5023b5a58b3c37207d65eeb5acbac2be3
Author: Krzysztof Kozlowski <krzysztof.kozlowski(a)canonical.com>
Date: Thu Jul 29 12:40:19 2021 +0200
nfc: fdp: constify several pointers
Several functions do not modify pointed data so arguments and local
variables can be const for correctness and safety. This allows also
making file-scope nci_core_get_config_otp_ram_version array const.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)canonical.com>
Signed-off-by: David S. Miller <davem(a)davemloft.net>
---
drivers/nfc/fdp/fdp.c | 18 +++++++++---------
drivers/nfc/fdp/fdp.h | 2 +-
drivers/nfc/fdp/i2c.c | 6 +++---
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/nfc/fdp/fdp.c b/drivers/nfc/fdp/fdp.c
index 3f5fba922c4d..c6b3334f24c9 100644
--- a/drivers/nfc/fdp/fdp.c
+++ b/drivers/nfc/fdp/fdp.c
@@ -52,7 +52,7 @@ struct fdp_nci_info {
u32 limited_otp_version;
u8 key_index;
- u8 *fw_vsc_cfg;
+ const u8 *fw_vsc_cfg;
u8 clock_type;
u32 clock_freq;
@@ -65,7 +65,7 @@ struct fdp_nci_info {
wait_queue_head_t setup_wq;
};
-static u8 nci_core_get_config_otp_ram_version[5] = {
+static const u8 nci_core_get_config_otp_ram_version[5] = {
0x04,
NCI_PARAM_ID_FW_RAM_VERSION,
NCI_PARAM_ID_FW_OTP_VERSION,
@@ -111,7 +111,7 @@ static inline int fdp_nci_patch_cmd(struct nci_dev *ndev, u8 type)
}
static inline int fdp_nci_set_production_data(struct nci_dev *ndev, u8 len,
- char *data)
+ const char *data)
{
return nci_prop_cmd(ndev, NCI_OP_PROP_SET_PDATA_OID, len, data);
}
@@ -236,7 +236,7 @@ static int fdp_nci_send_patch(struct nci_dev *ndev, u8 conn_id, u8 type)
static int fdp_nci_open(struct nci_dev *ndev)
{
- struct fdp_nci_info *info = nci_get_drvdata(ndev);
+ const struct fdp_nci_info *info = nci_get_drvdata(ndev);
return info->phy_ops->enable(info->phy);
}
@@ -260,7 +260,7 @@ static int fdp_nci_request_firmware(struct nci_dev *ndev)
{
struct fdp_nci_info *info = nci_get_drvdata(ndev);
struct device *dev = &info->phy->i2c_dev->dev;
- u8 *data;
+ const u8 *data;
int r;
r = request_firmware(&info->ram_patch, FDP_RAM_PATCH_NAME, dev);
@@ -269,7 +269,7 @@ static int fdp_nci_request_firmware(struct nci_dev *ndev)
return r;
}
- data = (u8 *) info->ram_patch->data;
+ data = info->ram_patch->data;
info->ram_patch_version =
data[FDP_FW_HEADER_SIZE] |
(data[FDP_FW_HEADER_SIZE + 1] << 8) |
@@ -610,9 +610,9 @@ static int fdp_nci_core_get_config_rsp_packet(struct nci_dev *ndev,
{
struct fdp_nci_info *info = nci_get_drvdata(ndev);
struct device *dev = &info->phy->i2c_dev->dev;
- struct nci_core_get_config_rsp *rsp = (void *) skb->data;
+ const struct nci_core_get_config_rsp *rsp = (void *) skb->data;
unsigned int i;
- u8 *p;
+ const u8 *p;
if (rsp->status == NCI_STATUS_OK) {
@@ -691,7 +691,7 @@ static const struct nci_ops nci_ops = {
int fdp_nci_probe(struct fdp_i2c_phy *phy, const struct nfc_phy_ops *phy_ops,
struct nci_dev **ndevp, int tx_headroom,
int tx_tailroom, u8 clock_type, u32 clock_freq,
- u8 *fw_vsc_cfg)
+ const u8 *fw_vsc_cfg)
{
struct device *dev = &phy->i2c_dev->dev;
struct fdp_nci_info *info;
diff --git a/drivers/nfc/fdp/fdp.h b/drivers/nfc/fdp/fdp.h
index dc048d4b977e..2e9161a4d7bf 100644
--- a/drivers/nfc/fdp/fdp.h
+++ b/drivers/nfc/fdp/fdp.h
@@ -23,7 +23,7 @@ struct fdp_i2c_phy {
int fdp_nci_probe(struct fdp_i2c_phy *phy, const struct nfc_phy_ops *phy_ops,
struct nci_dev **ndev, int tx_headroom, int tx_tailroom,
- u8 clock_type, u32 clock_freq, u8 *fw_vsc_cfg);
+ u8 clock_type, u32 clock_freq, const u8 *fw_vsc_cfg);
void fdp_nci_remove(struct nci_dev *ndev);
#endif /* __LOCAL_FDP_H_ */
diff --git a/drivers/nfc/fdp/i2c.c b/drivers/nfc/fdp/i2c.c
index 98e1876c9468..051c43a2a52f 100644
--- a/drivers/nfc/fdp/i2c.c
+++ b/drivers/nfc/fdp/i2c.c
@@ -36,7 +36,7 @@
print_hex_dump(KERN_DEBUG, prefix": ", DUMP_PREFIX_OFFSET, \
16, 1, (skb)->data, (skb)->len, 0)
-static void fdp_nci_i2c_reset(struct fdp_i2c_phy *phy)
+static void fdp_nci_i2c_reset(const struct fdp_i2c_phy *phy)
{
/* Reset RST/WakeUP for at least 100 micro-second */
gpiod_set_value_cansleep(phy->power_gpio, FDP_POWER_OFF);
@@ -47,7 +47,7 @@ static void fdp_nci_i2c_reset(struct fdp_i2c_phy *phy)
static int fdp_nci_i2c_enable(void *phy_id)
{
- struct fdp_i2c_phy *phy = phy_id;
+ const struct fdp_i2c_phy *phy = phy_id;
fdp_nci_i2c_reset(phy);
@@ -56,7 +56,7 @@ static int fdp_nci_i2c_enable(void *phy_id)
static void fdp_nci_i2c_disable(void *phy_id)
{
- struct fdp_i2c_phy *phy = phy_id;
+ const struct fdp_i2c_phy *phy = phy_id;
fdp_nci_i2c_reset(phy);
}
</cut>
4 years
- 3
- 2
Re: [CI-NOTIFY]: TCWG Bisect tcwg_kernel/llvm-master-aarch64-lts-allmodconfig - Build # 6 - Successful!
by Maxim Kuvyrkov
Hi Greg,
This appears to have been a fluke. Boot-testing succeeded before the merge and failed after. Boot-testing on allmodconfig doesn’t seem to be stable, so we are going to disable it.
Regards,
--
Maxim Kuvyrkov
https://www.linaro.org
> On 18 Aug 2021, at 08:38, Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> wrote:
>
> On Wed, Aug 18, 2021 at 05:22:07AM +0000, ci_notify(a)linaro.org wrote:
>> Successfully identified regression in *linux* in CI configuration tcwg_kernel/llvm-master-aarch64-lts-allmodconfig. So far, this commit has regressed CI configurations:
>> - tcwg_kernel/llvm-master-aarch64-lts-allmodconfig
>>
>> Culprit:
>> <cut>
>> commit 132a8267adabd645476b542b3b132c1b91988fe8
>> Author: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
>> Date: Thu Aug 12 13:22:21 2021 +0200
>>
>> Linux 5.10.58
>
> <snip>
>
> And what am I supposed to do with this information?
>
> --
> You received this message because you are subscribed to the Google Groups "Clang Built Linux" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to clang-built-linux+unsubscribe(a)googlegroups.com.
> To view this discussion on the web visit https://groups.google.com/d/msgid/clang-built-linux/YRyczv2OCq51edQh%40kroa….
4 years
- 1
- 0
clang-aarch64-full-2stage buildbot timeout
by Maxim Kuvyrkov
> > On Sep 22, 2021, at 11:23, Florian Hahn <florian_hahn at apple.com
> > wrote:
> >
> > Hi,
> >
> > It looks like a lot of the recent builds of clang-aarch64-full-2stage are timing out.
> >
> > E.g https://lab.llvm.org/buildbot/#/builders/179/builds/1078 while checking out sources
>
> > https://lab.llvm.org/buildbot/#/builders/179/builds/1076 during building stage2
> >
> > Is there anything that could be done to avoid such timeouts and avoid false positive failure emails?
> >
> > Cheers,
> > Florian
Hi Florian,
Thanks for the heads up. We’ve noticed these timeouts too, and have reduced the load in the machine. It appears to have helped.
>
> Looks like other bots are also hit by timeouts, including clang-arm64-windows-msvc-2stage (
> https://lab.llvm.org/buildbot/#/builders/120/builds/1197
> )
This one looks like a legitimate failure, and appears to have been fixed by https://github.com/llvm/llvm-project/commit/c6013f71a4555f6d9ef9c60e6bc4376… in build https://lab.llvm.org/buildbot/#/builders/120/builds/1200 .
Regards,
--
Maxim Kuvyrkov
https://www.linaro.org
4 years
- 1
- 0
[TCWG CI] 464.h264ref slowed down by 6% after llvm: Revert "Allow rematerialization of virtual reg uses"
by ci_notify＠linaro.org
After llvm commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Revert "Allow rematerialization of virtual reg uses"
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 6% from 11014 to 11697 perf samples
- 464.h264ref:[.] FastFullPelBlockMotionSearch slowed down by 40% from 1513 to 2118 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
cd investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 08d7eec06e8cf5c15a96ce11f311f1480291a441
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Date: Fri Sep 24 09:53:51 2021 -0700
Revert "Allow rematerialization of virtual reg uses"
Reverted due to two distcint performance regression reports.
This reverts commit 92c1fd19abb15bc68b1127a26137a69e033cdb39.
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 12 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 9 +-
llvm/test/CodeGen/AMDGPU/remat-sop.mir | 60 -
llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll | 28 +-
llvm/test/CodeGen/ARM/funnel-shift-rot.ll | 32 +-
llvm/test/CodeGen/ARM/funnel-shift.ll | 30 +-
.../test/CodeGen/ARM/illegal-bitfield-loadstore.ll | 30 +-
llvm/test/CodeGen/ARM/neon-copy.ll | 10 +-
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 227 +-
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 206 +-
llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 95 +-
llvm/test/CodeGen/Mips/llvm-ir/sub.ll | 31 +-
llvm/test/CodeGen/Mips/tls.ll | 4 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 120 +-
llvm/test/CodeGen/RISCV/atomic-signext.ll | 24 +-
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 96 +-
llvm/test/CodeGen/RISCV/mul.ll | 72 +-
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll | 12 +-
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll | 270 +-
llvm/test/CodeGen/RISCV/rv32zbb.ll | 94 +-
llvm/test/CodeGen/RISCV/rv32zbp.ll | 262 +-
llvm/test/CodeGen/RISCV/rv32zbt.ll | 206 +-
.../CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll | 150 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 146 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 3584 ++++++++++----------
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 664 ++--
llvm/test/CodeGen/RISCV/shifts.ll | 308 +-
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 208 +-
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 190 +-
llvm/test/CodeGen/Thumb/dyn-stackalloc.ll | 7 +-
.../tail-pred-disabled-in-loloops.ll | 14 +-
.../LowOverheadLoops/varying-outer-2d-reduction.ll | 64 +-
.../CodeGen/Thumb2/LowOverheadLoops/while-loops.ll | 67 +-
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll | 30 +-
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll | 82 +-
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll | 98 +-
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll | 529 +--
llvm/test/CodeGen/X86/addcarry.ll | 20 +-
llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll | 12 +-
llvm/test/CodeGen/X86/dag-update-nodetomatch.ll | 17 +-
.../X86/delete-dead-instrs-with-live-uses.mir | 4 +-
llvm/test/CodeGen/X86/inalloca-invoke.ll | 2 +-
llvm/test/CodeGen/X86/licm-regpressure.ll | 28 +-
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 40 +-
llvm/test/CodeGen/X86/sdiv_fix.ll | 5 +-
45 files changed, 4093 insertions(+), 4106 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index a0c52e2f1a13..c394ac910be1 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -117,11 +117,10 @@ public:
const MachineFunction &MF) const;
/// Return true if the instruction is trivially rematerializable, meaning it
- /// has no side effects. Uses of constants and unallocatable physical
- /// registers are always trivial to rematerialize so that the instructions
- /// result is independent of the place in the function. Uses of virtual
- /// registers are allowed but it is caller's responsility to ensure these
- /// operands are valid at the point the instruction is beeing moved.
+ /// has no side effects and requires no operands that aren't always available.
+ /// This means the only allowed uses are constants and unallocatable physical
+ /// registers so that the instructions result is independent of the place
+ /// in the function.
bool isTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA = nullptr) const {
return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
@@ -141,7 +140,8 @@ protected:
/// set, this hook lets the target specify whether the instruction is actually
/// trivially rematerializable, taking into consideration its operands. This
/// predicate must return false if the instruction has any side effects other
- /// than producing a value.
+ /// than producing a value, or if it requres any address registers that are
+ /// not always available.
/// Requirements must be check as stated in isTriviallyReMaterializable() .
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA) const {
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index fe7d60e0b7e2..1eab8e7443a7 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -921,8 +921,7 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
const MachineRegisterInfo &MRI = MF.getRegInfo();
// Remat clients assume operand 0 is the defined register.
- if (!MI.getNumOperands() || !MI.getOperand(0).isReg() ||
- MI.getOperand(0).isTied())
+ if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
return false;
Register DefReg = MI.getOperand(0).getReg();
@@ -984,6 +983,12 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
// same virtual register, though.
if (MO.isDef() && Reg != DefReg)
return false;
+
+ // Don't allow any virtual-register uses. Rematting an instruction with
+ // virtual register uses would length the live ranges of the uses, which
+ // is not necessarily a good idea, certainly not "trivial".
+ if (MO.isUse())
+ return false;
}
// Everything checked out.
diff --git a/llvm/test/CodeGen/AMDGPU/remat-sop.mir b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
index c9915aaabfde..ed799bfca028 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-sop.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
@@ -51,66 +51,6 @@ body: |
S_NOP 0, implicit %2
S_ENDPGM 0
...
-# The liverange of %0 covers a point of rematerialization, source value is
-# availabe.
----
-name: test_remat_s_mov_b32_vreg_src_long_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_remat_s_mov_b32_vreg_src_long_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_NOP 0, implicit %0
- S_ENDPGM 0
-...
-# The liverange of %0 does not cover a point of rematerialization, source value is
-# unavailabe and we do not want to artificially extend the liverange.
----
-name: test_no_remat_s_mov_b32_vreg_src_short_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_no_remat_s_mov_b32_vreg_src_short_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.1, addrspace 5)
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.0, addrspace 5)
- ; GCN: renamable $sgpr0 = S_MOV_B32 killed renamable $sgpr0
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.1, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.0, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_ENDPGM 0
-...
---
name: test_remat_s_mov_b64
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
index 175a2069a441..a4243276c70a 100644
--- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
+++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
@@ -29,20 +29,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; ENABLE-NEXT: pophs {r11, pc}
; ENABLE-NEXT: .LBB0_3: @ %while.body.preheader
; ENABLE-NEXT: movw r12, :lower16:skip
-; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: sub r1, r1, #1
; ENABLE-NEXT: movt r12, :upper16:skip
; ENABLE-NEXT: .LBB0_4: @ %while.body
; ENABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; ENABLE-NEXT: ldrb r1, [r0]
-; ENABLE-NEXT: ldrb r1, [r12, r1]
-; ENABLE-NEXT: add r0, r0, r1
-; ENABLE-NEXT: sub r1, r3, #1
-; ENABLE-NEXT: cmp r1, r3
+; ENABLE-NEXT: ldrb r3, [r0]
+; ENABLE-NEXT: ldrb r3, [r12, r3]
+; ENABLE-NEXT: add r0, r0, r3
+; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: cmp r3, r1
; ENABLE-NEXT: bhs .LBB0_6
; ENABLE-NEXT: @ %bb.5: @ %while.body
; ENABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; ENABLE-NEXT: cmp r0, r2
-; ENABLE-NEXT: mov r3, r1
+; ENABLE-NEXT: mov r1, r3
; ENABLE-NEXT: blo .LBB0_4
; ENABLE-NEXT: .LBB0_6: @ %if.end29
; ENABLE-NEXT: pop {r11, pc}
@@ -119,20 +119,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; DISABLE-NEXT: pophs {r11, pc}
; DISABLE-NEXT: .LBB0_3: @ %while.body.preheader
; DISABLE-NEXT: movw r12, :lower16:skip
-; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: sub r1, r1, #1
; DISABLE-NEXT: movt r12, :upper16:skip
; DISABLE-NEXT: .LBB0_4: @ %while.body
; DISABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; DISABLE-NEXT: ldrb r1, [r0]
-; DISABLE-NEXT: ldrb r1, [r12, r1]
-; DISABLE-NEXT: add r0, r0, r1
-; DISABLE-NEXT: sub r1, r3, #1
-; DISABLE-NEXT: cmp r1, r3
+; DISABLE-NEXT: ldrb r3, [r0]
+; DISABLE-NEXT: ldrb r3, [r12, r3]
+; DISABLE-NEXT: add r0, r0, r3
+; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: cmp r3, r1
; DISABLE-NEXT: bhs .LBB0_6
; DISABLE-NEXT: @ %bb.5: @ %while.body
; DISABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; DISABLE-NEXT: cmp r0, r2
-; DISABLE-NEXT: mov r3, r1
+; DISABLE-NEXT: mov r1, r3
; DISABLE-NEXT: blo .LBB0_4
; DISABLE-NEXT: .LBB0_6: @ %if.end29
; DISABLE-NEXT: pop {r11, pc}
diff --git a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
index ea15fcc5c824..55157875d355 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
@@ -73,13 +73,13 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: push {r4, r5, r11, lr}
; SCALAR-NEXT: rsb r3, r2, #0
; SCALAR-NEXT: and r4, r2, #63
-; SCALAR-NEXT: and r12, r3, #63
-; SCALAR-NEXT: rsb r3, r12, #32
+; SCALAR-NEXT: and lr, r3, #63
+; SCALAR-NEXT: rsb r3, lr, #32
; SCALAR-NEXT: lsl r2, r0, r4
-; SCALAR-NEXT: lsr lr, r0, r12
-; SCALAR-NEXT: orr r3, lr, r1, lsl r3
-; SCALAR-NEXT: subs lr, r12, #32
-; SCALAR-NEXT: lsrpl r3, r1, lr
+; SCALAR-NEXT: lsr r12, r0, lr
+; SCALAR-NEXT: orr r3, r12, r1, lsl r3
+; SCALAR-NEXT: subs r12, lr, #32
+; SCALAR-NEXT: lsrpl r3, r1, r12
; SCALAR-NEXT: subs r5, r4, #32
; SCALAR-NEXT: movwpl r2, #0
; SCALAR-NEXT: cmp r5, #0
@@ -88,8 +88,8 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: lsr r3, r0, r3
; SCALAR-NEXT: orr r3, r3, r1, lsl r4
; SCALAR-NEXT: lslpl r3, r0, r5
-; SCALAR-NEXT: lsr r0, r1, r12
-; SCALAR-NEXT: cmp lr, #0
+; SCALAR-NEXT: lsr r0, r1, lr
+; SCALAR-NEXT: cmp r12, #0
; SCALAR-NEXT: movwpl r0, #0
; SCALAR-NEXT: orr r1, r3, r0
; SCALAR-NEXT: mov r0, r2
@@ -245,15 +245,15 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r11, lr}
; CHECK-NEXT: push {r4, r5, r11, lr}
-; CHECK-NEXT: and r12, r2, #63
+; CHECK-NEXT: and lr, r2, #63
; CHECK-NEXT: rsb r2, r2, #0
-; CHECK-NEXT: rsb r3, r12, #32
+; CHECK-NEXT: rsb r3, lr, #32
; CHECK-NEXT: and r4, r2, #63
-; CHECK-NEXT: lsr lr, r0, r12
-; CHECK-NEXT: orr r3, lr, r1, lsl r3
-; CHECK-NEXT: subs lr, r12, #32
+; CHECK-NEXT: lsr r12, r0, lr
+; CHECK-NEXT: orr r3, r12, r1, lsl r3
+; CHECK-NEXT: subs r12, lr, #32
; CHECK-NEXT: lsl r2, r0, r4
-; CHECK-NEXT: lsrpl r3, r1, lr
+; CHECK-NEXT: lsrpl r3, r1, r12
; CHECK-NEXT: subs r5, r4, #32
; CHECK-NEXT: movwpl r2, #0
; CHECK-NEXT: cmp r5, #0
@@ -262,8 +262,8 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-NEXT: lsr r3, r0, r3
; CHECK-NEXT: orr r3, r3, r1, lsl r4
; CHECK-NEXT: lslpl r3, r0, r5
-; CHECK-NEXT: lsr r0, r1, r12
-; CHECK-NEXT: cmp lr, #0
+; CHECK-NEXT: lsr r0, r1, lr
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r0, #0
; CHECK-NEXT: orr r1, r0, r3
; CHECK-NEXT: mov r0, r2
diff --git a/llvm/test/CodeGen/ARM/funnel-shift.ll b/llvm/test/CodeGen/ARM/funnel-shift.ll
index 6372f9be2ca3..54c93b493c98 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift.ll
@@ -224,31 +224,31 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: bl __aeabi_uldivmod
; CHECK-NEXT: add r0, r2, #27
-; CHECK-NEXT: lsl r2, r7, #27
-; CHECK-NEXT: and r12, r0, #63
; CHECK-NEXT: lsl r6, r6, #27
+; CHECK-NEXT: and r1, r0, #63
+; CHECK-NEXT: lsl r2, r7, #27
; CHECK-NEXT: orr r7, r6, r7, lsr #5
-; CHECK-NEXT: rsb r3, r12, #32
-; CHECK-NEXT: lsr r2, r2, r12
; CHECK-NEXT: mov r6, #63
-; CHECK-NEXT: orr r2, r2, r7, lsl r3
-; CHECK-NEXT: subs r3, r12, #32
+; CHECK-NEXT: rsb r3, r1, #32
+; CHECK-NEXT: lsr r2, r2, r1
+; CHECK-NEXT: subs r12, r1, #32
; CHECK-NEXT: bic r6, r6, r0
+; CHECK-NEXT: orr r2, r2, r7, lsl r3
; CHECK-NEXT: lsl r5, r9, #1
-; CHECK-NEXT: lsrpl r2, r7, r3
-; CHECK-NEXT: subs r1, r6, #32
+; CHECK-NEXT: lsrpl r2, r7, r12
; CHECK-NEXT: lsl r0, r5, r6
-; CHECK-NEXT: lsl r4, r8, #1
+; CHECK-NEXT: subs r4, r6, #32
+; CHECK-NEXT: lsl r3, r8, #1
; CHECK-NEXT: movwpl r0, #0
-; CHECK-NEXT: orr r4, r4, r9, lsr #31
+; CHECK-NEXT: orr r3, r3, r9, lsr #31
; CHECK-NEXT: orr r0, r0, r2
; CHECK-NEXT: rsb r2, r6, #32
-; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: lsr r1, r7, r1
; CHECK-NEXT: lsr r2, r5, r2
-; CHECK-NEXT: orr r2, r2, r4, lsl r6
-; CHECK-NEXT: lslpl r2, r5, r1
-; CHECK-NEXT: lsr r1, r7, r12
-; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: orr r2, r2, r3, lsl r6
+; CHECK-NEXT: lslpl r2, r5, r4
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r1, #0
; CHECK-NEXT: orr r1, r2, r1
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
diff --git a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
index 0a0bb62b0a09..2922e0ed5423 100644
--- a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
+++ b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
@@ -91,17 +91,17 @@ define void @i56_or(i56* %a) {
; BE-LABEL: i56_or:
; BE: @ %bb.0:
; BE-NEXT: mov r1, r0
+; BE-NEXT: ldr r12, [r0]
; BE-NEXT: ldrh r2, [r1, #4]!
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: orr r2, r3, r2, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: strb r12, [r1, #2]
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: strb r2, [r1, #2]
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
%aa = load i56, i56* %a
@@ -127,13 +127,13 @@ define void @i56_and_or(i56* %a) {
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: strb r2, [r1, #2]
; BE-NEXT: orr r2, r3, r12, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: ldr r12, [r0]
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
diff --git a/llvm/test/CodeGen/ARM/neon-copy.ll b/llvm/test/CodeGen/ARM/neon-copy.ll
index 46490efb6631..09a991da2e59 100644
--- a/llvm/test/CodeGen/ARM/neon-copy.ll
+++ b/llvm/test/CodeGen/ARM/neon-copy.ll
@@ -1340,16 +1340,16 @@ define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, sp, #8
; CHECK-NEXT: vmov.u16 r1, d0[1]
-; CHECK-NEXT: and r12, r0, #3
+; CHECK-NEXT: and r0, r0, #3
; CHECK-NEXT: vmov.u16 r2, d0[2]
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vmov.u16 r3, d0[3]
-; CHECK-NEXT: orr r0, r0, r12, lsl #1
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vmov.u16 r12, d0[3]
+; CHECK-NEXT: orr r0, r3, r0, lsl #1
; CHECK-NEXT: vst1.16 {d0[0]}, [r0:16]
; CHECK-NEXT: vldr d0, [sp]
; CHECK-NEXT: vmov.16 d0[1], r1
; CHECK-NEXT: vmov.16 d0[2], r2
-; CHECK-NEXT: vmov.16 d0[3], r3
+; CHECK-NEXT: vmov.16 d0[3], r12
; CHECK-NEXT: add sp, sp, #8
; CHECK-NEXT: bx lr
%tmp = extractelement <8 x i16> %x, i32 0
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index a125446b27c3..8be7100d368b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -766,85 +766,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: move $2, $6
-; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
-; MMR3-NEXT: srlv $3, $7, $16
-; MMR3-NEXT: not16 $6, $16
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sll16 $2, $2, 1
-; MMR3-NEXT: sllv $2, $2, $6
-; MMR3-NEXT: li16 $6, 64
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: srlv $4, $4, $16
-; MMR3-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
-; MMR3-NEXT: subu16 $7, $6, $16
+; MMR3-NEXT: srlv $4, $7, $16
+; MMR3-NEXT: not16 $3, $16
+; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sll16 $2, $6, 1
+; MMR3-NEXT: sllv $3, $2, $3
+; MMR3-NEXT: li16 $2, 64
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: srlv $6, $6, $16
+; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: subu16 $7, $2, $16
; MMR3-NEXT: sllv $9, $5, $7
-; MMR3-NEXT: andi16 $5, $7, 32
-; MMR3-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
-; MMR3-NEXT: andi16 $6, $16, 32
-; MMR3-NEXT: sw $6, 36($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $3, $9
+; MMR3-NEXT: andi16 $2, $7, 32
+; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $5, $16, 32
+; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
+; MMR3-NEXT: move $4, $9
; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $3, $17, $5
-; MMR3-NEXT: movn $2, $4, $6
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: lw $17, 0($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $4, $17, $4
-; MMR3-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $6, 1
-; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $3
-; MMR3-NEXT: addiu $3, $16, -64
-; MMR3-NEXT: srav $1, $6, $3
-; MMR3-NEXT: andi16 $3, $3, 32
-; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $3
-; MMR3-NEXT: sllv $3, $6, $7
-; MMR3-NEXT: sw $3, 4($sp) # 4-byte Folded Spill
-; MMR3-NEXT: not16 $3, $7
-; MMR3-NEXT: srl16 $4, $17, 1
-; MMR3-NEXT: srlv $3, $4, $3
+; MMR3-NEXT: movn $4, $17, $2
+; MMR3-NEXT: movn $3, $6, $5
+; MMR3-NEXT: addiu $2, $16, -64
+; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srlv $5, $5, $2
+; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $17, 1
+; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: not16 $5, $2
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $4
+; MMR3-NEXT: srav $1, $17, $2
+; MMR3-NEXT: andi16 $2, $2, 32
+; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $2
+; MMR3-NEXT: sllv $2, $17, $7
+; MMR3-NEXT: not16 $4, $7
+; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $6, $7, 1
+; MMR3-NEXT: srlv $6, $6, $4
; MMR3-NEXT: sltiu $10, $16, 64
-; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $5, $3, $10
+; MMR3-NEXT: or16 $6, $2
+; MMR3-NEXT: srlv $2, $7, $16
+; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
+; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sllv $3, $4, $3
; MMR3-NEXT: or16 $3, $2
-; MMR3-NEXT: srlv $2, $17, $16
-; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $7, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sllv $17, $7, $4
-; MMR3-NEXT: or16 $17, $2
-; MMR3-NEXT: srav $11, $6, $16
-; MMR3-NEXT: lw $2, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $17, $11, $2
-; MMR3-NEXT: sra $2, $6, 31
+; MMR3-NEXT: srav $11, $17, $16
+; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $11, $4
+; MMR3-NEXT: sra $2, $17, 31
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: movn $4, $17, $10
-; MMR3-NEXT: lw $6, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $9, $6
-; MMR3-NEXT: lw $6, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: lw $7, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $3
+; MMR3-NEXT: move $8, $2
+; MMR3-NEXT: movn $8, $3, $10
+; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $6, $9, $3
+; MMR3-NEXT: li16 $3, 0
+; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $7, $3, $4
+; MMR3-NEXT: or16 $7, $6
; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
; MMR3-NEXT: movn $1, $2, $3
; MMR3-NEXT: movn $1, $7, $10
; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $3, $16
-; MMR3-NEXT: movn $11, $2, $6
+; MMR3-NEXT: movn $11, $2, $4
; MMR3-NEXT: movn $2, $11, $10
-; MMR3-NEXT: move $3, $4
+; MMR3-NEXT: move $3, $8
; MMR3-NEXT: move $4, $1
; MMR3-NEXT: lwp $16, 40($sp)
; MMR3-NEXT: addiusp 48
@@ -858,80 +852,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
-; MMR6-NEXT: move $12, $7
+; MMR6-NEXT: move $1, $7
; MMR6-NEXT: lw $3, 44($sp)
; MMR6-NEXT: li16 $2, 64
-; MMR6-NEXT: subu16 $16, $2, $3
-; MMR6-NEXT: sllv $1, $5, $16
-; MMR6-NEXT: andi16 $2, $16, 32
-; MMR6-NEXT: selnez $8, $1, $2
-; MMR6-NEXT: sllv $9, $4, $16
-; MMR6-NEXT: not16 $16, $16
-; MMR6-NEXT: srl16 $17, $5, 1
-; MMR6-NEXT: srlv $10, $17, $16
-; MMR6-NEXT: or $9, $9, $10
-; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $8, $8, $9
-; MMR6-NEXT: srlv $9, $7, $3
-; MMR6-NEXT: not16 $7, $3
-; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill
+; MMR6-NEXT: subu16 $7, $2, $3
+; MMR6-NEXT: sllv $8, $5, $7
+; MMR6-NEXT: andi16 $2, $7, 32
+; MMR6-NEXT: selnez $9, $8, $2
+; MMR6-NEXT: sllv $10, $4, $7
+; MMR6-NEXT: not16 $7, $7
+; MMR6-NEXT: srl16 $16, $5, 1
+; MMR6-NEXT: srlv $7, $16, $7
+; MMR6-NEXT: or $7, $10, $7
+; MMR6-NEXT: seleqz $7, $7, $2
+; MMR6-NEXT: or $7, $9, $7
+; MMR6-NEXT: srlv $9, $1, $3
+; MMR6-NEXT: not16 $16, $3
+; MMR6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $17, $6, 1
-; MMR6-NEXT: sllv $10, $17, $7
+; MMR6-NEXT: sllv $10, $17, $16
; MMR6-NEXT: or $9, $10, $9
; MMR6-NEXT: andi16 $17, $3, 32
; MMR6-NEXT: seleqz $9, $9, $17
; MMR6-NEXT: srlv $10, $6, $3
; MMR6-NEXT: selnez $11, $10, $17
; MMR6-NEXT: seleqz $10, $10, $17
-; MMR6-NEXT: or $8, $10, $8
-; MMR6-NEXT: seleqz $1, $1, $2
-; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: or $10, $10, $7
+; MMR6-NEXT: seleqz $12, $8, $2
+; MMR6-NEXT: or $8, $11, $9
; MMR6-NEXT: addiu $2, $3, -64
-; MMR6-NEXT: srlv $10, $5, $2
+; MMR6-NEXT: srlv $9, $5, $2
; MMR6-NEXT: sll16 $7, $4, 1
; MMR6-NEXT: not16 $16, $2
; MMR6-NEXT: sllv $11, $7, $16
; MMR6-NEXT: sltiu $13, $3, 64
-; MMR6-NEXT: or $1, $9, $1
-; MMR6-NEXT: selnez $8, $8, $13
-; MMR6-NEXT: or $9, $11, $10
-; MMR6-NEXT: srav $10, $4, $2
+; MMR6-NEXT: or $8, $8, $12
+; MMR6-NEXT: selnez $10, $10, $13
+; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: srav $11, $4, $2
; MMR6-NEXT: andi16 $2, $2, 32
-; MMR6-NEXT: seleqz $11, $10, $2
+; MMR6-NEXT: seleqz $12, $11, $2
; MMR6-NEXT: sra $14, $4, 31
; MMR6-NEXT: selnez $15, $14, $2
; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $11, $15, $11
-; MMR6-NEXT: seleqz $11, $11, $13
-; MMR6-NEXT: selnez $2, $10, $2
-; MMR6-NEXT: seleqz $10, $14, $13
-; MMR6-NEXT: or $8, $8, $11
-; MMR6-NEXT: selnez $8, $8, $3
-; MMR6-NEXT: selnez $1, $1, $13
+; MMR6-NEXT: or $12, $15, $12
+; MMR6-NEXT: seleqz $12, $12, $13
+; MMR6-NEXT: selnez $2, $11, $2
+; MMR6-NEXT: seleqz $11, $14, $13
+; MMR6-NEXT: or $10, $10, $12
+; MMR6-NEXT: selnez $10, $10, $3
+; MMR6-NEXT: selnez $8, $8, $13
; MMR6-NEXT: or $2, $2, $9
; MMR6-NEXT: srav $9, $4, $3
; MMR6-NEXT: seleqz $4, $9, $17
-; MMR6-NEXT: selnez $11, $14, $17
-; MMR6-NEXT: or $4, $11, $4
-; MMR6-NEXT: selnez $11, $4, $13
+; MMR6-NEXT: selnez $12, $14, $17
+; MMR6-NEXT: or $4, $12, $4
+; MMR6-NEXT: selnez $12, $4, $13
; MMR6-NEXT: seleqz $2, $2, $13
; MMR6-NEXT: seleqz $4, $6, $3
-; MMR6-NEXT: seleqz $6, $12, $3
+; MMR6-NEXT: seleqz $1, $1, $3
+; MMR6-NEXT: or $2, $8, $2
+; MMR6-NEXT: selnez $2, $2, $3
; MMR6-NEXT: or $1, $1, $2
-; MMR6-NEXT: selnez $1, $1, $3
-; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: or $4, $4, $8
-; MMR6-NEXT: or $6, $11, $10
-; MMR6-NEXT: srlv $2, $5, $3
-; MMR6-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $3, $7, $3
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: seleqz $2, $2, $17
-; MMR6-NEXT: selnez $3, $9, $17
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: selnez $2, $2, $13
-; MMR6-NEXT: or $3, $2, $10
-; MMR6-NEXT: move $2, $6
+; MMR6-NEXT: or $4, $4, $10
+; MMR6-NEXT: or $2, $12, $11
+; MMR6-NEXT: srlv $3, $5, $3
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: sllv $5, $7, $5
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: seleqz $3, $3, $17
+; MMR6-NEXT: selnez $5, $9, $17
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: selnez $3, $3, $13
+; MMR6-NEXT: or $3, $3, $11
; MMR6-NEXT: move $5, $1
; MMR6-NEXT: lw $16, 8($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index e4b4b3ae1d0f..ed2bfc9fcf60 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -776,77 +776,76 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 68($sp)
; MMR3-NEXT: li16 $2, 64
-; MMR3-NEXT: subu16 $17, $2, $16
-; MMR3-NEXT: sllv $9, $5, $17
-; MMR3-NEXT: andi16 $3, $17, 32
+; MMR3-NEXT: subu16 $7, $2, $16
+; MMR3-NEXT: sllv $9, $5, $7
+; MMR3-NEXT: move $17, $5
+; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $3, $7, 32
; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MMR3-NEXT: li16 $2, 0
; MMR3-NEXT: move $4, $9
; MMR3-NEXT: movn $4, $2, $3
-; MMR3-NEXT: srlv $5, $7, $16
+; MMR3-NEXT: srlv $5, $8, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 16($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sllv $2, $2, $3
; MMR3-NEXT: or16 $2, $5
-; MMR3-NEXT: srlv $7, $6, $16
+; MMR3-NEXT: srlv $5, $6, $16
+; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MMR3-NEXT: andi16 $3, $16, 32
; MMR3-NEXT: sw $3, 12($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $2, $7, $3
+; MMR3-NEXT: movn $2, $5, $3
; MMR3-NEXT: addiu $3, $16, -64
; MMR3-NEXT: or16 $2, $4
-; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $3, $6, $3
-; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $3, 1
-; MMR3-NEXT: sw $4, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $4
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: srlv $1, $3, $4
-; MMR3-NEXT: andi16 $4, $4, 32
+; MMR3-NEXT: srlv $4, $17, $3
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $4
+; MMR3-NEXT: lw $4, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $4, 1
+; MMR3-NEXT: not16 $5, $3
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $17
+; MMR3-NEXT: srlv $1, $4, $3
+; MMR3-NEXT: andi16 $3, $3, 32
+; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $3
; MMR3-NEXT: sltiu $10, $16, 64
; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: sllv $2, $3, $17
-; MMR3-NEXT: not16 $3, $17
-; MMR3-NEXT: srl16 $4, $6, 1
+; MMR3-NEXT: sllv $2, $4, $7
+; MMR3-NEXT: not16 $3, $7
+; MMR3-NEXT: lw $7, 0($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $4, $7, 1
; MMR3-NEXT: srlv $4, $4, $3
; MMR3-NEXT: or16 $4, $2
-; MMR3-NEXT: srlv $2, $6, $16
+; MMR3-NEXT: srlv $2, $7, $16
; MMR3-NEXT: lw $3, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $6, 0($sp) # 4-byte Folded Reload
; MMR3-NEXT: sllv $3, $6, $3
; MMR3-NEXT: or16 $3, $2
; MMR3-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MMR3-NEXT: srlv $2, $2, $16
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $2, $6
+; MMR3-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $2, $17
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movz $3, $17, $10
-; MMR3-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $4, $9, $17
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $4
+; MMR3-NEXT: li16 $6, 0
+; MMR3-NEXT: movz $3, $6, $10
+; MMR3-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $4, $9, $7
+; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $6, $7, $17
+; MMR3-NEXT: or16 $6, $4
; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $1, $17, $4
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $1, $7, $10
+; MMR3-NEXT: movn $1, $7, $4
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $1, $6, $10
; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $4, $16
-; MMR3-NEXT: movn $2, $17, $6
+; MMR3-NEXT: movn $2, $7, $17
; MMR3-NEXT: li16 $4, 0
; MMR3-NEXT: movz $2, $4, $10
; MMR3-NEXT: move $4, $1
@@ -856,91 +855,98 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
;
; MMR6-LABEL: lshr_i128:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: addiu $sp, $sp, -24
-; MMR6-NEXT: .cfi_def_cfa_offset 24
-; MMR6-NEXT: sw $17, 20($sp) # 4-byte Folded Spill
-; MMR6-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
+; MMR6-NEXT: addiu $sp, $sp, -32
+; MMR6-NEXT: .cfi_def_cfa_offset 32
+; MMR6-NEXT: sw $17, 28($sp) # 4-byte Folded Spill
+; MMR6-NEXT: sw $16, 24($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
; MMR6-NEXT: move $1, $7
-; MMR6-NEXT: move $7, $4
-; MMR6-NEXT: lw $3, 52($sp)
+; MMR6-NEXT: move $7, $5
+; MMR6-NEXT: lw $3, 60($sp)
; MMR6-NEXT: srlv $2, $1, $3
-; MMR6-NEXT: not16 $16, $3
-; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
-; MMR6-NEXT: move $4, $6
-; MMR6-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $5, $3
+; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: move $17, $6
+; MMR6-NEXT: sw $6, 16($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $6, $6, 1
-; MMR6-NEXT: sllv $6, $6, $16
+; MMR6-NEXT: sllv $6, $6, $5
; MMR6-NEXT: or $8, $6, $2
-; MMR6-NEXT: addiu $6, $3, -64
-; MMR6-NEXT: srlv $9, $5, $6
-; MMR6-NEXT: sll16 $2, $7, 1
-; MMR6-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
-; MMR6-NEXT: not16 $16, $6
+; MMR6-NEXT: addiu $5, $3, -64
+; MMR6-NEXT: srlv $9, $7, $5
+; MMR6-NEXT: move $6, $4
+; MMR6-NEXT: sll16 $2, $4, 1
+; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $16, $5
; MMR6-NEXT: sllv $10, $2, $16
; MMR6-NEXT: andi16 $16, $3, 32
; MMR6-NEXT: seleqz $8, $8, $16
; MMR6-NEXT: or $9, $10, $9
-; MMR6-NEXT: srlv $10, $4, $3
+; MMR6-NEXT: srlv $10, $17, $3
; MMR6-NEXT: selnez $11, $10, $16
; MMR6-NEXT: li16 $17, 64
; MMR6-NEXT: subu16 $2, $17, $3
-; MMR6-NEXT: sllv $12, $5, $2
+; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: move $17, $7
; MMR6-NEXT: andi16 $4, $2, 32
-; MMR6-NEXT: andi16 $17, $6, 32
-; MMR6-NEXT: seleqz $9, $9, $17
+; MMR6-NEXT: andi16 $7, $5, 32
+; MMR6-NEXT: sw $7, 20($sp) # 4-byte Folded Spill
+; MMR6-NEXT: seleqz $9, $9, $7
; MMR6-NEXT: seleqz $13, $12, $4
; MMR6-NEXT: or $8, $11, $8
; MMR6-NEXT: selnez $11, $12, $4
-; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: sllv $12, $6, $2
+; MMR6-NEXT: move $7, $6
+; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: not16 $2, $2
-; MMR6-NEXT: srl16 $6, $5, 1
+; MMR6-NEXT: srl16 $6, $17, 1
; MMR6-NEXT: srlv $2, $6, $2
; MMR6-NEXT: or $2, $12, $2
; MMR6-NEXT: seleqz $2, $2, $4
-; MMR6-NEXT: addiu $4, $3, -64
-; MMR6-NEXT: srlv $4, $7, $4
-; MMR6-NEXT: or $12, $11, $2
-; MMR6-NEXT: or $6, $8, $13
-; MMR6-NEXT: srlv $5, $5, $3
-; MMR6-NEXT: selnez $8, $4, $17
-; MMR6-NEXT: sltiu $11, $3, 64
-; MMR6-NEXT: selnez $13, $6, $11
-; MMR6-NEXT: or $8, $8, $9
+; MMR6-NEXT: srlv $4, $7, $5
+; MMR6-NEXT: or $11, $11, $2
+; MMR6-NEXT: or $5, $8, $13
+; MMR6-NEXT: srlv $6, $17, $3
+; MMR6-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: selnez $7, $4, $2
+; MMR6-NEXT: sltiu $8, $3, 64
+; MMR6-NEXT: selnez $12, $5, $8
+; MMR6-NEXT: or $7, $7, $9
+; MMR6-NEXT: lw $5, 12($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $9, $6, $2
+; MMR6-NEXT: sllv $9, $2, $5
; MMR6-NEXT: seleqz $10, $10, $16
-; MMR6-NEXT: li16 $2, 0
-; MMR6-NEXT: or $10, $10, $12
-; MMR6-NEXT: or $9, $9, $5
-; MMR6-NEXT: seleqz $5, $8, $11
-; MMR6-NEXT: seleqz $8, $2, $11
-; MMR6-NEXT: srlv $7, $7, $3
-; MMR6-NEXT: seleqz $2, $7, $16
-; MMR6-NEXT: selnez $2, $2, $11
+; MMR6-NEXT: li16 $5, 0
+; MMR6-NEXT: or $10, $10, $11
+; MMR6-NEXT: or $6, $9, $6
+; MMR6-NEXT: seleqz $2, $7, $8
+; MMR6-NEXT: seleqz $7, $5, $8
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: srlv $9, $5, $3
+; MMR6-NEXT: seleqz $11, $9, $16
+; MMR6-NEXT: selnez $11, $11, $8
; MMR6-NEXT: seleqz $1, $1, $3
-; MMR6-NEXT: or $5, $13, $5
-; MMR6-NEXT: selnez $5, $5, $3
-; MMR6-NEXT: or $5, $1, $5
-; MMR6-NEXT: or $2, $8, $2
-; MMR6-NEXT: seleqz $1, $9, $16
-; MMR6-NEXT: selnez $6, $7, $16
-; MMR6-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
-; MMR6-NEXT: seleqz $7, $7, $3
-; MMR6-NEXT: selnez $9, $10, $11
-; MMR6-NEXT: seleqz $4, $4, $17
-; MMR6-NEXT: seleqz $4, $4, $11
-; MMR6-NEXT: or $4, $9, $4
+; MMR6-NEXT: or $2, $12, $2
+; MMR6-NEXT: selnez $2, $2, $3
+; MMR6-NEXT: or $5, $1, $2
+; MMR6-NEXT: or $2, $7, $11
+; MMR6-NEXT: seleqz $1, $6, $16
+; MMR6-NEXT: selnez $6, $9, $16
+; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $9, $16, $3
+; MMR6-NEXT: selnez $10, $10, $8
+; MMR6-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $4, $4, $16
+; MMR6-NEXT: seleqz $4, $4, $8
+; MMR6-NEXT: or $4, $10, $4
; MMR6-NEXT: selnez $3, $4, $3
-; MMR6-NEXT: or $4, $7, $3
+; MMR6-NEXT: or $4, $9, $3
; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: selnez $1, $1, $11
-; MMR6-NEXT: or $3, $8, $1
-; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR6-NEXT: addiu $sp, $sp, 24
+; MMR6-NEXT: selnez $1, $1, $8
+; MMR6-NEXT: or $3, $7, $1
+; MMR6-NEXT: lw $16, 24($sp) # 4-byte Folded Reload
+; MMR6-NEXT: lw $17, 28($sp) # 4-byte Folded Reload
+; MMR6-NEXT: addiu $sp, $sp, 32
; MMR6-NEXT: jrc $ra
</cut>
4 years
- 1
- 0
[TCWG CI] 401.bzip2 grew in size by 2% after llvm: Revert "Allow rematerialization of virtual reg uses"
by ci_notify＠linaro.org
After llvm commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Revert "Allow rematerialization of virtual reg uses"
the following benchmarks grew in size by more than 1%:
- 401.bzip2 grew in size by 2% from 46428 to 47368 bytes
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -Os -flto
- Hardware: APM Mustang 8x X-Gene1
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_apm/llvm-master-aarch64-spec2k6-Os_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
cd investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 08d7eec06e8cf5c15a96ce11f311f1480291a441
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Date: Fri Sep 24 09:53:51 2021 -0700
Revert "Allow rematerialization of virtual reg uses"
Reverted due to two distcint performance regression reports.
This reverts commit 92c1fd19abb15bc68b1127a26137a69e033cdb39.
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 12 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 9 +-
llvm/test/CodeGen/AMDGPU/remat-sop.mir | 60 -
llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll | 28 +-
llvm/test/CodeGen/ARM/funnel-shift-rot.ll | 32 +-
llvm/test/CodeGen/ARM/funnel-shift.ll | 30 +-
.../test/CodeGen/ARM/illegal-bitfield-loadstore.ll | 30 +-
llvm/test/CodeGen/ARM/neon-copy.ll | 10 +-
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 227 +-
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 206 +-
llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 95 +-
llvm/test/CodeGen/Mips/llvm-ir/sub.ll | 31 +-
llvm/test/CodeGen/Mips/tls.ll | 4 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 120 +-
llvm/test/CodeGen/RISCV/atomic-signext.ll | 24 +-
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 96 +-
llvm/test/CodeGen/RISCV/mul.ll | 72 +-
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll | 12 +-
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll | 270 +-
llvm/test/CodeGen/RISCV/rv32zbb.ll | 94 +-
llvm/test/CodeGen/RISCV/rv32zbp.ll | 262 +-
llvm/test/CodeGen/RISCV/rv32zbt.ll | 206 +-
.../CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll | 150 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 146 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 3584 ++++++++++----------
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 664 ++--
llvm/test/CodeGen/RISCV/shifts.ll | 308 +-
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 208 +-
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 190 +-
llvm/test/CodeGen/Thumb/dyn-stackalloc.ll | 7 +-
.../tail-pred-disabled-in-loloops.ll | 14 +-
.../LowOverheadLoops/varying-outer-2d-reduction.ll | 64 +-
.../CodeGen/Thumb2/LowOverheadLoops/while-loops.ll | 67 +-
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll | 30 +-
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll | 82 +-
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll | 98 +-
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll | 529 +--
llvm/test/CodeGen/X86/addcarry.ll | 20 +-
llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll | 12 +-
llvm/test/CodeGen/X86/dag-update-nodetomatch.ll | 17 +-
.../X86/delete-dead-instrs-with-live-uses.mir | 4 +-
llvm/test/CodeGen/X86/inalloca-invoke.ll | 2 +-
llvm/test/CodeGen/X86/licm-regpressure.ll | 28 +-
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 40 +-
llvm/test/CodeGen/X86/sdiv_fix.ll | 5 +-
45 files changed, 4093 insertions(+), 4106 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index a0c52e2f1a13..c394ac910be1 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -117,11 +117,10 @@ public:
const MachineFunction &MF) const;
/// Return true if the instruction is trivially rematerializable, meaning it
- /// has no side effects. Uses of constants and unallocatable physical
- /// registers are always trivial to rematerialize so that the instructions
- /// result is independent of the place in the function. Uses of virtual
- /// registers are allowed but it is caller's responsility to ensure these
- /// operands are valid at the point the instruction is beeing moved.
+ /// has no side effects and requires no operands that aren't always available.
+ /// This means the only allowed uses are constants and unallocatable physical
+ /// registers so that the instructions result is independent of the place
+ /// in the function.
bool isTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA = nullptr) const {
return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
@@ -141,7 +140,8 @@ protected:
/// set, this hook lets the target specify whether the instruction is actually
/// trivially rematerializable, taking into consideration its operands. This
/// predicate must return false if the instruction has any side effects other
- /// than producing a value.
+ /// than producing a value, or if it requres any address registers that are
+ /// not always available.
/// Requirements must be check as stated in isTriviallyReMaterializable() .
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA) const {
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index fe7d60e0b7e2..1eab8e7443a7 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -921,8 +921,7 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
const MachineRegisterInfo &MRI = MF.getRegInfo();
// Remat clients assume operand 0 is the defined register.
- if (!MI.getNumOperands() || !MI.getOperand(0).isReg() ||
- MI.getOperand(0).isTied())
+ if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
return false;
Register DefReg = MI.getOperand(0).getReg();
@@ -984,6 +983,12 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
// same virtual register, though.
if (MO.isDef() && Reg != DefReg)
return false;
+
+ // Don't allow any virtual-register uses. Rematting an instruction with
+ // virtual register uses would length the live ranges of the uses, which
+ // is not necessarily a good idea, certainly not "trivial".
+ if (MO.isUse())
+ return false;
}
// Everything checked out.
diff --git a/llvm/test/CodeGen/AMDGPU/remat-sop.mir b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
index c9915aaabfde..ed799bfca028 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-sop.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
@@ -51,66 +51,6 @@ body: |
S_NOP 0, implicit %2
S_ENDPGM 0
...
-# The liverange of %0 covers a point of rematerialization, source value is
-# availabe.
----
-name: test_remat_s_mov_b32_vreg_src_long_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_remat_s_mov_b32_vreg_src_long_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_NOP 0, implicit %0
- S_ENDPGM 0
-...
-# The liverange of %0 does not cover a point of rematerialization, source value is
-# unavailabe and we do not want to artificially extend the liverange.
----
-name: test_no_remat_s_mov_b32_vreg_src_short_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_no_remat_s_mov_b32_vreg_src_short_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.1, addrspace 5)
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.0, addrspace 5)
- ; GCN: renamable $sgpr0 = S_MOV_B32 killed renamable $sgpr0
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.1, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.0, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_ENDPGM 0
-...
---
name: test_remat_s_mov_b64
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
index 175a2069a441..a4243276c70a 100644
--- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
+++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
@@ -29,20 +29,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; ENABLE-NEXT: pophs {r11, pc}
; ENABLE-NEXT: .LBB0_3: @ %while.body.preheader
; ENABLE-NEXT: movw r12, :lower16:skip
-; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: sub r1, r1, #1
; ENABLE-NEXT: movt r12, :upper16:skip
; ENABLE-NEXT: .LBB0_4: @ %while.body
; ENABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; ENABLE-NEXT: ldrb r1, [r0]
-; ENABLE-NEXT: ldrb r1, [r12, r1]
-; ENABLE-NEXT: add r0, r0, r1
-; ENABLE-NEXT: sub r1, r3, #1
-; ENABLE-NEXT: cmp r1, r3
+; ENABLE-NEXT: ldrb r3, [r0]
+; ENABLE-NEXT: ldrb r3, [r12, r3]
+; ENABLE-NEXT: add r0, r0, r3
+; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: cmp r3, r1
; ENABLE-NEXT: bhs .LBB0_6
; ENABLE-NEXT: @ %bb.5: @ %while.body
; ENABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; ENABLE-NEXT: cmp r0, r2
-; ENABLE-NEXT: mov r3, r1
+; ENABLE-NEXT: mov r1, r3
; ENABLE-NEXT: blo .LBB0_4
; ENABLE-NEXT: .LBB0_6: @ %if.end29
; ENABLE-NEXT: pop {r11, pc}
@@ -119,20 +119,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; DISABLE-NEXT: pophs {r11, pc}
; DISABLE-NEXT: .LBB0_3: @ %while.body.preheader
; DISABLE-NEXT: movw r12, :lower16:skip
-; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: sub r1, r1, #1
; DISABLE-NEXT: movt r12, :upper16:skip
; DISABLE-NEXT: .LBB0_4: @ %while.body
; DISABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; DISABLE-NEXT: ldrb r1, [r0]
-; DISABLE-NEXT: ldrb r1, [r12, r1]
-; DISABLE-NEXT: add r0, r0, r1
-; DISABLE-NEXT: sub r1, r3, #1
-; DISABLE-NEXT: cmp r1, r3
+; DISABLE-NEXT: ldrb r3, [r0]
+; DISABLE-NEXT: ldrb r3, [r12, r3]
+; DISABLE-NEXT: add r0, r0, r3
+; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: cmp r3, r1
; DISABLE-NEXT: bhs .LBB0_6
; DISABLE-NEXT: @ %bb.5: @ %while.body
; DISABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; DISABLE-NEXT: cmp r0, r2
-; DISABLE-NEXT: mov r3, r1
+; DISABLE-NEXT: mov r1, r3
; DISABLE-NEXT: blo .LBB0_4
; DISABLE-NEXT: .LBB0_6: @ %if.end29
; DISABLE-NEXT: pop {r11, pc}
diff --git a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
index ea15fcc5c824..55157875d355 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
@@ -73,13 +73,13 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: push {r4, r5, r11, lr}
; SCALAR-NEXT: rsb r3, r2, #0
; SCALAR-NEXT: and r4, r2, #63
-; SCALAR-NEXT: and r12, r3, #63
-; SCALAR-NEXT: rsb r3, r12, #32
+; SCALAR-NEXT: and lr, r3, #63
+; SCALAR-NEXT: rsb r3, lr, #32
; SCALAR-NEXT: lsl r2, r0, r4
-; SCALAR-NEXT: lsr lr, r0, r12
-; SCALAR-NEXT: orr r3, lr, r1, lsl r3
-; SCALAR-NEXT: subs lr, r12, #32
-; SCALAR-NEXT: lsrpl r3, r1, lr
+; SCALAR-NEXT: lsr r12, r0, lr
+; SCALAR-NEXT: orr r3, r12, r1, lsl r3
+; SCALAR-NEXT: subs r12, lr, #32
+; SCALAR-NEXT: lsrpl r3, r1, r12
; SCALAR-NEXT: subs r5, r4, #32
; SCALAR-NEXT: movwpl r2, #0
; SCALAR-NEXT: cmp r5, #0
@@ -88,8 +88,8 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: lsr r3, r0, r3
; SCALAR-NEXT: orr r3, r3, r1, lsl r4
; SCALAR-NEXT: lslpl r3, r0, r5
-; SCALAR-NEXT: lsr r0, r1, r12
-; SCALAR-NEXT: cmp lr, #0
+; SCALAR-NEXT: lsr r0, r1, lr
+; SCALAR-NEXT: cmp r12, #0
; SCALAR-NEXT: movwpl r0, #0
; SCALAR-NEXT: orr r1, r3, r0
; SCALAR-NEXT: mov r0, r2
@@ -245,15 +245,15 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r11, lr}
; CHECK-NEXT: push {r4, r5, r11, lr}
-; CHECK-NEXT: and r12, r2, #63
+; CHECK-NEXT: and lr, r2, #63
; CHECK-NEXT: rsb r2, r2, #0
-; CHECK-NEXT: rsb r3, r12, #32
+; CHECK-NEXT: rsb r3, lr, #32
; CHECK-NEXT: and r4, r2, #63
-; CHECK-NEXT: lsr lr, r0, r12
-; CHECK-NEXT: orr r3, lr, r1, lsl r3
-; CHECK-NEXT: subs lr, r12, #32
+; CHECK-NEXT: lsr r12, r0, lr
+; CHECK-NEXT: orr r3, r12, r1, lsl r3
+; CHECK-NEXT: subs r12, lr, #32
; CHECK-NEXT: lsl r2, r0, r4
-; CHECK-NEXT: lsrpl r3, r1, lr
+; CHECK-NEXT: lsrpl r3, r1, r12
; CHECK-NEXT: subs r5, r4, #32
; CHECK-NEXT: movwpl r2, #0
; CHECK-NEXT: cmp r5, #0
@@ -262,8 +262,8 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-NEXT: lsr r3, r0, r3
; CHECK-NEXT: orr r3, r3, r1, lsl r4
; CHECK-NEXT: lslpl r3, r0, r5
-; CHECK-NEXT: lsr r0, r1, r12
-; CHECK-NEXT: cmp lr, #0
+; CHECK-NEXT: lsr r0, r1, lr
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r0, #0
; CHECK-NEXT: orr r1, r0, r3
; CHECK-NEXT: mov r0, r2
diff --git a/llvm/test/CodeGen/ARM/funnel-shift.ll b/llvm/test/CodeGen/ARM/funnel-shift.ll
index 6372f9be2ca3..54c93b493c98 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift.ll
@@ -224,31 +224,31 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: bl __aeabi_uldivmod
; CHECK-NEXT: add r0, r2, #27
-; CHECK-NEXT: lsl r2, r7, #27
-; CHECK-NEXT: and r12, r0, #63
; CHECK-NEXT: lsl r6, r6, #27
+; CHECK-NEXT: and r1, r0, #63
+; CHECK-NEXT: lsl r2, r7, #27
; CHECK-NEXT: orr r7, r6, r7, lsr #5
-; CHECK-NEXT: rsb r3, r12, #32
-; CHECK-NEXT: lsr r2, r2, r12
; CHECK-NEXT: mov r6, #63
-; CHECK-NEXT: orr r2, r2, r7, lsl r3
-; CHECK-NEXT: subs r3, r12, #32
+; CHECK-NEXT: rsb r3, r1, #32
+; CHECK-NEXT: lsr r2, r2, r1
+; CHECK-NEXT: subs r12, r1, #32
; CHECK-NEXT: bic r6, r6, r0
+; CHECK-NEXT: orr r2, r2, r7, lsl r3
; CHECK-NEXT: lsl r5, r9, #1
-; CHECK-NEXT: lsrpl r2, r7, r3
-; CHECK-NEXT: subs r1, r6, #32
+; CHECK-NEXT: lsrpl r2, r7, r12
; CHECK-NEXT: lsl r0, r5, r6
-; CHECK-NEXT: lsl r4, r8, #1
+; CHECK-NEXT: subs r4, r6, #32
+; CHECK-NEXT: lsl r3, r8, #1
; CHECK-NEXT: movwpl r0, #0
-; CHECK-NEXT: orr r4, r4, r9, lsr #31
+; CHECK-NEXT: orr r3, r3, r9, lsr #31
; CHECK-NEXT: orr r0, r0, r2
; CHECK-NEXT: rsb r2, r6, #32
-; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: lsr r1, r7, r1
; CHECK-NEXT: lsr r2, r5, r2
-; CHECK-NEXT: orr r2, r2, r4, lsl r6
-; CHECK-NEXT: lslpl r2, r5, r1
-; CHECK-NEXT: lsr r1, r7, r12
-; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: orr r2, r2, r3, lsl r6
+; CHECK-NEXT: lslpl r2, r5, r4
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r1, #0
; CHECK-NEXT: orr r1, r2, r1
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
diff --git a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
index 0a0bb62b0a09..2922e0ed5423 100644
--- a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
+++ b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
@@ -91,17 +91,17 @@ define void @i56_or(i56* %a) {
; BE-LABEL: i56_or:
; BE: @ %bb.0:
; BE-NEXT: mov r1, r0
+; BE-NEXT: ldr r12, [r0]
; BE-NEXT: ldrh r2, [r1, #4]!
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: orr r2, r3, r2, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: strb r12, [r1, #2]
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: strb r2, [r1, #2]
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
%aa = load i56, i56* %a
@@ -127,13 +127,13 @@ define void @i56_and_or(i56* %a) {
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: strb r2, [r1, #2]
; BE-NEXT: orr r2, r3, r12, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: ldr r12, [r0]
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
diff --git a/llvm/test/CodeGen/ARM/neon-copy.ll b/llvm/test/CodeGen/ARM/neon-copy.ll
index 46490efb6631..09a991da2e59 100644
--- a/llvm/test/CodeGen/ARM/neon-copy.ll
+++ b/llvm/test/CodeGen/ARM/neon-copy.ll
@@ -1340,16 +1340,16 @@ define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, sp, #8
; CHECK-NEXT: vmov.u16 r1, d0[1]
-; CHECK-NEXT: and r12, r0, #3
+; CHECK-NEXT: and r0, r0, #3
; CHECK-NEXT: vmov.u16 r2, d0[2]
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vmov.u16 r3, d0[3]
-; CHECK-NEXT: orr r0, r0, r12, lsl #1
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vmov.u16 r12, d0[3]
+; CHECK-NEXT: orr r0, r3, r0, lsl #1
; CHECK-NEXT: vst1.16 {d0[0]}, [r0:16]
; CHECK-NEXT: vldr d0, [sp]
; CHECK-NEXT: vmov.16 d0[1], r1
; CHECK-NEXT: vmov.16 d0[2], r2
-; CHECK-NEXT: vmov.16 d0[3], r3
+; CHECK-NEXT: vmov.16 d0[3], r12
; CHECK-NEXT: add sp, sp, #8
; CHECK-NEXT: bx lr
%tmp = extractelement <8 x i16> %x, i32 0
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index a125446b27c3..8be7100d368b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -766,85 +766,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: move $2, $6
-; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
-; MMR3-NEXT: srlv $3, $7, $16
-; MMR3-NEXT: not16 $6, $16
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sll16 $2, $2, 1
-; MMR3-NEXT: sllv $2, $2, $6
-; MMR3-NEXT: li16 $6, 64
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: srlv $4, $4, $16
-; MMR3-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
-; MMR3-NEXT: subu16 $7, $6, $16
+; MMR3-NEXT: srlv $4, $7, $16
+; MMR3-NEXT: not16 $3, $16
+; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sll16 $2, $6, 1
+; MMR3-NEXT: sllv $3, $2, $3
+; MMR3-NEXT: li16 $2, 64
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: srlv $6, $6, $16
+; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: subu16 $7, $2, $16
; MMR3-NEXT: sllv $9, $5, $7
-; MMR3-NEXT: andi16 $5, $7, 32
-; MMR3-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
-; MMR3-NEXT: andi16 $6, $16, 32
-; MMR3-NEXT: sw $6, 36($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $3, $9
+; MMR3-NEXT: andi16 $2, $7, 32
+; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $5, $16, 32
+; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
+; MMR3-NEXT: move $4, $9
; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $3, $17, $5
-; MMR3-NEXT: movn $2, $4, $6
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: lw $17, 0($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $4, $17, $4
-; MMR3-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $6, 1
-; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $3
-; MMR3-NEXT: addiu $3, $16, -64
-; MMR3-NEXT: srav $1, $6, $3
-; MMR3-NEXT: andi16 $3, $3, 32
-; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $3
-; MMR3-NEXT: sllv $3, $6, $7
-; MMR3-NEXT: sw $3, 4($sp) # 4-byte Folded Spill
-; MMR3-NEXT: not16 $3, $7
-; MMR3-NEXT: srl16 $4, $17, 1
-; MMR3-NEXT: srlv $3, $4, $3
+; MMR3-NEXT: movn $4, $17, $2
+; MMR3-NEXT: movn $3, $6, $5
+; MMR3-NEXT: addiu $2, $16, -64
+; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srlv $5, $5, $2
+; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $17, 1
+; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: not16 $5, $2
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $4
+; MMR3-NEXT: srav $1, $17, $2
+; MMR3-NEXT: andi16 $2, $2, 32
+; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $2
+; MMR3-NEXT: sllv $2, $17, $7
+; MMR3-NEXT: not16 $4, $7
+; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $6, $7, 1
+; MMR3-NEXT: srlv $6, $6, $4
; MMR3-NEXT: sltiu $10, $16, 64
-; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $5, $3, $10
+; MMR3-NEXT: or16 $6, $2
+; MMR3-NEXT: srlv $2, $7, $16
+; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
+; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sllv $3, $4, $3
; MMR3-NEXT: or16 $3, $2
-; MMR3-NEXT: srlv $2, $17, $16
-; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $7, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sllv $17, $7, $4
-; MMR3-NEXT: or16 $17, $2
-; MMR3-NEXT: srav $11, $6, $16
-; MMR3-NEXT: lw $2, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $17, $11, $2
-; MMR3-NEXT: sra $2, $6, 31
+; MMR3-NEXT: srav $11, $17, $16
+; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $11, $4
+; MMR3-NEXT: sra $2, $17, 31
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: movn $4, $17, $10
-; MMR3-NEXT: lw $6, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $9, $6
-; MMR3-NEXT: lw $6, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: lw $7, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $3
+; MMR3-NEXT: move $8, $2
+; MMR3-NEXT: movn $8, $3, $10
+; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $6, $9, $3
+; MMR3-NEXT: li16 $3, 0
+; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $7, $3, $4
+; MMR3-NEXT: or16 $7, $6
; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
; MMR3-NEXT: movn $1, $2, $3
; MMR3-NEXT: movn $1, $7, $10
; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $3, $16
-; MMR3-NEXT: movn $11, $2, $6
+; MMR3-NEXT: movn $11, $2, $4
; MMR3-NEXT: movn $2, $11, $10
-; MMR3-NEXT: move $3, $4
+; MMR3-NEXT: move $3, $8
; MMR3-NEXT: move $4, $1
; MMR3-NEXT: lwp $16, 40($sp)
; MMR3-NEXT: addiusp 48
@@ -858,80 +852,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
-; MMR6-NEXT: move $12, $7
+; MMR6-NEXT: move $1, $7
; MMR6-NEXT: lw $3, 44($sp)
; MMR6-NEXT: li16 $2, 64
-; MMR6-NEXT: subu16 $16, $2, $3
-; MMR6-NEXT: sllv $1, $5, $16
-; MMR6-NEXT: andi16 $2, $16, 32
-; MMR6-NEXT: selnez $8, $1, $2
-; MMR6-NEXT: sllv $9, $4, $16
-; MMR6-NEXT: not16 $16, $16
-; MMR6-NEXT: srl16 $17, $5, 1
-; MMR6-NEXT: srlv $10, $17, $16
-; MMR6-NEXT: or $9, $9, $10
-; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $8, $8, $9
-; MMR6-NEXT: srlv $9, $7, $3
-; MMR6-NEXT: not16 $7, $3
-; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill
+; MMR6-NEXT: subu16 $7, $2, $3
+; MMR6-NEXT: sllv $8, $5, $7
+; MMR6-NEXT: andi16 $2, $7, 32
+; MMR6-NEXT: selnez $9, $8, $2
+; MMR6-NEXT: sllv $10, $4, $7
+; MMR6-NEXT: not16 $7, $7
+; MMR6-NEXT: srl16 $16, $5, 1
+; MMR6-NEXT: srlv $7, $16, $7
+; MMR6-NEXT: or $7, $10, $7
+; MMR6-NEXT: seleqz $7, $7, $2
+; MMR6-NEXT: or $7, $9, $7
+; MMR6-NEXT: srlv $9, $1, $3
+; MMR6-NEXT: not16 $16, $3
+; MMR6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $17, $6, 1
-; MMR6-NEXT: sllv $10, $17, $7
+; MMR6-NEXT: sllv $10, $17, $16
; MMR6-NEXT: or $9, $10, $9
; MMR6-NEXT: andi16 $17, $3, 32
; MMR6-NEXT: seleqz $9, $9, $17
; MMR6-NEXT: srlv $10, $6, $3
; MMR6-NEXT: selnez $11, $10, $17
; MMR6-NEXT: seleqz $10, $10, $17
-; MMR6-NEXT: or $8, $10, $8
-; MMR6-NEXT: seleqz $1, $1, $2
-; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: or $10, $10, $7
+; MMR6-NEXT: seleqz $12, $8, $2
+; MMR6-NEXT: or $8, $11, $9
; MMR6-NEXT: addiu $2, $3, -64
-; MMR6-NEXT: srlv $10, $5, $2
+; MMR6-NEXT: srlv $9, $5, $2
; MMR6-NEXT: sll16 $7, $4, 1
; MMR6-NEXT: not16 $16, $2
; MMR6-NEXT: sllv $11, $7, $16
; MMR6-NEXT: sltiu $13, $3, 64
-; MMR6-NEXT: or $1, $9, $1
-; MMR6-NEXT: selnez $8, $8, $13
-; MMR6-NEXT: or $9, $11, $10
-; MMR6-NEXT: srav $10, $4, $2
+; MMR6-NEXT: or $8, $8, $12
+; MMR6-NEXT: selnez $10, $10, $13
+; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: srav $11, $4, $2
; MMR6-NEXT: andi16 $2, $2, 32
-; MMR6-NEXT: seleqz $11, $10, $2
+; MMR6-NEXT: seleqz $12, $11, $2
; MMR6-NEXT: sra $14, $4, 31
; MMR6-NEXT: selnez $15, $14, $2
; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $11, $15, $11
-; MMR6-NEXT: seleqz $11, $11, $13
-; MMR6-NEXT: selnez $2, $10, $2
-; MMR6-NEXT: seleqz $10, $14, $13
-; MMR6-NEXT: or $8, $8, $11
-; MMR6-NEXT: selnez $8, $8, $3
-; MMR6-NEXT: selnez $1, $1, $13
+; MMR6-NEXT: or $12, $15, $12
+; MMR6-NEXT: seleqz $12, $12, $13
+; MMR6-NEXT: selnez $2, $11, $2
+; MMR6-NEXT: seleqz $11, $14, $13
+; MMR6-NEXT: or $10, $10, $12
+; MMR6-NEXT: selnez $10, $10, $3
+; MMR6-NEXT: selnez $8, $8, $13
; MMR6-NEXT: or $2, $2, $9
; MMR6-NEXT: srav $9, $4, $3
; MMR6-NEXT: seleqz $4, $9, $17
-; MMR6-NEXT: selnez $11, $14, $17
-; MMR6-NEXT: or $4, $11, $4
-; MMR6-NEXT: selnez $11, $4, $13
+; MMR6-NEXT: selnez $12, $14, $17
+; MMR6-NEXT: or $4, $12, $4
+; MMR6-NEXT: selnez $12, $4, $13
; MMR6-NEXT: seleqz $2, $2, $13
; MMR6-NEXT: seleqz $4, $6, $3
-; MMR6-NEXT: seleqz $6, $12, $3
+; MMR6-NEXT: seleqz $1, $1, $3
+; MMR6-NEXT: or $2, $8, $2
+; MMR6-NEXT: selnez $2, $2, $3
; MMR6-NEXT: or $1, $1, $2
-; MMR6-NEXT: selnez $1, $1, $3
-; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: or $4, $4, $8
-; MMR6-NEXT: or $6, $11, $10
-; MMR6-NEXT: srlv $2, $5, $3
-; MMR6-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $3, $7, $3
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: seleqz $2, $2, $17
-; MMR6-NEXT: selnez $3, $9, $17
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: selnez $2, $2, $13
-; MMR6-NEXT: or $3, $2, $10
-; MMR6-NEXT: move $2, $6
+; MMR6-NEXT: or $4, $4, $10
+; MMR6-NEXT: or $2, $12, $11
+; MMR6-NEXT: srlv $3, $5, $3
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: sllv $5, $7, $5
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: seleqz $3, $3, $17
+; MMR6-NEXT: selnez $5, $9, $17
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: selnez $3, $3, $13
+; MMR6-NEXT: or $3, $3, $11
; MMR6-NEXT: move $5, $1
; MMR6-NEXT: lw $16, 8($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index e4b4b3ae1d0f..ed2bfc9fcf60 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -776,77 +776,76 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 68($sp)
; MMR3-NEXT: li16 $2, 64
-; MMR3-NEXT: subu16 $17, $2, $16
-; MMR3-NEXT: sllv $9, $5, $17
-; MMR3-NEXT: andi16 $3, $17, 32
+; MMR3-NEXT: subu16 $7, $2, $16
+; MMR3-NEXT: sllv $9, $5, $7
+; MMR3-NEXT: move $17, $5
+; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $3, $7, 32
; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MMR3-NEXT: li16 $2, 0
; MMR3-NEXT: move $4, $9
; MMR3-NEXT: movn $4, $2, $3
-; MMR3-NEXT: srlv $5, $7, $16
+; MMR3-NEXT: srlv $5, $8, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 16($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sllv $2, $2, $3
; MMR3-NEXT: or16 $2, $5
-; MMR3-NEXT: srlv $7, $6, $16
+; MMR3-NEXT: srlv $5, $6, $16
+; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MMR3-NEXT: andi16 $3, $16, 32
; MMR3-NEXT: sw $3, 12($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $2, $7, $3
+; MMR3-NEXT: movn $2, $5, $3
; MMR3-NEXT: addiu $3, $16, -64
; MMR3-NEXT: or16 $2, $4
-; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $3, $6, $3
-; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $3, 1
-; MMR3-NEXT: sw $4, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $4
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: srlv $1, $3, $4
-; MMR3-NEXT: andi16 $4, $4, 32
+; MMR3-NEXT: srlv $4, $17, $3
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $4
+; MMR3-NEXT: lw $4, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $4, 1
+; MMR3-NEXT: not16 $5, $3
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $17
+; MMR3-NEXT: srlv $1, $4, $3
+; MMR3-NEXT: andi16 $3, $3, 32
+; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $3
; MMR3-NEXT: sltiu $10, $16, 64
; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: sllv $2, $3, $17
-; MMR3-NEXT: not16 $3, $17
-; MMR3-NEXT: srl16 $4, $6, 1
+; MMR3-NEXT: sllv $2, $4, $7
+; MMR3-NEXT: not16 $3, $7
+; MMR3-NEXT: lw $7, 0($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $4, $7, 1
; MMR3-NEXT: srlv $4, $4, $3
; MMR3-NEXT: or16 $4, $2
-; MMR3-NEXT: srlv $2, $6, $16
+; MMR3-NEXT: srlv $2, $7, $16
; MMR3-NEXT: lw $3, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $6, 0($sp) # 4-byte Folded Reload
; MMR3-NEXT: sllv $3, $6, $3
; MMR3-NEXT: or16 $3, $2
; MMR3-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MMR3-NEXT: srlv $2, $2, $16
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $2, $6
+; MMR3-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $2, $17
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movz $3, $17, $10
-; MMR3-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $4, $9, $17
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $4
+; MMR3-NEXT: li16 $6, 0
+; MMR3-NEXT: movz $3, $6, $10
+; MMR3-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $4, $9, $7
+; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $6, $7, $17
+; MMR3-NEXT: or16 $6, $4
; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $1, $17, $4
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $1, $7, $10
+; MMR3-NEXT: movn $1, $7, $4
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $1, $6, $10
; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $4, $16
-; MMR3-NEXT: movn $2, $17, $6
+; MMR3-NEXT: movn $2, $7, $17
; MMR3-NEXT: li16 $4, 0
; MMR3-NEXT: movz $2, $4, $10
; MMR3-NEXT: move $4, $1
@@ -856,91 +855,98 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
;
; MMR6-LABEL: lshr_i128:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: addiu $sp, $sp, -24
-; MMR6-NEXT: .cfi_def_cfa_offset 24
-; MMR6-NEXT: sw $17, 20($sp) # 4-byte Folded Spill
-; MMR6-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
+; MMR6-NEXT: addiu $sp, $sp, -32
+; MMR6-NEXT: .cfi_def_cfa_offset 32
+; MMR6-NEXT: sw $17, 28($sp) # 4-byte Folded Spill
+; MMR6-NEXT: sw $16, 24($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
; MMR6-NEXT: move $1, $7
-; MMR6-NEXT: move $7, $4
-; MMR6-NEXT: lw $3, 52($sp)
+; MMR6-NEXT: move $7, $5
+; MMR6-NEXT: lw $3, 60($sp)
; MMR6-NEXT: srlv $2, $1, $3
-; MMR6-NEXT: not16 $16, $3
-; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
-; MMR6-NEXT: move $4, $6
-; MMR6-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $5, $3
+; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: move $17, $6
+; MMR6-NEXT: sw $6, 16($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $6, $6, 1
-; MMR6-NEXT: sllv $6, $6, $16
+; MMR6-NEXT: sllv $6, $6, $5
; MMR6-NEXT: or $8, $6, $2
-; MMR6-NEXT: addiu $6, $3, -64
-; MMR6-NEXT: srlv $9, $5, $6
-; MMR6-NEXT: sll16 $2, $7, 1
-; MMR6-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
-; MMR6-NEXT: not16 $16, $6
+; MMR6-NEXT: addiu $5, $3, -64
+; MMR6-NEXT: srlv $9, $7, $5
+; MMR6-NEXT: move $6, $4
+; MMR6-NEXT: sll16 $2, $4, 1
+; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $16, $5
; MMR6-NEXT: sllv $10, $2, $16
; MMR6-NEXT: andi16 $16, $3, 32
; MMR6-NEXT: seleqz $8, $8, $16
; MMR6-NEXT: or $9, $10, $9
-; MMR6-NEXT: srlv $10, $4, $3
+; MMR6-NEXT: srlv $10, $17, $3
; MMR6-NEXT: selnez $11, $10, $16
; MMR6-NEXT: li16 $17, 64
; MMR6-NEXT: subu16 $2, $17, $3
-; MMR6-NEXT: sllv $12, $5, $2
+; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: move $17, $7
; MMR6-NEXT: andi16 $4, $2, 32
-; MMR6-NEXT: andi16 $17, $6, 32
-; MMR6-NEXT: seleqz $9, $9, $17
+; MMR6-NEXT: andi16 $7, $5, 32
+; MMR6-NEXT: sw $7, 20($sp) # 4-byte Folded Spill
+; MMR6-NEXT: seleqz $9, $9, $7
; MMR6-NEXT: seleqz $13, $12, $4
; MMR6-NEXT: or $8, $11, $8
; MMR6-NEXT: selnez $11, $12, $4
-; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: sllv $12, $6, $2
+; MMR6-NEXT: move $7, $6
+; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: not16 $2, $2
-; MMR6-NEXT: srl16 $6, $5, 1
+; MMR6-NEXT: srl16 $6, $17, 1
; MMR6-NEXT: srlv $2, $6, $2
; MMR6-NEXT: or $2, $12, $2
; MMR6-NEXT: seleqz $2, $2, $4
-; MMR6-NEXT: addiu $4, $3, -64
-; MMR6-NEXT: srlv $4, $7, $4
-; MMR6-NEXT: or $12, $11, $2
-; MMR6-NEXT: or $6, $8, $13
-; MMR6-NEXT: srlv $5, $5, $3
-; MMR6-NEXT: selnez $8, $4, $17
-; MMR6-NEXT: sltiu $11, $3, 64
-; MMR6-NEXT: selnez $13, $6, $11
-; MMR6-NEXT: or $8, $8, $9
+; MMR6-NEXT: srlv $4, $7, $5
+; MMR6-NEXT: or $11, $11, $2
+; MMR6-NEXT: or $5, $8, $13
+; MMR6-NEXT: srlv $6, $17, $3
+; MMR6-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: selnez $7, $4, $2
+; MMR6-NEXT: sltiu $8, $3, 64
+; MMR6-NEXT: selnez $12, $5, $8
+; MMR6-NEXT: or $7, $7, $9
+; MMR6-NEXT: lw $5, 12($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $9, $6, $2
+; MMR6-NEXT: sllv $9, $2, $5
; MMR6-NEXT: seleqz $10, $10, $16
-; MMR6-NEXT: li16 $2, 0
-; MMR6-NEXT: or $10, $10, $12
-; MMR6-NEXT: or $9, $9, $5
-; MMR6-NEXT: seleqz $5, $8, $11
-; MMR6-NEXT: seleqz $8, $2, $11
-; MMR6-NEXT: srlv $7, $7, $3
-; MMR6-NEXT: seleqz $2, $7, $16
-; MMR6-NEXT: selnez $2, $2, $11
+; MMR6-NEXT: li16 $5, 0
+; MMR6-NEXT: or $10, $10, $11
+; MMR6-NEXT: or $6, $9, $6
+; MMR6-NEXT: seleqz $2, $7, $8
+; MMR6-NEXT: seleqz $7, $5, $8
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: srlv $9, $5, $3
+; MMR6-NEXT: seleqz $11, $9, $16
+; MMR6-NEXT: selnez $11, $11, $8
; MMR6-NEXT: seleqz $1, $1, $3
-; MMR6-NEXT: or $5, $13, $5
-; MMR6-NEXT: selnez $5, $5, $3
-; MMR6-NEXT: or $5, $1, $5
-; MMR6-NEXT: or $2, $8, $2
-; MMR6-NEXT: seleqz $1, $9, $16
-; MMR6-NEXT: selnez $6, $7, $16
-; MMR6-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
-; MMR6-NEXT: seleqz $7, $7, $3
-; MMR6-NEXT: selnez $9, $10, $11
-; MMR6-NEXT: seleqz $4, $4, $17
-; MMR6-NEXT: seleqz $4, $4, $11
-; MMR6-NEXT: or $4, $9, $4
+; MMR6-NEXT: or $2, $12, $2
+; MMR6-NEXT: selnez $2, $2, $3
+; MMR6-NEXT: or $5, $1, $2
+; MMR6-NEXT: or $2, $7, $11
+; MMR6-NEXT: seleqz $1, $6, $16
+; MMR6-NEXT: selnez $6, $9, $16
+; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $9, $16, $3
+; MMR6-NEXT: selnez $10, $10, $8
+; MMR6-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $4, $4, $16
+; MMR6-NEXT: seleqz $4, $4, $8
+; MMR6-NEXT: or $4, $10, $4
; MMR6-NEXT: selnez $3, $4, $3
-; MMR6-NEXT: or $4, $7, $3
+; MMR6-NEXT: or $4, $9, $3
; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: selnez $1, $1, $11
-; MMR6-NEXT: or $3, $8, $1
-; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR6-NEXT: addiu $sp, $sp, 24
+; MMR6-NEXT: selnez $1, $1, $8
+; MMR6-NEXT: or $3, $7, $1
+; MMR6-NEXT: lw $16, 24($sp) # 4-byte Folded Reload
+; MMR6-NEXT: lw $17, 28($sp) # 4-byte Folded Reload
+; MMR6-NEXT: addiu $sp, $sp, 32
; MMR6-NEXT: jrc $ra
</cut>
4 years
- 1
- 0
[TCWG CI] 462.libquantum grew in size by 3% after llvm: [JumpThreading] Ignore free instructions
by ci_notify＠linaro.org
After llvm commit 1e3c6fc7cb9d2ee6a5328881f95d6643afeadbff
Author: Nikita Popov <nikita.ppv(a)gmail.com>
[JumpThreading] Ignore free instructions
the following benchmarks grew in size by more than 1%:
- 462.libquantum grew in size by 3% from 14035 to 14398 bytes
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: arm-linux-gnueabihf
- Compiler flags: -Os -flto -mthumb
- Hardware: APM Mustang 8x X-Gene1
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-1e3c6fc7cb9d2ee6a5328881f95d6643afeadbff
cd investigate-llvm-1e3c6fc7cb9d2ee6a5328881f95d6643afeadbff
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 1e3c6fc7cb9d2ee6a5328881f95d6643afeadbff
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 1a6e1ee42a6af255d45e3fd2fe87021dd31f79bb
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 1e3c6fc7cb9d2ee6a5328881f95d6643afeadbff
Author: Nikita Popov <nikita.ppv(a)gmail.com>
Date: Wed Sep 22 21:34:24 2021 +0200
[JumpThreading] Ignore free instructions
This is basically D108837 but for jump threading. Free instructions
should be ignored for the threading decision. JumpThreading already
skips some free instructions (like pointer bitcasts), but does not
skip various free intrinsics -- in fact, it currently gives them a
fairly large cost of 2.
Differential Revision: https://reviews.llvm.org/D110290
---
.../include/llvm/Transforms/Scalar/JumpThreading.h | 8 +--
llvm/lib/Transforms/Scalar/JumpThreading.cpp | 61 ++++++++++------------
.../Transforms/JumpThreading/free_instructions.ll | 24 +++++----
.../inlining-alignment-assumptions.ll | 12 ++---
4 files changed, 52 insertions(+), 53 deletions(-)
diff --git a/llvm/include/llvm/Transforms/Scalar/JumpThreading.h b/llvm/include/llvm/Transforms/Scalar/JumpThreading.h
index 816ea1071e52..0ac7d7c62b7a 100644
--- a/llvm/include/llvm/Transforms/Scalar/JumpThreading.h
+++ b/llvm/include/llvm/Transforms/Scalar/JumpThreading.h
@@ -44,6 +44,7 @@ class PHINode;
class SelectInst;
class SwitchInst;
class TargetLibraryInfo;
+class TargetTransformInfo;
class Value;
/// A private "module" namespace for types and utilities used by
@@ -78,6 +79,7 @@ enum ConstantPreference { WantInteger, WantBlockAddress };
/// revectored to the false side of the second if.
class JumpThreadingPass : public PassInfoMixin<JumpThreadingPass> {
TargetLibraryInfo *TLI;
+ TargetTransformInfo *TTI;
LazyValueInfo *LVI;
AAResults *AA;
DomTreeUpdater *DTU;
@@ -99,9 +101,9 @@ public:
JumpThreadingPass(bool InsertFreezeWhenUnfoldingSelect = false, int T = -1);
// Glue for old PM.
- bool runImpl(Function &F, TargetLibraryInfo *TLI, LazyValueInfo *LVI,
- AAResults *AA, DomTreeUpdater *DTU, bool HasProfileData,
- std::unique_ptr<BlockFrequencyInfo> BFI,
+ bool runImpl(Function &F, TargetLibraryInfo *TLI, TargetTransformInfo *TTI,
+ LazyValueInfo *LVI, AAResults *AA, DomTreeUpdater *DTU,
+ bool HasProfileData, std::unique_ptr<BlockFrequencyInfo> BFI,
std::unique_ptr<BranchProbabilityInfo> BPI);
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
diff --git a/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
index 688902ecb9ff..fe9a7211967c 100644
--- a/llvm/lib/Transforms/Scalar/JumpThreading.cpp
+++ b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
@@ -331,7 +331,7 @@ bool JumpThreading::runOnFunction(Function &F) {
BFI.reset(new BlockFrequencyInfo(F, *BPI, LI));
}
- bool Changed = Impl.runImpl(F, TLI, LVI, AA, &DTU, F.hasProfileData(),
+ bool Changed = Impl.runImpl(F, TLI, TTI, LVI, AA, &DTU, F.hasProfileData(),
std::move(BFI), std::move(BPI));
if (PrintLVIAfterJumpThreading) {
dbgs() << "LVI for function '" << F.getName() << "':\n";
@@ -360,7 +360,7 @@ PreservedAnalyses JumpThreadingPass::run(Function &F,
BFI.reset(new BlockFrequencyInfo(F, *BPI, LI));
}
- bool Changed = runImpl(F, &TLI, &LVI, &AA, &DTU, F.hasProfileData(),
+ bool Changed = runImpl(F, &TLI, &TTI, &LVI, &AA, &DTU, F.hasProfileData(),
std::move(BFI), std::move(BPI));
if (PrintLVIAfterJumpThreading) {
@@ -377,12 +377,14 @@ PreservedAnalyses JumpThreadingPass::run(Function &F,
}
bool JumpThreadingPass::runImpl(Function &F, TargetLibraryInfo *TLI_,
- LazyValueInfo *LVI_, AliasAnalysis *AA_,
- DomTreeUpdater *DTU_, bool HasProfileData_,
+ TargetTransformInfo *TTI_, LazyValueInfo *LVI_,
+ AliasAnalysis *AA_, DomTreeUpdater *DTU_,
+ bool HasProfileData_,
std::unique_ptr<BlockFrequencyInfo> BFI_,
std::unique_ptr<BranchProbabilityInfo> BPI_) {
LLVM_DEBUG(dbgs() << "Jump threading on function '" << F.getName() << "'\n");
TLI = TLI_;
+ TTI = TTI_;
LVI = LVI_;
AA = AA_;
DTU = DTU_;
@@ -514,7 +516,8 @@ static void replaceFoldableUses(Instruction *Cond, Value *ToVal) {
/// Return the cost of duplicating a piece of this block from first non-phi
/// and before StopAt instruction to thread across it. Stop scanning the block
/// when exceeding the threshold. If duplication is impossible, returns ~0U.
-static unsigned getJumpThreadDuplicationCost(BasicBlock *BB,
+static unsigned getJumpThreadDuplicationCost(const TargetTransformInfo *TTI,
+ BasicBlock *BB,
Instruction *StopAt,
unsigned Threshold) {
assert(StopAt->getParent() == BB && "Not an instruction from proper BB?");
@@ -550,26 +553,21 @@ static unsigned getJumpThreadDuplicationCost(BasicBlock *BB,
if (Size > Threshold)
return Size;
- // Debugger intrinsics don't incur code size.
- if (isa<DbgInfoIntrinsic>(I)) continue;
-
- // Pseudo-probes don't incur code size.
- if (isa<PseudoProbeInst>(I))
- continue;
-
- // If this is a pointer->pointer bitcast, it is free.
- if (isa<BitCastInst>(I) && I->getType()->isPointerTy())
- continue;
-
- // Freeze instruction is free, too.
- if (isa<FreezeInst>(I))
- continue;
-
// Bail out if this instruction gives back a token type, it is not possible
// to duplicate it if it is used outside this BB.
if (I->getType()->isTokenTy() && I->isUsedOutsideOfBlock(BB))
return ~0U;
+ // Blocks with NoDuplicate are modelled as having infinite cost, so they
+ // are never duplicated.
+ if (const CallInst *CI = dyn_cast<CallInst>(I))
+ if (CI->cannotDuplicate() || CI->isConvergent())
+ return ~0U;
+
+ if (TTI->getUserCost(&*I, TargetTransformInfo::TCK_SizeAndLatency)
+ == TargetTransformInfo::TCC_Free)
+ continue;
+
// All other instructions count for at least one unit.
++Size;
@@ -578,11 +576,7 @@ static unsigned getJumpThreadDuplicationCost(BasicBlock *BB,
// as having cost of 2 total, and if they are a vector intrinsic, we model
// them as having cost 1.
if (const CallInst *CI = dyn_cast<CallInst>(I)) {
- if (CI->cannotDuplicate() || CI->isConvergent())
- // Blocks with NoDuplicate are modelled as having infinite cost, so they
- // are never duplicated.
- return ~0U;
- else if (!isa<IntrinsicInst>(CI))
+ if (!isa<IntrinsicInst>(CI))
Size += 3;
else if (!CI->getType()->isVectorTy())
Size += 1;
@@ -2234,10 +2228,10 @@ bool JumpThreadingPass::maybethreadThroughTwoBasicBlocks(BasicBlock *BB,
}
// Compute the cost of duplicating BB and PredBB.
- unsigned BBCost =
- getJumpThreadDuplicationCost(BB, BB->getTerminator(), BBDupThreshold);
+ unsigned BBCost = getJumpThreadDuplicationCost(
+ TTI, BB, BB->getTerminator(), BBDupThreshold);
unsigned PredBBCost = getJumpThreadDuplicationCost(
- PredBB, PredBB->getTerminator(), BBDupThreshold);
+ TTI, PredBB, PredBB->getTerminator(), BBDupThreshold);
// Give up if costs are too high. We need to check BBCost and PredBBCost
// individually before checking their sum because getJumpThreadDuplicationCost
@@ -2345,8 +2339,8 @@ bool JumpThreadingPass::tryThreadEdge(
return false;
}
- unsigned JumpThreadCost =
- getJumpThreadDuplicationCost(BB, BB->getTerminator(), BBDupThreshold);
+ unsigned JumpThreadCost = getJumpThreadDuplicationCost(
+ TTI, BB, BB->getTerminator(), BBDupThreshold);
if (JumpThreadCost > BBDupThreshold) {
LLVM_DEBUG(dbgs() << " Not threading BB '" << BB->getName()
<< "' - Cost is too high: " << JumpThreadCost << "\n");
@@ -2614,8 +2608,8 @@ bool JumpThreadingPass::duplicateCondBranchOnPHIIntoPred(
return false;
}
- unsigned DuplicationCost =
- getJumpThreadDuplicationCost(BB, BB->getTerminator(), BBDupThreshold);
+ unsigned DuplicationCost = getJumpThreadDuplicationCost(
+ TTI, BB, BB->getTerminator(), BBDupThreshold);
if (DuplicationCost > BBDupThreshold) {
LLVM_DEBUG(dbgs() << " Not duplicating BB '" << BB->getName()
<< "' - Cost is too high: " << DuplicationCost << "\n");
@@ -3031,7 +3025,8 @@ bool JumpThreadingPass::threadGuard(BasicBlock *BB, IntrinsicInst *Guard,
ValueToValueMapTy UnguardedMapping, GuardedMapping;
Instruction *AfterGuard = Guard->getNextNode();
- unsigned Cost = getJumpThreadDuplicationCost(BB, AfterGuard, BBDupThreshold);
+ unsigned Cost =
+ getJumpThreadDuplicationCost(TTI, BB, AfterGuard, BBDupThreshold);
if (Cost > BBDupThreshold)
return false;
// Duplicate all instructions before the guard and the guard itself to the
diff --git a/llvm/test/Transforms/JumpThreading/free_instructions.ll b/llvm/test/Transforms/JumpThreading/free_instructions.ll
index f768ec996779..76392af77d33 100644
--- a/llvm/test/Transforms/JumpThreading/free_instructions.ll
+++ b/llvm/test/Transforms/JumpThreading/free_instructions.ll
@@ -5,26 +5,28 @@
; the jump threading threshold, as everything else are free instructions.
define i32 @free_instructions(i1 %c, i32* %p) {
; CHECK-LABEL: @free_instructions(
-; CHECK-NEXT: br i1 [[C:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
-; CHECK: if:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[IF2:%.*]], label [[ELSE2:%.*]]
+; CHECK: if2:
; CHECK-NEXT: store i32 -1, i32* [[P:%.*]], align 4
-; CHECK-NEXT: br label [[JOIN:%.*]]
-; CHECK: else:
-; CHECK-NEXT: store i32 -2, i32* [[P]], align 4
-; CHECK-NEXT: br label [[JOIN]]
-; CHECK: join:
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META0:![0-9]+]])
; CHECK-NEXT: store i32 1, i32* [[P]], align 4, !noalias !0
; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[P]], i64 32) ]
; CHECK-NEXT: store i32 2, i32* [[P]], align 4
+; CHECK-NEXT: [[P21:%.*]] = bitcast i32* [[P]] to i8*
+; CHECK-NEXT: [[P32:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* [[P21]])
+; CHECK-NEXT: [[P43:%.*]] = bitcast i8* [[P32]] to i32*
+; CHECK-NEXT: store i32 3, i32* [[P43]], align 4, !invariant.group !3
+; CHECK-NEXT: ret i32 0
+; CHECK: else2:
+; CHECK-NEXT: store i32 -2, i32* [[P]], align 4
+; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])
+; CHECK-NEXT: store i32 1, i32* [[P]], align 4, !noalias !4
+; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[P]], i64 32) ]
+; CHECK-NEXT: store i32 2, i32* [[P]], align 4
; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P]] to i8*
; CHECK-NEXT: [[P3:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* [[P2]])
; CHECK-NEXT: [[P4:%.*]] = bitcast i8* [[P3]] to i32*
; CHECK-NEXT: store i32 3, i32* [[P4]], align 4, !invariant.group !3
-; CHECK-NEXT: br i1 [[C]], label [[IF2:%.*]], label [[ELSE2:%.*]]
-; CHECK: if2:
-; CHECK-NEXT: ret i32 0
-; CHECK: else2:
; CHECK-NEXT: ret i32 1
;
br i1 %c, label %if, label %else
diff --git a/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll b/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
index 57014e856a09..f764a59dd8a2 100644
--- a/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
+++ b/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
@@ -32,13 +32,10 @@ define void @caller1(i1 %c, i64* align 1 %ptr) {
; ASSUMPTIONS-OFF-NEXT: br label [[COMMON_RET]]
;
; ASSUMPTIONS-ON-LABEL: @caller1(
-; ASSUMPTIONS-ON-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE1:%.*]]
-; ASSUMPTIONS-ON: false1:
-; ASSUMPTIONS-ON-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 4
-; ASSUMPTIONS-ON-NEXT: br label [[COMMON_RET]]
+; ASSUMPTIONS-ON-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE2:%.*]]
; ASSUMPTIONS-ON: common.ret:
-; ASSUMPTIONS-ON-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE1]] ], [ 2, [[TMP0:%.*]] ]
-; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(i64* [[PTR]], i64 8) ]
+; ASSUMPTIONS-ON-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE2]] ], [ 2, [[TMP0:%.*]] ]
+; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(i64* [[PTR:%.*]], i64 8) ]
; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
@@ -47,6 +44,9 @@ define void @caller1(i1 %c, i64* align 1 %ptr) {
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 [[DOTSINK]], i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: ret void
+; ASSUMPTIONS-ON: false2:
+; ASSUMPTIONS-ON-NEXT: store volatile i64 1, i64* [[PTR]], align 4
+; ASSUMPTIONS-ON-NEXT: br label [[COMMON_RET]]
;
br i1 %c, label %true1, label %false1
</cut>
4 years
- 2
- 2
[TCWG CI] Regression caused by llvm: Revert "Allow rematerialization of virtual reg uses"
by ci_notify＠linaro.org
[TCWG CI] Regression caused by llvm: Revert "Allow rematerialization of virtual reg uses":
commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Revert "Allow rematerialization of virtual reg uses"
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_llvm:
-5
# build_abe qemu:
-2
# linux_n_obj:
21880
# First few build errors in logs:
# 00:04:00 arch/arm/lib/xor-neon.c:30:2: error: This code requires at least version 4.6 of GCC [-Werror,-W#warnings]
# 00:04:00 make[1]: *** [scripts/Makefile.build:277: arch/arm/lib/xor-neon.o] Error 1
# 00:04:00 make: *** [Makefile:1868: arch/arm/lib] Error 2
# 00:05:21 crypto/wp512.c:782:13: error: stack frame size (1176) exceeds limit (1024) in function 'wp512_process_buffer' [-Werror,-Wframe-larger-than]
# 00:05:21 make[1]: *** [scripts/Makefile.build:277: crypto/wp512.o] Error 1
# 00:08:06 make: *** [Makefile:1868: crypto] Error 2
# 00:18:48 drivers/gpu/drm/selftests/test-drm_mm.c:372:12: error: stack frame size (1032) exceeds limit (1024) in function '__igt_reserve' [-Werror,-Wframe-larger-than]
# 00:18:49 make[4]: *** [scripts/Makefile.build:277: drivers/gpu/drm/selftests/test-drm_mm.o] Error 1
# 00:19:07 make[3]: *** [scripts/Makefile.build:540: drivers/gpu/drm/selftests] Error 2
# 00:30:18 drivers/firmware/tegra/bpmp-debugfs.c:357:16: error: stack frame size (1248) exceeds limit (1024) in function 'bpmp_debug_store' [-Werror,-Wframe-larger-than]
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_llvm:
-5
# build_abe qemu:
-2
# linux_n_obj:
21881
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_kernel/llvm-master-arm-mainline-allmodconfig
First_bad build: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-arm-mainline-…
Last_good build: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-arm-mainline-…
Baseline build: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-arm-mainline-…
Even more details: https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-arm-mainline-…
Reproduce builds:
<cut>
mkdir investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
cd investigate-llvm-08d7eec06e8cf5c15a96ce11f311f1480291a441
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-arm-mainline-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-arm-mainline-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-llvm-bisect-llvm-master-arm-mainline-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 08d7eec06e8cf5c15a96ce11f311f1480291a441
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 08d7eec06e8cf5c15a96ce11f311f1480291a441
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin(a)amd.com>
Date: Fri Sep 24 09:53:51 2021 -0700
Revert "Allow rematerialization of virtual reg uses"
Reverted due to two distcint performance regression reports.
This reverts commit 92c1fd19abb15bc68b1127a26137a69e033cdb39.
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 12 +-
llvm/lib/CodeGen/TargetInstrInfo.cpp | 9 +-
llvm/test/CodeGen/AMDGPU/remat-sop.mir | 60 -
llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll | 28 +-
llvm/test/CodeGen/ARM/funnel-shift-rot.ll | 32 +-
llvm/test/CodeGen/ARM/funnel-shift.ll | 30 +-
.../test/CodeGen/ARM/illegal-bitfield-loadstore.ll | 30 +-
llvm/test/CodeGen/ARM/neon-copy.ll | 10 +-
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 227 +-
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 206 +-
llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 95 +-
llvm/test/CodeGen/Mips/llvm-ir/sub.ll | 31 +-
llvm/test/CodeGen/Mips/tls.ll | 4 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 120 +-
llvm/test/CodeGen/RISCV/atomic-signext.ll | 24 +-
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 96 +-
llvm/test/CodeGen/RISCV/mul.ll | 72 +-
llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll | 12 +-
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll | 270 +-
llvm/test/CodeGen/RISCV/rv32zbb.ll | 94 +-
llvm/test/CodeGen/RISCV/rv32zbp.ll | 262 +-
llvm/test/CodeGen/RISCV/rv32zbt.ll | 206 +-
.../CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll | 150 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 146 +-
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 3584 ++++++++++----------
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 664 ++--
llvm/test/CodeGen/RISCV/shifts.ll | 308 +-
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 208 +-
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 190 +-
llvm/test/CodeGen/Thumb/dyn-stackalloc.ll | 7 +-
.../tail-pred-disabled-in-loloops.ll | 14 +-
.../LowOverheadLoops/varying-outer-2d-reduction.ll | 64 +-
.../CodeGen/Thumb2/LowOverheadLoops/while-loops.ll | 67 +-
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll | 30 +-
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll | 82 +-
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll | 98 +-
llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll | 529 +--
llvm/test/CodeGen/X86/addcarry.ll | 20 +-
llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll | 12 +-
llvm/test/CodeGen/X86/dag-update-nodetomatch.ll | 17 +-
.../X86/delete-dead-instrs-with-live-uses.mir | 4 +-
llvm/test/CodeGen/X86/inalloca-invoke.ll | 2 +-
llvm/test/CodeGen/X86/licm-regpressure.ll | 28 +-
llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 40 +-
llvm/test/CodeGen/X86/sdiv_fix.ll | 5 +-
45 files changed, 4093 insertions(+), 4106 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index a0c52e2f1a13..c394ac910be1 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -117,11 +117,10 @@ public:
const MachineFunction &MF) const;
/// Return true if the instruction is trivially rematerializable, meaning it
- /// has no side effects. Uses of constants and unallocatable physical
- /// registers are always trivial to rematerialize so that the instructions
- /// result is independent of the place in the function. Uses of virtual
- /// registers are allowed but it is caller's responsility to ensure these
- /// operands are valid at the point the instruction is beeing moved.
+ /// has no side effects and requires no operands that aren't always available.
+ /// This means the only allowed uses are constants and unallocatable physical
+ /// registers so that the instructions result is independent of the place
+ /// in the function.
bool isTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA = nullptr) const {
return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
@@ -141,7 +140,8 @@ protected:
/// set, this hook lets the target specify whether the instruction is actually
/// trivially rematerializable, taking into consideration its operands. This
/// predicate must return false if the instruction has any side effects other
- /// than producing a value.
+ /// than producing a value, or if it requres any address registers that are
+ /// not always available.
/// Requirements must be check as stated in isTriviallyReMaterializable() .
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
AAResults *AA) const {
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index fe7d60e0b7e2..1eab8e7443a7 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -921,8 +921,7 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
const MachineRegisterInfo &MRI = MF.getRegInfo();
// Remat clients assume operand 0 is the defined register.
- if (!MI.getNumOperands() || !MI.getOperand(0).isReg() ||
- MI.getOperand(0).isTied())
+ if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
return false;
Register DefReg = MI.getOperand(0).getReg();
@@ -984,6 +983,12 @@ bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
// same virtual register, though.
if (MO.isDef() && Reg != DefReg)
return false;
+
+ // Don't allow any virtual-register uses. Rematting an instruction with
+ // virtual register uses would length the live ranges of the uses, which
+ // is not necessarily a good idea, certainly not "trivial".
+ if (MO.isUse())
+ return false;
}
// Everything checked out.
diff --git a/llvm/test/CodeGen/AMDGPU/remat-sop.mir b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
index c9915aaabfde..ed799bfca028 100644
--- a/llvm/test/CodeGen/AMDGPU/remat-sop.mir
+++ b/llvm/test/CodeGen/AMDGPU/remat-sop.mir
@@ -51,66 +51,6 @@ body: |
S_NOP 0, implicit %2
S_ENDPGM 0
...
-# The liverange of %0 covers a point of rematerialization, source value is
-# availabe.
----
-name: test_remat_s_mov_b32_vreg_src_long_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_remat_s_mov_b32_vreg_src_long_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_NOP 0, implicit %0
- S_ENDPGM 0
-...
-# The liverange of %0 does not cover a point of rematerialization, source value is
-# unavailabe and we do not want to artificially extend the liverange.
----
-name: test_no_remat_s_mov_b32_vreg_src_short_lr
-tracksRegLiveness: true
-machineFunctionInfo:
- stackPtrOffsetReg: $sgpr32
-body: |
- bb.0:
- ; GCN-LABEL: name: test_no_remat_s_mov_b32_vreg_src_short_lr
- ; GCN: renamable $sgpr0 = IMPLICIT_DEF
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.1, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.1, addrspace 5)
- ; GCN: renamable $sgpr1 = S_MOV_B32 renamable $sgpr0
- ; GCN: SI_SPILL_S32_SAVE killed renamable $sgpr1, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.0, addrspace 5)
- ; GCN: renamable $sgpr0 = S_MOV_B32 killed renamable $sgpr0
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.1, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: renamable $sgpr1 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.0, addrspace 5)
- ; GCN: S_NOP 0, implicit killed renamable $sgpr1
- ; GCN: S_NOP 0, implicit killed renamable $sgpr0
- ; GCN: S_ENDPGM 0
- %0:sreg_32 = IMPLICIT_DEF
- %1:sreg_32 = S_MOV_B32 %0:sreg_32
- %2:sreg_32 = S_MOV_B32 %0:sreg_32
- %3:sreg_32 = S_MOV_B32 %0:sreg_32
- S_NOP 0, implicit %1
- S_NOP 0, implicit %2
- S_NOP 0, implicit %3
- S_ENDPGM 0
-...
---
name: test_remat_s_mov_b64
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
index 175a2069a441..a4243276c70a 100644
--- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
+++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
@@ -29,20 +29,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; ENABLE-NEXT: pophs {r11, pc}
; ENABLE-NEXT: .LBB0_3: @ %while.body.preheader
; ENABLE-NEXT: movw r12, :lower16:skip
-; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: sub r1, r1, #1
; ENABLE-NEXT: movt r12, :upper16:skip
; ENABLE-NEXT: .LBB0_4: @ %while.body
; ENABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; ENABLE-NEXT: ldrb r1, [r0]
-; ENABLE-NEXT: ldrb r1, [r12, r1]
-; ENABLE-NEXT: add r0, r0, r1
-; ENABLE-NEXT: sub r1, r3, #1
-; ENABLE-NEXT: cmp r1, r3
+; ENABLE-NEXT: ldrb r3, [r0]
+; ENABLE-NEXT: ldrb r3, [r12, r3]
+; ENABLE-NEXT: add r0, r0, r3
+; ENABLE-NEXT: sub r3, r1, #1
+; ENABLE-NEXT: cmp r3, r1
; ENABLE-NEXT: bhs .LBB0_6
; ENABLE-NEXT: @ %bb.5: @ %while.body
; ENABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; ENABLE-NEXT: cmp r0, r2
-; ENABLE-NEXT: mov r3, r1
+; ENABLE-NEXT: mov r1, r3
; ENABLE-NEXT: blo .LBB0_4
; ENABLE-NEXT: .LBB0_6: @ %if.end29
; ENABLE-NEXT: pop {r11, pc}
@@ -119,20 +119,20 @@ define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnon
; DISABLE-NEXT: pophs {r11, pc}
; DISABLE-NEXT: .LBB0_3: @ %while.body.preheader
; DISABLE-NEXT: movw r12, :lower16:skip
-; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: sub r1, r1, #1
; DISABLE-NEXT: movt r12, :upper16:skip
; DISABLE-NEXT: .LBB0_4: @ %while.body
; DISABLE-NEXT: @ =>This Inner Loop Header: Depth=1
-; DISABLE-NEXT: ldrb r1, [r0]
-; DISABLE-NEXT: ldrb r1, [r12, r1]
-; DISABLE-NEXT: add r0, r0, r1
-; DISABLE-NEXT: sub r1, r3, #1
-; DISABLE-NEXT: cmp r1, r3
+; DISABLE-NEXT: ldrb r3, [r0]
+; DISABLE-NEXT: ldrb r3, [r12, r3]
+; DISABLE-NEXT: add r0, r0, r3
+; DISABLE-NEXT: sub r3, r1, #1
+; DISABLE-NEXT: cmp r3, r1
; DISABLE-NEXT: bhs .LBB0_6
; DISABLE-NEXT: @ %bb.5: @ %while.body
; DISABLE-NEXT: @ in Loop: Header=BB0_4 Depth=1
; DISABLE-NEXT: cmp r0, r2
-; DISABLE-NEXT: mov r3, r1
+; DISABLE-NEXT: mov r1, r3
; DISABLE-NEXT: blo .LBB0_4
; DISABLE-NEXT: .LBB0_6: @ %if.end29
; DISABLE-NEXT: pop {r11, pc}
diff --git a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
index ea15fcc5c824..55157875d355 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift-rot.ll
@@ -73,13 +73,13 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: push {r4, r5, r11, lr}
; SCALAR-NEXT: rsb r3, r2, #0
; SCALAR-NEXT: and r4, r2, #63
-; SCALAR-NEXT: and r12, r3, #63
-; SCALAR-NEXT: rsb r3, r12, #32
+; SCALAR-NEXT: and lr, r3, #63
+; SCALAR-NEXT: rsb r3, lr, #32
; SCALAR-NEXT: lsl r2, r0, r4
-; SCALAR-NEXT: lsr lr, r0, r12
-; SCALAR-NEXT: orr r3, lr, r1, lsl r3
-; SCALAR-NEXT: subs lr, r12, #32
-; SCALAR-NEXT: lsrpl r3, r1, lr
+; SCALAR-NEXT: lsr r12, r0, lr
+; SCALAR-NEXT: orr r3, r12, r1, lsl r3
+; SCALAR-NEXT: subs r12, lr, #32
+; SCALAR-NEXT: lsrpl r3, r1, r12
; SCALAR-NEXT: subs r5, r4, #32
; SCALAR-NEXT: movwpl r2, #0
; SCALAR-NEXT: cmp r5, #0
@@ -88,8 +88,8 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
; SCALAR-NEXT: lsr r3, r0, r3
; SCALAR-NEXT: orr r3, r3, r1, lsl r4
; SCALAR-NEXT: lslpl r3, r0, r5
-; SCALAR-NEXT: lsr r0, r1, r12
-; SCALAR-NEXT: cmp lr, #0
+; SCALAR-NEXT: lsr r0, r1, lr
+; SCALAR-NEXT: cmp r12, #0
; SCALAR-NEXT: movwpl r0, #0
; SCALAR-NEXT: orr r1, r3, r0
; SCALAR-NEXT: mov r0, r2
@@ -245,15 +245,15 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r11, lr}
; CHECK-NEXT: push {r4, r5, r11, lr}
-; CHECK-NEXT: and r12, r2, #63
+; CHECK-NEXT: and lr, r2, #63
; CHECK-NEXT: rsb r2, r2, #0
-; CHECK-NEXT: rsb r3, r12, #32
+; CHECK-NEXT: rsb r3, lr, #32
; CHECK-NEXT: and r4, r2, #63
-; CHECK-NEXT: lsr lr, r0, r12
-; CHECK-NEXT: orr r3, lr, r1, lsl r3
-; CHECK-NEXT: subs lr, r12, #32
+; CHECK-NEXT: lsr r12, r0, lr
+; CHECK-NEXT: orr r3, r12, r1, lsl r3
+; CHECK-NEXT: subs r12, lr, #32
; CHECK-NEXT: lsl r2, r0, r4
-; CHECK-NEXT: lsrpl r3, r1, lr
+; CHECK-NEXT: lsrpl r3, r1, r12
; CHECK-NEXT: subs r5, r4, #32
; CHECK-NEXT: movwpl r2, #0
; CHECK-NEXT: cmp r5, #0
@@ -262,8 +262,8 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-NEXT: lsr r3, r0, r3
; CHECK-NEXT: orr r3, r3, r1, lsl r4
; CHECK-NEXT: lslpl r3, r0, r5
-; CHECK-NEXT: lsr r0, r1, r12
-; CHECK-NEXT: cmp lr, #0
+; CHECK-NEXT: lsr r0, r1, lr
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r0, #0
; CHECK-NEXT: orr r1, r0, r3
; CHECK-NEXT: mov r0, r2
diff --git a/llvm/test/CodeGen/ARM/funnel-shift.ll b/llvm/test/CodeGen/ARM/funnel-shift.ll
index 6372f9be2ca3..54c93b493c98 100644
--- a/llvm/test/CodeGen/ARM/funnel-shift.ll
+++ b/llvm/test/CodeGen/ARM/funnel-shift.ll
@@ -224,31 +224,31 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-NEXT: mov r3, #0
; CHECK-NEXT: bl __aeabi_uldivmod
; CHECK-NEXT: add r0, r2, #27
-; CHECK-NEXT: lsl r2, r7, #27
-; CHECK-NEXT: and r12, r0, #63
; CHECK-NEXT: lsl r6, r6, #27
+; CHECK-NEXT: and r1, r0, #63
+; CHECK-NEXT: lsl r2, r7, #27
; CHECK-NEXT: orr r7, r6, r7, lsr #5
-; CHECK-NEXT: rsb r3, r12, #32
-; CHECK-NEXT: lsr r2, r2, r12
; CHECK-NEXT: mov r6, #63
-; CHECK-NEXT: orr r2, r2, r7, lsl r3
-; CHECK-NEXT: subs r3, r12, #32
+; CHECK-NEXT: rsb r3, r1, #32
+; CHECK-NEXT: lsr r2, r2, r1
+; CHECK-NEXT: subs r12, r1, #32
; CHECK-NEXT: bic r6, r6, r0
+; CHECK-NEXT: orr r2, r2, r7, lsl r3
; CHECK-NEXT: lsl r5, r9, #1
-; CHECK-NEXT: lsrpl r2, r7, r3
-; CHECK-NEXT: subs r1, r6, #32
+; CHECK-NEXT: lsrpl r2, r7, r12
; CHECK-NEXT: lsl r0, r5, r6
-; CHECK-NEXT: lsl r4, r8, #1
+; CHECK-NEXT: subs r4, r6, #32
+; CHECK-NEXT: lsl r3, r8, #1
; CHECK-NEXT: movwpl r0, #0
-; CHECK-NEXT: orr r4, r4, r9, lsr #31
+; CHECK-NEXT: orr r3, r3, r9, lsr #31
; CHECK-NEXT: orr r0, r0, r2
; CHECK-NEXT: rsb r2, r6, #32
-; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: lsr r1, r7, r1
; CHECK-NEXT: lsr r2, r5, r2
-; CHECK-NEXT: orr r2, r2, r4, lsl r6
-; CHECK-NEXT: lslpl r2, r5, r1
-; CHECK-NEXT: lsr r1, r7, r12
-; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: orr r2, r2, r3, lsl r6
+; CHECK-NEXT: lslpl r2, r5, r4
+; CHECK-NEXT: cmp r12, #0
; CHECK-NEXT: movwpl r1, #0
; CHECK-NEXT: orr r1, r2, r1
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
diff --git a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
index 0a0bb62b0a09..2922e0ed5423 100644
--- a/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
+++ b/llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
@@ -91,17 +91,17 @@ define void @i56_or(i56* %a) {
; BE-LABEL: i56_or:
; BE: @ %bb.0:
; BE-NEXT: mov r1, r0
+; BE-NEXT: ldr r12, [r0]
; BE-NEXT: ldrh r2, [r1, #4]!
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: orr r2, r3, r2, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: strb r12, [r1, #2]
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: strb r2, [r1, #2]
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
%aa = load i56, i56* %a
@@ -127,13 +127,13 @@ define void @i56_and_or(i56* %a) {
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: strb r2, [r1, #2]
; BE-NEXT: orr r2, r3, r12, lsl #8
-; BE-NEXT: ldr r3, [r0]
-; BE-NEXT: orr r2, r2, r3, lsl #24
-; BE-NEXT: orr r12, r2, #384
-; BE-NEXT: lsr r2, r12, #8
-; BE-NEXT: strh r2, [r1]
-; BE-NEXT: bic r1, r3, #255
-; BE-NEXT: orr r1, r1, r12, lsr #24
+; BE-NEXT: ldr r12, [r0]
+; BE-NEXT: orr r2, r2, r12, lsl #24
+; BE-NEXT: orr r2, r2, #384
+; BE-NEXT: lsr r3, r2, #8
+; BE-NEXT: strh r3, [r1]
+; BE-NEXT: bic r1, r12, #255
+; BE-NEXT: orr r1, r1, r2, lsr #24
; BE-NEXT: str r1, [r0]
; BE-NEXT: mov pc, lr
diff --git a/llvm/test/CodeGen/ARM/neon-copy.ll b/llvm/test/CodeGen/ARM/neon-copy.ll
index 46490efb6631..09a991da2e59 100644
--- a/llvm/test/CodeGen/ARM/neon-copy.ll
+++ b/llvm/test/CodeGen/ARM/neon-copy.ll
@@ -1340,16 +1340,16 @@ define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, sp, #8
; CHECK-NEXT: vmov.u16 r1, d0[1]
-; CHECK-NEXT: and r12, r0, #3
+; CHECK-NEXT: and r0, r0, #3
; CHECK-NEXT: vmov.u16 r2, d0[2]
-; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vmov.u16 r3, d0[3]
-; CHECK-NEXT: orr r0, r0, r12, lsl #1
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vmov.u16 r12, d0[3]
+; CHECK-NEXT: orr r0, r3, r0, lsl #1
; CHECK-NEXT: vst1.16 {d0[0]}, [r0:16]
; CHECK-NEXT: vldr d0, [sp]
; CHECK-NEXT: vmov.16 d0[1], r1
; CHECK-NEXT: vmov.16 d0[2], r2
-; CHECK-NEXT: vmov.16 d0[3], r3
+; CHECK-NEXT: vmov.16 d0[3], r12
; CHECK-NEXT: add sp, sp, #8
; CHECK-NEXT: bx lr
%tmp = extractelement <8 x i16> %x, i32 0
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index a125446b27c3..8be7100d368b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -766,85 +766,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: move $2, $6
-; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
-; MMR3-NEXT: srlv $3, $7, $16
-; MMR3-NEXT: not16 $6, $16
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
-; MMR3-NEXT: sll16 $2, $2, 1
-; MMR3-NEXT: sllv $2, $2, $6
-; MMR3-NEXT: li16 $6, 64
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: srlv $4, $4, $16
-; MMR3-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
-; MMR3-NEXT: subu16 $7, $6, $16
+; MMR3-NEXT: srlv $4, $7, $16
+; MMR3-NEXT: not16 $3, $16
+; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sll16 $2, $6, 1
+; MMR3-NEXT: sllv $3, $2, $3
+; MMR3-NEXT: li16 $2, 64
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: srlv $6, $6, $16
+; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR3-NEXT: subu16 $7, $2, $16
; MMR3-NEXT: sllv $9, $5, $7
-; MMR3-NEXT: andi16 $5, $7, 32
-; MMR3-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
-; MMR3-NEXT: andi16 $6, $16, 32
-; MMR3-NEXT: sw $6, 36($sp) # 4-byte Folded Spill
-; MMR3-NEXT: move $3, $9
+; MMR3-NEXT: andi16 $2, $7, 32
+; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $5, $16, 32
+; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
+; MMR3-NEXT: move $4, $9
; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $3, $17, $5
-; MMR3-NEXT: movn $2, $4, $6
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: lw $17, 0($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $4, $17, $4
-; MMR3-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $6, 1
-; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: or16 $2, $3
-; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $3
-; MMR3-NEXT: addiu $3, $16, -64
-; MMR3-NEXT: srav $1, $6, $3
-; MMR3-NEXT: andi16 $3, $3, 32
-; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $3
-; MMR3-NEXT: sllv $3, $6, $7
-; MMR3-NEXT: sw $3, 4($sp) # 4-byte Folded Spill
-; MMR3-NEXT: not16 $3, $7
-; MMR3-NEXT: srl16 $4, $17, 1
-; MMR3-NEXT: srlv $3, $4, $3
+; MMR3-NEXT: movn $4, $17, $2
+; MMR3-NEXT: movn $3, $6, $5
+; MMR3-NEXT: addiu $2, $16, -64
+; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srlv $5, $5, $2
+; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $17, 1
+; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: not16 $5, $2
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: or16 $3, $4
+; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $4
+; MMR3-NEXT: srav $1, $17, $2
+; MMR3-NEXT: andi16 $2, $2, 32
+; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $2
+; MMR3-NEXT: sllv $2, $17, $7
+; MMR3-NEXT: not16 $4, $7
+; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $6, $7, 1
+; MMR3-NEXT: srlv $6, $6, $4
; MMR3-NEXT: sltiu $10, $16, 64
-; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $5, $3, $10
+; MMR3-NEXT: or16 $6, $2
+; MMR3-NEXT: srlv $2, $7, $16
+; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
+; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sllv $3, $4, $3
; MMR3-NEXT: or16 $3, $2
-; MMR3-NEXT: srlv $2, $17, $16
-; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $7, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sllv $17, $7, $4
-; MMR3-NEXT: or16 $17, $2
-; MMR3-NEXT: srav $11, $6, $16
-; MMR3-NEXT: lw $2, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $17, $11, $2
-; MMR3-NEXT: sra $2, $6, 31
+; MMR3-NEXT: srav $11, $17, $16
+; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $11, $4
+; MMR3-NEXT: sra $2, $17, 31
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: move $4, $2
-; MMR3-NEXT: movn $4, $17, $10
-; MMR3-NEXT: lw $6, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $9, $6
-; MMR3-NEXT: lw $6, 36($sp) # 4-byte Folded Reload
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: lw $7, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $3
+; MMR3-NEXT: move $8, $2
+; MMR3-NEXT: movn $8, $3, $10
+; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $6, $9, $3
+; MMR3-NEXT: li16 $3, 0
+; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $7, $3, $4
+; MMR3-NEXT: or16 $7, $6
; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
; MMR3-NEXT: movn $1, $2, $3
; MMR3-NEXT: movn $1, $7, $10
; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $3, $16
-; MMR3-NEXT: movn $11, $2, $6
+; MMR3-NEXT: movn $11, $2, $4
; MMR3-NEXT: movn $2, $11, $10
-; MMR3-NEXT: move $3, $4
+; MMR3-NEXT: move $3, $8
; MMR3-NEXT: move $4, $1
; MMR3-NEXT: lwp $16, 40($sp)
; MMR3-NEXT: addiusp 48
@@ -858,80 +852,79 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
-; MMR6-NEXT: move $12, $7
+; MMR6-NEXT: move $1, $7
; MMR6-NEXT: lw $3, 44($sp)
; MMR6-NEXT: li16 $2, 64
-; MMR6-NEXT: subu16 $16, $2, $3
-; MMR6-NEXT: sllv $1, $5, $16
-; MMR6-NEXT: andi16 $2, $16, 32
-; MMR6-NEXT: selnez $8, $1, $2
-; MMR6-NEXT: sllv $9, $4, $16
-; MMR6-NEXT: not16 $16, $16
-; MMR6-NEXT: srl16 $17, $5, 1
-; MMR6-NEXT: srlv $10, $17, $16
-; MMR6-NEXT: or $9, $9, $10
-; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $8, $8, $9
-; MMR6-NEXT: srlv $9, $7, $3
-; MMR6-NEXT: not16 $7, $3
-; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill
+; MMR6-NEXT: subu16 $7, $2, $3
+; MMR6-NEXT: sllv $8, $5, $7
+; MMR6-NEXT: andi16 $2, $7, 32
+; MMR6-NEXT: selnez $9, $8, $2
+; MMR6-NEXT: sllv $10, $4, $7
+; MMR6-NEXT: not16 $7, $7
+; MMR6-NEXT: srl16 $16, $5, 1
+; MMR6-NEXT: srlv $7, $16, $7
+; MMR6-NEXT: or $7, $10, $7
+; MMR6-NEXT: seleqz $7, $7, $2
+; MMR6-NEXT: or $7, $9, $7
+; MMR6-NEXT: srlv $9, $1, $3
+; MMR6-NEXT: not16 $16, $3
+; MMR6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $17, $6, 1
-; MMR6-NEXT: sllv $10, $17, $7
+; MMR6-NEXT: sllv $10, $17, $16
; MMR6-NEXT: or $9, $10, $9
; MMR6-NEXT: andi16 $17, $3, 32
; MMR6-NEXT: seleqz $9, $9, $17
; MMR6-NEXT: srlv $10, $6, $3
; MMR6-NEXT: selnez $11, $10, $17
; MMR6-NEXT: seleqz $10, $10, $17
-; MMR6-NEXT: or $8, $10, $8
-; MMR6-NEXT: seleqz $1, $1, $2
-; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: or $10, $10, $7
+; MMR6-NEXT: seleqz $12, $8, $2
+; MMR6-NEXT: or $8, $11, $9
; MMR6-NEXT: addiu $2, $3, -64
-; MMR6-NEXT: srlv $10, $5, $2
+; MMR6-NEXT: srlv $9, $5, $2
; MMR6-NEXT: sll16 $7, $4, 1
; MMR6-NEXT: not16 $16, $2
; MMR6-NEXT: sllv $11, $7, $16
; MMR6-NEXT: sltiu $13, $3, 64
-; MMR6-NEXT: or $1, $9, $1
-; MMR6-NEXT: selnez $8, $8, $13
-; MMR6-NEXT: or $9, $11, $10
-; MMR6-NEXT: srav $10, $4, $2
+; MMR6-NEXT: or $8, $8, $12
+; MMR6-NEXT: selnez $10, $10, $13
+; MMR6-NEXT: or $9, $11, $9
+; MMR6-NEXT: srav $11, $4, $2
; MMR6-NEXT: andi16 $2, $2, 32
-; MMR6-NEXT: seleqz $11, $10, $2
+; MMR6-NEXT: seleqz $12, $11, $2
; MMR6-NEXT: sra $14, $4, 31
; MMR6-NEXT: selnez $15, $14, $2
; MMR6-NEXT: seleqz $9, $9, $2
-; MMR6-NEXT: or $11, $15, $11
-; MMR6-NEXT: seleqz $11, $11, $13
-; MMR6-NEXT: selnez $2, $10, $2
-; MMR6-NEXT: seleqz $10, $14, $13
-; MMR6-NEXT: or $8, $8, $11
-; MMR6-NEXT: selnez $8, $8, $3
-; MMR6-NEXT: selnez $1, $1, $13
+; MMR6-NEXT: or $12, $15, $12
+; MMR6-NEXT: seleqz $12, $12, $13
+; MMR6-NEXT: selnez $2, $11, $2
+; MMR6-NEXT: seleqz $11, $14, $13
+; MMR6-NEXT: or $10, $10, $12
+; MMR6-NEXT: selnez $10, $10, $3
+; MMR6-NEXT: selnez $8, $8, $13
; MMR6-NEXT: or $2, $2, $9
; MMR6-NEXT: srav $9, $4, $3
; MMR6-NEXT: seleqz $4, $9, $17
-; MMR6-NEXT: selnez $11, $14, $17
-; MMR6-NEXT: or $4, $11, $4
-; MMR6-NEXT: selnez $11, $4, $13
+; MMR6-NEXT: selnez $12, $14, $17
+; MMR6-NEXT: or $4, $12, $4
+; MMR6-NEXT: selnez $12, $4, $13
; MMR6-NEXT: seleqz $2, $2, $13
; MMR6-NEXT: seleqz $4, $6, $3
-; MMR6-NEXT: seleqz $6, $12, $3
+; MMR6-NEXT: seleqz $1, $1, $3
+; MMR6-NEXT: or $2, $8, $2
+; MMR6-NEXT: selnez $2, $2, $3
; MMR6-NEXT: or $1, $1, $2
-; MMR6-NEXT: selnez $1, $1, $3
-; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: or $4, $4, $8
-; MMR6-NEXT: or $6, $11, $10
-; MMR6-NEXT: srlv $2, $5, $3
-; MMR6-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $3, $7, $3
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: seleqz $2, $2, $17
-; MMR6-NEXT: selnez $3, $9, $17
-; MMR6-NEXT: or $2, $3, $2
-; MMR6-NEXT: selnez $2, $2, $13
-; MMR6-NEXT: or $3, $2, $10
-; MMR6-NEXT: move $2, $6
+; MMR6-NEXT: or $4, $4, $10
+; MMR6-NEXT: or $2, $12, $11
+; MMR6-NEXT: srlv $3, $5, $3
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: sllv $5, $7, $5
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: seleqz $3, $3, $17
+; MMR6-NEXT: selnez $5, $9, $17
+; MMR6-NEXT: or $3, $5, $3
+; MMR6-NEXT: selnez $3, $3, $13
+; MMR6-NEXT: or $3, $3, $11
; MMR6-NEXT: move $5, $1
; MMR6-NEXT: lw $16, 8($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index e4b4b3ae1d0f..ed2bfc9fcf60 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -776,77 +776,76 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: .cfi_offset 17, -4
; MMR3-NEXT: .cfi_offset 16, -8
; MMR3-NEXT: move $8, $7
-; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
+; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 68($sp)
; MMR3-NEXT: li16 $2, 64
-; MMR3-NEXT: subu16 $17, $2, $16
-; MMR3-NEXT: sllv $9, $5, $17
-; MMR3-NEXT: andi16 $3, $17, 32
+; MMR3-NEXT: subu16 $7, $2, $16
+; MMR3-NEXT: sllv $9, $5, $7
+; MMR3-NEXT: move $17, $5
+; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
+; MMR3-NEXT: andi16 $3, $7, 32
; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MMR3-NEXT: li16 $2, 0
; MMR3-NEXT: move $4, $9
; MMR3-NEXT: movn $4, $2, $3
-; MMR3-NEXT: srlv $5, $7, $16
+; MMR3-NEXT: srlv $5, $8, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 16($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
-; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sllv $2, $2, $3
; MMR3-NEXT: or16 $2, $5
-; MMR3-NEXT: srlv $7, $6, $16
+; MMR3-NEXT: srlv $5, $6, $16
+; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MMR3-NEXT: andi16 $3, $16, 32
; MMR3-NEXT: sw $3, 12($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $2, $7, $3
+; MMR3-NEXT: movn $2, $5, $3
; MMR3-NEXT: addiu $3, $16, -64
; MMR3-NEXT: or16 $2, $4
-; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR3-NEXT: srlv $3, $6, $3
-; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
-; MMR3-NEXT: sll16 $4, $3, 1
-; MMR3-NEXT: sw $4, 0($sp) # 4-byte Folded Spill
-; MMR3-NEXT: addiu $5, $16, -64
-; MMR3-NEXT: not16 $5, $5
-; MMR3-NEXT: sllv $5, $4, $5
-; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: or16 $5, $4
-; MMR3-NEXT: addiu $4, $16, -64
-; MMR3-NEXT: srlv $1, $3, $4
-; MMR3-NEXT: andi16 $4, $4, 32
+; MMR3-NEXT: srlv $4, $17, $3
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
-; MMR3-NEXT: movn $5, $1, $4
+; MMR3-NEXT: lw $4, 28($sp) # 4-byte Folded Reload
+; MMR3-NEXT: sll16 $6, $4, 1
+; MMR3-NEXT: not16 $5, $3
+; MMR3-NEXT: sllv $5, $6, $5
+; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload
+; MMR3-NEXT: or16 $5, $17
+; MMR3-NEXT: srlv $1, $4, $3
+; MMR3-NEXT: andi16 $3, $3, 32
+; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
+; MMR3-NEXT: movn $5, $1, $3
; MMR3-NEXT: sltiu $10, $16, 64
; MMR3-NEXT: movn $5, $2, $10
-; MMR3-NEXT: sllv $2, $3, $17
-; MMR3-NEXT: not16 $3, $17
-; MMR3-NEXT: srl16 $4, $6, 1
+; MMR3-NEXT: sllv $2, $4, $7
+; MMR3-NEXT: not16 $3, $7
+; MMR3-NEXT: lw $7, 0($sp) # 4-byte Folded Reload
+; MMR3-NEXT: srl16 $4, $7, 1
; MMR3-NEXT: srlv $4, $4, $3
; MMR3-NEXT: or16 $4, $2
-; MMR3-NEXT: srlv $2, $6, $16
+; MMR3-NEXT: srlv $2, $7, $16
; MMR3-NEXT: lw $3, 16($sp) # 4-byte Folded Reload
-; MMR3-NEXT: lw $6, 0($sp) # 4-byte Folded Reload
; MMR3-NEXT: sllv $3, $6, $3
; MMR3-NEXT: or16 $3, $2
; MMR3-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MMR3-NEXT: srlv $2, $2, $16
-; MMR3-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $3, $2, $6
+; MMR3-NEXT: lw $17, 12($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $3, $2, $17
; MMR3-NEXT: movz $5, $8, $16
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movz $3, $17, $10
-; MMR3-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $4, $9, $17
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $7, $17, $6
-; MMR3-NEXT: or16 $7, $4
+; MMR3-NEXT: li16 $6, 0
+; MMR3-NEXT: movz $3, $6, $10
+; MMR3-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
+; MMR3-NEXT: movn $4, $9, $7
+; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $6, $7, $17
+; MMR3-NEXT: or16 $6, $4
; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload
-; MMR3-NEXT: movn $1, $17, $4
-; MMR3-NEXT: li16 $17, 0
-; MMR3-NEXT: movn $1, $7, $10
+; MMR3-NEXT: movn $1, $7, $4
+; MMR3-NEXT: li16 $7, 0
+; MMR3-NEXT: movn $1, $6, $10
; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload
; MMR3-NEXT: movz $1, $4, $16
-; MMR3-NEXT: movn $2, $17, $6
+; MMR3-NEXT: movn $2, $7, $17
; MMR3-NEXT: li16 $4, 0
; MMR3-NEXT: movz $2, $4, $10
; MMR3-NEXT: move $4, $1
@@ -856,91 +855,98 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
;
; MMR6-LABEL: lshr_i128:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: addiu $sp, $sp, -24
-; MMR6-NEXT: .cfi_def_cfa_offset 24
-; MMR6-NEXT: sw $17, 20($sp) # 4-byte Folded Spill
-; MMR6-NEXT: sw $16, 16($sp) # 4-byte Folded Spill
+; MMR6-NEXT: addiu $sp, $sp, -32
+; MMR6-NEXT: .cfi_def_cfa_offset 32
+; MMR6-NEXT: sw $17, 28($sp) # 4-byte Folded Spill
+; MMR6-NEXT: sw $16, 24($sp) # 4-byte Folded Spill
; MMR6-NEXT: .cfi_offset 17, -4
; MMR6-NEXT: .cfi_offset 16, -8
; MMR6-NEXT: move $1, $7
-; MMR6-NEXT: move $7, $4
-; MMR6-NEXT: lw $3, 52($sp)
+; MMR6-NEXT: move $7, $5
+; MMR6-NEXT: lw $3, 60($sp)
; MMR6-NEXT: srlv $2, $1, $3
-; MMR6-NEXT: not16 $16, $3
-; MMR6-NEXT: sw $16, 8($sp) # 4-byte Folded Spill
-; MMR6-NEXT: move $4, $6
-; MMR6-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $5, $3
+; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT: move $17, $6
+; MMR6-NEXT: sw $6, 16($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $6, $6, 1
-; MMR6-NEXT: sllv $6, $6, $16
+; MMR6-NEXT: sllv $6, $6, $5
; MMR6-NEXT: or $8, $6, $2
-; MMR6-NEXT: addiu $6, $3, -64
-; MMR6-NEXT: srlv $9, $5, $6
-; MMR6-NEXT: sll16 $2, $7, 1
-; MMR6-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
-; MMR6-NEXT: not16 $16, $6
+; MMR6-NEXT: addiu $5, $3, -64
+; MMR6-NEXT: srlv $9, $7, $5
+; MMR6-NEXT: move $6, $4
+; MMR6-NEXT: sll16 $2, $4, 1
+; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
+; MMR6-NEXT: not16 $16, $5
; MMR6-NEXT: sllv $10, $2, $16
; MMR6-NEXT: andi16 $16, $3, 32
; MMR6-NEXT: seleqz $8, $8, $16
; MMR6-NEXT: or $9, $10, $9
-; MMR6-NEXT: srlv $10, $4, $3
+; MMR6-NEXT: srlv $10, $17, $3
; MMR6-NEXT: selnez $11, $10, $16
; MMR6-NEXT: li16 $17, 64
; MMR6-NEXT: subu16 $2, $17, $3
-; MMR6-NEXT: sllv $12, $5, $2
+; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: move $17, $7
; MMR6-NEXT: andi16 $4, $2, 32
-; MMR6-NEXT: andi16 $17, $6, 32
-; MMR6-NEXT: seleqz $9, $9, $17
+; MMR6-NEXT: andi16 $7, $5, 32
+; MMR6-NEXT: sw $7, 20($sp) # 4-byte Folded Spill
+; MMR6-NEXT: seleqz $9, $9, $7
; MMR6-NEXT: seleqz $13, $12, $4
; MMR6-NEXT: or $8, $11, $8
; MMR6-NEXT: selnez $11, $12, $4
-; MMR6-NEXT: sllv $12, $7, $2
+; MMR6-NEXT: sllv $12, $6, $2
+; MMR6-NEXT: move $7, $6
+; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: not16 $2, $2
-; MMR6-NEXT: srl16 $6, $5, 1
+; MMR6-NEXT: srl16 $6, $17, 1
; MMR6-NEXT: srlv $2, $6, $2
; MMR6-NEXT: or $2, $12, $2
; MMR6-NEXT: seleqz $2, $2, $4
-; MMR6-NEXT: addiu $4, $3, -64
-; MMR6-NEXT: srlv $4, $7, $4
-; MMR6-NEXT: or $12, $11, $2
-; MMR6-NEXT: or $6, $8, $13
-; MMR6-NEXT: srlv $5, $5, $3
-; MMR6-NEXT: selnez $8, $4, $17
-; MMR6-NEXT: sltiu $11, $3, 64
-; MMR6-NEXT: selnez $13, $6, $11
-; MMR6-NEXT: or $8, $8, $9
+; MMR6-NEXT: srlv $4, $7, $5
+; MMR6-NEXT: or $11, $11, $2
+; MMR6-NEXT: or $5, $8, $13
+; MMR6-NEXT: srlv $6, $17, $3
+; MMR6-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: selnez $7, $4, $2
+; MMR6-NEXT: sltiu $8, $3, 64
+; MMR6-NEXT: selnez $12, $5, $8
+; MMR6-NEXT: or $7, $7, $9
+; MMR6-NEXT: lw $5, 12($sp) # 4-byte Folded Reload
; MMR6-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $6, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT: sllv $9, $6, $2
+; MMR6-NEXT: sllv $9, $2, $5
; MMR6-NEXT: seleqz $10, $10, $16
-; MMR6-NEXT: li16 $2, 0
-; MMR6-NEXT: or $10, $10, $12
-; MMR6-NEXT: or $9, $9, $5
-; MMR6-NEXT: seleqz $5, $8, $11
-; MMR6-NEXT: seleqz $8, $2, $11
-; MMR6-NEXT: srlv $7, $7, $3
-; MMR6-NEXT: seleqz $2, $7, $16
-; MMR6-NEXT: selnez $2, $2, $11
+; MMR6-NEXT: li16 $5, 0
+; MMR6-NEXT: or $10, $10, $11
+; MMR6-NEXT: or $6, $9, $6
+; MMR6-NEXT: seleqz $2, $7, $8
+; MMR6-NEXT: seleqz $7, $5, $8
+; MMR6-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT: srlv $9, $5, $3
+; MMR6-NEXT: seleqz $11, $9, $16
+; MMR6-NEXT: selnez $11, $11, $8
; MMR6-NEXT: seleqz $1, $1, $3
-; MMR6-NEXT: or $5, $13, $5
-; MMR6-NEXT: selnez $5, $5, $3
-; MMR6-NEXT: or $5, $1, $5
-; MMR6-NEXT: or $2, $8, $2
-; MMR6-NEXT: seleqz $1, $9, $16
-; MMR6-NEXT: selnez $6, $7, $16
-; MMR6-NEXT: lw $7, 12($sp) # 4-byte Folded Reload
-; MMR6-NEXT: seleqz $7, $7, $3
-; MMR6-NEXT: selnez $9, $10, $11
-; MMR6-NEXT: seleqz $4, $4, $17
-; MMR6-NEXT: seleqz $4, $4, $11
-; MMR6-NEXT: or $4, $9, $4
+; MMR6-NEXT: or $2, $12, $2
+; MMR6-NEXT: selnez $2, $2, $3
+; MMR6-NEXT: or $5, $1, $2
+; MMR6-NEXT: or $2, $7, $11
+; MMR6-NEXT: seleqz $1, $6, $16
+; MMR6-NEXT: selnez $6, $9, $16
+; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $9, $16, $3
+; MMR6-NEXT: selnez $10, $10, $8
+; MMR6-NEXT: lw $16, 20($sp) # 4-byte Folded Reload
+; MMR6-NEXT: seleqz $4, $4, $16
+; MMR6-NEXT: seleqz $4, $4, $8
+; MMR6-NEXT: or $4, $10, $4
; MMR6-NEXT: selnez $3, $4, $3
-; MMR6-NEXT: or $4, $7, $3
+; MMR6-NEXT: or $4, $9, $3
; MMR6-NEXT: or $1, $6, $1
-; MMR6-NEXT: selnez $1, $1, $11
-; MMR6-NEXT: or $3, $8, $1
-; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload
-; MMR6-NEXT: lw $17, 20($sp) # 4-byte Folded Reload
-; MMR6-NEXT: addiu $sp, $sp, 24
+; MMR6-NEXT: selnez $1, $1, $8
+; MMR6-NEXT: or $3, $7, $1
+; MMR6-NEXT: lw $16, 24($sp) # 4-byte Folded Reload
+; MMR6-NEXT: lw $17, 28($sp) # 4-byte Folded Reload
+; MMR6-NEXT: addiu $sp, $sp, 32
; MMR6-NEXT: jrc $ra
</cut>
4 years
- 2
- 1
[TCWG CI] Regression caused by binutils: [gdb/testsuite] Add gdb.testsuite/dump-system-info.exp
by ci_notify＠linaro.org
[TCWG CI] Regression caused by binutils: [gdb/testsuite] Add gdb.testsuite/dump-system-info.exp:
commit b4e4386a2e58ba6ce8d02b952f1bc6ceb8fc95d1
Author: Tom de Vries <tdevries(a)suse.de>
[gdb/testsuite] Add gdb.testsuite/dump-system-info.exp
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-8
# build_abe newlib:
-6
# build_abe stage2 -- --patch linaro-local/vect-metric-branch --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-5
# true:
0
# benchmark -- -O3_VECT_mthumb artifacts/build-b4e4386a2e58ba6ce8d02b952f1bc6ceb8fc95d1/results_id:
1
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-8
# build_abe newlib:
-6
# build_abe stage2 -- --patch linaro-local/vect-metric-branch --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-5
# true:
0
# benchmark -- -O3_VECT_mthumb artifacts/build-baseline/results_id:
1
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_gnu_eabi_stm32/gnu_eabi-master-arm_eabi-coremark-O3_VECT
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Reproduce builds:
<cut>
mkdir investigate-binutils-b4e4386a2e58ba6ce8d02b952f1bc6ceb8fc95d1
cd investigate-binutils-b4e4386a2e58ba6ce8d02b952f1bc6ceb8fc95d1
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /binutils/ ./ ./bisect/baseline/
cd binutils
# Reproduce first_bad build
git checkout --detach b4e4386a2e58ba6ce8d02b952f1bc6ceb8fc95d1
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 3814a9e1fe77c01c7e872c25afa198537d4ac780
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit b4e4386a2e58ba6ce8d02b952f1bc6ceb8fc95d1
Author: Tom de Vries <tdevries(a)suse.de>
Date: Fri Sep 24 12:39:14 2021 +0200
[gdb/testsuite] Add gdb.testsuite/dump-system-info.exp
When interpreting the testsuite results, it's often relevant what kind of
machine the testsuite ran on. On a local machine one can just do
/proc/cpuinfo, but in case of running tests using a remote system
that distributes test runs to other remote systems that are not directly
accessible, that's not possible.
Fix this by dumping /proc/cpuinfo into the gdb.log, as well as lsb_release -a
and uname -a.
We could do this at the start of each test run, by putting it into unix.exp
or some such. However, this might be too verbose, so we choose to put it into
its own test-case, such that it get triggered in a full testrun, but not when
running one or a subset of tests.
We put the test-case into the gdb.testsuite directory, which is currently the
only place in the testsuite where we do not test gdb. [ Though perhaps this
could be put into a new gdb.info directory, since the test-case doesn't
actually test the testsuite. ]
Tested on x86_64-linux.
---
gdb/testsuite/gdb.testsuite/dump-system-info.exp | 48 ++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/gdb/testsuite/gdb.testsuite/dump-system-info.exp b/gdb/testsuite/gdb.testsuite/dump-system-info.exp
new file mode 100644
index 00000000000..bf181469bd5
--- /dev/null
+++ b/gdb/testsuite/gdb.testsuite/dump-system-info.exp
@@ -0,0 +1,48 @@
+# Copyright 2021 Free Software Foundation, Inc.
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# The purpose of this test-case is to dump /proc/cpuinfo and similar system
+# info into gdb.log.
+
+# Check if /proc/cpuinfo is available.
+set res [remote_exec target "test -r /proc/cpuinfo"]
+set status [lindex $res 0]
+set output [lindex $res 1]
+
+if { $status == 0 && $output == "" } {
+ verbose -log "Cpuinfo available, dumping:"
+ remote_exec target "cat /proc/cpuinfo"
+} else {
+ verbose -log "Cpuinfo not available"
+}
+
+set res [remote_exec target "lsb_release -a"]
+set status [lindex $res 0]
+set output [lindex $res 1]
+
+if { $status == 0 } {
+ verbose -log "lsb_release -a availabe, dumping:\n$output"
+} else {
+ verbose -log "lsb_release -a not available"
+}
+
+set res [remote_exec target "uname -a"]
+set status [lindex $res 0]
+set output [lindex $res 1]
+
+if { $status == 0 } {
+ verbose -log "uname -a availabe, dumping:\n$output"
+} else {
+ verbose -log "uname -a not available"
+}
</cut>
4 years
- 2
- 1
[TCWG CI] 464.h264ref slowed down by 3% after llvm: Fix test from 8dd42f, capitalization in test
by ci_notify＠linaro.org
After llvm commit e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
Author: Erich Keane <erich.keane(a)intel.com>
Fix test from 8dd42f, capitalization in test
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 3% from 10973 to 11249 perf samples
- 464.h264ref:[.] FastFullPelBlockMotionSearch slowed down by 12% from 1446 to 1619 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
cd investigate-llvm-e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 77d200a546136c2855063613ff4bca1f682fb23a
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit e8e2edd8ca88f8b0a7dba141349b2aa83284f3af
Author: Erich Keane <erich.keane(a)intel.com>
Date: Fri Sep 24 10:24:17 2021 -0700
Fix test from 8dd42f, capitalization in test
---
clang/test/CXX/drs/dr17xx.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CXX/drs/dr17xx.cpp b/clang/test/CXX/drs/dr17xx.cpp
index 42303c83ae3c..c8648908ebda 100644
--- a/clang/test/CXX/drs/dr17xx.cpp
+++ b/clang/test/CXX/drs/dr17xx.cpp
@@ -129,7 +129,7 @@ namespace dr1778 { // dr1778: 9
namespace dr1762 { // dr1762: 14
#if __cplusplus >= 201103L
float operator ""_E(const char *);
- // expected-error@+2 {{invalid suffix on literal; c++11 requires a space between literal and identifier}}
+ // expected-error@+2 {{invalid suffix on literal; C++11 requires a space between literal and identifier}}
// expected-warning@+1 {{user-defined literal suffixes not starting with '_' are reserved; no literal will invoke this operator}}
float operator ""E(const char *);
#endif
</cut>
4 years
- 2
- 1
Re: [TCWG CI] 456.hmmer slowed down by 6% after llvm: Allow rematerialization of virtual reg uses
by Maxim Kuvyrkov
Thanks, Stanislav,
FWIW, it will be, probably, easier for you to just rebuild the compiler, it is an x86_64-linux-gnu -> arm-linux-gnueabihf cross. This link has the build log [1].
cmake -G Ninja ../llvm/llvm '-DLLVM_ENABLE_PROJECTS=clang;lld' -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_ASSERTIONS=True -DCMAKE_INSTALL_PREFIX=../llvm-install -DLLVM_TARGETS_TO_BUILD=ARM
Then compile the pre-processed source with plain -O2 or -O3 optimisation settings.
[1] https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Regards,
--
Maxim Kuvyrkov
https://www.linaro.org
> On 24 Sep 2021, at 20:30, Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com> wrote:
>
> [AMD Official Use Only]
>
> I have reverted the whole change. There was yet another perf regression report.
>
> Stas
>
> From: Mekhanoshin, Stanislav
> Sent: Thursday, September 23, 2021 11:48
> To: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org>
> Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org>
> Subject: RE: [TCWG CI] 456.hmmer slowed down by 6% after llvm: Allow rematerialization of virtual reg uses
>
> Thanks. I see the reload. There shall not be extra pressure since that is the whole idea, make pressure less. However, I see more spills in that specific file, fast_algorithms.s if I get it right.
> Can I get the IR for it? Something to feed llc.
>
> Stas
>
> From: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org>
> Sent: Thursday, September 23, 2021 2:31
> To: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com>
> Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org>
> Subject: Re: [TCWG CI] 456.hmmer slowed down by 6% after llvm: Allow rematerialization of virtual reg uses
>
> [CAUTION: External Email]
>
> Thanks, Stanislav.
>
> I’ve looked into profile dumps, and 456.hmmer’s hot loop get several additional reloads. E.g., "ldr r1, [sp, #84]” generates 203 additional samples, which translates into 20 seconds of time just for that one instruction.
>
> See the attached profile dumps and the the screenshot with the hot loop highlighted.
>
> Maybe your patch increases register pressure too much?
>
> Regards,
>
> --
> Maxim Kuvyrkov
> https://www.linaro.org
>
> > On 22 Sep 2021, at 22:35, Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com> wrote:
> >
> > [AMD Official Use Only]
> >
> > There are actually couple things worth to try if that is easy:
> >
> > https://reviews.llvm.org/D109077
> > https://reviews.llvm.org/differential/diff/374324/
> >
> > Both may slightly change spill weights and then spilling pattern.
> >
> > Stas
> >
> > -----Original Message-----
> > From: Mekhanoshin, Stanislav
> > Sent: Wednesday, September 22, 2021 12:09
> > To: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org>
> > Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org>
> > Subject: RE: [TCWG CI] 456.hmmer slowed down by 6% after llvm: Allow rematerialization of virtual reg uses
> >
> > I assume some of the newly rematerialized instructions caused perf drops. Probably some very specific ones. I would appreciate if you could point them to me.
> > In addition I believe I would need to have a linked or optimized bitcode to feed into llc.
> >
> > Stas
> >
> > -----Original Message-----
> > From: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org>
> > Sent: Wednesday, September 22, 2021 12:06
> > To: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com>
> > Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org>
> > Subject: Re: [TCWG CI] 456.hmmer slowed down by 6% after llvm: Allow rematerialization of virtual reg uses
> >
> > [CAUTION: External Email]
> >
> > Hi Stanislav,
> >
> > That's fair; I or someone from Linaro will try to analyze this and follow up here.
> >
> > On a more general note, what info would you like to see in these benchmarking regression reports?
> >
> > Thanks,
> >
> > --
> > Maxim Kuvyrkov
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.linar…
> >
> >
> >> On Sep 22, 2021, at 9:40 PM, Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com> wrote:
> >>
> >> [AMD Official Use Only]
> >>
> >> Hm... I'd really like to help, but I do not think I can do anything with megabytes of code in an asm which I do not understand and tons of differences in 48 asm files.
> >> What I can see there is overall less spilling code which was the intent in the first place: hmmer has 4 less spill opcodes overall and sphinx has 27 less of them.
> >> I doubt I could say much more without someone pointing to the actual root cause.
> >>
> >> Stas
> >>
> >> -----Original Message-----
> >> From: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org>
> >> Sent: Wednesday, September 22, 2021 5:16
> >> To: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com>
> >> Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org>
> >> Subject: Re: [TCWG CI] 456.hmmer slowed down by 6% after llvm: Allow rematerialization of virtual reg uses
> >>
> >> [CAUTION: External Email]
> >>
> >> Hi Stanislav,
> >>
> >> Attached is a tarball with -save-temps output (pre-processed source and generated assembly) for first-bad run (your commit) and last-good run (immediate parent of your commit).
> >>
> >> --
> >> Maxim Kuvyrkov
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.linar…
> >>
> >>> On 20 Sep 2021, at 23:15, Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com> wrote:
> >>>
> >>> [AMD Official Use Only]
> >>>
> >>> Thanks for letting me know. Some regressions are inevitable, however do you happen to have any analysis and dumps? I myself do not understand ARM ISA well...
> >>>
> >>> Stas
> >>>
> >>> -----Original Message-----
> >>> From: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org>
> >>> Sent: Wednesday, September 15, 2021 5:52
> >>> To: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin(a)amd.com>
> >>> Cc: linaro-toolchain <linaro-toolchain(a)lists.linaro.org>
> >>> Subject: Re: [TCWG CI] 456.hmmer slowed down by 6% after llvm: Allow rematerialization of virtual reg uses
> >>>
> >>> [CAUTION: External Email]
> >>>
> >>> Hi Stanislav,
> >>>
> >>> FYI, your patch seems to be slowing down two of SPEC CPU2006 tests on 32-bit ARM at -O2 and -O3 optimization levels.
> >>>
> >>> --
> >>> Maxim Kuvyrkov
> >>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.linar…
> >>>
> >>
> >>
> >
> <image001.png>
4 years
- 1
- 0
[TCWG CI] Regression caused by binutils: Automatic date update in version.in
by ci_notify＠linaro.org
[TCWG CI] Regression caused by binutils: Automatic date update in version.in:
commit fcc561a54de2beb19cb325094fbd3ec76f96e520
Author: GDB Administrator <gdbadmin(a)sourceware.org>
Automatic date update in version.in
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-8
# build_abe newlib:
-6
# build_abe stage2 -- --patch linaro-local/vect-metric-branch --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-5
# true:
0
# benchmark -- -O3_LTO_VECT_mthumb artifacts/build-fcc561a54de2beb19cb325094fbd3ec76f96e520/results_id:
1
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-8
# build_abe newlib:
-6
# build_abe stage2 -- --patch linaro-local/vect-metric-branch --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard:
-5
# true:
0
# benchmark -- -O3_LTO_VECT_mthumb artifacts/build-baseline/results_id:
1
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_gnu_eabi_stm32/gnu_eabi-release-arm_eabi-coremark-O3_LTO_VECT
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea…
Reproduce builds:
<cut>
mkdir investigate-binutils-fcc561a54de2beb19cb325094fbd3ec76f96e520
cd investigate-binutils-fcc561a54de2beb19cb325094fbd3ec76f96e520
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_ea… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /binutils/ ./ ./bisect/baseline/
cd binutils
# Reproduce first_bad build
git checkout --detach fcc561a54de2beb19cb325094fbd3ec76f96e520
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 27439f0edab99c6870cf7fe042074e47632f3fbd
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit fcc561a54de2beb19cb325094fbd3ec76f96e520
Author: GDB Administrator <gdbadmin(a)sourceware.org>
Date: Wed Sep 22 00:00:31 2021 +0000
Automatic date update in version.in
---
bfd/version.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bfd/version.h b/bfd/version.h
index 338c1288a22..c45d963473c 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -16,7 +16,7 @@
In releases, the date is not included in either version strings or
sonames. */
-#define BFD_VERSION_DATE 20210921
+#define BFD_VERSION_DATE 20210922
#define BFD_VERSION @bfd_version@
#define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@
#define REPORT_BUGS_TO @report_bugs_to@
</cut>
4 years
- 1
- 0