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[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O2_LTO - Build # 16 - Successful!

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Successfully identified regression in *gcc* in CI configuration tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO. So far, this commit has regressed CI configurations: - tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO Culprit: <cut> commit de56f95afaaa22c67cbeec780921d63e8b34514e Author: Xionghu Luo <luoxhu(a)linux.ibm.com> Date: Tue May 18 21:34:18 2021 -0500 Run pass_sink_code once more before store_merging Gimple sink code pass runs quite early, there may be some new oppertunities exposed by later gimple optmization passes, this patch runs the sink code pass once more before store_merging. For detailed discussion, please refer to: https://gcc.gnu.org/pipermail/gcc-patches/2020-December/562352.html Tested the SPEC2017 performance on P8LE, 544.nab_r is improved by 2.43%, but no big changes to other cases, GEOMEAN is improved quite small with 0.25%. gcc/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * passes.def: Add sink_code pass before store_merging. * tree-ssa-sink.c (pass_sink_code:clone): New. gcc/testsuite/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * gcc.dg/tree-ssa/ssa-sink-1.c: Adjust. * gcc.dg/tree-ssa/ssa-sink-2.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-3.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-4.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-5.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-6.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-7.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-8.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-9.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-10.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-13.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-14.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-16.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-17.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-18.c: New. </cut> Results regressed to (for first_bad == de56f95afaaa22c67cbeec780921d63e8b34514e) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO -- artifacts/build-de56f95afaaa22c67cbeec780921d63e8b34514e/results_id: 1 # 447.dealII,dealII_base.default regressed by 103 from (for last_good == 39ed6a88c74db5412652f0167d03f71eca4f02fc) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO -- artifacts/build-39ed6a88c74db5412652f0167d03f71eca4f02fc/results_id: 1 Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of last_good: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2_LTO/381 Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of first_bad: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2_LTO/350 Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Configuration details: Reproduce builds: <cut> mkdir investigate-gcc-de56f95afaaa22c67cbeec780921d63e8b34514e cd investigate-gcc-de56f95afaaa22c67cbeec780921d63e8b34514e git clone https://git.linaro.org/toolchain/jenkins-scripts mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh cd gcc # Reproduce first_bad build git checkout --detach de56f95afaaa22c67cbeec780921d63e8b34514e ../artifacts/test.sh # Reproduce last_good build git checkout --detach 39ed6a88c74db5412652f0167d03f71eca4f02fc ../artifacts/test.sh cd .. </cut> History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Full commit (up to 1000 lines): <cut> commit de56f95afaaa22c67cbeec780921d63e8b34514e Author: Xionghu Luo <luoxhu(a)linux.ibm.com> Date: Tue May 18 21:34:18 2021 -0500 Run pass_sink_code once more before store_merging Gimple sink code pass runs quite early, there may be some new oppertunities exposed by later gimple optmization passes, this patch runs the sink code pass once more before store_merging. For detailed discussion, please refer to: https://gcc.gnu.org/pipermail/gcc-patches/2020-December/562352.html Tested the SPEC2017 performance on P8LE, 544.nab_r is improved by 2.43%, but no big changes to other cases, GEOMEAN is improved quite small with 0.25%. gcc/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * passes.def: Add sink_code pass before store_merging. * tree-ssa-sink.c (pass_sink_code:clone): New. gcc/testsuite/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * gcc.dg/tree-ssa/ssa-sink-1.c: Adjust. * gcc.dg/tree-ssa/ssa-sink-2.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-3.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-4.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-5.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-6.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-7.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-8.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-9.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-10.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-13.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-14.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-16.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-17.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-18.c: New. --- gcc/passes.def | 1 + gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c | 212 ++++++++++++++++++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c | 15 -- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c | 2 +- gcc/tree-ssa-sink.c | 1 + 17 files changed, 229 insertions(+), 30 deletions(-) diff --git a/gcc/passes.def b/gcc/passes.def index de39fa48b3d..945d2bc797c 100644 --- a/gcc/passes.def +++ b/gcc/passes.def @@ -348,6 +348,7 @@ along with GCC; see the file COPYING3. If not see NEXT_PASS (pass_phiopt, false /* early_p */); NEXT_PASS (pass_fold_builtins); NEXT_PASS (pass_optimize_widening_mul); + NEXT_PASS (pass_sink_code); NEXT_PASS (pass_store_merging); NEXT_PASS (pass_tail_calls); /* If DCE is not run before checking for uninitialized uses, diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c index 411585a6dc4..57b501681f3 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c @@ -7,4 +7,4 @@ foo (int a, int b, int c) return c ? x : a; } /* We should sink the x = a * b calculation into the branch that returns x. */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c index 37e4d2fe687..535cb3208f5 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c @@ -16,4 +16,4 @@ void foo (void) } } -/* { dg-final { scan-tree-dump-times "Sinking # VUSE" 4 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking # VUSE" 4 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c index a65ba35d4ba..584fd91f43a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c @@ -21,5 +21,5 @@ void test () /* We should sink/merge all stores and end up with a single BB. */ -/* { dg-final { scan-tree-dump-times "MEM\[^\n\r\]* = 0;" 3 "sink" } } */ -/* { dg-final { scan-tree-dump-times "<bb " 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "MEM\[^\n\r\]* = 0;" 3 "sink1" } } */ +/* { dg-final { scan-tree-dump-times "<bb " 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c index 771cd4420c4..f5418b06deb 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c @@ -13,5 +13,5 @@ void foo (int b) /* We should have sunk the store and inserted a PHI to merge the stored values. */ -/* { dg-final { scan-tree-dump-times " = PHI" 1 "sink" } } */ -/* { dg-final { scan-tree-dump-times "x = " 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times " = PHI" 1 "sink1" } } */ +/* { dg-final { scan-tree-dump-times "x = " 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c index 610c8d60ebe..012b165fbab 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c @@ -10,5 +10,5 @@ int f(int n) return j; } -/* { dg-final { scan-tree-dump "Sinking j_. = __builtin_ffs" "sink" } } */ +/* { dg-final { scan-tree-dump "Sinking j_. = __builtin_ffs" "sink1" } } */ /* { dg-final { scan-tree-dump "return 2;" "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c index cf2e2a0f766..d0aeeb312cc 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c @@ -12,4 +12,4 @@ int my_f(int a, int b) } /* We should sink the call to pure_f to the if block. */ -/* { dg-final { scan-tree-dump "Sinking # VUSE" "sink" } } */ +/* { dg-final { scan-tree-dump "Sinking # VUSE" "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c new file mode 100644 index 00000000000..421c78eba50 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c @@ -0,0 +1,212 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-sink-stats" } */ + +#include <stdint.h> + +#define HLOG 16 +#define MAX_LIT (1 << 5) +typedef const uint8_t *LZF_HSLOT; +typedef LZF_HSLOT LZF_STATE[1 << (HLOG)]; + +int +compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) +{ + LZF_STATE htab; + + uint8_t *ip = in_data; + uint8_t *op = out_data; + uint8_t *in_end = ip + in_len; + uint8_t *out_end = op + out_len; + uint8_t *ref; + + unsigned long off; + unsigned int hval; + int lit; + + if (!in_len || !out_len) + return 0; + + lit = 0; + op++; + hval = (((ip[0]) << 8) | ip[1]); + + while (ip < in_end - 2) + { + uint8_t *hslot; + + hval = (((hval) << 8) | ip[2]); + hslot = (uint8_t*)(htab + (((hval >> (3 * 8 - 16)) - hval * 5) & ((1 << (16)) - 1))); + + ref = *hslot + in_data; + *hslot = ip - in_data; + + if (1 && (off = ip - ref - 1) < (1 << 13) && ref > in_data + && ref[2] == ip[2] + && ((ref[1] << 8) | ref[0]) == ((ip[1] << 8) | ip[0])) + { + unsigned int len = 2; + unsigned int maxlen = in_end - ip - len; + maxlen + = maxlen > ((1 << 8) + (1 << 3)) ? ((1 << 8) + (1 << 3)) : maxlen; + + if ((op + 3 + 1 >= out_end) != 0) + if (op - !lit + 3 + 1 >= out_end) + return 0; + + op[-lit - 1] = lit - 1; + op -= !lit; + + for (;;) + { + if (maxlen > 16) + { + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + } + + do + { + len++; + } + while (len < maxlen && ip[len] == ref[len]); + + break; + } + + len -= 2; + ip++; + + if (len < 7) + { + *op++ = (off >> 8) + (len << 5); + } + else + { + *op++ = (off >> 8) + (7 << 5); + *op++ = len - 7; + } + *op++ = off; + lit = 0; + op++; + ip += len + 1; + + if (ip >= in_end - 2) + break; + + --ip; + --ip; + + hval = (((ip[0]) << 8) | ip[1]); + hval = (((hval) << 8) | ip[2]); + htab[(((hval >> (3 * 8 - 16)) - hval * 5) & ((1 << (16)) - 1))] + = (LZF_HSLOT)(ip - in_data); + ip++; + + hval = (((hval) << 8) | ip[2]); + htab[(((hval >> (3 * 8 - 16)) - hval * 5) & ((1 << (16)) - 1))] + = (LZF_HSLOT)(ip - in_data); + ip++; + } + else + { + if (op >= out_end) + return 0; + + lit++; + *op++ = *ip++; + + if (lit == (1 << 5)) + { + op[-lit - 1] = lit - 1; + lit = 0; + op++; + } + } + } + if (op + 3 > out_end) /* at most 3 bytes can be missing here */ + return 0; + + while (ip < in_end) + { + lit++; + *op++ = *ip++; + if (lit == MAX_LIT) + { + op[-lit - 1] = lit - 1; /* stop run */ + lit = 0; + op++; /* start run */ + } + } + + op[-lit - 1] = lit - 1; /* end run */ + op -= !lit; /* undo run if length is zero */ + + return op - out_data; + } + + /* For this case, pass sink2 sinks statements from hot loop header to loop + exits after gimple loop optimizations, which generates instructions executed + each iteration in loop, but the results are used outside of loop: + With -m64, + "Sinking _367 = (uint8_t *) _320; + from bb 31 to bb 90 + Sinking _320 = _321 + ivtmp.25_326; + from bb 31 to bb 90 + Sinking _321 = (unsigned long) ip_229; + from bb 31 to bb 90 + Sinking len_158 = _322 + 4294967295; + from bb 31 to bb 33" + When -m32, Power and X86 will sink 3 instructions, but arm ilp32 couldn't + sink due to ivopts chooses two IV candidates instead of one, which is + expected, so this case is restricted to lp64 only so far. */ + + /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c index 6aa5a182a3a..a0b4734b1e0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c @@ -9,4 +9,4 @@ bar (int a, int b, int c) return y; } /* We should sink the x = a * b calculation into the else branch */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c index 599997e0e6b..e69de29bb2d 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c @@ -1,15 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-sink-stats" } */ -extern void foo(int a); -int -main (int argc) -{ - int a; - a = argc + 1; - if (argc + 3) - { - foo (a); - } -} -/* We should sink the a = argc + 1 calculation into the if branch */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c index 784edd2fc87..1e3cfa93fa8 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c @@ -17,4 +17,4 @@ main (int argc) foo2 (a); } /* We should sink the first a = b + c calculation into the else branch */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c index dbdde39add6..f04da5da9b0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c @@ -44,4 +44,4 @@ void foo(int16_t runs[], uint8_t alpha[], int x, int count) } /* We should not sink the next_runs = runs + x calculation after the loop. */ -/* { dg-final { scan-tree-dump-times "Sunk statements:" 0 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements:" 0 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c index 1abae9f7943..31f5af330f9 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c @@ -14,4 +14,4 @@ int foo(int *a, int r) /* *a = 1 should be sunk to the else block. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c index ec3288f4e69..bd748442edc 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c @@ -15,4 +15,4 @@ int foo(int *a, int r, short *b) /* *a = 1 should be sunk to the else block. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c index 48af4218fc0..4b23b567fd0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c @@ -24,4 +24,4 @@ int foo(int *a, int r, short *b) /* *a = 1 should be sunk into the default case. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c index 509a76330a4..32bfc81741a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c @@ -15,4 +15,4 @@ int foo(int *a, int r, int *b) /* *a = 1 should be sunk to the else block. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/tree-ssa-sink.c b/gcc/tree-ssa-sink.c index d33e56ef915..d252cbb5c51 100644 --- a/gcc/tree-ssa-sink.c +++ b/gcc/tree-ssa-sink.c @@ -819,6 +819,7 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { return flag_tree_sink != 0; } virtual unsigned int execute (function *); + opt_pass *clone (void) { return new pass_sink_code (m_ctxt); } }; // class pass_sink_code </cut>

3 years, 10 months

1
0
0 0

Flang buildbot workers

by Andrzej Warzynski

Hi, I've just noticed that all of Flang's buildbot workers managed by Linaro are offline: https://lab.llvm.org/buildbot/#/builders (type "flang" in the search box). As 8 out of 10 Flang's workers are managed by Linaro, in practice this means that we have almost no testing :( Please, could you look into this or let me know who to get in touch with? Thank you, -Andrzej IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

3 years, 10 months

3
8
0 0

[ACTIVITY] week ending 20 Jun 2021

by Richard Henderson

[UM-2] * Version 2 of signal trampolines, * Version 1 of vdso, * RFC patch set for #360 (unaligned mmio), * Beginning on #404 (breakpoint slowdown), - convert cris, nios2, avr to translator loop. - translator_use_goto_tb Both of these, working toward improving the recognition of pc's with bp's, and avoiding the need for any tb flushing at all. r~

3 years, 10 months

1
0
0 0

[ACTIVITY] 14-18 June 2021

by Christophe Lyon

== Progress == * GCC - MVE/vectorization: committed patches for vec_pack / vec_unpack - handling feedback on patch for PR 100757 * GCC upstream validation: - reported a couple of regressions == Next == Now leaving Linaro, hopefully I can continue to work on: * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M Thanks for the great time at Linaro!

3 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 18 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Usual code review and pull request wrangling (nothing major this week) + Added information to our documentation about what Arm architecture features our emulation supports (we get asked this from time to time, and users shouldn't have to dig through back issues of the Changelogs or decipher the ID register updates in the source code...) + Investigated some bugs in v8.1M VLDR/VSTR sysreg detected by trying to run some gcc test cases under QEMU: sent patches + KVM Forum programme committee meeting & voting on talk abstracts * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Fixed various issues in the first-part-of-MVE patchset; it's now through code review and ready to go in + Started looking at the logical-immediate insns + Progress meter: 74/210 (35%) (still) -- PMM

3 years, 11 months

1
0
0 0

[ACTIVITY] week ending 13 Jun 2021

by Richard Henderson

[UM-2] Upstream bugs: #390, fix posted #403, fix posted #360, lots of investigation, and work on updating a patch from 2017. I have a workable change, which ought to be improved. Reorg for tcg bswap opcode. r~

3 years, 11 months

1
0
0 0

[ACTIVITY] 7-11 June 2021

by Christophe Lyon

== Progress == * GCC - MVE/vectorization: committed patches for vhadd/vrhadd and vclz - handling feedback on patch for vec_pack / vec_unpack - PR 100757 * GCC upstream validation: - reported a couple of regressions == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

3 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 10 June

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] + Code review: + v4 of Shashi's ITS series. I think this is getting pretty close to good to go in now. * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Completed implementation of PSR.ECI handling + Implemented VADDV + Sent out an interim patchset for early code review (55 patches, ~3400 lines, covers about 35% of the ISA) + Started working through the code review comments from rth + Progress meter: 74/210 (35%) -- PMM

3 years, 11 months

1
0
0 0

[ACTIVITY] week ending 6 June 2021

by Richard Henderson

[UM-2] * Refresh tci patch set. * Review: - target/s390 vector enhancements - arm refactor * Knocked up a tcg patch for Peter's MVE work. r~

3 years, 11 months

1
0
0 0

[ACTIVITY] 31 May - 4 June 2021

by Prathamesh Kulkarni

== This Week == * GCC (1) PR66791 (replace builtins with gcc vector extensions): - Waiting for feedback on vmul_n patch - Created patch for vector comparison ops. (2) PR97906 (missed lowering to vacge) - Submitted patch upstream. (3) PR98435 (missed optimization in expanding vec constructor) - Submitted patch upstream. * Sick leave - Off on thursday. == Next Week == - Continue with PR66791 - Address comments for PR97906 and PR98435

3 years, 11 months

1
0
0 0

[ACTIVITY] week ending Jun. 6 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted [RFC PATCH] configure: allow the overriding of default-config in the build Message-Id: <20210528163116.31902-1-alex.bennee(a)linaro.org> - posted [PATCH v16 00/99] arm tcg/kvm refactor and split with kvm only support Message-Id: <20210604155312.15902-1-alex.bennee(a)linaro.org> [STR-9] <https://projects.linaro.org/browse/STR-9> QEMU Device and Machine Models ([QEMU-418]) =========================================== - started prepping v3 of the kvm-unit-tests [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] semihosting/arm-compat: remove heuristic softmmu SYS_HEAPINFO Message-Id: <20210601090715.22330-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [5/5] ======================= [RFC PATCH 0/3] Cache modelling TCG plugin Message-Id: <20210529152203.40358-1-ma.mandourr(a)gmail.com> [PATCH v2 00/28] Convert floatx80 and float128 to FloatParts Message-Id: <20210525150706.294968-1-richard.henderson(a)linaro.org> [PATCH v7 00/27] TCI fixes and cleanups Message-Id: <20210601150106.12761-1-richard.henderson(a)linaro.org> [PATCH v8 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210526170432.343588-1-philmd(a)redhat.com> [PATCH v2 00/12] hw: Various Kconfig fixes Message-Id: <20210515173716.358295-1-philmd(a)redhat.com> Absences ======== Current Review Queue ==================== TODO [PATCH 0/5] virtio: Add vhost-user based RNG service Message-Id: <20210601200305.1772391-1-mathieu.poirier(a)linaro.org> ========================================================================================================================== TODO [PATCH v2 00/11] linux-user changes to run docker Message-Id: <20210531055019.10149-1-yamamoto(a)midokura.com> ================================================================================================================ TODO [PATCH V5 0/2] Virtio support for toolstack on Arm (Was "IOREQ feature (+ virtio-mmio) on Arm") Message-Id: <1621603005-5799-1-git-send-email-olekstysh(a)gmail.com> ====================================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== -- Alex Bennée

3 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 4 Jun

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] + Code review: - reviewed the easy half of the "aarch64 support for osx hvf accelerator" patchseries - RTH's bfloat16 support series + Misc bugs: - Sent a patchset fixing a compile failure reported by MS when the 'virt' board is not enabled (requires a custom local config) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Working through the details of how PSR.ECI works for resuming half-executed insns (annoyingly awkward to implement for a subfeature that will almost never get used...). I have most of an implementation now but it needs a bit of new functionality in TCG ("throw away any TCG ops we just generated and rewind to point X") which RTH hasn't written yet :-) + None of that work corresponds to adding more insn patterns, so no change on the Progress meter: 73/210 (34%) -- PMM

3 years, 11 months

1
0
0 0

[ACTIVITY] 31 May - 4 June 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - reported a couple of regressions * GCC - MVE/vectorization: committed patches for vans - submitted patch for vhadd/vrhadd - WIP on vclz / vec_pack / vec_unpack - PR 100757 == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

3 years, 11 months

1
0
0 0

[ACTIVITY] 24-28 May 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - reported a couple of regressions * GCC - MVE/vectorization: committed patches for vld2/vst2, vld4/st4, vaddv - WIP on vhadd/vrhadd == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

3 years, 11 months

1
0
0 0

[ACTIVITY] week ending May. 30 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - more work on getting [arm refactor] ready for posting - posted [RFC PATCH] configure: allow the overriding of default-config in the build Message-Id: <20210528163116.31902-1-alex.bennee(a)linaro.org> [arm refactor] <https://github.com/stsquad/qemu/tree/arm/refactor-tcg-accel-split-v16> QEMU Device and Machine Models ([QEMU-418]) =========================================== - posted [kvm-unit-tests PATCH v2 0/4] enable LPI and ITS for TCG Message-Id: <20210525172628.2088-4-alex.bennee(a)linaro.org> [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 1/7] gitlab: explicitly reference the upstream registry Message-Id: <20210525112431.22005-1-alex.bennee(a)linaro.org> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Completed Reviews [5/5] ======================= [PATCH 0/5] linux-user changes to run docker Message-Id: <20210524045412.15152-1-yamamoto(a)midokura.com> [PATCH 0/4] gitlab-ci: Allow using FreeBSD runners Message-Id: <20210510152254.2543047-1-f4bug(a)amsat.org> [RFC PATCH 0/5] Use ccache in the gitlab-CI Message-Id: <20210414081907.871437-1-thuth(a)redhat.com> [PATCH 0/9] gitlab-ci: Make mainstream CI green again Message-Id: <20210525082556.4011380-1-f4bug(a)amsat.org> [PATCH] HMP: added cpustats to removed_features.rst Message-Id: <20210527191028.24febe7e(a)bahia.lan> Absences ======== Current Review Queue ==================== TODO [PATCH V5 0/2] Virtio support for toolstack on Arm (Was "IOREQ feature (+ virtio-mmio) on Arm") Message-Id: <1621603005-5799-1-git-send-email-olekstysh(a)gmail.com> ====================================================================================================================================================================== TODO [PATCH v2 00/12] hw: Various Kconfig fixes Message-Id: <20210515173716.358295-1-philmd(a)redhat.com> ====================================================================================================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== -- Alex Bennée

3 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 27 May

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] + Code review: - SVE2 series v7 (now finally done) - RTH's tlb_flush range refactoring - A few other minor patchsets + Arm pullrequest: SVE2 emulation support is now upstream + Misc bugs: - sent some patches fixing a few coverity nits in our test suite code * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Implemented: - VQDMULL, VRHADD, VADC, VSBC, VCADD, VHCADD - LCTP, LETP, WLSTP, DLSTP (the tail-predicating loop insns) - Progress meter: 73/210 (34%) -- PMM

3 years, 11 months

1
0
0 0

[ACTIVITY] 17 - 21 May 2021

by Prathamesh Kulkarni

== This Week == * PR66791 (Replace builtins with C operations in intrinsics) - vtst: Committed patch to trunk. - vshl_n: Patch results in worse code-gen, abandoned. - vmul_n: Created patch, looking into testsuite fallout * PR97906 (Missed lowering abs(x) >= abs(y) to vcage x, y) - Investigated PR and have a WIP fix. == Next Week == - Continue with PR66791, PR97906

3 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 21 May

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review: - bfloat16 support patchset - v3 of ITS emulation patchset + Misc bugs: - sent a patch fixing a bug where we sometimes selected the wrong stack pointer when doing a v8M exception return in a case involving tail-chaining (needed by an upcoming Arm TF-M change) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Sent a small patchset which implements a few preliminary MVE things (VPR register, FPSCR.QC bit, fixing checks for existing insns which now need to be "FP or MVE" rather than just "FP") + Implemented: - VADD VSUB VMULL VHADD VHSUB VQADD VQSUB VQDMULH VQRDMULH scalar - VBRSR, VPST, VQDMULH, VQRDMULH, VQADD, VQSUB - VQSHL VQRSHL VSHL VRSHL vector forms - VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH Progress meter: 63/210 (30%) -- PMM

3 years, 12 months

1
0
0 0

[ACTIVITY] week ending May. 23 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - worked with Viresh on getting more reliable Xen up and running - formally took over Caludio's arm branch as I need it for mine - preparing [my version] for posting [my version] <https://github.com/stsquad/qemu/tree/arm/refactor-tcg-accel-split-v16> QEMU Upstream Work ([UM-2]) =========================== - finally got [PULL v2 00/29] testing and plugin updates Message-Id: <20210518090720.21915-1-alex.bennee(a)linaro.org> merged - posted [PATCH v1 0/8] various misc fixes (gitlab, gdbstub, plugins) Message-Id: <20210520174303.12310-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Other ===== - [Blog post on QEMU went live] [Blog post on QEMU went live] <https://www.linaro.org/blog/many-uses-of-qemu/> Current Review Queue ==================== TODO [PATCH v2 00/12] hw: Various Kconfig fixes Message-Id: <20210515173716.358295-1-philmd(a)redhat.com> ====================================================================================================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== -- Alex Bennée

3 years, 12 months

1
0
0 0

[ACTIVITY] 17-21 May 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - reported a couple of regressions * GCC - MVE/vectorization: committed patches for vcmp, waiting for feedback on the remaining patches for vld2/vst2, vld4/st4 - started work on vaddv support - committed a few testsuite improvement patches - committed patch for PR 42579 * Misc - looking at gdb issue with register names in target description == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

3 years, 12 months

1
0
0 0

[ACTIVITY] week ending 16 May 2021

by Richard Henderson

3 day week. [UM-2 # QEMU Upstream] * Refresh target/i386 translate user/sysemu cleanup. * Pull request for half of my softfloat reorg. * Tiny pull request for collected tcg patches. [QEMU-349 # SVE2] * Processing Peter's review comments. Another 3 day week this week. r~

3 years, 12 months

1
0
0 0

[ACTIVITY] 10-14 May 2021

by Christophe Lyon

Short week (2.5 days off) == Progress == * GCC upstream validation: - discussing update of the list of configs * GCC - MVE/vectorization: committing cleanup patches for vcmp, waiting for feedback on the remaining patches for vcmp, vld2/vst2, vld4/st4 * Misc - scripts patch reviews - looking at gdb issue with register names in target description == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

3 years, 12 months

1
0
0 0

[ACTIVITY] report week ending 14 May

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review: - Managed to review all of RTH's 82-patch SVE2 patchset... + Misc bugs: - fixed some errors in modelling of SRAM in AN547 board - fixed a bug in GICv3 EOI (EL3 should be able to handle Group 1 NS IRQs) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Implemented multiply-add-long-dual-accumulate insns (VMLALDAV, VMLSLDAV, VRMLALDAVH, VRMLSLDAVH) Progress meter: 40/210 (19%) -- PMM

4 years

1
0
0 0

[ACTIVITY] week ending May. 16 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - did some investigation on getting [Gunyah hypervisor] up and running - debugging xl domU launch under QEMU - got reverse debugging working on virtio ;-) [STR-9] <https://projects.linaro.org/browse/STR-9> [Gunyah hypervisor] <https://github.com/quic/gunyah-hypervisor> QEMU Upstream Work ([UM-2]) =========================== - reviewed a large chunk of rth's FloatParts opus Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org> - posted [PATCH v3 00/31] testing/next pre-PR (hexagon, tricore, misc) Message-Id: <20210512102051.12134-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Other ===== [Linaro JIRA Issues] Updates for LBO-99: QEMU's usage in Linaro Message-Id: <01000178a38e5f60-4b7149b0-b71b-4952-869f-cabdfb9078a6-000000(a)email.amazonses.com> Completed Reviews [1/1] ======================= [PATCH 00/72] Convert floatx80 and float128 to FloatParts Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org> Absences ======== - Bank Holiday on Monday Current Review Queue ==================== TODO [PATCH v3 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210429234201.125565-1-shashi.mallela(a)linaro.org> =========================================================================================================================== TODO [PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS Message-Id: <20210505030443.25310-1-rebecca(a)nuviainc.com> ==================================================================================================================================== TODO [PATCH v6 00/82] target/arm: Implement SVE2 Message-Id: <20210430202610.1136687-1-richard.henderson(a)linaro.org> =================================================================================================================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== -- Alex Bennée

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Bootstrap-O3 broken on 32-bit ARM

by Maxim Kuvyrkov

Hi Richard, Your patch a076632e274abe344ca7648b7c7f299273d4cbe0 appears to have broken bootstrap-O3 for 32-bit armhf. Do you have an AArch32-capable machine to reproduce/investigate this on? Let me know if not, and I'll make a proper bug report with a testcase. ICE: 00:33:32 In function ‘syscall.forkExec’: 00:33:32 go1: error: address taken, but ADDRESSABLE bit not set 00:33:32 PHI argument 00:33:32 &go..C479; 00:33:32 for PHI node 00:33:32 err$__object_78 = PHI <err$__object_76(58), &go..C479(59)> 00:33:32 during GIMPLE pass: fre 00:33:32 go1: internal compiler error: verify_ssa failed 00:33:32 0x9c18d7 verify_ssa(bool, bool) 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/tree-ssa.c:1214 00:33:32 0x6f8d5b execute_function_todo 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2049 00:33:32 0x6f9abf do_per_function 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:1687 00:33:32 0x6f9abf execute_todo 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2096 00:33:32 Please submit a full bug report, 00:33:32 with preprocessed source if appropriate. 00:33:32 Please include the complete backtrace with any bug report. 00:33:32 See <https://gcc.gnu.org/bugs/> for instructions. 00:33:32 Makefile:3001: recipe for target 'syscall.lo' failed Full build log: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… Regards, -- Maxim Kuvyrkov https://www.linaro.org > On May 11, 2021, at 8:15 AM, tcwg-jira (Jira) <projects(a)linaro.org> wrote: > > There is 1 comment. > > > GNU Toolchain / <Mail Attachment.png> GNU-692 IN PROGRESS > Regressions from tcwg_binutils/tcwg_cross/tcwg_gnu CI > > View issue · Add comment > > 1 comment > > tcwg-jira on 11/May/21 5:04 AM > > Successfully identified regression in gcc in CI configuration tcwg_gnu/gnu-master-arm-bootstrap_O3. So far, this commit has regressed CI configurations: > • tcwg_gnu/gnu-master-arm-bootstrap_O3 > Culprit: > <cut> > commit a076632e274abe344ca7648b7c7f299273d4cbe0 > Author: Richard Biener <rguenther(a)suse.de> > Date: Fri May 7 09:51:18 2021 +0200 > middle-end/100464 - avoid spurious TREE_ADDRESSABLE in folding debug stmts > canonicalize_constructor_val was setting TREE_ADDRESSABLE on bases > of ADDR_EXPRs but that's futile when we're dealing with CTOR values > in debug stmts. This rips out the code which was added for Java > and should have been an assertion when we didn't have debug stmts. > To not regress g++.dg/tree-ssa/array-temp1.C we have to adjust the > testcase to not look for a no longer applied invalid optimization. > 2021-05-10 Richard Biener <rguenther(a)suse.de> > PR middle-end/100464 > PR c++/100468 > gcc/ > • gimple-fold.c (canonicalize_constructor_val): Do not set > TREE_ADDRESSABLE. > gcc/cp/ > • call.c (set_up_extended_ref_temp): Mark the temporary > addressable if the TARGET_EXPR was. > gcc/testsuite/ > • gcc.dg/pr100464.c: New testcase. > • g++.dg/tree-ssa/array-temp1.C: Adjust. > </cut> > Details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… > Even more details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… > > > This message was sent by Atlassian Jira (v8.11.1#811002-sha1:94cd716) > Jira is improving email notifications, share your feedback! > Get Jira notifications on your phone! Download the Jira Server app for Android or iOS.

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