- linaro-toolchain - lists.linaro.org

[ACTIVITY] 16-20 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: more patterns updates (vshl, vshr). WIP * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

5 years

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[ACTIVITY] report week ending 20 Nov

by Peter Maydell

Generally productive week rather derailed at the end by a sudden onset of toothache Thursday night :-/ Progress: * UM-2 [QEMU upstream maintainership] + usual release cycle work * VIRT-364 [QEMU support for ARMv8.1-M extensions] + Worked through the remaining set of identified new features for v8.1M implementing them. + Fixed a handful of pre-existing bugs along the way. + Sent out a patchset with all this plus the "Implement (no-MVE) Cortex-M55 model" patch on top, since we now have all the pieces needed for it. + The next and final piece of work here is to implement a model of a board that uses the Cortex-M55. -- PMM

5 years, 1 month

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[ACTIVITY] week ending Nov. 15 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO Portability Demo ([STR-13]) ================================== - recorded AGL demo videos (KVM, TCG Xen Dom0 with and without Xen aware kernel) - recorded [preview version of talk] [STR-13] <https://projects.linaro.org/browse/STR-13> [preview version of talk] <https://fileserver.linaro.org/s/wgt2AAj9rxYqJop> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 for 5.1 00/10] various fixes (CI, Xen, plugins) Message-Id: <20201110192316.26397-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [2/2] ======================= [for-5.2 0/9] docs: Move orphan top-level .rst files into manuals Message-Id: <20201112144041.32278-1-peter.maydell(a)linaro.org> [PATCH v3 00/41] Mirror map JIT memory for TCG Message-Id: <20201106032921.600200-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2020-11-14 Sat 11:52] Had a brief look over, waiting for next revision Added: <2020-11-06 Fri> Current Review Queue ==================== * [PATCH v2 0/4] linux/sparc: more get/set_context fixes Message-Id: <20201106152738.26026-1-peter.maydell(a)linaro.org> Added: <2020-11-06 Fri> * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> -- Alex Bennée

5 years, 1 month

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[ACTIVITY] 9-13 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: started patterns updates (vand, vorr, veor) * Misc - investigated LP bug 1747966 (https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966) there is a fix in binutils upstream: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0e6a3f07f50723d18… * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

5 years, 1 month

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[ACTIVITY] report week ending 13 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + investigated and fixed a bug that had been lurking unfixed in our n800 models for years which prevented guest boot of Maemo images + docs tidyup: moved "orphan" rST documents into the manual structure so they actually get shipped to users + usual release candidate related work * VIRT-364 [QEMU support for ARMv8.1-M extensions] + working on handling for new FP system registers; the FPCXT regs in particular have some tricky corners... thanks -- PMM

5 years, 1 month

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[ACTIVITY] week ending 8 Nov 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] * Fix neon register offsets big-endian hosts. * Fix neon register offsets for VTBL. * Working through a 4th revision of float128_muladd. * Random patch review and bug fixes. [UM-61 # TCG Core Maintainership ] * Two revisions of split w^x patch set. r~

5 years, 1 month

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Demo of using etm traces on arm for instructions and functions recording and reverse debugging

by Zied Guermazi

hi all, to demonstrate extending gdb to use etm traces for implementing btrace on arm processors, I have made this video available on youtube https://youtu.be/ptKbJRNUqUI users can then have access to process record and replay, on instructions and functions level (https://sourceware.org/gdb/current/onlinedocs/gdb/Process-Record-and-Replay…) and reverse debugging(https://www.gnu.org/software/gdb/news/reversible.html) we have all functionalities available for intel PT except tracing multi-threaded applications. In this demo I have "reconstructed" the cspr register to enable setting breakpoints in reverse debugging. it is still dirty (adds arm specific register to an architecture agnostic structure) but it shows that it works when implemented properly Kind Regards Zied Guermazi

5 years, 1 month

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[ACTIVITY] 2-6 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - PR96767: patch committed - PR96770: patch committed - patch for C++ thunks with -mpure-code and cortex-m0: patches committed - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: handling feedback * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

5 years, 1 month

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[ACTIVITY] week ending Nov. 8 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Raised two more Xen related cards, [STR-19] and [STR-20] [STR-19] <https://projects.linaro.org/browse/STR-19> [STR-20] <https://projects.linaro.org/browse/STR-20> VirtIO Portability Demo ([STR-13]) ================================== - syned on current status of demo and discussed options - attempted to record the KVM demo, killed my MachiatoBin with load - another go on Monday [STR-13] <https://projects.linaro.org/browse/STR-13> QEMU Support for Xen ([STR-20]) =============================== - posted [RFC PATCH 00/15] Xen guest-loader and arm64 build fixes/enhancements Message-Id: <20201105175153.30489-1-alex.bennee(a)linaro.org> [STR-20] <https://projects.linaro.org/browse/STR-20> Upstream Work ([QEMU-109]) ========================== - finally got round to looking at rth's [128 bit softfloat proposal] - posted [PATCH v2] docs: add some notes on the sbsa-ref machine Message-Id: <20201104165254.24822-1-alex.bennee(a)linaro.org> [128 bit softfloat proposal] <https://github.com/stsquad/qemu/tree/review/rth-sf128> Other ===== - TSC Review prep - Annual Review Completed Reviews [0/0] ======================= Absences ======== - Home schooling Current Review Queue ==================== * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v3 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20201014052140.1146924-1-crosa(a)redhat.com> Added: <2020-10-14 Wed> -- Alex Bennée

5 years, 1 month

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[ACTIVITY] report week ending 6 Nov

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + usual release cycle work + Our Coverity-Scan issues had been left untended a bit too long: went through them doing triage, reporting them back to patch submitters, and writing a few fixes for some of the easy ones + That took me down a rabbit-hole of fixing some issues with our sparc64 usermode emulation so I could demonstrate that the coverity fixes hadn't broken anything... thanks -- PMM

5 years, 1 month

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GDB: status of branch tracing on arm processors using coresight etm traces

by Zied Guermazi

hi all I am announcing updates in the implementation of branch tracing using coresight etm in GDB. in this update, functions and instruction history are running successfully on single threaded applications. reverse debugging is basically working with the limitation that sometimes cspr register (register 25) is required but current implementation does not provide it. the feature requires linux kernel v 4.19 or higher with manual etm sink setup. 5.9.1 or higher for automatic sink selection. GDB gdb.btrace test suite was adapted to run on arm processors. here is the summary of the gdb.btrace test results executed on an STM32MP157 (ARM cortex A7) with Linux kernel 5.9.1 === gdb Summary === # of expected passes 390 # of unexpected failures 119 # of unsupported tests 4 following tests are 100% successful: - buffer-size - enable - instruction_history - function_call_history - data - delta - cpu - gcore - record_goto-step - dlopen - vdso - segv GDB source code is available on https://github.com/gzied/binutils-gdb/tree/gdb_arm_coresight many thanks to GDB and linaro communities for their support Kind Regards Zied Guermazi

5 years, 1 month

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Re: GDB: etm traces decoding and breakpoints for arm targets

by Zied Guermazi

hi Thanks Mike for your support, it was very helpful. to put everything together, on arm, gdb inserts a sw breakpoint by patching the code with an undefined instruction ( see comments in arm-tdep.c line7687) when a breakpoint is hit, an exception number 9 "Undefined Instruction exception" is raised and a branch packet with this info is generated in etm traces, the trap is get handled by the kernel and it sends the appropriate signal to gdb process. when the user continues the execution, gdb patches back the code and executes the instruction. this leads to the instruction traced twice with an exception in between, the same happens for next executed instruction here is the log of decoded packets [btrace] [ftrace] update insn: fun = main, file = ./function_call_history.c, level = 0, insn = [1; 2) cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE */<= first execution attempt that raises an undefined instruction exception/* trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400534 end addr = 0x400536 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 [btrace] [ftrace] update insn: fun = main, file = ./function_call_history.c, level = 0, insn = [1; 3) cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION */<= the exception is traced/* trace_chan_id: 18 exception number: 9 */<= undefined instruction exception/* cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE */<= execution of the original instruction/* trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400534 end addr = 0x400536 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 as the code was changed during execution, it can not be reconstructed during traces decoding. in addition, and for tracing applications running on Linux, we are not interested in capturing raised exceptions, we can consider rolling back last instruction in ftraces. As this is not obvious, we can consider ignoring the repeated instruction as a workaround. for tracing bare metal software, we need to keep tracing exception, so we can have a flag for ignoring exceptions, and activate or dis-activate it according to the context. what do you think about it, shall I go for implementing it as described above? Kind Regards Zied Guermazi On 02.11.20 12:59, Mike Leach wrote: > Hi Zeid, > > On Sat, 31 Oct 2020 at 23:11, Zied Guermazi <zied.guermazi(a)trande.de> wrote: >> hi, >> >> while testing the implementation in gdb of branch tracing on arm >> processors using etm, I faced the the situation where a breakpoint was >> set, was hit and then the execution of the program was continued. While >> decoding generated traces, I got the address of the breakpoint >> (0x400552) executed twice, and then the following address (0x400554) >> also executed twice. the instruction at (0x400554) is a BL ( a function >> call) and the second execution corrupts the function history. >> >> here is a dump of generated trace elements >> >> >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400552 >> end addr = 0x400554 >> instructions count = 1 >> last_i_type: OCSD_INSTR_OTHER >> last_i_subtype: OCSD_S_INSTR_NONE >> last instruction was executed >> last instruction size: 2 >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400552 >> end addr = 0x400554 >> instructions count = 1 >> last_i_type: OCSD_INSTR_OTHER >> last_i_subtype: OCSD_S_INSTR_NONE >> last instruction was executed >> last instruction size: 2 >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400554 >> end addr = 0x400558 >> instructions count = 1 >> last_i_type: OCSD_INSTR_BR >> last_i_subtype: OCSD_S_INSTR_BR_LINK >> last instruction was executed >> last instruction size: 4 >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400554 >> end addr = 0x400558 >> instructions count = 1 >> last_i_type: OCSD_INSTR_BR >> last_i_subtype: OCSD_S_INSTR_BR_LINK >> last instruction was executed >> last instruction size: 4 >> >> the explanation I have for this behavior is that : >> >> -when setting the software breakpoint, the memory content of the >> instruction (at 0x400552) was altered to the instruction BKPT, >> >> -when the breakpoint was hit, the original opcode was set at (0x400552) >> and a BKPT was set to the next instruction address (0x400554), then the >> execution was continued >> >> -when the second breakpoint (0x400554) was hit, the a BKPT opcode was >> set at (0x400552) and the original opcode was set at (0x400554) then the >> execution was continued >> >> I am using the function "int target_read_code (CORE_ADDR memaddr, >> gdb_byte *myaddr, ssize_t len)" to give program memory content to the >> decoder. so the collected etm traces are correct, but, as memory was >> altered in between, the decoder is "cheated". >> >> I need to identify the re-execution of code due to breakpoint handling, >> and roll back its impact on etm decoding. >> >> is there a mean to get the actual content of program memory including >> patched addresses? >> >> is there a means of getting the history of patched addresses during the >> debugging of a program? >> >> what is the type and subtype of a BKPT instruction in a decoded trace >> elements? >> > I can only really comment on this question. The type / subtype > information in the output from the decoder is generated from the > decoder walking the memory image of the executed trace - not from the > trace packets themselves. > The decoder classifies instructions according to how they will affect > trace flow with the "other" category being set for the majority of > instructions. The categories are: other, branch, indirect branch, ISB > / DSB / DMB / WFI / WFE. > These are important in program flow trace (PTM 1.x, ETM 4.x) as these > determine which instruction we attach the E/N atoms to. BKPT will be > classified as "other", if it is seen, as it has no effect on normal > program flow. It will cause an exception which has a specific trace > packet format. > > Regards > > Mike > > >> do you have any other idea for handling this situation? >> >> >> I am attaching the source code of the program as well as the >> disassembled binary. the code was compiled as an application running on >> linux on an ARMv7 A (STM32MP157 SoC). the breakpoint was set at line 43 >> in the source code (line 238 in the disassembled code) >> >> >> Kind Regards >> >> Zied Guermazi >> >> _______________________________________________ >> CoreSight mailing list >> CoreSight(a)lists.linaro.org >> https://lists.linaro.org/mailman/listinfo/coresight > >

5 years, 1 month

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GDB: etm traces decoding and breakpoints for arm targets

by Zied Guermazi

hi, while testing the implementation in gdb of branch tracing on arm processors using etm, I faced the the situation where a breakpoint was set, was hit and then the execution of the program was continued. While decoding generated traces, I got the address of the breakpoint (0x400552) executed twice, and then the following address (0x400554) also executed twice. the instruction at (0x400554) is a BL ( a function call) and the second execution corrupts the function history. here is a dump of generated trace elements --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400552 end addr = 0x400554 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400552 end addr = 0x400554 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400554 end addr = 0x400558 instructions count = 1 last_i_type: OCSD_INSTR_BR last_i_subtype: OCSD_S_INSTR_BR_LINK last instruction was executed last instruction size: 4 --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400554 end addr = 0x400558 instructions count = 1 last_i_type: OCSD_INSTR_BR last_i_subtype: OCSD_S_INSTR_BR_LINK last instruction was executed last instruction size: 4 the explanation I have for this behavior is that : -when setting the software breakpoint, the memory content of the instruction (at 0x400552) was altered to the instruction BKPT, -when the breakpoint was hit, the original opcode was set at (0x400552) and a BKPT was set to the next instruction address (0x400554), then the execution was continued -when the second breakpoint (0x400554) was hit, the a BKPT opcode was set at (0x400552) and the original opcode was set at (0x400554) then the execution was continued I am using the function "int target_read_code (CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)" to give program memory content to the decoder. so the collected etm traces are correct, but, as memory was altered in between, the decoder is "cheated". I need to identify the re-execution of code due to breakpoint handling, and roll back its impact on etm decoding. is there a mean to get the actual content of program memory including patched addresses? is there a means of getting the history of patched addresses during the debugging of a program? what is the type and subtype of a BKPT instruction in a decoded trace elements? do you have any other idea for handling this situation? I am attaching the source code of the program as well as the disassembled binary. the code was compiled as an application running on linux on an ARMv7 A (STM32MP157 SoC). the breakpoint was set at line 43 in the source code (line 238 in the disassembled code) Kind Regards Zied Guermazi

5 years, 1 month

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[ACTIVITY] report week ending 30 Oct

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + more code review and assembly of the last pull request for softfreeze for QEMU 5.2 + noticed that our AArch32 Neon emulation doesn't work on big-endian hosts. RTH fixed most of this and I wrote a couple of patches to fix bugs in some insns that were only noticeable once we got out of the "anything working on vectors is broken" state :-) + looked at trying to get our documentation to build with Sphinx 3, which has made some annoying incompatible changes to the markup it accepts * VIRT-364 [QEMU support for ARMv8.1-M extensions] + started implementation of new insns VSCCLRM, CLRM, and the new FP sysregs accessed via VLDR/VSTR KVM Forum (virtual conference) was this week. Some interesting talks: * Will Deacon on what Google is doing to introduce KVM into Android * Marc Zyngier/Christoffer Dall on a virtual-only interrupt controller that's less of a big lump of code to put on a security boundary than a full-on GIC * Salil Mehta on the current problems with doing Arm vCPU hotplug in KVM thanks -- PMM

5 years, 1 month

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[ACTIVITY] week ending Nov. 1 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Stratos sync call, discussion on AGL demo - Google sync call - Created a first cut of additional Xen work cards under [STR-16] [STR-16] <https://projects.linaro.org/browse/STR-16> VirtIO Portability Demo ([STR-13]) ================================== - Created a [branch with the experimental ioreq (virtio-mmio) support] - developing understanding of the ioreq piece - posted [PATCH] meson.build: fix building of Xen support for aarch64 Message-Id: <20201028174406.23424-1-alex.bennee(a)linaro.org> - continued work and expanded into [branch to clean-up and add "virt" machine] [STR-13] <https://projects.linaro.org/browse/STR-13> [branch with the experimental ioreq (virtio-mmio) support] <http://git.linaro.org/people/alex.bennee/linux.git/shortlog/refs/heads/expe…> [branch to clean-up and add "virt" machine] <https://github.com/stsquad/qemu/tree/xen/add-xen-virt-machine> Upstream Work ([QEMU-109]) ========================== - posted [PULL 0/8] testing and misc (gitdm, gitlab, docker, make) Message-Id: <20201027095938.28673-1-alex.bennee(a)linaro.org> [QEMU-109] <https://projects.linaro.org/browse/QEMU-109> Other ===== - KVM Forum 2020 Completed Reviews [2/2] ======================= [PATCH 0/2] tcg: optimize across branches Message-Id: <20201013222330.173525-1-richard.henderson(a)linaro.org> [PATCH 00/15] remove bios_name variable Message-Id: <20201026143028.3034018-8-pbonzini(a)redhat.com> Absences ======== - Welsh lockdown next week - Children at home Current Review Queue ==================== * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v3 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20201014052140.1146924-1-crosa(a)redhat.com> Added: <2020-10-14 Wed> -- Alex Bennée

5 years, 1 month

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Please make clang-cmake-armv7-selfhost-neon and clang-cmake-thumbv7-full-sh green

by Galina Kistanova

5 years, 1 month

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[ACTIVITY] 26-30 October 2020

by Christophe Lyon

* 2 days off == Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - PR96767: patch accepted - PR96770: patch accepted - patch for C++ thunks with -mpure-code and cortex-m0: iterating, almost OK - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers - added monitoring for disk space on dev machines == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

5 years, 1 month

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[ACTIVITY] week ending 25 Oct 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] More time than I expected on float128_muladd, adjusting the codebase to share code with float64_muladd. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Posted v12, adjusting one of the smoke tests vs a distro linker bug (fixed in mainline). r~

5 years, 1 month

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[ACTIVITY] week ending Oct. 25 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO RPMB ([STR-5]) ===================== - Synced with with Ulf/Illias on enhancements for eMMC stacks - need to support 512 frames somehow for the CSD, everything else should be fine [STR-5] <https://projects.linaro.org/browse/STR-5> VirtIO Portability Demo ([STR-13]) ================================== - More work on trying to get Xen working on MB - more failures, this time GIC related. Might just stick to KVM - Created a [branch with the experimental ioreq (virtio-mmio) support] - Got Virgl based acceleration working on both TCG and KVM - so now fast graphics! - posted [PATCH v1 0/4] add guest-loader (for direct Xen boot) Message-Id: <20201021170842.25762-1-alex.bennee(a)linaro.org> [STR-13] <https://projects.linaro.org/browse/STR-13> [branch with the experimental ioreq (virtio-mmio) support] <http://git.linaro.org/people/alex.bennee/linux.git/shortlog/refs/heads/expe…> Upstream Work ([QEMU-109]) ========================== - Some discussion on converting the final bits of 96/128 bit softfloat - posted [RFC PATCH 0/8] fpu: experimental conversion of float128_addsub Message-Id: <20201020163738.27700-1-alex.bennee(a)linaro.org> - partial reviewed [RFC PATCH 00/15] softfloat: alternate conversion of float128_addsub Message-Id: <20201021045149.1582203-1-richard.henderson(a)linaro.org> - posted [PATCH v1 0/6] testing/next (gitdm, acceptance, docker, gitlab) Message-Id: <20201021163136.27324-5-alex.bennee(a)linaro.org> Other ===== - reclaiming space for my gmail (98.5% used!) Completed Reviews [1/1] ======================= [PATCH 0/2] tcg: optimize across branches Message-Id: <20201013222330.173525-1-richard.henderson(a)linaro.org> Absences ======== - Welsh lockdown next week - Children at home Current Review Queue ==================== * [PATCH v3 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20201014052140.1146924-1-crosa(a)redhat.com> Added: <2020-10-14 Wed> * [PATCH v6 0/5] Enable plugin support on msys2/mingw Message-Id: <20201013002806.1447-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> * [PATCH v7 0/4] Improve cirrus msys2 Message-Id: <20201012233740.190-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> * [PATCH RFC 00/22] Support of Virtual CPU Hotplug for ARMv8 Arch Message-Id: <20200613213629.21984-1-salil.mehta(a)huawei.com> Added: <2020-09-23 Wed> -- Alex Bennée

5 years, 1 month

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[ACTIVITY] 19-23 October 2020

by Christophe Lyon

* 2 days off == Progress == * GCC upstream validation: - identified several regressions, but they had already been reported * GCC - PR96767: no feedback - PR96770: no feedback - patch for C++ thunks with -mpure-code and cortex-m0: handling further feedback - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

5 years, 1 month

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Toolchain for cross compiling

by Suresh Nulu

Hi, I am new to toolchains. I would like to know information on building toolchains for different architectures. My objective is to build a cross compiling toolchain for AARCH64 BE target on the RHEL7.6 build system. It would be great if you can give me pointers on how to compile toolchains. Do we have any Wiki pages on building linaro toolchains for different architectures? Appreciate your help. Regards Suresh

5 years, 2 months

2
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[ACTIVITY] 12-16 October 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions - committed minor cleanup fixes - fixed broken trunk build with gcc-4.8 * GCC - PR96767: no feedback - PR96770: no feedback - patch for C++ thunks with -mpure-code and cortex-m0: sent updated patch - Neon intrinsics: sent patch to implement vceqq, vceqz and vceqzq for p64. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

5 years, 2 months

1
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[ACTIVITY] week ending 11 Oct 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] Completed capstone update. Flushed tcg patch queue. Fixed a decodetree issue for pmm. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Refreshed BTI linux-user patch set. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Fixed a couple of MTE bugs reported by Arm. r~

5 years, 2 months

1
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[ACTIVITY] week ending Oct. 11 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO Portability Demo ([STR-13]) ================================== - sync up discussion - posted [RFC PATCH 0/4] generic loader FDT support (for direct Xen boot) Message-Id: <20201009170742.23695-1-alex.bennee(a)linaro.org> - now GICv3 and GICv2 boot fine under TCG, pointing finger at EFI/Grub [STR-13] <https://projects.linaro.org/browse/STR-13> Upstream Work ([QEMU-109]) ========================== - posted [PATCH v1 00/22] testing and plugin fixes with gitdm updates (pre PR) Message-Id: <20201007160038.26953-1-alex.bennee(a)linaro.org> - posted [PULL 00/22] acceptance regressions, testing, gitdm, plugins Message-Id: <20201009163147.28512-1-alex.bennee(a)linaro.org> Other ===== - spent some time on JIRA cleanup for PoR - preparation for TSC health check call Completed Reviews [3/3] ======================= [PATCH v3 0/6] Enable plugin support on msys2/mingw Message-Id: <20201001163429.1348-1-luoyonggang(a)gmail.com> - CLOSING NOTE [2020-10-06 Tue 12:37] A few rough edges but seems to be on track, merged first few patches. Added: <2020-10-01 Thu> [PATCH 00/12] contrib/gitdm: First round of updates Message-Id: <20201006160653.2391972-1-f4bug(a)amsat.org> - CLOSING NOTE [2020-10-10 Sat 17:00] Merged Added: <2020-10-06 Tue> [PATCH 0/2] .mailmap: Fixes since v5.1 Message-Id: <20201004172644.2027440-1-f4bug(a)amsat.org> - CLOSING NOTE [2020-10-10 Sat 17:00] Merged Added: <2020-10-04 Sun> Absences ======== Current Review Queue ==================== * [PATCH RFC 00/22] Support of Virtual CPU Hotplug for ARMv8 Arch Message-Id: <20200613213629.21984-1-salil.mehta(a)huawei.com> Added: <2020-09-23 Wed> * [RFC PATCH 0/3] Automatically convert configure options to meson build options Message-Id: <20200913100534.22084-1-pbonzini(a)redhat.com> Added: <2020-09-13 Sun> * [PATCH 0/6] misc: Some inclusive terminology changes Message-Id: <20200910070131.435543-1-philmd(a)redhat.com> Added: <2020-09-10 Thu> * [PATCH 00/43] tcg patch queue Message-Id: <20200909001647.532249-1-richard.henderson(a)linaro.org> Added: <2020-09-09 Wed> -- Alex Bennée

5 years, 2 months

1
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[ACTIVITY] report week ending 9 Oct

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + another round of code review and target-arm queue wrangling + found and fixed an edge-case bug in setting Q flag in SMLAD insn + fixed a GICv3 emulation bug where we didn't ever raise maintenance interrupts * VIRT-364 [QEMU support for ARMv8.1-M extensions] + went through Arm ARM and identified exactly what the "v8.1M changes which aren't part of a named architectural feature" are (for QEMU-409 subtask) + implemented some parts of NOCP handling that were left as TODO comments for being v8.1M-specific + implemented conditional-select insns (CSEL, CSINC, CSINV, CSNEG) + implemented low-overhead-loops and branch-future (in the 'trivial' don't-cache-anything way the architecture permits) thanks -- PMM

5 years, 2 months

1
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