Progress:
* VIRT-65 [QEMU upstream maintainership]
- more work on rST doc conversion. I've started in on converting the
documentation that we auto-generate from doc comments in json files
(this covers QEMU's QMP protocol and a similar protocol for the
guest-agent).
I now have something that is basically the right shape and correctly
handles 'Command' and 'Object' (with 'Enum' and Alternate' and some
other corner cases still to do). Might be able to send a patchset out
next week with luck. This is I think the last major obstacle to the
rST conversion -- once it's done the rest is just simple-but-tedious
conversion of the remaining document files.
- code review:
+ aspeed 'misc fixes and extensions' patchset
+ "Stop wrongly programming GICR_PENDBASER.PTZ bit" bugfix patch
+ KVM 'adjust virtual time when VM starts/stops' patchset
+ last few unreviewed patches in RTH's VHE patchset respin
-- PMM
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: fixed bugs found when
running the testsuite with the new option activated. Adding warnings
to help understand potential placement changes.
* GCC:
* GCC-9: continued work for validation of -mpure-code on v6m: the
patch applies cleanly in the branch, but there are unexpected failures
compared to trunk. Debugging.
* GCC upstream validation:
- reported a couple of failures/regressions
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* GCC-9: continue work for validation of -mpure-code on v6m
== Progress ==
* Updating lldb for the latest Morello architecture changes
* Started running the tests for llvm 10.0.0-rc1
== Plan ==
* Check up on the release
* More Morello
[LLD]
Fixed interworking problem causing Thumb2 kernel not to
Some diagnosis of LLD problem when .ctor and .init_array initialisers are used.
[LLVM-MC]
Upstream reviews for some methods to avoid llvm-mc making symbols
inter-positionable that the code generator has assumed are not.
[Morello]
reviews.
[Other]
Clean up my Jira tickets so that they can be passed on or closed.
This is my last week as a Linaro assignee, will be going back to the
Arm as of next week. I've really enjoyed my time here, thank you for
having me.
Buildbots, busy week that took up most of spare time
- deploying timezone fix to containers
- a couple of weekend patches that broke Arm and AArch64 bisected and
followed up.
- difficult to track down stage-2 failure that was difficult to work
out whether there was a bug in clang, or a code-gen failure in the
backend, also made it harder to bisect. Turned out that it had caused
more easy to bisect failures in other projects and by the time I'd
found the patch it had been fixed.
[ClangBuiltLinux]
LLD's simplified interworking looks to be insufficient for the linux
kernel thumb-2 build. Got agreement with upstream on how to proceed.
Have a patch ready to send upstream.
A small amount of upstream review and bisecting some Linaro CI build
failure for the -fpatchable-functions feature in Clang-10. Looks to
have been resolved.
[VIRT-327 # Richard's upstream QEMU work ]
* tcg patch queue flush, including some VHE prereqs.
* target/hppa patch queue flushing.
* combined the two in-flight avr patch sets, hoping
to move that project to completion.
* patch review.
* target/s390x local variable "leak" fix,
to satisfy a static analyzer.
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
* started rebasing, and addressing the collected
comments from v4 in December.
r~
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: debugging
* GCC:
* GCC-9: continued work for validation of -mpure-code on v6m: local
newlib/crt0 patches, patched simulator. Running various validation
configurations
* GCC upstream validation:
- reported a couple of failures/regressions
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* GCC-9: continue work for validation of -mpure-code on v6m
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ RTH's bug fix for the PAuth ComputePAC operation
+ patchset adding DMA support for Exynos4210 UARTs
- small patchset documenting the right way to conditionally run
expensive computations that are only needed for trace event output,
and updating a handful of places that used an older (worse) method
- more QEMU documentation conversion to rST; in particular wrote a
Sphinx 'hxtool' extension to handle pulling out fragments of documentation
from QEMU's '.hx' files which define and document command line options
thanks
-- PMM
hiI am progressing in the implementation of the proposal "GDB process record and replay with ARM Coresight" https://lists.linaro.org/pipermail/coresight/2019-July/003021.html
so far I was able to use perf events to configure the drivers for etm and collect the traces. the code was tested successfully on an STM32MP157A discovery kit (arm v7). and I can collect the traces from the perf mmapped aux area.
For parsing them I needed to gather information about the cpu and etm registers. those are available in the events of type PERF_RECORD_AUXTRACE_INFO in the priv section. priv is a kind of "opaque" data structure where the layout is depending on the perf pmu drivers. the implementation of perf tool gives a good example to follow. I needed also to make a wrapper around opencsd library and again perf was offering a good example to follow.
those are good reasons to think about factoring out the functionality of parsing etm traces on linux system in a dedicated library that can be reused by other software, a kind of libcoresightperf.is there any plan or ongoing activities for such a library?
Kind RegardsZied Guermazi
== Progress ==
* More EuroLLVM submissions reviews
* More investigations into Morello bare metal debugging
* Started looking into updating lldb for the latest Morello architecture
changes
* Asked Adhemerval to look into PR44157
== Plan ==
* More Morello
* Keep an eye out for 10.0.0 - rc1
[VIRT-327 # Richard's upstream QEMU work ]
* Implement x86_64-linux-user vsyscall page,
which should keep Peter's pre-merge testing working.
* Another tcg queue pull without the bits that depend
on the vsyscall implementation above.
* Posted v2 of some fixes to -accel option processing.
* Posted v2 of some fixes to target/arm syn data syndrome bits.
* Wrote some test cases for a target/arm pauth sbox fix.
* Investigated a fix for memory layout of -static-pie binaries.
* Random patch review.
r~
QEMU Tooling ([VIRT-252])
=========================
Extend gdbstub for SVE ([VIRT-281])
- posted [PATCH v5 00/22] gdbstub refactor and SVE support (+check-tcg
tweaks) Message-Id: <20200114150953.27659-3-alex.bennee(a)linaro.org>
[VIRT-281] <https://projects.linaro.org/browse/VIRT-281>
Upstream Work ([VIRT-109])
==========================
- played with [for-5.0 PATCH 00/11] Support for reverse debugging with
GDB Message-Id:
<157709434917.12933.4351155074716553976.stgit@pasha-Precision-3630-Tower>
- still broken but could be build stability
- while reviewing vsyscall patches ran into qemu-x86_64, buster
/sbin/ldconfig and setup_arg_pages (a mind dump) Message-Id:
<874kwukmxr.fsf(a)linaro.org>
- posted [qemu-web PATCH] documentation: update links to readthedocs
Message-Id: <20200113103550.1133-1-alex.bennee(a)linaro.org>
- we successfully recovered the qemu project name for rtd
[VIRT-109] <https://projects.linaro.org/browse/VIRT-109>
Completed Reviews [3/3]
=======================
[for-5.0 PATCH 00/11] Support for reverse debugging with GDB
Message-Id: <157709434917.12933.4351155074716553976.stgit@pasha-Precision-3630-Tower>
- CLOSING NOTE [2020-01-13 Mon 18:00]
Introduces some regressions into check-block that need to be fixed
first.
Added: <2020-01-06 Mon>
[PATCH 0/4] migration: Replace gemu_log with qemu_log
Message-Id: <20200114030138.260347-1-jkz(a)google.com>
[PATCH 0/3] linux-user: Implement x86_64 vsyscalls
Message-Id: <20200114210921.11216-4-richard.henderson(a)linaro.org>
Current Review Queue
====================
* [PATCH v2 0/7] configure: Improve PIE and other linkage
Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org>
Added: <2020-01-06 Mon>
* {RFC PATCH v3 000/132} Proof of concept for Meson integration
Message-Id: <1576155176-2464-1-git-send-email-pbonzini(a)redhat.com>
Added: <2019-12-12 Thu>
* {PATCH 0/2} tests/acceptance: Add boot vmlinux test
Message-Id: <20191206140012.15517-1-wainersm(a)redhat.com>
Added: <2019-12-06 Fri>
* {RFC PATCH 00/10} hw/avr: Introduce the Arduino board
Message-Id: <20191128015030.27543-1-f4bug(a)amsat.org>
Added: <2019-11-28 Thu>
--
Alex Bennée
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: found problems in the
testsuite when the flag is activated by default
* GCC:
- trying to find a way to add run more validation of -mpure-code on
v6m, to support a request to backport to gcc-9: need to patch newlib's
crt0.S which has some offending sequences
* GCC upstream validation:
- updated scripts to cope with the new git repo and release branches names
* misc:
- infra fixes / troubleshooting / reviews
- fixed problems with automatic bisection of gcc regressions
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* GCC-9: continue work for validation of -mpure-code on v6m
Morello
- Upstream LLD INPUT_SECTION_FLAGS that I implemented downstream.
Quite a few review comments to work through but I think I'm close to
getting something accepted. This will hopefully come in useful for LLD
with embedded systems.
- Wrote down some definitions for the new relocations.
LLD
- landed fix for clang-built-linux-812 linux allyesconfig problem.
- Quite a few upstream LLD and MC reviews
Other
Some research for the clang built linux conference.
== Progress ==
* Out of office for 2 days
* Reviewed EuroLLVM submissions
* A bit more investigation into Morello bare metal debugging
== Plan ==
* PR44157
* Morello bare metal debugging
Hello Linaro team,
I want to use your cross compiler version 6.3.1, but I miss the library
asound and its header (alsa/asoundlib.h)
What do I need to do to fix this ?
Best regards,
Markus Bollinger
Hi Ana,
I don't know anything about the POC myself, but I'm forwarding this so our
QEMU folks can answer.
Cheers,
Diana
---------- Forwarded message ---------
From: Ana Pazos <apazos(a)quicinc.com>
Date: Fri, 10 Jan 2020 at 19:08
Subject: about QEMU support for SVE2 POC
To: diana.picus(a)linaro.org <diana.picus(a)linaro.org>
Cc: Ana Pazos <apazos(a)quicinc.com>
Hello Diana,
We at Qualcomm are trying to find out the POC for QEMU support for SVE2.
We have been using QEMU with SVE support, and need to find out when SVE2
support will be added to QEMU.
I assume Linaro is involved in this task. Do you know the POC?
Thanks for the help!
Ana.
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: sent updated versions with
testcases and doc.
* GCC:
- trying to find a way to add run more validation of -mpure-code on
v6m, to support a request to backport to gcc-9
- proposal to implement LLVM's -arm-assume-misaligned-load-store
rejected by the community
* GCC upstream validation:
- reported/checked a few issues
* misc:
- infra fixes / troubleshooting / reviews
- investigating problems with automatic bisection of gcc regressions
- fixed a long-standing bug in proot
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
[VIRT-327 # Richard's upstream QEMU work ]
* TCG patch queue flush, including phase 1 increase for
number of mmu_idx, on which VHE is dependent.
* Random patch review.
* Capstone update.
* cputlb cleanup in prep for modeling ASIDs.
r~
