o LLVM
* Machine outliner:
- Debugging issue in LLVM bootstrap.
- Preparing BKK19 Hacking session presentation.
o Misc
* Various meetings and discussions.
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Picked up my partial patch set and started on it again.
It is improved by having done the pauth/bti/mte work.
But still a work in progress.
[VIRT-327 # Richard's upstream QEMU work ]
Version 3 of tcg/ppc vector instructions.
Reviewed target/rx v4.
Fixed thread=single expansion of casp after Alex did all the
hard work tracking down the kernel failure, and writing me a
test case.
Looking into the size of the softmmu tlb expansion. Current
thinking is to move tlb out of CPUArchState into a new struct
that precedes env, so that the tlb is at small negative offsets
from env, so that {mask, table} is loadable with LDP/LDRD.
r~
Upstream Work ([VIRT-109])
==========================
- posted some CI clean-ups for next 4.0-rc
- posted {PATCH v1 0/3 for 4.0} reduce timeouts on Travis
Message-Id: <20190319124800.7454-1-alex.bennee(a)linaro.org>
- posted {PATCH} .travis.yml: reduce number of targets built while
disabling things Message-Id:
<20190321124857.28132-1-alex.bennee(a)linaro.org>
- will send PR on Monday
- while testing {Qemu-devel} {PATCH 3/4} memory: introduce
memory_global_after_dirty_log_sync Message-Id:
<20180209104546.29401-4-pbonzini(a)redhat.com>
- discovered regression -cpu max -accel tcg,thread=single with
ARM64_LSE_ATOMICS kernel breaks
- this is likely due to different code paths for non-MTTCG atomics
- however attempts [to reproduce in linux-user] have so far drawn
a blank
- have notified rth who can hopefully find the problem
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[to reproduce in linux-user]
https://github.com/stsquad/qemu/tree/for-4.0/mttcg-and-lse-atomics
Other
=====
- more work on Connect presentation
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {Qemu-devel} {multiprocess RFC PATCH 00/37} Initial support of multi-process qemu
Message-Id: <20190307072025.8041-1-elena.ufimtseva(a)oracle.com>
* {Qemu-devel} {PATCH 0/6} Refine exec
Message-Id: <20190321082555.21118-1-richardw.yang(a)linux.intel.com>
* {PATCH v5 00/26} KVM: arm64: SVE guest support
Message-Id: <1553017938-710-1-git-send-email-Dave.Martin(a)arm.com>
* {PATCH v4 00/19} Acceptance Tests: target architecture support
Message-Id: <20190312121150.8638-1-crosa(a)redhat.com>
* {PATCH 0/5} travis-ci: Build EDK2 roms
Message-Id: <20190311003052.13778-1-philmd(a)redhat.com>
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ tagged rc0 for QEMU 4.0.0; various other release-ish work
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ more progress with FP support: lazy state saving and the vlldm/vlstm
insns now implemented. FP support is now feature-complete, though
some bugs likely remain to be fixed.
* A day or so taken up by move to a new desktop machine (but
builds should go faster now!)
NB: I'm not working on Wednesday or Friday next week.
thanks
-- PMM
== Progress ==
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- LLVM 8.0.0 is out!
* [Thumb GlobalISel] Bugfixes [LLVM-544]
- Patch for alignment issues ready to commit next week
- With the patch, we can build clang successfully, but it fails some
of its tests
- Investigated one of the tests, it's failing because we end up
representing 'true' as '-1'. Going to prepare a patch for that next
week
* IR SVE Reviews [LLVM-545]
- Reviewed D32530 - Scalable Vector IR Type
* Buildbot babysitting
- Reported some failures upstream
- Complained about non-deterministic libfuzzer tests
== Plan ==
* LLVM-544, LLVM-545
== Progress ==
* FDPIC
- Setting up new stm32f429-disc1 board. Still not working with recent kernel
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- added qemu as a toolchain component supported by ABE.
- merged tcwg_bmk branch into master
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs update
[LLVM-542] Compiling zephyr with clang
- Shared patches with Zephyr team lead, who has integrated them into a
private branch and has locally fixed some of the
incompatibilities/warnings
- Went through the Zephyr samples to get build instructions for the
ones compatible with Arm dev-boards.
[Intel-CET] patches to LLD (similar to BTI)
- Reviewed patches and made suggestion for an alternative design. Will
need to re-review the follow up this week.
[LLVM-523] .ARM.exidx redesign
- Responded to review comments, will need to ping again this week.
Linaro Connect
- Preparations for hack room
- Started on Presentation on cross compilation, need to finish slides this week.
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ]
Three versions posted, with good review on the crypto side.
Generalized our existing infrastructure to use crypto quality
numbers by default, and decent deterministic numbers when
given the -seed command-line argument. Converted our existing
hw random number devices; implemented the AA64 registers;
filled in the PPC64 stubs; implemented the X86 tcg insns.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed and revised some target/hppa patches from Sven.
Final pull request for hppa for 4.0.
Final pull request for decodetree.
Revised the tcg extract2 patch set; delay this for 4.1.
r~
== This Week ==
* PR88839 (8/10)
- Addressing suggestions by Richard.
- Patch works for all cases except for VNx2DI/VNx2DF modes. I have a
workaround for those two cases but investigating for a better
approach.
* Validation (1/10)
- Submitted patches to merge tcwg_gnu branch into master for jenkins-scripts/
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
Upstream Work ([VIRT-109])
==========================
- posted {PATCH} scripts/qemugdb: re-license timers.py to GPLv2 or
later Message-Id: <20190311165538.6623-1-alex.bennee(a)linaro.org>
- started discussion on the state of QEMU CI Message-Id:
<6D897F0B-D7A6-4A16-93E0-3F68FF53B0BE(a)euphon.net>
- looked at GitLab's runners as an CI scaling option
- looks like [arm64 support has somewhat stalled]
- spammed Peter with PRs for Tuesday's softfreeze
- posted {PULL 00/26} final testing updates for 4.0 Message-Id:
<20190312170931.25013-1-alex.bennee(a)linaro.org>
- including {PATCH v2 0/7} testing/next for softfreeze Message-Id:
<20190312105547.4755-1-alex.bennee(a)linaro.org>
- and {PATCH v4 00/21} final tcg tests for 4.0 Message-Id:
<20190312155947.14918-1-alex.bennee(a)linaro.org>
- posted {PULL 0/5} gitdm updates for 4.0 Message-Id:
<20190312193458.9171-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[arm64 support has somewhat stalled]
https://gitlab.com/gitlab-org/gitlab-runner/merge_requests/725
Other
=====
- more work on Connect presentation
Completed Reviews [1/1]
=======================
{Qemu-devel} {PATCH} ci: store Patchew configuration in the tree
Message-Id: <20190315091941.23669-1-pbonzini(a)redhat.com>
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {PATCH v4 00/19} Acceptance Tests: target architecture support
Message-Id: <20190312121150.8638-1-crosa(a)redhat.com>
* {PATCH 0/5} travis-ci: Build EDK2 roms
Message-Id: <20190311003052.13778-1-philmd(a)redhat.com>
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {PATCH+RFC 0/6} target/arm: Define cortex-a{73,75,76}
Message-Id: <20190223023957.18865-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH 0/9} tcg: Add tcg_gen_extract2_{i32,i64}
Message-Id: <20190307144126.31847-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {RFC PATCH 0/6} pc: Support firmware configuration with -blockdev
Message-Id: <20190225183757.27378-1-armbru(a)redhat.com>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ lots of code review and other work for softfreeze
+ tracked down the bug that caused regressions running UEFI in a
KVM guest with commit 823e1b3818f9b1, and sent out a fix
thanks
-- PMM
== Progress ==
* FDPIC
- Setting up new stm32f429-disc1 board. Boots OK with buildroot's
default 4.11 kernel. Boot seems to fail starting with 4.13 (recent
kernel needed to have FDPIC support)
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- adding qemu as a toolchain component supported by ABE. A bit
convoluted because of manifest handling.
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs
- add QEMU to list of components built by ABE
== Progress ==
* Out of office 1 day (Thursday)
* [Thumb GlobalISel] Bugfixes [LLVM-544]
- The test-suite compiles and executes without failures (with
fallback to DAG ISel)
- We get some bus errors in the selfhost, which are due to unaligned
64-bit stores. Apparently when alignment checks were introduced in the
legalizer, they were only used for types < 32 bits. Currently testing
a patch to fix this oversight.
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- rc5 looks good on AArch64, ARM is still in progress (waited for LSS-570)
== Plan ==
* Wrap up LLVM-544
* Upload rc5 when ARM is ready
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Posted v4, with system mode only.
[VIRT-298 # ARMv8.4-CondM, Condition flag manipulation ]
[VIRT-329 # ARMv8.5-CondM, Condition flag manipulation ]
[VIRT-337 # ARMv8.0-SB, Speculation Barrier ]
[VIRT-338 # ARMv8.0-PredInv, Prediction Invalidation ]
[VIRT-330 # ARMv8.5-FRINT, Floating-point to integer ]
All upstream.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390x vector patch set 3.
Reviewed renesas rx patch set 3.
Posted some patches and thoughts for
https://bugs.linaro.org/show_bug.cgi?id=4274
Implemented extract2 as a tcg opcode.
Minor hppa bug fixes.
Lots more work on decodetree and A32+T32+T16 conversion.
r~
- Intel CET review (Related to BTI support in LLD), raised issue of
multiple PT_NOTE sections one per alignment
https://reviews.llvm.org/D59120 , commented on command line options.
- LLVM-523 redesigned the LLD handling of ARM exidx sections to
centralise more of the Arm specific implementation details in one
place. Hope to post upstream to get some movement on the review to add
missing .ARM.exidx sections for chrome OS team.
- LLVM-542 Managed to build most of the Zephyr examples for clang,
shared patches to do so with zephyr tech lead.
- Some research for some ABI topics.
- Some thoughts for Linaro connect activities, started team calendar.
Next week:
- Start on my connect presentation
o LLVM
* Machine outliner:
- Stack alignment and refactoring.
- Start to prepare BKK19 talk
* Bots babysitting
* Built 8.0.0-rc4 binaries for x86 and ARM, got issues to start the job on D05
o Misc
* Completed BKK19 and EuroLLVM trips.
* Various meetings and discussions.
== Progress ==
* FDPIC
- (GNU-411) GDB: debugging problems with FDPIC support. Working on
setup of an stm32 board.
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- debugging new benchmarking round-robin jobs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs
- add QEMU to list of components built by ABE
Reply
Forward
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ code review
- add watchdog device to stellaris boards
- bcm2836 "local timer" device
- RTH's rolled-up patchset for SB, PredInv, CondM, FRINT extensions
- Eric's patchset to allow the 'virt' board to have more than 255GB of RAM
- a patchset to add a "generic nommu" board for NiosII
+ assembled a target-arm pull request for softfreeze
+ fixed some minor issues with the "build sphinx docs" patches,
and got them into master (and then fixed some more minor issues...)
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ progress on M-profile floating point:
- finished first draft of changes to exception handling code
- this is now on hold as we are into softfreeze for QEMU 4.0 and other
work for that release will take priority for the next few weeks
thanks
-- PMM
== This Week ==
* PR88839 - Poor implementation of blend like permutes (4/10)
- Addressing suggestions by Richard on patch
* GCC vectorizer (2/10)
- Background reading
* Validation (1/10)
- Added more bootstrap configs for tcwg_gnu job
- Committed patch to abe to enable bootstrap implicitly when buildconfig is set.
- Started tracking for tcwg_gnu ci job (init_configuration == false).
* Public holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
o LLVM
* Back to machine outliner after vacation
- Rebased on upstream master branch
- Working on stack alignment and refactoring.
o Misc
* Preparing BKK19 and EuroLLVM trips.
* Various meetings and discussions.
* PR88838
- I have a patch which solves this.
* adds iv in Pmode but compare_type in 32bit
- It exposes a latent bug in fwprop in regression testing
- Looking into it
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
Progress:
[VIRT-274 # ARMv8.2-FHM, Floating-point multiplication variant ]
Now upstream.
[VIRT-298 # ARMv8.4-CondM, Condition flag manipulation ]
[VIRT-329 # ARMv8.5-CondM, Condition flag manipulation ]
[VIRT-337 # ARMv8.0-SB, Speculation Barrier ]
[VIRT-338 # ARMv8.0-PredInv, Prediction Invalidation ]
[VIRT-330 # ARMv8.5-FRINT, Floating-point to integer ]
Posted an omnibus of SB+PredInv+CondM+FRINT that I have
labeled "v3", as 3 > any individual revision previously used.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390x vector patch set v2.
Implemented pattern groups in decodetree.
Prototyped A32 conversion to decodetree;
started a second revision that incorporates T32.
Started looking at
https://bugs.linaro.org/show_bug.cgi?id=4274
I can swizzle things around by changing the group name from
"cp_regs" to the predefined "system", but somehow those regs
are *also* registered with "general". Which means the
undesired behaviour by which "info regs" prints all of the
system registers still exists.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ upstream code review and pull request handling
+ respin of patchset to enable building our Sphinx RST documentation
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ progress on M-profile floating point:
- have written code to handle the smaller parts of the feature
(insn decode, registers, etc)
- started on changes to exception handling
- lazy save/restore still to do after that
* a lot of admin/meeting stuff this week
* softfreeze now less than two weeks away, need to
focus on what needs to be done before then...
thanks
-- PMM
