[LLVM-542] Compiling zephyr with clang
- Shared patches with Zephyr team lead, who has integrated them into a
private branch and has locally fixed some of the
incompatibilities/warnings
- Went through the Zephyr samples to get build instructions for the
ones compatible with Arm dev-boards.
[Intel-CET] patches to LLD (similar to BTI)
- Reviewed patches and made suggestion for an alternative design. Will
need to re-review the follow up this week.
[LLVM-523] .ARM.exidx redesign
- Responded to review comments, will need to ping again this week.
Linaro Connect
- Preparations for hack room
- Started on Presentation on cross compilation, need to finish slides this week.
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ]
Three versions posted, with good review on the crypto side.
Generalized our existing infrastructure to use crypto quality
numbers by default, and decent deterministic numbers when
given the -seed command-line argument. Converted our existing
hw random number devices; implemented the AA64 registers;
filled in the PPC64 stubs; implemented the X86 tcg insns.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed and revised some target/hppa patches from Sven.
Final pull request for hppa for 4.0.
Final pull request for decodetree.
Revised the tcg extract2 patch set; delay this for 4.1.
r~
== This Week ==
* PR88839 (8/10)
- Addressing suggestions by Richard.
- Patch works for all cases except for VNx2DI/VNx2DF modes. I have a
workaround for those two cases but investigating for a better
approach.
* Validation (1/10)
- Submitted patches to merge tcwg_gnu branch into master for jenkins-scripts/
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
Upstream Work ([VIRT-109])
==========================
- posted {PATCH} scripts/qemugdb: re-license timers.py to GPLv2 or
later Message-Id: <20190311165538.6623-1-alex.bennee(a)linaro.org>
- started discussion on the state of QEMU CI Message-Id:
<6D897F0B-D7A6-4A16-93E0-3F68FF53B0BE(a)euphon.net>
- looked at GitLab's runners as an CI scaling option
- looks like [arm64 support has somewhat stalled]
- spammed Peter with PRs for Tuesday's softfreeze
- posted {PULL 00/26} final testing updates for 4.0 Message-Id:
<20190312170931.25013-1-alex.bennee(a)linaro.org>
- including {PATCH v2 0/7} testing/next for softfreeze Message-Id:
<20190312105547.4755-1-alex.bennee(a)linaro.org>
- and {PATCH v4 00/21} final tcg tests for 4.0 Message-Id:
<20190312155947.14918-1-alex.bennee(a)linaro.org>
- posted {PULL 0/5} gitdm updates for 4.0 Message-Id:
<20190312193458.9171-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[arm64 support has somewhat stalled]
https://gitlab.com/gitlab-org/gitlab-runner/merge_requests/725
Other
=====
- more work on Connect presentation
Completed Reviews [1/1]
=======================
{Qemu-devel} {PATCH} ci: store Patchew configuration in the tree
Message-Id: <20190315091941.23669-1-pbonzini(a)redhat.com>
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {PATCH v4 00/19} Acceptance Tests: target architecture support
Message-Id: <20190312121150.8638-1-crosa(a)redhat.com>
* {PATCH 0/5} travis-ci: Build EDK2 roms
Message-Id: <20190311003052.13778-1-philmd(a)redhat.com>
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {PATCH+RFC 0/6} target/arm: Define cortex-a{73,75,76}
Message-Id: <20190223023957.18865-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH 0/9} tcg: Add tcg_gen_extract2_{i32,i64}
Message-Id: <20190307144126.31847-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {RFC PATCH 0/6} pc: Support firmware configuration with -blockdev
Message-Id: <20190225183757.27378-1-armbru(a)redhat.com>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ lots of code review and other work for softfreeze
+ tracked down the bug that caused regressions running UEFI in a
KVM guest with commit 823e1b3818f9b1, and sent out a fix
thanks
-- PMM
== Progress ==
* FDPIC
- Setting up new stm32f429-disc1 board. Boots OK with buildroot's
default 4.11 kernel. Boot seems to fail starting with 4.13 (recent
kernel needed to have FDPIC support)
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- adding qemu as a toolchain component supported by ABE. A bit
convoluted because of manifest handling.
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs
- add QEMU to list of components built by ABE
== Progress ==
* Out of office 1 day (Thursday)
* [Thumb GlobalISel] Bugfixes [LLVM-544]
- The test-suite compiles and executes without failures (with
fallback to DAG ISel)
- We get some bus errors in the selfhost, which are due to unaligned
64-bit stores. Apparently when alignment checks were introduced in the
legalizer, they were only used for types < 32 bits. Currently testing
a patch to fix this oversight.
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- rc5 looks good on AArch64, ARM is still in progress (waited for LSS-570)
== Plan ==
* Wrap up LLVM-544
* Upload rc5 when ARM is ready
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Posted v4, with system mode only.
[VIRT-298 # ARMv8.4-CondM, Condition flag manipulation ]
[VIRT-329 # ARMv8.5-CondM, Condition flag manipulation ]
[VIRT-337 # ARMv8.0-SB, Speculation Barrier ]
[VIRT-338 # ARMv8.0-PredInv, Prediction Invalidation ]
[VIRT-330 # ARMv8.5-FRINT, Floating-point to integer ]
All upstream.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390x vector patch set 3.
Reviewed renesas rx patch set 3.
Posted some patches and thoughts for
https://bugs.linaro.org/show_bug.cgi?id=4274
Implemented extract2 as a tcg opcode.
Minor hppa bug fixes.
Lots more work on decodetree and A32+T32+T16 conversion.
r~
- Intel CET review (Related to BTI support in LLD), raised issue of
multiple PT_NOTE sections one per alignment
https://reviews.llvm.org/D59120 , commented on command line options.
- LLVM-523 redesigned the LLD handling of ARM exidx sections to
centralise more of the Arm specific implementation details in one
place. Hope to post upstream to get some movement on the review to add
missing .ARM.exidx sections for chrome OS team.
- LLVM-542 Managed to build most of the Zephyr examples for clang,
shared patches to do so with zephyr tech lead.
- Some research for some ABI topics.
- Some thoughts for Linaro connect activities, started team calendar.
Next week:
- Start on my connect presentation
o LLVM
* Machine outliner:
- Stack alignment and refactoring.
- Start to prepare BKK19 talk
* Bots babysitting
* Built 8.0.0-rc4 binaries for x86 and ARM, got issues to start the job on D05
o Misc
* Completed BKK19 and EuroLLVM trips.
* Various meetings and discussions.
== Progress ==
* FDPIC
- (GNU-411) GDB: debugging problems with FDPIC support. Working on
setup of an stm32 board.
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- debugging new benchmarking round-robin jobs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs
- add QEMU to list of components built by ABE
Reply
Forward
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ code review
- add watchdog device to stellaris boards
- bcm2836 "local timer" device
- RTH's rolled-up patchset for SB, PredInv, CondM, FRINT extensions
- Eric's patchset to allow the 'virt' board to have more than 255GB of RAM
- a patchset to add a "generic nommu" board for NiosII
+ assembled a target-arm pull request for softfreeze
+ fixed some minor issues with the "build sphinx docs" patches,
and got them into master (and then fixed some more minor issues...)
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ progress on M-profile floating point:
- finished first draft of changes to exception handling code
- this is now on hold as we are into softfreeze for QEMU 4.0 and other
work for that release will take priority for the next few weeks
thanks
-- PMM
== This Week ==
* PR88839 - Poor implementation of blend like permutes (4/10)
- Addressing suggestions by Richard on patch
* GCC vectorizer (2/10)
- Background reading
* Validation (1/10)
- Added more bootstrap configs for tcwg_gnu job
- Committed patch to abe to enable bootstrap implicitly when buildconfig is set.
- Started tracking for tcwg_gnu ci job (init_configuration == false).
* Public holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
o LLVM
* Back to machine outliner after vacation
- Rebased on upstream master branch
- Working on stack alignment and refactoring.
o Misc
* Preparing BKK19 and EuroLLVM trips.
* Various meetings and discussions.
* PR88838
- I have a patch which solves this.
* adds iv in Pmode but compare_type in 32bit
- It exposes a latent bug in fwprop in regression testing
- Looking into it
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
Progress:
[VIRT-274 # ARMv8.2-FHM, Floating-point multiplication variant ]
Now upstream.
[VIRT-298 # ARMv8.4-CondM, Condition flag manipulation ]
[VIRT-329 # ARMv8.5-CondM, Condition flag manipulation ]
[VIRT-337 # ARMv8.0-SB, Speculation Barrier ]
[VIRT-338 # ARMv8.0-PredInv, Prediction Invalidation ]
[VIRT-330 # ARMv8.5-FRINT, Floating-point to integer ]
Posted an omnibus of SB+PredInv+CondM+FRINT that I have
labeled "v3", as 3 > any individual revision previously used.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390x vector patch set v2.
Implemented pattern groups in decodetree.
Prototyped A32 conversion to decodetree;
started a second revision that incorporates T32.
Started looking at
https://bugs.linaro.org/show_bug.cgi?id=4274
I can swizzle things around by changing the group name from
"cp_regs" to the predefined "system", but somehow those regs
are *also* registered with "general". Which means the
undesired behaviour by which "info regs" prints all of the
system registers still exists.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ upstream code review and pull request handling
+ respin of patchset to enable building our Sphinx RST documentation
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ progress on M-profile floating point:
- have written code to handle the smaller parts of the feature
(insn decode, registers, etc)
- started on changes to exception handling
- lazy save/restore still to do after that
* a lot of admin/meeting stuff this week
* softfreeze now less than two weeks away, need to
focus on what needs to be done before then...
thanks
-- PMM
[LLVM-494] LLD is now turned on for clang linux kernel defconfig builds
[LLVM-542] Worked out how to get Zephyr (Linaro's choice of IoT
embedded OS) compiling with clang. Looks like it is going to be
difficult to get linking with clang/lld so I've used the gcc/ld.bfd
for now.
Linux kernel sent a draft patch to try and alleviate some object
ordering problems that arise when linking the linux kernel with LTO.
[Misc]
Intel patch to add CET to LLD https://reviews.llvm.org/D58102
I mention this as this is related to BTI and CFI and
.note.gnu.property sections. There has been some pushback to the use
of .note.gnu.property sections, and in Intel's case their 2 level PLT
scheme although it seems like as this has been mitigated by the
presence of this option in gcc for some time. I have noticed that we
tend to do design of a feature in one community (LLVM, GNU) and then
attempt to win over the other one with leverage that the other
community supports it. We may need to cast our early feedback net a
bit wider to mitigate the chance that one of the communities blocks
one of our features.
There was an interesting RFC on a linker feature for improving
code-size for mobile phones
http://lists.llvm.org/pipermail/llvm-dev/2019-February/130583.html in
essence an application is developed with loadable features implemented
in DSOs loaded by dlopen. The entry points of the DSO are recorded,
then all the input objects are given to the static linker which then
performs LTO and creates stripped down DSOs that must be loaded at a
specific offset from the application (shrinking them but losing the
shared part of DSO).
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- posted {PATCH v3 0/3} softmmu demacro Message-Id:
<20190215143115.28777-1-alex.bennee(a)linaro.org>
- looks like there is still a bug on x86 TCG Message-Id:
<20190219182528.GA19925@flamenco>
- started v4 re-base, but realised we need better testing so
- posted {PATCH v2 00/16} Enabling tcg/tests for cris and system
mode xtensa & arm Message-Id:
<c3a65d4b-8720-2957-1394-032823a78760(a)redhat.com>
- started writing an i386 test case (x86 exercises more of the
softmmu edge cases)
- started reviewing v3 of plugin patches
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v5} hw/block: better reporting on pflash backing file
mismatch Message-Id: <20190227111347.15063-1-alex.bennee(a)linaro.org>
- tested the possible ahci/migrate fix Message-Id:
<20190227121052.GD2602@work-vm> for hang identified last week
- posted {PULL 0/7} softfloat updates, mostly for s390x Message-Id:
<20190226141201.16999-1-alex.bennee(a)linaro.org>
- posted {PATCH v1 0/6} current state of gitdm/next Message-Id:
<20190226164656.mhasc4xxfjf34hns@function>
- and follow-up {PATCH v2 0/5} gitdm/next updates Message-Id:
<20190301100310.22345-4-alex.bennee(a)linaro.org>
- added some stats to VIRT-26/VIRT-326 for possible KPI use
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other
=====
- more drafting of Connect talk
Completed Reviews [1/1]
=======================
{PATCH v2 00/11} pflash: Fixes and cleanups
Message-Id: <20190226193408.23862-5-armbru(a)redhat.com>
- CLOSING NOTE [2019-03-01 Fri 16:59]
Looks like a good cleanup
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {Qemu-devel} {PATCH 00/23} tests/tcg/xtensa: conditionalize xtensa tests
Message-Id: <20190219061111.10231-1-jcmvbkbc(a)gmail.com>
* {PATCH 00/10} Rework debug exception handling code
Message-Id: <20190301132809.24653-7-will.deacon(a)arm.com>
* {PATCH v2 00/11} Enable build and install of our rST docs
Message-Id: <20190228145624.24885-1-peter.maydell(a)linaro.org>
* {PATCH+RFC 0/6} target/arm: Define cortex-a{73,75,76}
Message-Id: <20190223023957.18865-1-richard.henderson(a)linaro.org>
* {PATCH v3 00/20} Acceptance Tests: target architecture support
Message-Id: <20190221005753.27955-1-crosa(a)redhat.com>
--
Alex Bennée
== Progress ==
* [Thumb GlobalISel] Support global variables [LLVM-540]
- Committed upstream
* [Thumb GlobalISel] Support G_CTLZ [LLVM-543]
- Committed upstream
- We now have the same level of support for Thumb2 and ARM mode
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Tested and uploaded rc3
== Plan ==
* Out of office between 4 - 8 March (i.e. next week)
* GlobalISel bugfixing and cleanup (both ARM and Thumb2)
== Progress ==
* PR88836
- I have a patch (for backend and CSE) which now passes bootstrap and
regression except for one testcase failure (which looks like a pattern
issue). Looking into it.
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
- Not convinced that it is a gcc issue. Looking into the dwarf specification.
* PR88838
- Looking at it.
- Also familiarising with auto-vectorisation of SVE
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
[LLVM-158] Monitor and maintain buildbots
- Some work to track down a faulty msan test on AArch64 that was
intermittently failing.
- Spent some time trying to reproduce an intermittent failure in libfuzzer.
[LLVM-523] Synthesise EXIDX_CANTUNWIND entries for sections without tables.
- Not getting much response from upstream beyond a vague suggestion to
rewrite the whole of .ARM.exidx handling as a single custom section. I
may have to go down this path to get the feature accepted, even if it
is to show that it is a bad idea.
[LLVM-496] LLD in linux kernel
- Submitted patch to ignore -p (--no-pipeline-knowledge) which is used
by the AArch32 linux kernel.
- Submitted patch to integrate LLD in TCWG kernel regression test.
- Learned, the hard way, about how the linux kernel build system works
and how to pass extra flags.
Reviews:
Spent an awful long time looking at how clang passes options to GNU as
to try and match the existing clang defaults. I'm not sure I've seen
anything much more confusing than tracing through target features from
clang to llvm and back again.
