[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Posted v4, with system mode only.
[VIRT-298 # ARMv8.4-CondM, Condition flag manipulation ]
[VIRT-329 # ARMv8.5-CondM, Condition flag manipulation ]
[VIRT-337 # ARMv8.0-SB, Speculation Barrier ]
[VIRT-338 # ARMv8.0-PredInv, Prediction Invalidation ]
[VIRT-330 # ARMv8.5-FRINT, Floating-point to integer ]
All upstream.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390x vector patch set 3.
Reviewed renesas rx patch set 3.
Posted some patches and thoughts for
https://bugs.linaro.org/show_bug.cgi?id=4274
Implemented extract2 as a tcg opcode.
Minor hppa bug fixes.
Lots more work on decodetree and A32+T32+T16 conversion.
r~
- Intel CET review (Related to BTI support in LLD), raised issue of
multiple PT_NOTE sections one per alignment
https://reviews.llvm.org/D59120 , commented on command line options.
- LLVM-523 redesigned the LLD handling of ARM exidx sections to
centralise more of the Arm specific implementation details in one
place. Hope to post upstream to get some movement on the review to add
missing .ARM.exidx sections for chrome OS team.
- LLVM-542 Managed to build most of the Zephyr examples for clang,
shared patches to do so with zephyr tech lead.
- Some research for some ABI topics.
- Some thoughts for Linaro connect activities, started team calendar.
Next week:
- Start on my connect presentation
o LLVM
* Machine outliner:
- Stack alignment and refactoring.
- Start to prepare BKK19 talk
* Bots babysitting
* Built 8.0.0-rc4 binaries for x86 and ARM, got issues to start the job on D05
o Misc
* Completed BKK19 and EuroLLVM trips.
* Various meetings and discussions.
== Progress ==
* FDPIC
- (GNU-411) GDB: debugging problems with FDPIC support. Working on
setup of an stm32 board.
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- debugging new benchmarking round-robin jobs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs
- add QEMU to list of components built by ABE
Reply
Forward
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ code review
- add watchdog device to stellaris boards
- bcm2836 "local timer" device
- RTH's rolled-up patchset for SB, PredInv, CondM, FRINT extensions
- Eric's patchset to allow the 'virt' board to have more than 255GB of RAM
- a patchset to add a "generic nommu" board for NiosII
+ assembled a target-arm pull request for softfreeze
+ fixed some minor issues with the "build sphinx docs" patches,
and got them into master (and then fixed some more minor issues...)
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ progress on M-profile floating point:
- finished first draft of changes to exception handling code
- this is now on hold as we are into softfreeze for QEMU 4.0 and other
work for that release will take priority for the next few weeks
thanks
-- PMM
== This Week ==
* PR88839 - Poor implementation of blend like permutes (4/10)
- Addressing suggestions by Richard on patch
* GCC vectorizer (2/10)
- Background reading
* Validation (1/10)
- Added more bootstrap configs for tcwg_gnu job
- Committed patch to abe to enable bootstrap implicitly when buildconfig is set.
- Started tracking for tcwg_gnu ci job (init_configuration == false).
* Public holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
o LLVM
* Back to machine outliner after vacation
- Rebased on upstream master branch
- Working on stack alignment and refactoring.
o Misc
* Preparing BKK19 and EuroLLVM trips.
* Various meetings and discussions.
* PR88838
- I have a patch which solves this.
* adds iv in Pmode but compare_type in 32bit
- It exposes a latent bug in fwprop in regression testing
- Looking into it
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
Progress:
[VIRT-274 # ARMv8.2-FHM, Floating-point multiplication variant ]
Now upstream.
[VIRT-298 # ARMv8.4-CondM, Condition flag manipulation ]
[VIRT-329 # ARMv8.5-CondM, Condition flag manipulation ]
[VIRT-337 # ARMv8.0-SB, Speculation Barrier ]
[VIRT-338 # ARMv8.0-PredInv, Prediction Invalidation ]
[VIRT-330 # ARMv8.5-FRINT, Floating-point to integer ]
Posted an omnibus of SB+PredInv+CondM+FRINT that I have
labeled "v3", as 3 > any individual revision previously used.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390x vector patch set v2.
Implemented pattern groups in decodetree.
Prototyped A32 conversion to decodetree;
started a second revision that incorporates T32.
Started looking at
https://bugs.linaro.org/show_bug.cgi?id=4274
I can swizzle things around by changing the group name from
"cp_regs" to the predefined "system", but somehow those regs
are *also* registered with "general". Which means the
undesired behaviour by which "info regs" prints all of the
system registers still exists.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ upstream code review and pull request handling
+ respin of patchset to enable building our Sphinx RST documentation
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ progress on M-profile floating point:
- have written code to handle the smaller parts of the feature
(insn decode, registers, etc)
- started on changes to exception handling
- lazy save/restore still to do after that
* a lot of admin/meeting stuff this week
* softfreeze now less than two weeks away, need to
focus on what needs to be done before then...
thanks
-- PMM
[LLVM-494] LLD is now turned on for clang linux kernel defconfig builds
[LLVM-542] Worked out how to get Zephyr (Linaro's choice of IoT
embedded OS) compiling with clang. Looks like it is going to be
difficult to get linking with clang/lld so I've used the gcc/ld.bfd
for now.
Linux kernel sent a draft patch to try and alleviate some object
ordering problems that arise when linking the linux kernel with LTO.
[Misc]
Intel patch to add CET to LLD https://reviews.llvm.org/D58102
I mention this as this is related to BTI and CFI and
.note.gnu.property sections. There has been some pushback to the use
of .note.gnu.property sections, and in Intel's case their 2 level PLT
scheme although it seems like as this has been mitigated by the
presence of this option in gcc for some time. I have noticed that we
tend to do design of a feature in one community (LLVM, GNU) and then
attempt to win over the other one with leverage that the other
community supports it. We may need to cast our early feedback net a
bit wider to mitigate the chance that one of the communities blocks
one of our features.
There was an interesting RFC on a linker feature for improving
code-size for mobile phones
http://lists.llvm.org/pipermail/llvm-dev/2019-February/130583.html in
essence an application is developed with loadable features implemented
in DSOs loaded by dlopen. The entry points of the DSO are recorded,
then all the input objects are given to the static linker which then
performs LTO and creates stripped down DSOs that must be loaded at a
specific offset from the application (shrinking them but losing the
shared part of DSO).
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- posted {PATCH v3 0/3} softmmu demacro Message-Id:
<20190215143115.28777-1-alex.bennee(a)linaro.org>
- looks like there is still a bug on x86 TCG Message-Id:
<20190219182528.GA19925@flamenco>
- started v4 re-base, but realised we need better testing so
- posted {PATCH v2 00/16} Enabling tcg/tests for cris and system
mode xtensa & arm Message-Id:
<c3a65d4b-8720-2957-1394-032823a78760(a)redhat.com>
- started writing an i386 test case (x86 exercises more of the
softmmu edge cases)
- started reviewing v3 of plugin patches
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v5} hw/block: better reporting on pflash backing file
mismatch Message-Id: <20190227111347.15063-1-alex.bennee(a)linaro.org>
- tested the possible ahci/migrate fix Message-Id:
<20190227121052.GD2602@work-vm> for hang identified last week
- posted {PULL 0/7} softfloat updates, mostly for s390x Message-Id:
<20190226141201.16999-1-alex.bennee(a)linaro.org>
- posted {PATCH v1 0/6} current state of gitdm/next Message-Id:
<20190226164656.mhasc4xxfjf34hns@function>
- and follow-up {PATCH v2 0/5} gitdm/next updates Message-Id:
<20190301100310.22345-4-alex.bennee(a)linaro.org>
- added some stats to VIRT-26/VIRT-326 for possible KPI use
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other
=====
- more drafting of Connect talk
Completed Reviews [1/1]
=======================
{PATCH v2 00/11} pflash: Fixes and cleanups
Message-Id: <20190226193408.23862-5-armbru(a)redhat.com>
- CLOSING NOTE [2019-03-01 Fri 16:59]
Looks like a good cleanup
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {Qemu-devel} {PATCH 00/23} tests/tcg/xtensa: conditionalize xtensa tests
Message-Id: <20190219061111.10231-1-jcmvbkbc(a)gmail.com>
* {PATCH 00/10} Rework debug exception handling code
Message-Id: <20190301132809.24653-7-will.deacon(a)arm.com>
* {PATCH v2 00/11} Enable build and install of our rST docs
Message-Id: <20190228145624.24885-1-peter.maydell(a)linaro.org>
* {PATCH+RFC 0/6} target/arm: Define cortex-a{73,75,76}
Message-Id: <20190223023957.18865-1-richard.henderson(a)linaro.org>
* {PATCH v3 00/20} Acceptance Tests: target architecture support
Message-Id: <20190221005753.27955-1-crosa(a)redhat.com>
--
Alex Bennée
== Progress ==
* [Thumb GlobalISel] Support global variables [LLVM-540]
- Committed upstream
* [Thumb GlobalISel] Support G_CTLZ [LLVM-543]
- Committed upstream
- We now have the same level of support for Thumb2 and ARM mode
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Tested and uploaded rc3
== Plan ==
* Out of office between 4 - 8 March (i.e. next week)
* GlobalISel bugfixing and cleanup (both ARM and Thumb2)
== Progress ==
* PR88836
- I have a patch (for backend and CSE) which now passes bootstrap and
regression except for one testcase failure (which looks like a pattern
issue). Looking into it.
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
- Not convinced that it is a gcc issue. Looking into the dwarf specification.
* PR88838
- Looking at it.
- Also familiarising with auto-vectorisation of SVE
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
[LLVM-158] Monitor and maintain buildbots
- Some work to track down a faulty msan test on AArch64 that was
intermittently failing.
- Spent some time trying to reproduce an intermittent failure in libfuzzer.
[LLVM-523] Synthesise EXIDX_CANTUNWIND entries for sections without tables.
- Not getting much response from upstream beyond a vague suggestion to
rewrite the whole of .ARM.exidx handling as a single custom section. I
may have to go down this path to get the feature accepted, even if it
is to show that it is a bad idea.
[LLVM-496] LLD in linux kernel
- Submitted patch to ignore -p (--no-pipeline-knowledge) which is used
by the AArch32 linux kernel.
- Submitted patch to integrate LLD in TCWG kernel regression test.
- Learned, the hard way, about how the linux kernel build system works
and how to pass extra flags.
Reviews:
Spent an awful long time looking at how clang passes options to GNU as
to try and match the existing clang defaults. I'm not sure I've seen
anything much more confusing than tracing through target features from
clang to llvm and back again.
re-essayer de flash le kernel sur la board (mais est-ce possible vu
qu'il semble plus gros que la flash?)
$ openocd -f /usr/share/openocd/scripts/board/stm32f429discovery.cfg
-f flash-kernel.cfg
[...]
Info : device id = 0x20016419
Info : flash size = 2048kbytes
Info : Dual Bank 2048 kiB STM32F42x/43x/469/479 found
Warn : no flash bank found for address 0
wrote 0 bytes from file
/home/lyon/src/kernel/linux/arch/arm/boot/xipImage in 0.007352s (0.000
KiB/s)
** Programming Finished **
demander de l'aide aux gens de ST?
re-essayer avec un openocd plus recent
== Progress ==
* FDPIC
- (GNU-411) GDB: debugging problems with FDPIC support. Trying to
setup a stm32 board to avoid problems with unsupported configurations
mix between kernel and qemu.
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- debugging new benchmarking round-robin jobs
== Next ==
Holidays, back on March 4th
== Next-next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ patch review: RTH's JSConv/FHM patchset
+ sent another arm pull request
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ Implemented and wired up the SSE-200 Message Handling Units
+ Implemented the mechanism by which a guest can power up CPU 1
+ Sent out patches for these; this can run the Zephyr MHU/dualcore testcase
+ Started looking at implementing floating point support for M profile
thanks
-- PMM
== Progress ==
* [Thumb GlobalISel] Support control flow [LLVM-530]
- Committed upstream
* [Thumb GlobalISel] Support accessing the stack [LLVM-527]
- Committed upstream
* [Thumb GlobalISel] Support floating point [LLVM-531]
- Committed upstream
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Investigated the release blocker from rc1, turned out to be an
issue with the filesystem used in the container on the APMs
- Changed the release job to run on the D05 instead, where we use a
different container [LLVM-539]
- Testing still in progress
== Plan ==
* [Thumb GlobalISel] Support global variables [LLVM-540]
* Out of office between 4 - 8 March
== Progress ==
* PR88834:
* Have a patch for ivopt and backend that generates the required
addressing mode and code. Still need cleanup and some improvements.
* PR88836
Made the required changes to the backend.
CSE is still not happening. Looked at CSE in detail and made few
changes but still need more work. The issues are:
- Parallel rtx with one setting a register and other using it will
be immediately invalidated as the invalidation happens after
processing both.
- If CSE is such that one instruction is with one constant operand
and other with constant in a register, it will not be detected
- VEC_DUPLICATE is not handled.
- Not sure any other pass like GCSE is a better option
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
[VIRT-68 # QEMU should implement tagged pointer support ]
Closed. We merged these patches on Feb 5.
[VIRT-242 # ARMv8.3-JSCVT ]
Sent v4.
[VIRT-274 # ARMv8.2-FHM, Floating-point multiplication variant ]
Sent v2.
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Sent v3 vs 00eac6.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390 floating point extension feature.
Fixed AT_PLATFORM for arm-linux-user and aarch64_be-linux-user.
Implemented missing float_round_to_odd functionality.
r~
QEMU Tooling ([VIRT-252])
=========================
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
QEMU plugin support ([VIRT-280])
- posted {PATCH v3 0/3} softmmu demacro Message-Id:
<20190215143115.28777-1-alex.bennee(a)linaro.org>
- awaiting v3 of plugin patches :todo
Upstream Work ([VIRT-109])
==========================
- posted {PULL 00/18} testing updates: travis/cirrus/vm-test/binfmt
Message-Id: <20190211130507.8710-1-alex.bennee(a)linaro.org>
- posted {PATCH v2 0/6} HWCAP_CPUID registers for aarch64 Message-Id:
<20190205190224.2198-1-alex.bennee(a)linaro.org>
- fixes pulled into target-arm.next
- test case held back due to compiler version needed, need to respin
- posted {PATCH v2} hw/block: report when pflash backing file isn't
aligned Message-Id: <20190215122808.22301-1-alex.bennee(a)linaro.org>
- prompted further discussion on best solution as -pflash fails in
ways -bios doesn't
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other
=====
- Spent time building cross-tools for Debian/ARM64
- sent {PATCH} binutils: enable s390x/ppc64el on arm64 hosts
Message-Id: <20190212140851.22478-1-alex.bennee(a)linaro.org>
- Discussion on [Debian #921458] (buster apt source qemu)
- upstream consensus seems to be it is acceptable
- apt-get build-dep --arch-only qemu
[Debian #921458]
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=921458
Completed Reviews [1/1]
=======================
{RFC} arm: Allow system registers for KVM guests to be changed by QEMU code
Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org>
- CLOSING NOTE [2019-02-13 Wed 16:30]
Looks fine, although we still need to keep squashing single-step
while debug is on
Absences
========
- 15-18th Feb (long w/e)
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {PATCH 0/4} target/arm: Reduce overhead of cpu_get_tb_cpu_state
Message-Id: <20190214040652.4811-1-richard.henderson(a)linaro.org>
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {Qemu-devel} {PATCH v6 00/49} linux-user: Split do_syscall
Message-Id: <20190118213122.22865-1-richard.henderson(a)linaro.org>
* {PATCH 0/5} target/mips: Add MSA ASE tests
Message-Id: <1550001205-7883-1-git-send-email-aleksandar.markovic(a)rt-rk.com>
* {Qemu-arm} {PATCH 00/25} Kconfig dependencies for ARM machines
Message-Id: <1549694366-1284-1-git-send-email-thuth(a)redhat.com>
* {RFC QEMU v2 0/2} arm/virt: Account for guest pause time
Message-Id: <1543352837-21529-1-git-send-email-bijan.mottahedeh(a)oracle.com>
--
Alex Bennée
