== Progress ==
* SVE ACLE
- Revised and reviewed svbic main briant svbic_z for bool
* Fixing uninit warning suppression from tree-ch pass
- Implemented a patch to handle this and regression test is fine.
Will post for review once stage 1 opens
* tree-reassoc improvements
- Looking at possible data structures to best represent
== Plan ==
* Continue with SVE ACLE
* Continue with tree-reassoc
[VIRT-294 # ARMv8.3-PAuth, Pointer Authentication ]
Finished up the linux-user emulation, and posted.
Reviewed a patch set from Huawei also touching PAuth.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed riscv decodetree v4 patchset.
Partial review of new target/rx patchset. It is confusing enough
to make me want to tackle the variable-length decodetree problem.
Reviewed softtlb resize v7 patchset; ported that to the remaining
tcg backends.
Part way through reviewing Peter's MPS2 patch set.
r~
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- started reviewing {RFC v2 00/38} Plugin support Message-Id:
<20181209193749.12277-1-cota(a)braap.org>
- some bitrot when applied to current tree :/
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- respin {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.bennee(a)linaro.org>
- re-based [v3 branch] - I think the id reg stuff is now addressed
by rth's fixes
- still need to address other review comments
- posted {RFC PATCH 0/3} vmbuild tweaks for BSD targets Message-Id:
<20190121171543.32422-1-alex.bennee(a)linaro.org>
- posted {PATCH v3 00/11} current fpu/next queue (tests & build fix)
Message-Id: <20190122215016.18697-12-alex.bennee(a)linaro.org>
- finally solved the weird endianess issue
- merged in {PULL v2 00/11} check-softfloat, fp-bench and clang
compile fixes Message-Id:
<20190123114220.16972-1-alex.bennee(a)linaro.org>
- posted {PATCH v1 00/14} testing/next (binfmt_misc, vm-build and BSD
CI) Message-Id: <20190125140017.6092-1-alex.bennee(a)linaro.org>
- also did some work on [the linux-user multiarch but it is not
ready yet]
- need to finish the re-work of [system test and misc arch] tests
:todo
- will be useful for test cases for plugins
- also more test cases queued up for system tests
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[v3 branch]
https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3
[the linux-user multiarch but it is not ready yet]
https://github.com/stsquad/qemu/tree/testing/next-with-linux-user
[system test and misc arch]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2
Completed Reviews [2/2]
=======================
{PATCH 00/18} Acceptance Tests: target architecture support
Message-Id: <20190117185628.21862-1-crosa(a)redhat.com>
- CLOSING NOTE [2019-01-25 Fri 19:33]
Still a few edge cases to work out
{PATCH 0/2} contrib: gitdm: Some updates
Message-Id: <1547807155-4526-1-git-send-email-aleksandar.markovic(a)rt-rk.com>
- CLOSING NOTE [2019-01-25 Fri 19:33]
Queued to my tree
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code
Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH v3 0/4} tcg: support heterogenous CPU clusters
Message-Id: <20190121152218.9592-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH RFC 00/11} Add Renesas RX archtecture
Message-Id: <20190121131602.55003-1-ysato(a)users.sourceforge.jp>
* {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI
Message-Id: <20190110121736.23448-1-richard.henderson(a)linaro.org>
* {PATCH v5 00/73} per-CPU locks
Message-Id: <20181213050453.9677-1-cota(a)braap.org>
--
Alex Bennée
Majority of the week spent preparing for Fosdem talk on LLD:
- Built Chrome for Arm and AArch64 to investigate link time
performance on non-X86 platforms
-- Both gold and bfd take a considerable amount of time to produce
stubs/veneers/errata fixes
-- AArch64 link time is comparable to X86
- LLD gets more usage out of multithreading than gold
- Studied Gold and BFD structure to compare to LLD
- About half of slides written.
Some minor involvement with some investigations for ClangBuiltLinux.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ code review:
- 'SBSA reference' model (now quite close to being in shape to go in)
- RTH's BTI patchset
- RTH's patchset adding TBI support to user-mode emulation
+ sent patches fixing the last lot of clang
-Waddress-of-packed-member warnings
+ had another look at the prototype work I did to use Sphinx
for QEMU's documentation -- updated the patchset and started
looking at how to tie it into our makefiles.
+ sent patches fixing a handful of underdecodings in our A64 decoder,
where we should have UNDEFed but did not
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ sent out v1 of the patchset implementing the SSE-200 and MPS2 AN521 model
+ read through the Musca-B1 docs to confirm what we can easily
put into an initial implementation of a model
thanks
-- PMM
== Progress ==
* Out of office on Monday
* [Thumb GlobalISel] Support G_SHL, G_ASHR, G_LSHR [LLVM-517]
- Committed upstream
* [Thumb GlobalISel] Support G_SDIV and G_UDIV [LLVM-516]
- Most of the work done, ready to commit next week
* LLVM 8.0 Release for ARM & AArch64 [LLVM-526]
- Started a few jobs, but ran into some trouble with our containers
- Will look more into it next week
* Use new version of GCC on buildbots [LLVM-515]
- Got it to work and committed patch; we have 2 silent bots running with GCC-7
- Will keep monitoring the bots and if they seem stable we can merge
to tcwg-llvmprod next week
== Plan ==
* Test LLVM 8.0.0 RC1
* Commit LLVM-516
* More GlobalISel
* Out of office on Friday
Hi Martin and Linaro-toolchain team,
We want to use 4.8.5 cross compile toolchain to build ko.
But we can't find such version on the release site[1].
Is there a 4.8.5 cross compile toolchain?
[1] https://releases.linaro.org/components/toolchain/gcc-linaro/
Best,
Xinliang
== Progress ==
* SVE ACLE
- Committed patches for
* svabs, svneg, svnot and svsqrt series
* svdiv series
* svmulh series
* svand, svorr, and sveor series
* svdot series
- Working on svbic and svbic_b variants
* Others
- Looking into tree-reassoc improvements for next stage1
- Looked into kernel plugin issue for arm
== Plan ==
* Continue with SVE ACLE
* Continue with tree-reassoc
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Posted v1.
[VIRT-327 # Richard's upstream QEMU work ]
Posted v6 of linux-user split. Based on Laurent's feedback,
I'm running LTP myself this time, at least for a few guests.
r~
Upstream Work ([VIRT-109])
==========================
- posted {PULL 0/5} gitdm updates with final 2018 stats Message-Id:
<20190114160956.7513-1-alex.bennee(a)linaro.org>
- posted {PULL 00/21} misc testing fixes for Travis and docker
Message-Id: <20190114150129.1013-1-alex.bennee(a)linaro.org>
- we have gone green again
- posted {PULL 0/7} check-softfloat, fp-bench and clang compile fixes
Message-Id: <20190117132703.17790-1-alex.bennee(a)linaro.org>
- some alt-OS issues and a weird failure on s390x
- spent some time getting a working s390x setup to investigate
- posted {PATCH} target/s390x: define TCG_GUEST_DEFAULT_MO for MTTCG
Message-Id: <20190118171848.27332-1-alex.bennee(a)linaro.org>
- need to investigate why s390x breaks so weirdly
- messed around with a little [CONFIG_TCG type cleanups]
- need to finish the re-work of [system test and misc arch] tests
:todo
- will be useful for test cases for plugins
- also more test cases queued up for system tests
- respin {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.bennee(a)linaro.org> :todo
- in branch [v3 branch]
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[CONFIG_TCG type cleanups]
https://github.com/stsquad/qemu/tree/misc/config-tcg-cleanups
[system test and misc arch]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2
[v3 branch]
https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3
Other Tasks
===========
- wrote up and submitted abstract for Connect
- I still hope to the history of TCG for TCWG room as well
Completed Reviews [4/4]
=======================
{Qemu-devel} {PATCH} .cirrus.yml: basic compile and test for FreeBSD
Message-Id: <CAPyFy2Dw2F3ks_5f8cvWjrsOTS0_Ybr5kELUpyHQmOQWUaeuFg(a)mail.gmail.com>
- CLOSING NOTE [2019-01-16 Wed 15:01]
Adds FreeBSD testing, yet another CI system
{PATCH v2} softfloat: enforce softfloat if the host's FMA is broken
Message-Id: <20181225070305.18221-1-cota(a)braap.org>
- CLOSING NOTE [2019-01-16 Wed 15:03]
Queued to my tree
{PATCH v6 0/3} Dynamic TLB sizing
Message-Id: <20190114165017.27298-1-cota(a)braap.org>
- CLOSING NOTE [2019-01-17 Thu 10:53]
Found a few issues.
{PATCH v7 0/3} Dynamic TLB sizing
Message-Id: <20190116170114.26802-1-cota(a)braap.org>
- CLOSING NOTE [2019-01-18 Fri 16:54]
Looks good to me now.
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {PATCH 0/2} contrib: gitdm: Some updates
Message-Id: <1547807155-4526-1-git-send-email-aleksandar.markovic(a)rt-rk.com>
* {PATCH 00/18} Acceptance Tests: target architecture support
Message-Id: <20190117185628.21862-1-crosa(a)redhat.com>
* {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI
Message-Id: <20190110121736.23448-1-richard.henderson(a)linaro.org>
* {PATCH v5 00/73} per-CPU locks
Message-Id: <20181213050453.9677-1-cota(a)braap.org>
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code
Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org>
--
Alex Bennée
[LLVM-521] LLD and taking the address of an ifunc
Went through the possible combinations (pic, pie, non-pic, exec,
shared,...) found one relocation that gcc uses that clang doesn't,
hence mc and LLD don't support. Raised upstream pr. Also found that
clang's code-sequence for -fpie doesn't seem to guarantee ifunc
pointer equivalence when linking -fpie (non-got generating sequence
used when ifunc is in same translation unit). Will need some further
investigation to confirm.
[LLVM-499] Support for linking the linux kernel
Committed -pic-veneer support and associated overflow fix, now merged
to 8.0 branch.
Other:
- Started work on Fosdem presentation on LLD performance. Studying
ld.bfd and ld.gold source code to look for structural differences
between them and LLD.
- Submitted presentation for next Linaro Connect
- Review for comdat group and unused section elimination.
- On buildbot duty.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ some code review, and another arm pull-request (including
RTH's pointer auth work)
+ sent patch fixing a bug in the gdbstub memory access path that
meant it was always making accesses as NonSecure even if the
guest CPU was currently Secure
+ sent patch fixing checkpatch to not wrongly complain about
block comments starting "/**"
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ I have a model of the SSE-200 subsystem used by the Musca board,
and a model of the MPS2 AN521 FPGA image which uses it. (Since it is
basically "our existing MPS2 AN505 model, but with SSE-200 rather than
IoTKit" it's a useful stepping stone to the Musca board.) There are
still some bugs and missing features, but it seems to mostly be
functional (it can run the ARM Trusted Firmware M test binary.)
thanks
-- PMM
== Progress ==
* FDPIC
- (GNU-411) GDB: gdbserver did not start because of a qemu-user
feature. Worked around it.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, still
- qemu-3.1 memory consumption. Got some clarifications from IT team
about LSF reports.. It seems qemu-3.1 consumes more memory in some
cases, though.
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. No progress.
- (GNU-597) Fixed arm testcase.
- PR 85596 committed doc fix
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- dealing with nasty ST-internal infrastructure problems
- (GNU-592): improved benchmarking scripts
- experimenting with new build servers
- ran Linaro binary toolchain tests on gcc-arm release, filled a few bug reports
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Validation:
- isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for
aarch64-linux target
== Progress ==
* [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491]
- Committed upstream
* [ARM & Thumb GlobalISel] Support calls to vararg functions [LLVM-490]
- This gets rid of all the fallbacks in the test-suite related to
calls to printf (which is a lot)
- Committed upstream
* Use new version of GCC on buildbots [LLVM-515]
- Fiddled with this a bit, but couldn't test much due to dockerd
being broken for a couple of days
- Manual installation of g++-7 from PPA works, but when trying the
same steps in the dockerfile it keeps restarting; need to investigate
why
== Plan ==
* More of the same
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2019.01 snapshot of the Linaro GCC 7 source package.
The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
This snapshot1 is based on FSF GCC 7.4+svn267072 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2019.01 stable2 periodic release.
Interesting changes in this GCC source package snapshot include:
Updates to GCC 7.4+svn267072
Linaro bug 4007: “Internal compiler error with -mcpu=thunderx2t99” is fixed
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development.
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development mailing list:
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at #linaro-tcwg
* Bug reports should be filed in Bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at Linaro support:
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
== Progress ==
* SVE ACLE
- Revised svmla, svmls, svmad and svmsb and committed after getting ACK
- Revised again posted for review
* svabs, svneg, svnot and svsqrt series
* svdiv series
* svmulh series
* svand, svorr, and sveor series
* svdot series
== Plan ==
* Contine with sve acle
[LLVM-520] LLD Fix movt/movw relocation overflow
Now committed upstream.
[LLVM-521] Taking the address of an ifunc in AArch64
Prompted by a bug report and comment about pointer equivalence, spent
some time looking into gold, lld and bfd behaviour to ensure that LLD
is at least correct.
Other
Some investigation into LLD non-support of common-page-size and
whether this is significant for code-size. Used in response to query
about whether LLD should change default value of max-page-size.
Thoughts about whether a linker must generate cantunwind .ARM.exidx
sections for code sections missing a .ARM.exidx section. If C++ code
with exceptions is interleaved with some assembly code without
.ARM.exidx sections then the assembly code can match the address range
of the C++ code that precedes it.
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ rth's pointer-auth emulation patchset
+ more devices for the microbit board model
+ support for u-boot "noload" image type
+ gdbstub multiprocess extension support for use when the board
model has multiple asymmetric clusters (like Xilinx Zynq boards)
- finished debugging patch for aarch64 host linux-user to distinguish
SEGV on read from SEGV on write by looking at the ESR context struct
from the kernel rather than by looking at the faulting insn; sent it.
- sent patch to fix linux-user pread64/pwrite64 with NULL buffer and 0 length
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
- Sent out patchset fixing heterogenous CPU support (required a lot
of thought about what we might need to fix and not all that much
code, in the end)
- Started work on refactoring our IoTKit model to also support
the extra pieces required by the SSE-200 subsystem used in the Musca
thanks
-- PMM