SVE Support ([VIRT-198])
========================
RISU Support for SVE ([VIRT-199])
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- get back to merging/preparing the SVE series :todo
[VIRT-199] https://projects.linaro.org/browse/VIRT-199
SVE Reviews
~~~~~~~~~~~
- reviewed {PATCH 0/9} target/arm: Fixups for ARM_FEATURE_V8_FP16
Message-Id: <20180425012300.14698-1-richard.henderson(a)linaro.org>
SoftFloat Bugs ([VIRT-69])
==========================
- CLOSING NOTE [2018-05-18 Fri 16:41]
I think all known bugs have fixes now merged.
[VIRT-69] https://projects.linaro.org/browse/VIRT-69
Upstream Work ([VIRT-109])
==========================
- catch-up on review queue :todo
- posted {PATCH v4 00/49} fix building of tests/tcg Message-Id:
<20180517174718.10107-1-alex.bennee(a)linaro.org>
- spin v5 and get merged :todo
- posted {PATCH v2 0/2} support reading of CNT{VCT|FRQ}_EL0 from
user-space Message-Id:
<20180518114424.18054-1-alex.bennee(a)linaro.org>
- posted {RFC PATCH 0/2} Travis Stability Patches Message-Id:
<20180518091440.1559-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[a gdb bug] https://sourceware.org/bugzilla/show_bug.cgi?id=23127
Fixing up tests/tcg
~~~~~~~~~~~~~~~~~~~
- posted {PATCH v4 00/49} fix building of tests/tcg Message-Id:
<20180517174718.10107-1-alex.bennee(a)linaro.org>
KVM CI Loop ([VIRT-2])
======================
- need to sync-up on the current state of this work :todo
[VIRT-2] https://projects.linaro.org/browse/VIRT-2
[our wiki] https://wiki.linaro.org/Core/Virtualization
Other Tasks
===========
- Investigate weird QEMU CI OBS build issue :todo
- the OBS build should be failing the RISU tests but isn't, despite
the commit id it reports
- bringing up my SyncQuacer DevBox with Gentoo
- needed one patch for Nouveau w.r.t 32/64 bit PCIE lanes
- needed to manually patch LVM to build initrd Message-Id:
<20180516201903.24309-1-alex.bennee(a)linaro.org>
Completed Reviews [7/7]
=======================
{PATCH v6 0/3} target/arm: Add a dynamic XML-description of the cp-registers to GDB
Message-Id: <1524153386-3550-1-git-send-email-abdallah.bouassida(a)lauterbach.com>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE tested with new gdb - some weirdness on timer register
{PATCH 00/19} softfloat: Clean up NaN handling
Message-Id: <20180511004345.26708-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-05-11 Fri 20:55]
Found a few minor bugs, rth re-spinning with my float-to-float stuff
{PATCH v4 00/11} target/arm: Fixups for ARM_FEATURE_V8_FP16
Message-Id: <20180512003217.9105-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-05-15 Tue 11:42]
Despite initial confusion on branch tested fine on both, all good.
{Qemu-devel} {PATCH 0/9} target/arm: Implement v8.1-Atomics
Message-Id: <20180427002651.28356-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-05-15 Tue 11:43]
Already merged, others have reviewed
{PATCH v2 00/27} softfloat patch roundup
Message-Id: <20180512004311.9299-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-05-15 Tue 11:45]
v5 released
{PATCH v5 00/28} softfloat patch roundup
Message-Id: <20180514221219.7091-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-05-15 Tue 15:10]
Looking good.
{PATCH v6 00/28} softfloat patch roundup
Message-Id: <20180515222540.9988-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-05-18 Fri 16:16]
Merged upstream
Absences
========
- CBG Beer Festival (half day sometime next week)
- VNC18 Connect (17th-21st September 2018)
- KVM Forum 2018 (24th-26th October 2018)
Current Review Queue
====================
* {Qemu-arm} {PATCH v3-a 00/27} target/arm: Scalable Vector Extension
Message-Id: <20180516223007.10256-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH} gdbstub: Clarify what gdb_handlesig() is doing
Message-Id: <20180515181958.25837-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH 0/9} Honor CPU_DUMP_FPU
Message-Id: <20180511035240.4016-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {RFC PATCH v2 00/12} iommu: add MemTxAttrs argument to IOMMU translate function
Message-Id: <CAFEAcA_Dei48HtKk6GnEgXYcXdY2htCXej4pSfY+q9V6f=abdA(a)mail.gmail.com>
* {RFC PATCH 00/12} tests/tcg: Add TriCore tests
Message-Id: <20180501142222.19154-1-kbastian(a)mail.uni-paderborn.de>
* {PATCH v3 00/15} fp-test + hardfloat
Message-Id: <1522883475-27858-1-git-send-email-cota(a)braap.org>
--
Alex Bennée
[Activity]
[TCWG-1319] Link AOSP with LLD.
Closed this out as I've gone as far as I can profitably go without
being an Android expert.
- With trunk LLD I can now link and boot AOSP with LLD without any
use_clang_lld=false on both Arm and AArch64 emulators. I also managed
to get it to boot on a Hikey960 (aarch64).
- Communicated recent additions to LLD in aid of building AOSP, and
extra command line options needed to the Google team.
Landed support for GCC inline assembly constraint S in LLVM.
Some comments on LTO + linker script proposal on llvm-dev mailing list.
Started thinking in more detail about ICF=safe.
- Decided that LLVM was a better place to do this than clang after
attempting to use libtooling.
- There is an existing LLVM pass called merge functions that does what
ICF does but at the LLVM IR level
-- This is off by default, maybe worth looking at as part of LTO and
code-size reductions.
- Started to write a prototype pass that uses
Function::isAddressTaken() although I think that this may give me too
pessimistic a result.
Peter
Progress: [short week, 3 days]
* VIRT-65 [QEMU upstream maintainership]
+ code review
- make system registers visible via gdbstub
- Richard's patches to fix various softfloat issues
* VIRT-164 [improve Cortex-M emulation]
+ MPC emulation:
- rebased and fixed up conflicts with a different series that
touched the same parts of the memory system
- realised that passing txattrs to IOMMUs means we need to
change the notifier API; came up with a plan to handle this
by using "IOMMU indexes" analogous to our existing TCG MMU
indexes. Updated everything to the new API that comes out
of that approach.
- started on tidying up the final loose ends; hope to have
something I can send to the list early next week
thanks
-- PMM
o 3 days off
== Progress ==
o LLVM
* Thumbv8 bot failures:
- Reproduced the issue on TX1
- These test cases need to be disabled for ARM targets (patch on-going).
o Misc
* Various meetings and discussions.
[VIRT-243 # ARMv8.1-Atomic instructions ]
v3 posted and merged.
[Upstream]
(Upgraded my laptop to Fedora 28, which lead to...)
Posted a patch for gcc 8 Werrors.
Posted patches for clang 6 Werrors.
Sent pull for Emilio's TranslateOps patches.
Sent pull for my openrisc decodetree patches.
Sent pull for tcg-next.
Reviewed microblaze patches.
Posted two rounds of softfloat snan patches.
Posted two rounds of fp16 patches.
[VIRT-198 # QEMU: SVE Emulation Support ]
Most of this week's work was on indirectly related patch sets. In particular,
fp16 and atomics. The last round of check-gcc testing had
FAIL: gcc.dg/vect/slp-multitypes-2.c execution test
FAIL: gcc.target/aarch64/advsimd-intrinsics/vldX.c -O0 execution test
FAIL: gcc.target/aarch64/advsimd-intrinsics/vqtbX.c -O0 execution test
as the only remaining (relevant) failures. I believe that the latter two are
generic tcg failures that are cured by this week's tcg-next pull, but have not
yet re-based everything to be sure.
r~
SVE Support ([VIRT-198])
========================
RISU Support for SVE ([VIRT-199])
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- regenerate more half-precision test cases
[VIRT-199] https://projects.linaro.org/browse/VIRT-199
SVE Reviews
~~~~~~~~~~~
- started reviewing {PATCH 0/9} target/arm: Fixups for
ARM_FEATURE_V8_FP16 Message-Id:
<20180425012300.14698-1-richard.henderson(a)linaro.org>
- fixed a couple of other problems testing picked up, see [this
branch]
[this branch] https://github.com/stsquad/qemu/tree/review/rth-fp16-fixes
SoftFloat Bugs ([VIRT-69])
==========================
- posted {PATCH v3 0/5} refactor float-to-float and fix AHP
Message-Id: <20180510094206.15354-1-alex.bennee(a)linaro.org>
- fixes up the current cases, AArch32 is lagging in later rev
support
- rth had a go at a canonical NaN solution
- reviewed {PATCH 00/19} softfloat: Clean up NaN handling Message-Id:
<20180511004345.26708-1-richard.henderson(a)linaro.org>
[VIRT-69] https://projects.linaro.org/browse/VIRT-69
Upstream Work ([VIRT-109])
==========================
- catch-up on review queue :todo
- reviewed {PATCH v6 0/3} target/arm: Add a dynamic XML-description of
the cp-registers to GDB Message-Id:
<1524153386-3550-1-git-send-email-abdallah.bouassida(a)lauterbach.com>
- finished testing - some wierdness with register values
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[a gdb bug] https://sourceware.org/bugzilla/show_bug.cgi?id=23127
Fixing up tests/tcg
~~~~~~~~~~~~~~~~~~~
- posted {PATCH v3 00/46} fix building of tests/tcg Message-Id:
<20180424152405.10304-1-alex.bennee(a)linaro.org>
- series looking pretty good, more comments incoming
- working on [v4 of the series]
[v4 of the series]
https://github.com/stsquad/qemu/tree/testing/tcg-tests-revival-v4
KVM CI Loop ([VIRT-2])
======================
- need to sync-up on the current state of this work :todo
[VIRT-2] https://projects.linaro.org/browse/VIRT-2
[our wiki] https://wiki.linaro.org/Core/Virtualization
Other Tasks
===========
- Investigate weird QEMU CI OBS build issue :todo
- the OBS build should be failing the RISU tests but isn't, despite
the commit id it reports
- bringing up my SyncQuacer, did some serial port debugging to debug
DIMMS
- turns out supported DIMMs are "4GB UDIMM and 16GB RDIMM"
- will need new firmware to get the 16GB UDIMMs working
[ARMv8.2-LPA support] https://projects.linaro.org/browse/TCWG-1395
[ARMv8.2-LVA] https://projects.linaro.org/browse/TCWG-1396
Completed Reviews [5/5]
=======================
{PATCH v6 0/3} target/arm: Add a dynamic XML-description of the cp-registers to GDB
Message-Id: <1524153386-3550-1-git-send-email-abdallah.bouassida(a)lauterbach.com>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE tested with new gdb - some weirdness on timer register
{PATCH 00/19} softfloat: Clean up NaN handling
Message-Id: <20180511004345.26708-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-05-11 Fri 20:55]
Found a few minor bugs, rth re-spinning with my float-to-float stuff
Absences
========
- Bank Holiday (May 7th)
- VNC18 Connect (17th-21st September 2018)
- KVM Forum 2018 (24th-26th October 2018)
Current Review Queue
====================
* {Qemu-devel} {PATCH 0/9} target/arm: Implement v8.1-Atomics
Message-Id: <20180427002651.28356-1-richard.henderson(a)linaro.org>
* {RFC PATCH 00/12} tests/tcg: Add TriCore tests
Message-Id: <20180501142222.19154-1-kbastian(a)mail.uni-paderborn.de>
* {RFC PATCH v2 00/19} reverse debugging
Message-Id: <20180428123627.12445.9923.stgit@pasha-VirtualBox>
* {PATCH 0/2} arm64: Report signal frame size to userspace via auxv
Message-Id: <1525776211-28169-1-git-send-email-Dave.Martin(a)arm.com>
* {Qemu-devel} {PATCH v4 0/4} qemu-thread: support --enable-debug-mutex
Message-Id: <20180423053927.13715-1-peterx(a)redhat.com>
* {PATCH v3 00/15} fp-test + hardfloat
Message-Id: <1522883475-27858-1-git-send-email-cota(a)braap.org>
--
Alex Bennée
4 day week
[TCWG-1236] Android on LLD
Android team have switched to LLD by default for most modules. Looking
to switch over the course of a release.
I've been looking at the list of modules that don't work with LLD and
investigating.
- Sent some patches upstream to add some missing features needed by
Android such as --keep-unique
[Other]
Reviewed some patches for LLD and MC
Sent a patch upstream for support of the "S" constraint in AArch64
inline assembly.
Progress: [short week, 3 days]
* VIRT-65 [QEMU upstream maintainership]
+ code review
- RTH's FP16 bugfixing patchset
- Alex's float-to-float conversion patchset
- fixes to SD card CRC checking
- various minor linux-user cleanups
* VIRT-164 [improve Cortex-M emulation]
+ working on emulation of Memory Protection Controller: have a working
prototype that needs a few loose ends tidied up
thanks
-- PMM
Hi, Maxim
Do we have any build for native aarch64 toolchain GCC 7.3?
I checked snapshots.linaro.org:
https://snapshots.linaro.org/components/toolchain/gcc-linaro/7.3-2018.04/
But it only has x86 versions.
Somebody pinged me from the 96boards community to ask for that. He
asked for GCC 7.3. What being used in ERP 17.12, as I checked, is GCC
6.3.
Thank you very much.
Best regards,
Guodong Xu
Progress:
[Upstream]
* Push tcg patch queue
* Posted v2 of ARMv8.2-FP16 fixes
[VIRT-243 # ARMv8.1-Atomic instructions ]
* Posted v3 of the patch set.
Passes the gcc testsuite.
[VIRT-198 # QEMU: SVE Emulation Support ]
* I now have a set of gcc testsuite failures
that are unequivocally SVE vector issues.
r~
o 2 days off
== Progress ==
o GNU releases
* Some support to MM.
* Monthly snapshots deployed.
o LLVM
* Benchmarking job still on-going
* Investigating Thumbv8 bot failures
o Misc
* Various meetings and discussions.
[Activity]
[TCWG-1384]
- Implemented missing TLS LE relocations in LLD
- Found out while testing that LLVM had the range check in locally
resoloved fixups for Thumb2 BL wrong, and was not range checking B.w
or Bcc.W at all. Patches submitted for review.
[LLD]
- Submitted extra test cases to improve code-coverage
- Arm LLD 2 stage build-bot including test suite now configured
(thanks Maxim!), will be active upstream soon.
- Started to think about how ICF could be implemented in clang
-- Should be able to make a prototype using clang libtooling
[TCWG-1236]
- Added aarch64 emulation used by Android to LLD
- Tried and failed to get Android to boot when using LLD, narrowed
down the number of modules that could be problematic but I think that
the main symptom is dlopen failing on some modules.
- Found that Google have added LLD support to the Android build system
with a very slightly tweaked version of LLD. This will successfully
boot Android. The main differences are:
-- Google's LLD is a few weeks behind trunk.
-- They have reverted a couple of patches that add undefined symbols
from Shared Objects and allow these to resolve against static
libraries. These patches are correct and I think it is just exposing
some library dependency problems in Android.
-- They are setting -zmax-page-size to 4K on AArch64, LLD defaults to 64K.
--- Android dynamic linker does use 4K page size, but Gold still
seems to use a 64K max page size and I can't see why overaligning
would cause problems.
-- A handful of modules have LLD disabled.
[Plans]
- Investigate differences in trunk and Google Android LLD to see if I
can pinpoint why trunk is failing to boot Android.
- Start to build a prototype with libtooling that records when the
address of a function/member-function/lambda is taken.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ code review:
- RTH's v8.1 atomics emulation patchset
- bugfix to cmsdk UART model
- bugfix to MPUIR access check for OMAP/StrongARM emulation
- Alex's float-to-float conversion refactoring
- SMMUv3 now fully reviewed and in target-arm.next
+ tracked down a bug in our handling of "DUP" vector instruction
that turned out to be in the new x86 codegen backend that tries
to use MMX instructions and wasn't quite getting it right. Patch sent.
* VIRT-164 [improve Cortex-M emulation]
+ working on emulation of Memory Protection Controller; I think we can
do this neatly using QEMU's IOMMU emulation framework, but it needs
some improvements to the framework to make that work:
- feed memory transaction attributes to the IOMMU translate function
so it can use secure/nonsecure attribute to make decisions
- allow TCG code to handle accessing data and executing from RAM
that's on the far side of an IOMMU (currently it asserts if you
set up a system with an IOMMU in the CPU's data path)
I have some prototype patches that deal with these and use them in an MPC
model, which need debugging.
thanks
-- PMM
- Off Tuesday (May 1st)
== Progress ==
* GCC
- FDPIC
- GCC: updating patches to handle new target name: lots of
testsuite and target libs configure changes needed.
- QEMU: patches merged in master, thanks to Peter's reviews.
* GCC upstream validation:
- reported a few new failures/regressions
* Infrastructure:
- patch reviews
- stopped trying to use TK1s until they are back in Jenkins
- cleanup
- tcwg-1404: small patches to prepare use of slaves outside our VPN
* misc (conf-calls, meetings, emails, ....)
== Next ==
* very short week (only Monday)
* FDPIC:
- GCC continue cleanup
* GCC upstream validation
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2018.04
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.3+svn259627 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2018.05 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.3-2018.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.3+svn259627
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn259634 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the next maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2018.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn259634
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
* Short week - a public holiday
* Return jump function
- Writing up issues with test cases for upstream discussion based on
the ipa-cp implementation
* LLVM astar regression
- Trying to reproduce with trunk LLVM vs trunk gcc
- Clang build fails in tx1 (likely due to not enough memory ?)
- Set it up on dev-01. I see about ~2% difference. The difference
goes away when I use -fno-devirtualize-speculative. This suggests the
issue is still present. Perf results are also consistent with this.
- Reducing a self-contained test case
== Progress ==
o GNU releases
* Various support on process and infra.
o LLVM
* Benchmarking job on-going
* Buildbots baby-sitting
* Completed EuroLLVM feedback
* Created ticket: outliner support on ARM
After internal and upstream discussions.
o Misc
* Various meetings and discussions.
Progress:
[Upstream]
Patch set posted implementing some missing ARMv8.2-FP16 instructions.
I believe Alex has gone back to double check if there are any more.
[VIRT-243]
Initial patch posted for the ARMv8.1-Atomics extension.
Looking at the summary from Friday night's test run suggests there are
errors; I'll be looking at those next week.
r~
Activity:
[TCWG-1384] Add support for missing TLS local exec relocations tl LLD
Have an implementation ready to go upstream next week. In process
found that Gold and BFD disagreed on test output. Turns out that there
was a bug in BFD, reviewed Renlin Li's patch for it. Took rather more
of my time than I expected.
[TCWG-1375] Set 4 patches upstream to complete the removal of the
global subtarget
No response as yet.
Raised https://bugs.llvm.org/show_bug.cgi?id=37212 clang and gcc are
producing technically illegal ELF for debug information (references to
local symbols defined in comdat groups), both gold and bfd have
special case code to handle this case, lld does not. Leads to loss of
debug illusion for templated and inlined C++ functions.
Other
- Some research into how spec files and multilib works in gcc to see
how it could fit into clang's driver model.
- Joined the ELF ABI google group to fulfil a promise I'd made at Euro
LLVM to comment on a thread about debug information in comdat groups.
Holiday on Tuesday
Plans:
- Ping reviews.
- Push fix for TCWG-1384 upstream alongside some refactoring patches.
- Add some more tests to LLD to close some holes in the code-coverage
statistics.
- Continue looking at laundry list of small LLD changes.
- Get back to building Android.