== Progress ==
* Out of office on Friday [2/10]
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039] [2/10]
- Committed G_FPOW and G_FADD upstream
- Most of the other soft float libcalls are just a matter of boilerplate
* [GlobalISel] Investigate divmod [TCWG-1086] [5/10]
- Working on a patch to support G_(S|U)REM in GlobalISel
- Found an inconsistency in DAGISel, sent a patch upstream
* Misc [1/10]
- Mailing lists, meetings
- Buildbot monitoring (did a bisection, reverted a few patches)
== Plan ==
* Out of office on Monday
* Send patch for TCWG-1086
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.04 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.3+svn246668 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246668
* Backport of [Bugfix] [AArch32] PR target/71436: Restrict
*load_multiple pattern till after LRA
* Backport of [Bugfix] [AArch32] PR target/79911: Invalid vec_select arguments
* Backport of [Bugfix] [AArch64] PR target/79889: Error message on
target attribute on aarch64
* Backport of [Bugfix] [AArch64] PR target/79913: VEC_SELECT bugs in
aarch64 patterns
* Backport of [Bugfix] [AArch64] PR target/79925: tweaks to quoting in
error messages
* Backport of [AArch32] Fix small multiply feature
* Backport of [AArch64] Enable AES fusion with -mcpu=generic
* Backport of [AArch64] Fix bootstrap due to wide_int .elt (0) uninit warning
* Backport of [AArch64] Fix incorrect INS in SIMD mov pattern
* Backport of [AArch64] Fix search_line_fast for aarch64/ILP32
* Backport of [AArch64] Fix typo in aarch64.opt (dummping -> dumping)
* Backport of [AArch64] Improve cost model for ThunderX2 CN99xx
* Backport of [AArch64] Improve generic branch cost
* Backport of [AArch64] more poly64 intrinsics and tests
* Backport of [AArch64] Use 'x' constraint for vector HFmode
multiplication by indexed element instructions
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn246667 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the next
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2017.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.4+svn246667
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1] Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2] Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [4/10] Release branch is not created,
but test result
looks good.
** Fix PR 19942, patch v2 is OK. Need to fix some nits before check
in.
** Intel btrace python interface discussion. Good to see that Intel
people accept my suggested new interface, and finalize the details of
the new interface.
* TCWG-1040, Review SVE patches. [4/10]
The overall goal is to remove MAX_REGISTER_SIZE.
Reviewed some Alan's patches, and wrote two patches to remove
MAX_REGISTER_SIZE in frame.c and regcache.c.
* Misc, meeting, [2/10]
~ Plan ~
* More remote tests for GDB 8.0 release.
* SVE patches review, and start to think about GDB target description
changes for SVE.
* Public holiday on Friday and next Monday.
--
Yao Qi
== Progress ==
[TCWG-614] Long Range Thunks
- Posted for upstream review. I may have to do some refactoring of the
address allocation first to unify the linker-script and non
linker-script cases.
- Started work on a prototype that fabricates linker script commands
for the default non linker-script case. Failing 7 tests of 1007 and it
is a mess so some work to do here.
[TLS] Fixed recent breakage in ARM TLS caused by change in the way
that values are written to the GOT.
== Plans ==
Progress the prototype address allocation far enough to post upstream
for comment, I think that this is likely to take a few iterations to
get right.
== Planned Absences ==
ACCU 2017 27-29 April
== This Week ==
* TCWG-1005 (6/10)
- All ICE's resolved with firefox -;)
- Few improvements still left - handling indirect calls, handle cases
when return value from malloc'd function has more than single use.
* Validation (1/10)
- patch for adding --set buildconfig option to abe
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Get back to TCWG-1010 (bitwise-dce)
- Validation
== Progress ==
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][3/10]
- Ran more tests and reported the results upstream
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
- Started supporting G_FREM and G_FPOW, which are already handled by
the target-independent code
- Committed G_FREM upstream, G_FPOW is ready to commit first thing next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Moved llvm-helper-scripts
* Misc [3/10]
- Mailing lists, code reviews, meetings
== Plan ==
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
=== This Week ===
GDB Kernel Awarenes - Kernel Dump setup for ARM [9/10]
-- Background study on kdump and try to find working steps for QEMU ARM.
-- There is a problem with kdump-tools install script with QEMU
-- Tried building kernel for Raspberry Pi2 and Pi3 with kdump, no
success so far.
-- Setup B2260 with debian and try kdump setup
-- Setup and kernel config successful but kdump couldn't configure
-- Tried the same with HiKey board
Miscellaneous Activities [1/10]
-- Meetings, Emails etc.
=== Next Week ===
GDB Kernel Awarenes
-- Start merging Peter's and IBM patches
-- Look around for help on Kdump setup.
== This Week ==
* TCWG-1005 (6/10)
- Fixed firefox ICE
- Unfortunately that gives rise to another ICE with ipa-icf pass :(
Investigating if this
caused by the patch or a latent bug in ipa-icf.
- Builds well with chromium
* Validation (1/10)
- abe/extraconfig patches
- backport review
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
~ Progress ~
* TCWG-1050, GDB 8.0 release. [7/10]
** Fix PR 19942, but looks my patch is completely wrong as I fully
misunderstood the "reference count" in GDB. Writing the v2.
** Intel btrace python interface discussion, a marathon discussion
about both the interface and implementation. Good thing is that we
agree that we need to change the interface. This takes most of my
time this week.
* TCWG-1040, Review SVE patches. [2/10]
Some discussions on avoid copying register contents to a local buffer
again, which is from my review comments to Alan's patch and my
suggested patch. Spend some time on understanding the zero
initialization of union in C++. I'll update my suggested patch.
* Update AArch32 GDB buildbot option, so we can get more reasonable
test result. [1/10]
~ Plan ~
* More remote tests for GDB 8.0 release.
* Fix PR 19942.
* One day off on Thu.
--
Yao Qi
[Eurollvm]
Attended, we have recorded our thoughts in EuroLLVM 2017 Recap doc
[TCWG-614] Range extension thunks
- I've finished my downstream implementation, and have written almost
all the lld tests I'd like to write
- Still need to test on real large programs such as libclang.so
- Made a start at breaking down the implementation into smaller
patches that can be sensibly upstreamed
Plans for next week
[TCWG-614]
- Aiming to start upstreaming on Monday, I'm expecting this to be
quite a drawn out process
- Continue testing on ARM Linux
Planned Absences
ACCU conference 2017 27-29 April
== Progress ==
* Validation
- helped with new llvm build scripts and jobs
- improvements to container scripts to cope with llvm's higher needs
in resources
- improved tcwg-regression tests
- various to remove dependencies on env variables
- comparison script now reports the associated .exp file name,
making it easier to reproduce a regression
- experimented with lava
- started work on benchmarking scripts
* GCC
- keeping an eye on trunk regressions
- update to qemu-2.8.0 introduced regressions in validation for
armeb on some atomic tests
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation:
- hopefully nothing :)
* Benchmarking:scripting
== Progress ==
* EuroLLVM trip [6/10]
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][2/10]
- Apple wants to switch the default O0 to GlobalISel for AArch64, so
we need to run tests and gather metrics
- I'm running the test-suite and selfhost with GlobalISel to see how
it performs
* Misc [2/10]
- Mailing list, code reviews, meetings, herding GlobalISel cats
(we're trying to open more communication channels with Apple so we can
unblock progress)
== Plan ==
* Wrap up TCWG-1074
* Learn more TableGen and do more code review
Hello all,
I've been using GCC 4.9.4 for a while now (arm-linux-gnueabi-gcc (Linaro
GCC 4.9-2017.01) 4.9.4), and I found this strange behavior:
In the library header (libm5op.h):
-----
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run);
#ifdef __cplusplus
}
#endif
-----
In the library C file (m5op_arm_.c):
-----
#include "stdio.h"
#include <stdlib.h>
#include "libm5op.h"
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run)
{
// Code here using args
}
-----
The code above is in
/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ and compiled as a
library with GCC 6.3.1 and is ok:
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -O3
-fno-optimize-sibling-calls -c m5op_arm_.c -o m5op_arm_.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c m5op_arm.S -o m5op_arm.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-ar
rcs libm5op32.a m5op_arm_.o m5op_arm.o
The library is used in a source code compiled with the GCC 4.9.4 describe
at the begining.
In the C file:
-----
#include <libm5op.h>
S_regmatch(pTHX_ regnode *prog)
{
warm_and_run_(161, 818);
// Code continues
}
------
This source is compile with:
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c -o regexec.o -DSPEC_CPU -DNDEBUG -DPERL_CORE -static -marm
-march=armv7-a - mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat-abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/ SPEC_CPU2006v1.1-aarch64/m5op/
-DGEM5_ARM32=1 -DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 regexec.c
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-static -marm -march=armv7-a -mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat- abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ -DGEM5_ARM32=1
-DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 av.o deb.o doio.o doop.o
dump.o globals.o gv.o hv.o locale.o mg.o numeric.o op.o pad.o perl.o
perlapi.o perlio.o perlmain.o perly.o pp.o pp_ctl.o pp_hot.o pp_pack.o
pp_sort.o pp_sys.o regcomp.o regexec.o run.o scope.o sv.o taint.o toke.o
universal.o utf8.o util.o xsutils.o Base64.o Cwd.o Dumper.o HiRes.o IO.o
Peek.o attrs.o poll.o stdio.o DynaLoader.o MD5.o Storable.o Parser.o
specrand.o Hostname.o Opcode.o -lm -lm5op32 -lm5op32 -o
perlbench
Finally, the assembled code of S_regmatch has:
-----
af2d0: e3a000a1 mov r0, #161 ; 0xa1
af2d4: e3001332 movw r1, #818 ; 0x332
af2d8: e58d3018 str r3, [sp, #24]
af2dc: e58d2028 str r2, [sp, #40] ; 0x28
af2e0: fa02615c blx 147858 <warm_and_run_>
-----
So, this means that warm_and_run_ is assumed by GCC 4.9.4 to have 32 bits
arguments, while they are indeed 64 bits. This seems to be a bug for me.
The code in the library is correctly allocating 2*32 bits regs for each
argument.
For now, I'm using int32_t, and I just thought it could be useful to
feedback you guys.
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
== Progress ==
* Validation
- finally merged most of work of the past weeks
- main jobs are now using start-container scripts
- helped with new llvm build scripts and jobs
- abe initial config for gcc7: need to investigate a binutils build
problem in a trusty container
- improved tcwg-regression tests, identified a regression for bug-2123
- many validation-related patches to review
* GCC
- reported a regresion upstream
* misc (conf-calls, meetings, emails, ....)
- started discussing benchmarking
== Next ==
* Validation:
- a few patches pending review (to improve reports, debug-ability of
containers, ...)
- work on a new proposal to upgrade our qemu
- probably more cleanup needed in the jobs (slaves, basedir scm option, ...)
- improve tcwg-regression
- boot kernel after build
* Benchmarking: start to contribute
== Progress ==
o Linaro GCC/Validation (6/10)
* Validation/Infra patch reviews
* Upstream monitoring job
* Release automation:
- Reworking tcwg-release.sh
o Misc (4/10)
* Various meetings and discussions.
== Plan ==
o Focusing on release automation and validation
Achievements:
[TCWG-614] Range extension Thunks
- About 3 hours in total of rebasing due to upstream refactoring
- Have finished the non-linkerscript tests and fixed all the bugs
detected by them
- Started the linkerscript tests, no problems found so far
[TLS]
- Some explanation to upstream of how ARM TLS works
- Discovered that upstream have broken TLS global-dynamic for
executables, I have a fix but will need to write a test case.
Plans for next week:
- Euro LLVM Monday, Tuesday
- Continue with TCWG-614
-- Try and link clang (> 30 Mb) to test range thunks on some real programs
-- Aim to get something ready for upstream review by end of week, may
slip to beginning of next week depending on if I find any hard to
debug problems.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [6/10]
** Pushed a fix to AArch64 process record bug on PRFM instruction.
AArch64 native test looks good now.
** Start to look at ARM native test, triage the fails in
watch-bitfields.exp. Test doesn't fail on old Linux kernel, likely
a kernel bug. Further analysis is needed.
** Request reverting Intel btrace python interface before release, as
they are too btrace-specific.
** Fixing a bug about thread_info refcount issue. Testing the patch.
* Discussion on RTOS awareness in debugging. OpenOCD people want GDB
aware more about different RTOSes. [1/10]
* TCWG-1040, SVE patches review, [2/10]
* Misc, [1/10]
~ Plan ~
* Take a look at native ARM testing, and cross testing.
* Post my fix to thread_info refcount issue.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037] [3/10]
- Got some patches ready but they depend on the TableGen support for
predicates, which has not been committed upstream yet
* [GlobalISel] Use proper calling conv for calls [TCWG-1051] [1/10]
- Patch accepted upstream, will commit next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Started migrating tcwg-release-tools to Python 3, still in progress
* Misc [5/10]
- Mailing lists, code reviews, buildbot monitoring, catching up after Connect
- LLVM social in Stockholm
- Fiddling with the new container for our LLVM buildmasters
== Plan ==
* Commit TCWG-1051, maybe TCWG-1037 too depending on upstream progress
* More GlobalISel code reviews
* TCWG-896
* Out of office for EuroLLVM (24 - 29 March)
[TCWG-614] Range extension Thunks
Worked all week on this. I've got a prototype that is nearly feature
complete. It passes the existing tests when run in a single pass. I'm
now trying to get it to run in multiple passes.
Plans
[TCWG-614] Range extension Thunks
Start adding tests for the new functionality and doubtless spending a
lot of time fixing problems. If I'm lucky I may have something that I
can at least in part send upstream for review by the end of the week.
~ Progress ~
* Three days off [6/10]
* TCWG-1050, GDB 8.0 release. [2/10]
Pushed in some patches fixing ARM reverse debugging bug.
Investigating a GDB internal error.
Review Python btrace stuff, still trying to make it more generic.
* Misc, [2/10], catch up emails
~ Plan ~
* TCWG-1050.
* Review IBM linux kernel awareness patches.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.03 snapshot of the Linaro GCC 6 source package.
This monthly snapshot[1] is based on FSF GCC 6.3+svn246148 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246148
* Backport of [Bugfix] [AArch64] PR target/71112 ICE with -fpie on
aarch64 ILP32 big-endian
* Backport of [Bugfix] [AArch64] PR target/71727 -O3 -mstrict-align
produces code which assumes unaligned vector accesses work
* Backport of [Bugfix] [AArch64] PR target/78382 ICE when compiling on
aarch64 in ILP32 mode with traditional thread local storage and pic
* Backport of [AArch32] Add vfpv2 and neon-vfpv3
* Backport of [AArch32] Fix assembly comment syntax in -mprint-tune-info
* Backport of [AArch64] Add commandline support for -march=armv8.3-a
* Backport of [AArch64] Expand DImode constant stores to two SImode
stores when profitable
* Backport of [AArch64] Fix aarch64 PGO bootstrap
* Backport of [AArch64] Fix exception handling for ILP32 aarch64
* Backport of [AArch64] Have the verbose cost model output output be
controllable
* Backport of [AArch64] Implement popcount pattern
* Backport of [AArch64] Optimized implementation of search_line_fast
for the CPP lexer
* Backport of [AArch64] Use new target pass registration framework for
FMA steering pass
* Backport of [Testsuite] [AArch32] Add Cortex-A15 tuning to
gcc.dg/uninit-pred-8_a.c
* Backport of [Testsuite] [AArch32] Skip optional_mthumb tests if GCC
has a default mode
* Backport of [Testsuite] [AArch32] Updating testcase unsigned-extend-2.c
* Backport of [Testsuite] [AArch64] Fix
gcc.dg/torture/float32-builtin.c with RTL checking
* Backport of [Testsuite] [AArch64] PR middle-end/78142 more registers
to be used for on gcc.target/aarch64/vector_initialization_nostack.c
* Backport of [Cleanup] [AArch32] Define arm_arch_core_flags in a single file
* Backport of [Cleanup] [AArch32] Remove unimplemented option -macps-float
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
