=== This Week ===
Monitor LLDB buildbot for minimum down time. [TCWG-712] [1/10]
-- LLDB Arm build was broken and then fixed upstream but a buildbot script bug.
-- Fixed buildbot script to make sure not every type of build is
refreshed after a breakage.
Investigate LLDB testsuite failures on Pine64 target (AArch32 and
AArch64 modes) [TCWG-1012] [3/10]
-- Investigated and fixed TestRegisterVariables
(https://reviews.llvm.org/D28666)
-- Fixed a log issue which I initially thought was a bug.
(https://reviews.llvm.org/rL291889)
-- No further AArch64 failures except for one test timedout needs
further investigation.
-- Some tests fail randomly on AArch32 but pass when run individually.
More investigation needed.
LLDB Arm/AArch64 Investigate and fix testsuite crashes (Pine64
Crashes) [TCWG-792] [2/10]
-- There was some problem occuring when multiple versions of python
are installed on tester.
-- Also some tests are leaving behind runaway processes.
-- Cleaned up testers removed python issue ended up reducing test time
to 3 minutes.
-- Trying to track runaway processes.
Miscellaneous Activities [4/10]
-- Travel to Islamabad for Hungary visa interview (9th-10th Jan 2017).
-- Meetings, Emails etc.
=== Next Week ===
ARM/AArch64 hardware breakpoints [TCWG-717]
-- Investigate current status and create task breakdown.
Investigate LLDB testsuite failures on Pine64 target (AArch32 and
AArch64 modes) [TCWG-1012]
-- Further tracking on runaway processes when running AArch32 testsuite.
-- Investigation of timedout tests on AArch64.
o Teaching activity (4/10)
== Progress ==
o Linaro GCC/Validation (4/10)
* Merge FSF GCC 6 branch into Linaro one
* Backports reviews
* Delivered snapshot of 6.3-2017.01 source package
* Merge FSF 4.9 branch into Linaro one
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Last GCC 4.9 snapshot
o GCC 5.4 release
[TCWG-614] Long branch thunks:
Implemented a prototype of the existing Thunk implementation using
Synthetic (Linker created sections) and moved it close to the area it
will need to go for Long Branch Thunk work.
Worked on this exclusively all week.
Plans for next week:
[TCWG-614] Long branch thunks:
Tidy up and refactor prototype to a point where I can post for
upstream review. This won't be long-branch thunk support but it will
be a significant intermediate step.
Do a draft plan of Connect submission and decide how long I need.
== Progress ==
* [ARM] Use AddDefaultPred everywhere [TCWG-987] [1/10]
- Proposed a refactoring first [TCWG-1015]
- Rebased initial patch after the refactoring, still waiting for review
* Refactor AddDefaultPred [TCWG-1015] [4/10]
- Initial implementation was a bit heavyweight, so I worked on a
simpler version based on people's suggestions
- Committed upstream
* Misc [5/10]
- Got up to speed after vacation
- Booked travel for Connect and EuroLLVM
- FOSDEM slides
- Upstream code reviews
- Reverted and ran pre-commit tests for some compiler-rt patches
that broke the buildbots
== Plan ==
* 3 days off (Mon-Wed)
* [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980]
- I have 3 patches in upstream review, I will keep pinging them
- Putting GlobalISel work on hold until these patches go through
~ Progress ~
* TCWG-984 Handle exception/error in disassembly, [4/10]
Patches are posted and reviewed. Three patches to opcodes
are approved and committed. V2 is done to address comments
on C++ and unit tests. V2 are being tested.
* Patches review, [4/10]
** Review some preparatory SVE patches from Alan.
They are good to me, but I expect Joel or someone else to take a look
as well.
** Linux kernel awareness debugging.
Review the patch sent from linaro, but some one from IBM sends
a similar patch series. These two patch sets look similar, but are
different on some parts.
* Conversation with Paul (openocd maintainer) on irc. [1/10]
They really want me to look at some gdb+openocd issues. My Hikey
will arrive soon, but they give me some explanations on why cortex-m
board is better than cortex-a board in bare-metal, because of
simplicity. I explained to them why Linaro focused on cortex-a
devices so far.
* Linaro Connect. [1/10]
Register the connect, book flight and hotel.
~ Plan ~
* TCWG-984 and TCWG-333
* Carefully read Dave M's SVE user space VL control API.
* Carefully read IBM's kernel debugging patches.
--
Yao Qi
== This Week ==
* TCWG-1005 (malloc attr propagation) (6/10)
- Worked through bootstrap failures
- Patch found 35 functions that could have malloc attribute during gcc build
- The current analysis to find candidate functions is too restrictive, working
on improving that.
- Wrote few test-cases.
* TCWG-1006 (returns_nonnull attr propagation) (2/10)
- WIP prototype patch
* TCWG-1010 (bitwise-dce) (1/10)
- Going thru demanded-bits analysis
* Misc (1/10)
- Meetings
== Next Week ==
- Continue working on TCWG-1005, TCWG-1006 and TCWG-1010
== Progress ==
* Validation
- improvements and bug fixes:
ABE #2764. and make_docs problem for gcc-4.9 builds)
Enhanced abe validation to check builds of
gcc-4.9, 5 and 6.
make-and-test-release now works.
buildbench now works
* GCC
- Committed fix for pr78253
- discussions on releases (packaging, process improvements)
- a few backports for our 6.2-2017.01 snapshot
* misc (conf-calls, meetings, emails, ....)
- bugzilla followup
- moving from ex40-01 to dev-01
- Connect registration: on-going
== Next ==
* ABE & Jenkins jobs patches reviews and bug fixes
* GCC:
- bug fixing
Thanks guys, that was it.
I did not realize the build system was omitting the flags.
On Fri, Jan 13, 2017 at 2:23 AM, Pinski, Andrew
<Andrew.Pinski(a)cavium.com> wrote:
> Can you try -march=armv8+crypto ?
>
> -----Original Message-----
> From: linaro-toolchain [mailto:linaro-toolchain-bounces@lists.linaro.org] On Behalf Of Jeffrey Walton
> Sent: Thursday, January 12, 2017 10:56 PM
> To: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>
> Subject: Does Linaro's GCC 4.9 include Crypto extensions and intrinsics?
>
> Please forgive my ignorance. I'm working on a Pine64 dev-board Pine64 supplies Linaro's GCC 4.9.2 toolchain.
>
> I am catching a compile error, and I am trying to determine why.
>
> Does Linaro's GCC 4.9 provide AES and SHA intrinsics?
Please forgive my ignorance. I'm working on a Pine64 dev-board Pine64
supplies Linaro's GCC 4.9.2 toolchain.
I am catching a compile error, and I am trying to determine why.
Does Linaro's GCC 4.9 provide AES and SHA intrinsics?
**********
$ uname -a
Linux pine64 3.10.102-2-pine64-longsleep #66 SMP PREEMPT Sat Jul 16
10:53:13 CEST 2016 aarch64 GNU/Linux
$ gcc --version
gcc (Debian/Linaro 4.9.2-10) 4.9.2
Copyright (C) 2014 Free Software Foundation, Inc.
**********
$ CFLAGS="-DMBEDTLS_HAVE_ARMV8A_CE=1" make DEBUG=1 V=1
CC aes_armv8a_ce.c
aes_armv8a_ce.c: In function 'mbedtls_armv8a_ce_aes_crypt_ecb':
aes_armv8a_ce.c:65:4: warning: implicit declaration of function
'vaeseq_u8' [-Wimplicit-function-declaration]
state_vec = vaeseq_u8( state_vec, roundkey_vec );
^
aes_armv8a_ce.c:65:14: error: incompatible types when assigning to
type 'uint8x16_t' from type 'int'
state_vec = vaeseq_u8( state_vec, roundkey_vec );
^
aes_armv8a_ce.c:67:4: warning: implicit declaration of function
'vaesmcq_u8' [-Wimplicit-function-declaration]
state_vec = vaesmcq_u8( state_vec );
^
aes_armv8a_ce.c:67:14: error: incompatible types when assigning to
type 'uint8x16_t' from type 'int'
state_vec = vaesmcq_u8( state_vec );
^
aes_armv8a_ce.c:74:13: error: incompatible types when assigning to
type 'uint8x16_t' from type 'int'
state_vec = vaeseq_u8( state_vec, roundkey_vec );
^
aes_armv8a_ce.c:84:4: warning: implicit declaration of function
'vaesdq_u8' [-Wimplicit-function-declaration]
state_vec = vaesdq_u8( state_vec, roundkey_vec );
^
aes_armv8a_ce.c:84:14: error: incompatible types when assigning to
type 'uint8x16_t' from type 'int'
state_vec = vaesdq_u8( state_vec, roundkey_vec );
^
aes_armv8a_ce.c:86:4: warning: implicit declaration of function
'vaesimcq_u8' [-Wimplicit-function-declaration]
state_vec = vaesimcq_u8( state_vec );
^
aes_armv8a_ce.c:86:14: error: incompatible types when assigning to
type 'uint8x16_t' from type 'int'
state_vec = vaesimcq_u8( state_vec );
^
aes_armv8a_ce.c:93:13: error: incompatible types when assigning to
type 'uint8x16_t' from type 'int'
state_vec = vaesdq_u8( state_vec, roundkey_vec );
^
aes_armv8a_ce.c: In function 'mbedtls_armv8a_ce_gcm_mult':
aes_armv8a_ce.c:138:2: warning: implicit declaration of function
'vmull_high_p64' [-Wimplicit-function-declaration]
r1 = (uint8x16_t)vmull_high_p64( (poly64x2_t)a_p, (poly64x2_t)b_p );
^
aes_armv8a_ce.c:138:2: error: can't convert between vector values of
different size
aes_armv8a_ce.c:141:2: error: can't convert between vector values of
different size
t0 = (uint8x16_t)vmull_high_p64( (poly64x2_t)a_p, (poly64x2_t)t0 );
^
aes_armv8a_ce.c:150:2: error: can't convert between vector values of
different size
t0 = (uint8x16_t)vmull_high_p64( (poly64x2_t)r1, (poly64x2_t)p );
^
Makefile:170: recipe for target 'aes_armv8a_ce.o' failed
make[1]: *** [aes_armv8a_ce.o] Error 1
Makefile:17: recipe for target 'lib' failed
make: *** [lib] Error 2
**********
CC sha1_armv8a_ce.c
sha1_armv8a_ce.c: In function 'mbedtls_armv8a_ce_sha1_process':
sha1_armv8a_ce.c:99:2: warning: implicit declaration of function
'vsha1h_u32' [-Wimplicit-function-declaration]
e1 = vsha1h_u32( a );
^
sha1_armv8a_ce.c:100:2: warning: implicit declaration of function
'vsha1cq_u32' [-Wimplicit-function-declaration]
abcd = vsha1cq_u32( abcd, e, wk0 ); /* 0 */
^
sha1_armv8a_ce.c:100:7: error: incompatible types when assigning to
type 'uint32x4_t' from type 'int'
abcd = vsha1cq_u32( abcd, e, wk0 ); /* 0 */
^
sha1_armv8a_ce.c:102:2: warning: implicit declaration of function
'vsha1su0q_u32' [-Wimplicit-function-declaration]
w0 = vsha1su0q_u32( w0, w1, w2 );
^
sha1_armv8a_ce.c:102:5: error: incompatible types when assigning to
type 'uint32x4_t' from type 'int'
w0 = vsha1su0q_u32( w0, w1, w2 );
^
sha1_armv8a_ce.c:106:7: error: incompatible types when assigning to
type 'uint32x4_t' from type 'int'
abcd = vsha1cq_u32( abcd, e1, wk1 ); /* 1 */
^
sha1_armv8a_ce.c:108:2: warning: implicit declaration of function
'vsha1su1q_u32' [-Wimplicit-function-declaration]
w0 = vsha1su1q_u32( w0, w3 );
^
sha1_armv8a_ce.c:108:5: error: incompatible types when assigning to
type 'uint32x4_t' from type 'int'
w0 = vsha1su1q_u32( w0, w3 );
^
sha1_armv8a_ce.c:109:5: error: incompatible types when assigning to
type 'uint32x4_t' from type 'int'
w1 = vsha1su0q_u32( w1, w2, w3 );
^
...
**********
$ grep -IR vaeseq_u8 /usr/include
/usr/include/clang/3.5.0/include/arm_neon.h:__ai uint8x16_t
vaeseq_u8(uint8x16_t __p0, uint8x16_t __p1) {
/usr/include/clang/3.5.0/include/arm_neon.h:__ai uint8x16_t
vaeseq_u8(uint8x16_t __p0, uint8x16_t __p1) {
/usr/include/clang/3.5/include/arm_neon.h:__ai uint8x16_t
vaeseq_u8(uint8x16_t __p0, uint8x16_t __p1) {
/usr/include/clang/3.5/include/arm_neon.h:__ai uint8x16_t
vaeseq_u8(uint8x16_t __p0, uint8x16_t __p1) {
$
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.01 snapshot of the Linaro GCC 6 source package.
This monthly snapshot[1] is based on FSF GCC 6.3+svn244220 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.02
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn244220
* Backport of [Bugfix] Fix PR77673: bswap loads passed end of object
* Backport of [ARMv8-M] [AArch32] 1/7 Move memory model declarations
in memmodel.h
* Backport of [ARMv8-M] [AArch32] 2/7 Adapt atomic and exclusive load
and store to ARMv8-M Baseline
* Backport of [ARMv8-M] [AArch32] 3/7 Refactor atomic compare_and_swap
to make it fit for ARMv8-M Baseline
* Backport of [ARMv8-M] [AArch32] 4/7 Adapt atomic compare and swap to
ARMv8-M Baseline
* Backport of [ARMv8-M] [AArch32] 5/7 Adapt other atomic operations to
ARMv8-M Baseline
* Backport of [ARMv8-M] [AArch32] 7/7 Enable ARMv8-M atomic and
synchronization support for ARMv8-M Baseline
* Backport of [ARMv8-M] [AArch32] Added support for ARMV8-M Security
Extension cmse_nonsecure_caller intrinsic
* Backport of [ARMv8-M] [AArch32] Add multilib mapping for Cortex-M23
& Cortex-M33
* Backport of [ARMv8-M] [AArch32] Add support for ARM Cortex-M23 processor
* Backport of [ARMv8-M] [AArch32] Add support for ARM Cortex-M33 processor
* Backport of [ARMv8-M] [AArch32] Add support for ARMv8-M's Secure
Extensions flag and intrinsics
* Backport of [ARMv8-M] [AArch32] ARMv8-M Security Extension's
cmse_nonsecure_call: use __gnu_cmse_nonsecure_call
* Backport of [ARMv8-M] [AArch32] ARMv8-M Security Extension's
cmse_nonsecure_entry: __acle_se label and bxns return
* Backport of [ARMv8-M] [AArch32] ARMv8-M Security Extension's
cmse_nonsecure_entry: clear registers
* Backport of [ARMv8-M] [AArch32] Fix various arm failures with config-list.mk
* Backport of [ARMv8-M] [AArch32] Force soft float in ARMv6-M and
ARMv8-M Baseline options
* Backport of [ARMv8-M] [AArch32] Handling ARMv8-M Security
Extension's cmse_nonsecure_call attribute
* Backport of [ARMv8-M] [AArch32] Handling ARMv8-M Security
Extension's cmse_nonsecure_entry attribute
* Backport of [ARMv8-M] [AArch32] Make arm_feature_set agree with type
of FL_* macros
* Backport of [ARMv8-M] [AArch32] Optional -mthumb for Thumb only targets
* Backport of [AArch64] 1/3 Add missing Poly64_t intrinsics to GCC
* Backport of [AArch64] 2/3 Add missing Poly64_t intrinsics to GCC
* Backport of [AArch64] 3/3 Add tests for missing Poly64_t intrinsics to GCC
* Backport of [AArch64] Add more Poly64_t intrinsics to GCC
* Backport of [AArch64] more poly64 intrinsics
* Backport of [Testsuite] [AArch64] Fix failing poly64 tests on ARM
* Backport of [Testsuite] [AArch64] Lower iterator count on
gcc.dg/atomic/c11-atomic-exec-5.c for AARCH64
* Backport of [Cleanup] Improve comment for struct symbolic_number in bswap pass
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
o 1 day off (2/10)
o Teaching activity (4/10)
== Progress ==
o Linaro GCC/Validation (2/10)
* 5.4-2017.01-rc1 release notes and publication
* Some infra bugfixes and reviews
o Misc (1/10)
* Various meetings and discussions.
* Plan for 2017
== Plan ==
o GCC 6 branch merge and snapshot
== Activity ==
- [PR64946] abs vectorization fails for char/short types
* Trying to tackle this with ABSU_EXPR
* Experimented with implemented in FE vs in gimplification
* Hope to get a working prototype this week
- Misc
* gcc-patches/bug list
* Plan for 2017
== Plans for next week ==
- PR64946
- Catch up on pending patches
=== This Week ===
Back from month long holiday had a surgery during this period.
Add Pine64 as tester to LLDB buildbot [TCWG-1011] [3/10]
-- Configure Pine64 with Ubuntu 16.04 image
-- Configure network on Pine64 to be used with LLDB buildbot
-- Configure Pine64 for AArch32 mode execution
-- Configure LLDB buildbot to include Pine64 as tester in both AArch32
and AArch64 modes.
-- Run buildbot with Pine64 and monitor stability
Monitor LLDB buildbot for minimum down time. [TCWG-712]
-- Return from break reset buildbot and testers.
Investigate LLDB testsuite failures on Pine64 target (AArch32 and
AArch64 modes) [TCWG-1012] [2/10]
-- Some tests pass when run individually.
-- Some tests fail only when run in testsuite, similar steps pass when
run using LLDB commandline.
LLDB Arm/AArch64 Investigate and fix testsuite crashes (Pine64
Crashes) [TCWG-792] [1/10]
-- LLDB crashing unexpectedly on Pine64 as well.
-- Initial investigation suggests test run fine individually and in
single thread mode.
Meetings and other Miscellaneous Activities [1/10]
-- Browse through email backlog.
-- Prepared a future ToDo list.
BUD17 Travel - Schengen visa application for Budapest, Hungary. [3/10]
-- Information gathering and correspondance.
-- Form filling and preparation supporting documentation.
-- Application submission.
-- Interview date is on 10th Jan 2017.
=== Next Week ===
Investigate LLDB testsuite failures on Pine64 target (AArch32 and
AArch64 modes) [TCWG-1012]
-- Continue to investigate, possible fix trivial issues and mark rest
as xfail with appropriate bug reports.
LLDB Arm/AArch64 Investigate and fix testsuite crashes (Pine64
Crashes) [TCWG-792]
-- Find a reliable reason to the issue as this hampers our buildbot work.
BUD17 Travel - Schengen visa application for Budapest, Hungary.
-- Budapest visa interview travelling to Islamabad 9 - 10 Jan 2017.
== Activity ==
TCWG-919 Thunks to undefined symbols
Now committed upstream
TCWG-614 Long branch thunks
Sent RFC to llvm-dev
Have a good idea about how to proceed.
First step is to rewrite existing implementation using synthetic sections.
Currently thinking about the best way to do this.
Wrote first draft of Fosdem 2017 presentation
Booked travel for Fosdem
Registered for Linaro Connect
== Plans for next week ==
Linaro TCWG-614 Long branch thunks
Aim to get a patch out for review for thunks as synthetic sections
== Progress ==
* Out of office [2/10]
* [ARM GlobalISel] Use CC support for lowering args/return [TCWG-946] [1/10]
- Brushed up and committed upstream
* [ARM] Use AddDefaultPred everywhere [TCWG-987] [3/10]
- Patches in upstream review
* Misc [4/10]
- Mailing lists, meetings, 2017 objectives
- Code reviews
- FOSDEM slides
- Investigated buildbot failures and reverted some patches (and ran
a precommit on the next version)
== Plan ==
* Vacation until January 9th, 2017
~ Progress ~
* Fix foreign frame problem in C++ exception unwinding. PR 20939. [2/10]
Being discussed. We agreed on the approach fixing the bug. Need a
patch.
Find other issues during the investigation, and fixed them. PR 20953,
PR 20954, and PR 20955 are fixed.
* GDB exception handling is broken on i686-w64-mingw32. PR 20977. [3/10]
In short, we can't use longjmp in SJLJ exception handling. Need post
an RFC.
* Upstream patches review. [5/10]
** SVE GDB patches review.
Carefully read the patches line by line for the first time. Find some
issues on target descriptions, and post my comments upstreams. Hack
GDBserver to get SVE on normal juno board. Need more time to think
about how to move on.
** Review sparc target descriptions.
** 7.12.1 release discussion.
~ Plan ~
* PR 20939, PR 20977.
* On Holiday from Wed.
--
Yao Qi
== Progress ==
o Linaro GCC/Validation (7/10)
* Completed backports
* Merged FSF branches (5 and 6)
* Released 2016.12 source snapshots (5 and 6)
* Closed bugzillas #1925, #2575 and #1963
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o Finish on-going tasks before holiday (Tuesday evening).
Progress:
TCWG-985 PIE on ARM broken
- Now fixed
TCWG-911 Eglibc requires a .ARM.attributes section for dlopen
- Worked around this with a simple hack to retain the first build
attribute section seen. This should suffice for the majority of
use-cases on a host platform using the default compiler. More work is
needed later. Now upstreamed.
TCWG-919 Thunks to undefined symbols
- In upstream review, as expected got some push back, I had hoped to
have resolved this on Thursday and committed today, but no response
last night.
PR31332 X86 pic plt sequences broken
- Worked out a fix, but haven't sent upstream due to needing to spend
quite a bit of time writing tests.
Other:
About 3/4 way of writing up AArch64 Ifunc for possible inclusion in
some public facing documentation.
Got a new blank machine from IT with permission to install linux
myself. Have now built myself a 16.04 machine and got my environment
set up.
Planned absences:
- on holiday for two weeks, back on Tuesday 3rd December
Next year:
- Top priority is long range thunks in lld, followed by an ARM lld build bot.
== Progress ==
* [ARM GlobalISel] Add support for integers < 32 bits wide [TCWG-980] [4/10]
- A number of patches in upstream review
* [ARM] Refactor AddrMode3 [TCWG-989] [1/10]
- Did some preliminary investigations / tinkering for removing a
hack in the representation of LDRH
* Rewrite llvm-projs in Python [TCWG-833] [2/10]
- More refactoring etc
- It is finally done, yay
* Misc [3/10]
- Address review comments on outstanding patches (committed
TCWG-925, still waiting for TCWG-946)
- AArch64 3.9.1 release [TCWG-886]
- Meetings, mailing lists, code reviews
== Plan ==
* [ARM] Refactor AddrMode3 [TCWG-989]
* FOSDEM slides
* Vacation between December 24th and January 9th.
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.12 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.2+svn243594 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.02
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.2+svn243594
* Linaro BZ #2575: backport from trunk r239561, r242555.
* Backport of [Bugfix] [AArch32] PR target/78041
* Backport of [Bugfix] Fix test names for trad.exp tests PR testsuite/78136
* Backport of [Bugfix] PR middle-end/78201
* Backport of [Bugfix] PR tree-optimization/71636
* Backport of [AArch32] Implementing vmaxnmQ_ST and vminnmQ_ST intrinsincs
* Backport of [AArch64] aarch64-*-freebsd* support for gcc
* Backport of [AArch64] Add a SHA1H pattern
* Backport of [AArch64] Align FP callee-saves
* Backport of [AArch64] Improve stack adjustment
* Backport of [AArch64] Improve stack adjustment: add testcase
* Backport of [Cleanup] Fix typo in name
* Backport of [Cleanup] Remove all uses of
TARGET_FLT_EVAL_METHOD_NON_DEFAULT and poison it
* Backport of [Cleanup] Remove redundant TARGET_VFP
* Backport of [Misc] Optimize strchr to strlen (1/2)
* Backport of [Misc] Optimize strchr to strlen (2/2)
* Backport of [Testsuite] [AArch32] Fix failing vminnm/vmaxnm test on ARM
* Backport of [Testsuite] [AArch32] FP16 ARM Alternative format
variants of AAPCS tests
* Backport of [Testsuite] Fix traditional cpp test failure
* Backport of [Testsuite] Report DejaGnu ERROR messages in compare_tests
* Backport of [Testsuite] Report DejaGnu ERROR messages in dg-extract-results
* Backport of [Cleanup] [AArch32] Remove redundant model field from
FPU descriptions
* Backport of [Cleanup] [AArch32] Use VAR_P
* Backport of [Cleanup] [AArch64] aarch64-c.o should depend on TARGET_H
* Backport of [Cleanup] [AArch64] Add a comment before each set of cores
* Backport of [Cleanup] [AArch64] Add function comments to some
prologue/epilogue helpers
* Backport of [Cleanup] [AArch64] Cleanup add expander
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn243604 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the next
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.12/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.4+svn243604
* Linaro BZ #2575: backport from trunk r232812.
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Progress:
TCWG-829 Ifunc support
- Refactored implementation using synthetic sections upstreamed. Found
out that x86 ifunc was broken and probably hadn't ever worked so I
fixed that while I was there.
PR31332 x86 pic plt sequences broken
- Found out that x86 pic and pie is broken in lld, the implementation
assumes that .got is immediately followed by .got.plt with no gap. As
lld makes no such guarantees it is easy to break with a trivial
example. Raised PR31332 after investigating the root cause. Spent
quite a bit of time on this, even though it is x86 specific, I wanted
to make sure I hadn't broken it.
Fosdem-2017
- Submitted a llvm-devroom talk on lld to Fosdem (post deadline, but
probably still up for consideration)
Plans for this week:
TCWG-985 PIE on ARM broken
- I have a simple fix that should be simple to upstream
TCWG-919 Thunks to undefined symbols
- I have a downstream patch, but there is risk I'll be asked to refactor
TCWG-911 Eglibc requires a .ARM.attributes section for dlopen
- There is a trivial hack to make this work; just use the first ARM
attributes section and throw away the rest. A proper solution to
support ARM attributes merging will take some time.
PR31332 x86 pic plt sequences broken
- I think I can fix this fairly cheaply which while not directly
relevant to ARM, it does give me another easily accessible target to
test on my desk top and has some community benefits.
Ifuncs
- LLD doesn't support taking the address of ifuncs for any
architecture. I don't think that this is common practice, but it is a
latent problem that it might be good to fix now when ifunc is in my
head.
Planned holidays:
19th December till end of the year, back on Tuesday 3rd January