== Progress ==
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][3/10]
- Ran more tests and reported the results upstream
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
- Started supporting G_FREM and G_FPOW, which are already handled by
the target-independent code
- Committed G_FREM upstream, G_FPOW is ready to commit first thing next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Moved llvm-helper-scripts
* Misc [3/10]
- Mailing lists, code reviews, meetings
== Plan ==
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
=== This Week ===
GDB Kernel Awarenes - Kernel Dump setup for ARM [9/10]
-- Background study on kdump and try to find working steps for QEMU ARM.
-- There is a problem with kdump-tools install script with QEMU
-- Tried building kernel for Raspberry Pi2 and Pi3 with kdump, no
success so far.
-- Setup B2260 with debian and try kdump setup
-- Setup and kernel config successful but kdump couldn't configure
-- Tried the same with HiKey board
Miscellaneous Activities [1/10]
-- Meetings, Emails etc.
=== Next Week ===
GDB Kernel Awarenes
-- Start merging Peter's and IBM patches
-- Look around for help on Kdump setup.
== This Week ==
* TCWG-1005 (6/10)
- Fixed firefox ICE
- Unfortunately that gives rise to another ICE with ipa-icf pass :(
Investigating if this
caused by the patch or a latent bug in ipa-icf.
- Builds well with chromium
* Validation (1/10)
- abe/extraconfig patches
- backport review
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
~ Progress ~
* TCWG-1050, GDB 8.0 release. [7/10]
** Fix PR 19942, but looks my patch is completely wrong as I fully
misunderstood the "reference count" in GDB. Writing the v2.
** Intel btrace python interface discussion, a marathon discussion
about both the interface and implementation. Good thing is that we
agree that we need to change the interface. This takes most of my
time this week.
* TCWG-1040, Review SVE patches. [2/10]
Some discussions on avoid copying register contents to a local buffer
again, which is from my review comments to Alan's patch and my
suggested patch. Spend some time on understanding the zero
initialization of union in C++. I'll update my suggested patch.
* Update AArch32 GDB buildbot option, so we can get more reasonable
test result. [1/10]
~ Plan ~
* More remote tests for GDB 8.0 release.
* Fix PR 19942.
* One day off on Thu.
--
Yao Qi
[Eurollvm]
Attended, we have recorded our thoughts in EuroLLVM 2017 Recap doc
[TCWG-614] Range extension thunks
- I've finished my downstream implementation, and have written almost
all the lld tests I'd like to write
- Still need to test on real large programs such as libclang.so
- Made a start at breaking down the implementation into smaller
patches that can be sensibly upstreamed
Plans for next week
[TCWG-614]
- Aiming to start upstreaming on Monday, I'm expecting this to be
quite a drawn out process
- Continue testing on ARM Linux
Planned Absences
ACCU conference 2017 27-29 April
== Progress ==
* Validation
- helped with new llvm build scripts and jobs
- improvements to container scripts to cope with llvm's higher needs
in resources
- improved tcwg-regression tests
- various to remove dependencies on env variables
- comparison script now reports the associated .exp file name,
making it easier to reproduce a regression
- experimented with lava
- started work on benchmarking scripts
* GCC
- keeping an eye on trunk regressions
- update to qemu-2.8.0 introduced regressions in validation for
armeb on some atomic tests
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation:
- hopefully nothing :)
* Benchmarking:scripting
== Progress ==
* EuroLLVM trip [6/10]
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][2/10]
- Apple wants to switch the default O0 to GlobalISel for AArch64, so
we need to run tests and gather metrics
- I'm running the test-suite and selfhost with GlobalISel to see how
it performs
* Misc [2/10]
- Mailing list, code reviews, meetings, herding GlobalISel cats
(we're trying to open more communication channels with Apple so we can
unblock progress)
== Plan ==
* Wrap up TCWG-1074
* Learn more TableGen and do more code review
Hello all,
I've been using GCC 4.9.4 for a while now (arm-linux-gnueabi-gcc (Linaro
GCC 4.9-2017.01) 4.9.4), and I found this strange behavior:
In the library header (libm5op.h):
-----
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run);
#ifdef __cplusplus
}
#endif
-----
In the library C file (m5op_arm_.c):
-----
#include "stdio.h"
#include <stdlib.h>
#include "libm5op.h"
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run)
{
// Code here using args
}
-----
The code above is in
/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ and compiled as a
library with GCC 6.3.1 and is ok:
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -O3
-fno-optimize-sibling-calls -c m5op_arm_.c -o m5op_arm_.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c m5op_arm.S -o m5op_arm.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-ar
rcs libm5op32.a m5op_arm_.o m5op_arm.o
The library is used in a source code compiled with the GCC 4.9.4 describe
at the begining.
In the C file:
-----
#include <libm5op.h>
S_regmatch(pTHX_ regnode *prog)
{
warm_and_run_(161, 818);
// Code continues
}
------
This source is compile with:
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c -o regexec.o -DSPEC_CPU -DNDEBUG -DPERL_CORE -static -marm
-march=armv7-a - mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat-abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/ SPEC_CPU2006v1.1-aarch64/m5op/
-DGEM5_ARM32=1 -DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 regexec.c
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-static -marm -march=armv7-a -mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat- abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ -DGEM5_ARM32=1
-DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 av.o deb.o doio.o doop.o
dump.o globals.o gv.o hv.o locale.o mg.o numeric.o op.o pad.o perl.o
perlapi.o perlio.o perlmain.o perly.o pp.o pp_ctl.o pp_hot.o pp_pack.o
pp_sort.o pp_sys.o regcomp.o regexec.o run.o scope.o sv.o taint.o toke.o
universal.o utf8.o util.o xsutils.o Base64.o Cwd.o Dumper.o HiRes.o IO.o
Peek.o attrs.o poll.o stdio.o DynaLoader.o MD5.o Storable.o Parser.o
specrand.o Hostname.o Opcode.o -lm -lm5op32 -lm5op32 -o
perlbench
Finally, the assembled code of S_regmatch has:
-----
af2d0: e3a000a1 mov r0, #161 ; 0xa1
af2d4: e3001332 movw r1, #818 ; 0x332
af2d8: e58d3018 str r3, [sp, #24]
af2dc: e58d2028 str r2, [sp, #40] ; 0x28
af2e0: fa02615c blx 147858 <warm_and_run_>
-----
So, this means that warm_and_run_ is assumed by GCC 4.9.4 to have 32 bits
arguments, while they are indeed 64 bits. This seems to be a bug for me.
The code in the library is correctly allocating 2*32 bits regs for each
argument.
For now, I'm using int32_t, and I just thought it could be useful to
feedback you guys.
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
== Progress ==
* Validation
- finally merged most of work of the past weeks
- main jobs are now using start-container scripts
- helped with new llvm build scripts and jobs
- abe initial config for gcc7: need to investigate a binutils build
problem in a trusty container
- improved tcwg-regression tests, identified a regression for bug-2123
- many validation-related patches to review
* GCC
- reported a regresion upstream
* misc (conf-calls, meetings, emails, ....)
- started discussing benchmarking
== Next ==
* Validation:
- a few patches pending review (to improve reports, debug-ability of
containers, ...)
- work on a new proposal to upgrade our qemu
- probably more cleanup needed in the jobs (slaves, basedir scm option, ...)
- improve tcwg-regression
- boot kernel after build
* Benchmarking: start to contribute
== Progress ==
o Linaro GCC/Validation (6/10)
* Validation/Infra patch reviews
* Upstream monitoring job
* Release automation:
- Reworking tcwg-release.sh
o Misc (4/10)
* Various meetings and discussions.
== Plan ==
o Focusing on release automation and validation
Achievements:
[TCWG-614] Range extension Thunks
- About 3 hours in total of rebasing due to upstream refactoring
- Have finished the non-linkerscript tests and fixed all the bugs
detected by them
- Started the linkerscript tests, no problems found so far
[TLS]
- Some explanation to upstream of how ARM TLS works
- Discovered that upstream have broken TLS global-dynamic for
executables, I have a fix but will need to write a test case.
Plans for next week:
- Euro LLVM Monday, Tuesday
- Continue with TCWG-614
-- Try and link clang (> 30 Mb) to test range thunks on some real programs
-- Aim to get something ready for upstream review by end of week, may
slip to beginning of next week depending on if I find any hard to
debug problems.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [6/10]
** Pushed a fix to AArch64 process record bug on PRFM instruction.
AArch64 native test looks good now.
** Start to look at ARM native test, triage the fails in
watch-bitfields.exp. Test doesn't fail on old Linux kernel, likely
a kernel bug. Further analysis is needed.
** Request reverting Intel btrace python interface before release, as
they are too btrace-specific.
** Fixing a bug about thread_info refcount issue. Testing the patch.
* Discussion on RTOS awareness in debugging. OpenOCD people want GDB
aware more about different RTOSes. [1/10]
* TCWG-1040, SVE patches review, [2/10]
* Misc, [1/10]
~ Plan ~
* Take a look at native ARM testing, and cross testing.
* Post my fix to thread_info refcount issue.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037] [3/10]
- Got some patches ready but they depend on the TableGen support for
predicates, which has not been committed upstream yet
* [GlobalISel] Use proper calling conv for calls [TCWG-1051] [1/10]
- Patch accepted upstream, will commit next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Started migrating tcwg-release-tools to Python 3, still in progress
* Misc [5/10]
- Mailing lists, code reviews, buildbot monitoring, catching up after Connect
- LLVM social in Stockholm
- Fiddling with the new container for our LLVM buildmasters
== Plan ==
* Commit TCWG-1051, maybe TCWG-1037 too depending on upstream progress
* More GlobalISel code reviews
* TCWG-896
* Out of office for EuroLLVM (24 - 29 March)
[TCWG-614] Range extension Thunks
Worked all week on this. I've got a prototype that is nearly feature
complete. It passes the existing tests when run in a single pass. I'm
now trying to get it to run in multiple passes.
Plans
[TCWG-614] Range extension Thunks
Start adding tests for the new functionality and doubtless spending a
lot of time fixing problems. If I'm lucky I may have something that I
can at least in part send upstream for review by the end of the week.
~ Progress ~
* Three days off [6/10]
* TCWG-1050, GDB 8.0 release. [2/10]
Pushed in some patches fixing ARM reverse debugging bug.
Investigating a GDB internal error.
Review Python btrace stuff, still trying to make it more generic.
* Misc, [2/10], catch up emails
~ Plan ~
* TCWG-1050.
* Review IBM linux kernel awareness patches.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.03 snapshot of the Linaro GCC 6 source package.
This monthly snapshot[1] is based on FSF GCC 6.3+svn246148 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246148
* Backport of [Bugfix] [AArch64] PR target/71112 ICE with -fpie on
aarch64 ILP32 big-endian
* Backport of [Bugfix] [AArch64] PR target/71727 -O3 -mstrict-align
produces code which assumes unaligned vector accesses work
* Backport of [Bugfix] [AArch64] PR target/78382 ICE when compiling on
aarch64 in ILP32 mode with traditional thread local storage and pic
* Backport of [AArch32] Add vfpv2 and neon-vfpv3
* Backport of [AArch32] Fix assembly comment syntax in -mprint-tune-info
* Backport of [AArch64] Add commandline support for -march=armv8.3-a
* Backport of [AArch64] Expand DImode constant stores to two SImode
stores when profitable
* Backport of [AArch64] Fix aarch64 PGO bootstrap
* Backport of [AArch64] Fix exception handling for ILP32 aarch64
* Backport of [AArch64] Have the verbose cost model output output be
controllable
* Backport of [AArch64] Implement popcount pattern
* Backport of [AArch64] Optimized implementation of search_line_fast
for the CPP lexer
* Backport of [AArch64] Use new target pass registration framework for
FMA steering pass
* Backport of [Testsuite] [AArch32] Add Cortex-A15 tuning to
gcc.dg/uninit-pred-8_a.c
* Backport of [Testsuite] [AArch32] Skip optional_mthumb tests if GCC
has a default mode
* Backport of [Testsuite] [AArch32] Updating testcase unsigned-extend-2.c
* Backport of [Testsuite] [AArch64] Fix
gcc.dg/torture/float32-builtin.c with RTL checking
* Backport of [Testsuite] [AArch64] PR middle-end/78142 more registers
to be used for on gcc.target/aarch64/vector_initialization_nostack.c
* Backport of [Cleanup] [AArch32] Define arm_arch_core_flags in a single file
* Backport of [Cleanup] [AArch32] Remove unimplemented option -macps-float
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
* 2 days out of office (Thursday & Friday)
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
- Committed support for GEPs and 32-bit constants, which enables us
to put call parameters on the stack
- Proposed a fix for an AArch64 issue where the size of the stack
was computed incorrectly if the last parameter was sign- or
zero-extended into a stack slot
* Misc
- Mailing list etc.
== Plan ==
* Connect
2 day week:
== Activity ==
[TCWG-617] Range extension thunks
- rebased patch after coming back from holiday, took some time as
quite a bit had changed, patch still in upstream review.
- Have downstream patches to make inline thunks work with linker
scripts, will post for review next week.
== Plan ==
At linaro connect all next week
== Planned absences ==
Euro LLVM 27-28 March
~ Progress ~
* GDB 8.0 release, TCWG-1050, [5/10].
Release branch will be created on March 15th.
Fixed some instruction decoding in reverse debugging. Tested.
Added a unit test for arm process recording for some instructions.
To be posted upstream.
PR gdb/21165 is fixed.
* SVE GDB patches review, TCWG-1035, [3/10]
SVE patches review. One of Alan's patch is to remove some lines of
code written 19 years ago, which was to fix a bug at that moment.
A lot of archeology. Hopefully the author is still in RedHat, and
get more information on the fix. Alan's patch is correct.
* Upstream patches review. [2/10]
** Some python bindings on intel btrace. Make it more portable,
hopefully these python apis can be used for CoreSight in the
future.
~ Plan ~
* Linaro Connect.
* March 13th -- 15th, holiday.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Fix atomic loads/stores after r294993 [TCWG-1041] [1/10]
- For the moment we just bail out if we have any atomic loads /
stores. This is better than silently replacing them with non-atomic
operations.
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038] [6/10]
- Committed support for calls with args/returns in registers (ints,
pointers, floating point)
- Found and reported a bug in the AArch64 backend
- Working on lowering stack arguments: committed support for stores,
still working on adding support for GEPs and constants so we can
actually compute the addresses that we have to store to
* Misc [3/10]
- Meetings, mailing lists, code reviews
- Connect slides
- Buildbots (reverted patches with flaky tests, fixed mips-specific
test to run only when mips is built)
== Plan ==
* Out of office on Thursday and Friday
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
== Progress ==
* Validation
- more work on use of containers, ssh-agent & jenkins problems
- added an experimental job to prepare the migration to
the new scripts
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Holidays next week
* Connect
