- linaro-toolchain - lists.linaro.org

[ACTIVITY] week ending Jan. 22 2023

by Alex Bennée

Project Stratos =============== - finished draft of [proposal for Unprivilaged VirtIO API] - sent out for comment [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> vhost-device maintainer effort ([UM-196]) - a few version bump reviews [UM-196] <https://linaro.atlassian.net/browse/UM-196> Plugin register access ([QEMU-495]) =================================== - posted [PATCH v2 00/21] gdbstub: re-organise to for better compilation behaviour Message-Id: <20230105164320.2164095-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] docs: add some details about compilation units to coding style Message-Id: <20230103104758.767266-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: fix handling of HLT semihosting in system mode Message-Id: <20230105114304.2017493-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] testing: probe gdb for supported architectures ahead of time Message-Id: <20230105181533.2235792-1-alex.bennee(a)linaro.org> - posted [PATCH v2] scripts/ci: update gitlab-runner playbook to use latest runner Message-Id: <20230106152338.2599827-1-alex.bennee(a)linaro.org> - posted [PATCH 00/18] testing/next updates (gitlab, docker, check-tcg) Message-Id: <20230119180419.30304-1-alex.bennee(a)linaro.org> - updated maintainer trees, running [CI over weekend] [UM-2] <https://linaro.atlassian.net/browse/UM-2> [CI over weekend] <https://gitlab.com/stsquad/qemu/-/pipelines/753447926> Completed Reviews [7/7] ======================= [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH v2] semihosting: add O_BINARY flag in host_open for NT compatibility Message-Id: <20230106102018.20520-1-eiakovlev(a)linux.microsoft.com> [PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64 Message-Id: <75da8346.1fd34.1856e0d08ef.Coremail.fanwj(a)mail.ustc.edu.cn> [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> [PATCH v2 00/22] tcg: exit_tb tidy, goto_tb reorg Message-Id: <20230109014248.2894281-1-richard.henderson(a)linaro.org> [PATCH v3 0/8] Fix win32/msys2 shader compilation & update lcitool deps Message-Id: <20230110080246.536056-1-marcandre.lureau(a)redhat.com> Other ===== - bit of travel forecasting Current Review Queue ==================== TODO [PATCH 0/3] various aarch64 fixes for running Hyper-V on TCG Message-Id: <20230105221251.17896-1-eiakovlev(a)linux.microsoft.com> =================================================================================================================================== TODO [PATCH 0/4] tsan fixes Message-Id: <20230108163905.59601-1-cota(a)braap.org> ============================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 7 months

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[TCWG CI] [TCWG CI] 481.wrf failed to build after gdb-13-branchpoint-388-g71fa8692930: sim: cris: move arch-specific file compilation to top-level

by ci_notify＠linaro.org

After gdb-13-branchpoint-388-g71fa8692930 commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> sim: cris: move arch-specific file compilation to top-level the following benchmarks slowed down by more than 3%: - 481.wrf failed to build - 416.gamess failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: arm-linux-gnueabihf - Compiler flags: -O3 -flto -marm - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of gdb-13-branchpoint-388-g71fa8692930 commit for tcwg_bmk-code_speed-spec2k6: commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> Date: Sun Jan 1 13:40:11 2023 -0500 sim: cris: move arch-specific file compilation to top-level * gnu-arm-master-O3_LTO ** After gdb-13-branchpoint-388-g71fa8692930 commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 ** Author: Mike Frysinger <vapier(a)gentoo.org> ** ** sim: cris: move arch-specific file compilation to top-level ** ** the following benchmarks slowed down by more than 3%: ** - 481.wrf failed to build ** - 416.gamess failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Reproduce current build: <cut> mkdir -p investigate-binutils-71fa8692930cd5fc3f332415cf642d3aa5f55fc6 cd investigate-binutils-71fa8692930cd5fc3f332415cf642d3aa5f55fc6 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> Date: Sun Jan 1 13:40:11 2023 -0500 sim: cris: move arch-specific file compilation to top-level --- sim/Makefile.in | 3 --- sim/cris/local.mk | 3 --- 2 files changed, 6 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index 435c36b2b83..0ad692126e7 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -4801,9 +4801,6 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< >$@ @SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD): cris/hw-config.h -@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: cris/%.c -@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) - @SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c @SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) @SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS) diff --git a/sim/cris/local.mk b/sim/cris/local.mk index 912ca12a32f..3950baed7a1 100644 --- a/sim/cris/local.mk +++ b/sim/cris/local.mk @@ -47,9 +47,6 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h noinst_LIBRARIES += %D%/libsim.a -%D%/%.o: %D%/%.c - $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) - %D%/%.o: common/%.c $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) </cut>

2 years, 7 months

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[TCWG CI] [TCWG CI] 459.GemsFDTD failed to build after glibc-2.36.9000-435-g569cfcc6bf: hurd: Fix _NOFLSH value

by ci_notify＠linaro.org

After glibc-2.36.9000-435-g569cfcc6bf commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> hurd: Fix _NOFLSH value the following benchmarks slowed down by more than 3%: - 459.GemsFDTD failed to build - 436.cactusADM failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. For your convenience, we have uploaded tarballs with pre-processed source and assembly files at: - First_bad save-temps: $FIRST_BAD_ARTIFACTS/save-temps/ - Last_good save-temps: $LAST_GOOD_ARTIFACTS/save-temps/ - Baseline save-temps: $BASELINE_ARTIFACTS/save-temps/ Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 -flto - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of glibc-2.36.9000-435-g569cfcc6bf commit for tcwg_bmk-code_speed-spec2k6: commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> Date: Sun Jan 15 20:54:42 2023 +0100 hurd: Fix _NOFLSH value shifting 1 (thus an integer) left 31 bit is undefined behavior. We have to make it an unsigned integer to properly get 0x80000000 (like done in other places). * gnu-aarch64-master-O3_LTO ** After glibc-2.36.9000-435-g569cfcc6bf commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 ** Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> ** ** hurd: Fix _NOFLSH value ** ** the following benchmarks slowed down by more than 3%: ** - 459.GemsFDTD failed to build ** - 436.cactusADM failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Reproduce current build: <cut> mkdir -p investigate-glibc-569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 cd investigate-glibc-569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> Date: Sun Jan 15 20:54:42 2023 +0100 hurd: Fix _NOFLSH value shifting 1 (thus an integer) left 31 bit is undefined behavior. We have to make it an unsigned integer to properly get 0x80000000 (like done in other places). --- bits/termios.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bits/termios.h b/bits/termios.h index ae62d00853..4439c2f14e 100644 --- a/bits/termios.h +++ b/bits/termios.h @@ -246,7 +246,7 @@ struct termios # define NOKERNINFO (1 << 25) /* Disable VSTATUS. */ # define PENDIN (1 << 29) /* Retype pending input (state). */ #endif -#define _NOFLSH (1 << 31) /* Disable flush after interrupt. */ +#define _NOFLSH (1U << 31) /* Disable flush after interrupt. */ #define NOFLSH _NOFLSH /* Control characters. */ </cut>

2 years, 7 months

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[TCWG CI] [TCWG CI] 521.wrf_r slowed down by 5% after basepoints/gcc-13-5062-gcb93c5f8008: Subject: [committed, pushed, Modula2] Added missing dependency.

by ci_notify＠linaro.org

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2 years, 7 months

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[TCWG CI] [TCWG CI] 445.gobmk slowed down by 6% after llvmorg-16-init-16383-g9b5f62685ab4: [SLP]Fix cost of the broadcast buildvector/gather.

by ci_notify＠linaro.org

After llvmorg-16-init-16383-g9b5f62685ab4 commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> [SLP]Fix cost of the broadcast buildvector/gather. the following benchmarks slowed down by more than 3%: - 445.gobmk slowed down by 6% from 10321 to 10904 perf samples Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: Clang + Glibc + LLVM Linker - Version: all components were built from their tip of trunk - Target: arm-linux-gnueabihf - Compiler flags: -O3 -flto -marm - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-16-init-16383-g9b5f62685ab4 commit for tcwg_bmk-code_speed-spec2k6: commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> Date: Wed Dec 21 13:38:38 2022 -0800 [SLP]Fix cost of the broadcast buildvector/gather. Need to include the cost of the initial insertelement to the cost of the broadcasts. Also, need to adjust the cost of the gather/buildvector if the element is inserted into poison/undef vector. Differential Revision: https://reviews.llvm.org/D140498 * llvm-arm-master-O3_LTO ** After llvmorg-16-init-16383-g9b5f62685ab4 commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b ** Author: Alexey Bataev <a.bataev(a)outlook.com> ** ** [SLP]Fix cost of the broadcast buildvector/gather. ** ** the following benchmarks slowed down by more than 3%: ** - 445.gobmk slowed down by 6% from 10321 to 10904 perf samples ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Reproduce current build: <cut> mkdir -p investigate-llvm-9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b cd investigate-llvm-9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> Date: Wed Dec 21 13:38:38 2022 -0800 [SLP]Fix cost of the broadcast buildvector/gather. Need to include the cost of the initial insertelement to the cost of the broadcasts. Also, need to adjust the cost of the gather/buildvector if the element is inserted into poison/undef vector. Differential Revision: https://reviews.llvm.org/D140498 --- llvm/include/llvm/Analysis/TargetTransformInfo.h | 12 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 4 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 54 +-- llvm/lib/Analysis/TargetTransformInfo.cpp | 8 +- .../Target/AArch64/AArch64TargetTransformInfo.cpp | 7 +- .../Target/AArch64/AArch64TargetTransformInfo.h | 4 +- .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h | 2 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 7 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 4 +- .../Target/Hexagon/HexagonTargetTransformInfo.cpp | 6 +- .../Target/Hexagon/HexagonTargetTransformInfo.h | 4 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 9 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 4 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 7 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 +- .../Target/SystemZ/SystemZTargetTransformInfo.cpp | 5 +- .../Target/SystemZ/SystemZTargetTransformInfo.h | 4 +- .../WebAssembly/WebAssemblyTargetTransformInfo.cpp | 5 +- .../WebAssembly/WebAssemblyTargetTransformInfo.h | 4 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 42 ++- llvm/lib/Target/X86/X86TargetTransformInfo.h | 4 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 21 +- .../Analysis/CostModel/X86/loop_v2-inseltpoison.ll | 2 +- llvm/test/Analysis/CostModel/X86/loop_v2.ll | 2 +- .../X86/masked-intrinsic-cost-inseltpoison.ll | 4 +- .../CostModel/X86/masked-intrinsic-cost.ll | 4 +- .../CostModel/X86/vector-insert-inseltpoison.ll | 120 +++---- llvm/test/Analysis/CostModel/X86/vector-insert.ll | 120 +++---- .../Analysis/CostModel/X86/vshift-ashr-codesize.ll | 50 +-- .../CostModel/X86/vshift-ashr-cost-inseltpoison.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-ashr-cost.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-ashr-latency.ll | 18 +- .../CostModel/X86/vshift-ashr-sizelatency.ll | 50 +-- .../Analysis/CostModel/X86/vshift-lshr-codesize.ll | 82 +---- .../CostModel/X86/vshift-lshr-cost-inseltpoison.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-lshr-cost.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-lshr-latency.ll | 102 ++---- .../CostModel/X86/vshift-lshr-sizelatency.ll | 82 +---- .../Analysis/CostModel/X86/vshift-shl-codesize.ll | 82 +---- .../CostModel/X86/vshift-shl-cost-inseltpoison.ll | 138 ++----- .../test/Analysis/CostModel/X86/vshift-shl-cost.ll | 138 ++----- .../Analysis/CostModel/X86/vshift-shl-latency.ll | 102 ++---- .../CostModel/X86/vshift-shl-sizelatency.ll | 174 ++------- llvm/test/Transforms/SLPVectorizer/X86/cse.ll | 7 +- .../Transforms/SLPVectorizer/X86/malformed_phis.ll | 140 ++++---- .../X86/remark_gather-load-redux-cost.ll | 2 +- .../SLPVectorizer/X86/used-reduced-op.ll | 399 +++++++++++---------- 50 files changed, 941 insertions(+), 1522 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 6200af73842c..a9cb8717ffa8 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1193,7 +1193,8 @@ public: /// case is to provision the cost of vectorization/scalarization in /// vectorizer passes. InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index = -1) const; + unsigned Index = -1, Value *Op0 = nullptr, + Value *Op1 = nullptr) const; /// \return The expected cost of vector Insert and Extract. /// This is used when instruction is available, and implementation @@ -1786,7 +1787,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I) = 0; virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) = 0; + unsigned Index, Value *Op0, + Value *Op1) = 0; virtual InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) = 0; @@ -2358,9 +2360,9 @@ public: const Instruction *I) override { return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) override { - return Impl.getVectorInstrCost(Opcode, Val, Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) override { + return Impl.getVectorInstrCost(Opcode, Val, Index, Op0, Op1); } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) override { diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index e81e430f6624..262b42a05d99 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -585,8 +585,8 @@ public: return 1; } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) const { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) const { return 1; } diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index aabb94d82c4b..f27c6899d757 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -90,10 +90,12 @@ private: InstructionCost Cost = 0; // Broadcast cost is equal to the cost of extracting the zero'th element // plus the cost of inserting it into every element of the result vector. - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, 0); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, 0, + nullptr, nullptr); for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i, + nullptr, nullptr); } return Cost; } @@ -110,8 +112,10 @@ private: // vector and finally index 3 of second vector and insert them at index // <0,1,2,3> of result vector. for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i); - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i, + nullptr, nullptr); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, i, + nullptr, nullptr); } return Cost; } @@ -134,9 +138,9 @@ private: // type. for (int i = 0; i != NumSubElts; ++i) { Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, - i + Index); - Cost += - thisT()->getVectorInstrCost(Instruction::InsertElement, SubVTy, i); + i + Index, nullptr, nullptr); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, SubVTy, i, + nullptr, nullptr); } return Cost; } @@ -158,10 +162,10 @@ private: // the source type plus the cost of inserting them into the result vector // type. for (int i = 0; i != NumSubElts; ++i) { - Cost += - thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVTy, + i, nullptr, nullptr); Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, - i + Index); + i + Index, nullptr, nullptr); } return Cost; } @@ -212,7 +216,7 @@ private: FixedVectorType::get( PointerType::get(VT->getElementType(), 0), VT->getNumElements()), - -1) + -1, nullptr, nullptr) : 0; InstructionCost LoadCost = VT->getNumElements() * @@ -237,7 +241,7 @@ private: Instruction::ExtractElement, FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()), VT->getNumElements()), - -1) + + -1, nullptr, nullptr) + getCFInstrCost(Instruction::Br, CostKind) + getCFInstrCost(Instruction::PHI, CostKind)); } @@ -722,9 +726,11 @@ public: if (!DemandedElts[i]) continue; if (Insert) - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, Ty, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, Ty, i, + nullptr, nullptr); if (Extract) - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, i); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, i, + nullptr, nullptr); } return Cost; @@ -1123,7 +1129,7 @@ public: InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) { return thisT()->getVectorInstrCost(Instruction::ExtractElement, VecTy, - Index) + + Index, nullptr, nullptr) + thisT()->getCastInstrCost(Opcode, Dst, VecTy->getElementType(), TTI::CastContextHint::None, TTI::TCK_RecipThroughput); @@ -1184,14 +1190,20 @@ public: return 1; } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) { return getRegUsageForType(Val->getScalarType()); } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) { - return thisT()->getVectorInstrCost(I.getOpcode(), Val, Index); + Value *Op0 = nullptr; + Value *Op1 = nullptr; + if (auto *IE = dyn_cast<InsertElementInst>(&I)) { + Op0 = IE->getOperand(0); + Op1 = IE->getOperand(1); + } + return thisT()->getVectorInstrCost(I.getOpcode(), Val, Index, Op0, Op1); } InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, @@ -2246,7 +2258,8 @@ public: ArithCost += NumReduxLevels * thisT()->getArithmeticInstrCost(Opcode, Ty, CostKind); return ShuffleCost + ArithCost + - thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } /// Try to calculate the cost of performing strict (in-order) reductions, @@ -2353,7 +2366,8 @@ public: // The last min/max should be in vector registers and we counted it above. // So just need a single extractelement. return ShuffleCost + MinMaxCost + - thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 7459ce18c3cf..d03a8cf14172 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -897,13 +897,13 @@ InstructionCost TargetTransformInfo::getCmpSelInstrCost( return Cost; } -InstructionCost TargetTransformInfo::getVectorInstrCost(unsigned Opcode, - Type *Val, - unsigned Index) const { +InstructionCost TargetTransformInfo::getVectorInstrCost( + unsigned Opcode, Type *Val, unsigned Index, Value *Op0, Value *Op1) const { // FIXME: Assert that Opcode is either InsertElement or ExtractElement. // This is mentioned in the interface description and respected by all // callers, but never asserted upon. - InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index); + InstructionCost Cost = + TTIImpl->getVectorInstrCost(Opcode, Val, Index, Op0, Op1); assert(Cost >= 0 && "TTI should not produce negative costs!"); return Cost; } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index ae12ae951d75..f5f6c07f766a 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -2034,8 +2034,8 @@ InstructionCost AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, // Get the cost for the extract. We compute the cost (if any) for the extend // below. - InstructionCost Cost = - getVectorInstrCost(Instruction::ExtractElement, VecTy, Index); + InstructionCost Cost = getVectorInstrCost(Instruction::ExtractElement, VecTy, + Index, nullptr, nullptr); // Legalize the types. auto VecLT = getTypeLegalizationCost(VecTy); @@ -2128,7 +2128,8 @@ InstructionCost AArch64TTIImpl::getVectorInstrCostHelper(Type *Val, } InstructionCost AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { return getVectorInstrCostHelper(Val, Index, false /* HasRealUse */); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index e309117a885b..6eaff9566b8c 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -169,8 +169,8 @@ public: InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I = nullptr); - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index af72ba2daa2d..00e6970291bf 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -790,7 +790,8 @@ GCNTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, } InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { switch (Opcode) { case Instruction::ExtractElement: case Instruction::InsertElement: { @@ -799,7 +800,7 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, if (EltSize < 32) { if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) return 0; - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } // Extracts are just reads of a subregister, so are free. Inserts are @@ -810,7 +811,7 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return Index == ~0u ? 2 : 0; } default: - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h index 347ce87acd26..4a1137dcf2e2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -162,7 +162,7 @@ public: using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index); + unsigned Index, Value *Op0, Value *Op1); bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const; bool isSourceOfDivergence(const Value *V) const; diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp index 365c005b2503..c3dd321a7b9c 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp @@ -108,14 +108,15 @@ InstructionCost R600TTIImpl::getCFInstrCost(unsigned Opcode, } InstructionCost R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { switch (Opcode) { case Instruction::ExtractElement: case Instruction::InsertElement: { unsigned EltSize = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType()); if (EltSize < 32) { - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } // Extracts are just reads of a subregister, so are free. Inserts are @@ -126,7 +127,7 @@ InstructionCost R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return Index == ~0u ? 2 : 0; } default: - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } } diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h index f1a198fd14e4..9045cc773189 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h @@ -62,7 +62,7 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index); + unsigned Index, Value *Op0, Value *Op1); }; } // end namespace llvm diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 8eec432a4a66..07786ea82738 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -874,7 +874,8 @@ InstructionCost ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, } InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { // Penalize inserting into an D-subregister. We end up with a three times // lower estimated throughput on swift. if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement && @@ -893,7 +894,7 @@ InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, if (ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32) return std::max<InstructionCost>( - BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U); + BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1), 2U); } if (ST->hasMVEIntegerOps() && (Opcode == Instruction::InsertElement || @@ -906,7 +907,7 @@ InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return LT.first * (ValTy->getScalarType()->isIntegerTy() ? 4 : 1); } - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } InstructionCost ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index db96c3da54cf..6b1e6444c516 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -240,8 +240,8 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index 779577816fb9..6089c865cedf 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -329,7 +329,8 @@ InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, } InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType() : Val; if (Opcode == Instruction::InsertElement) { @@ -338,7 +339,8 @@ InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (ElemTy->isIntegerTy(32)) return Cost; // If it's not a 32-bit value, there will need to be an extract. - return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index); + return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index, + Op0, Op1); } if (Opcode == Instruction::ExtractElement) diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 49d9520b8323..d41299ff6413 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -154,8 +154,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I = nullptr) { diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 3b952f11be34..328a70ec43f6 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -675,7 +675,8 @@ InstructionCost PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { assert(Val->isVectorTy() && "This must be a vector type"); int ISD = TLI->InstructionOpcodeToISD(Opcode); @@ -685,7 +686,8 @@ InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (!CostFactor.isValid()) return InstructionCost::getMax(); - InstructionCost Cost = BaseT::getVectorInstrCost(Opcode, Val, Index); + InstructionCost Cost = + BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); Cost *= CostFactor; if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { @@ -827,7 +829,8 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, if (Src->isVectorTy() && Opcode == Instruction::Store) for (int i = 0, e = cast<FixedVectorType>(Src)->getNumElements(); i < e; ++i) - Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i); + Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i, nullptr, + nullptr); return Cost; } diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h index 9db903baf407..810a7d0d62ef 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -126,8 +126,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 02ce1b135f7f..ed8af25998b0 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1216,12 +1216,13 @@ InstructionCost RISCVTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { assert(Val->isVectorTy() && "This must be a vector type"); if (Opcode != Instruction::ExtractElement && Opcode != Instruction::InsertElement) - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // Legalize the type. std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Val); @@ -1235,7 +1236,7 @@ InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return LT.first; if (!isTypeLegal(Val)) - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // In RVV, we could use vslidedown + vmv.x.s to extract element from vector // and vslideup + vmv.s.x to insert element to vector. diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 80c7ca3564d7..5df266ba35b5 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -157,8 +157,8 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp index 5d00e56ae347..d6736319a404 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -996,7 +996,8 @@ InstructionCost SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost SystemZTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { // vlvgp will insert two grs into a vector register, so only count half the // number of instructions. if (Opcode == Instruction::InsertElement && Val->isIntOrIntVectorTy(64)) @@ -1012,7 +1013,7 @@ InstructionCost SystemZTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return Cost; } - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); } // Check if a load may be folded as a memory operand in its user. diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h index 5ac3d8149a1d..33c3778d572c 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -107,8 +107,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); bool isFoldableLoad(const LoadInst *Ld, const Instruction *&FoldedValue); InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp index 38464627e742..b94dcd63ad8b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp @@ -82,9 +82,10 @@ InstructionCost WebAssemblyTTIImpl::getArithmeticInstrCost( InstructionCost WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, + Value *Op0, Value *Op1) { InstructionCost Cost = - BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); + BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // SIMD128's insert/extract currently only take constant indices. if (Index == -1u) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h index 7eed7ef44af7..4f54a762042f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -66,8 +66,8 @@ public: ArrayRef<const Value *> Args = ArrayRef<const Value *>(), const Instruction *CxtI = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); /// @} diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 7d08a1654be7..5b6c7d86cebe 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -4257,7 +4257,8 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { static const CostTblEntry SLMCostTbl[] = { { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, @@ -4330,6 +4331,14 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, } } + MVT MScalarTy = LT.second.getScalarType(); + auto IsCheapPInsrPExtrInsertPS = [&]() { + return (MScalarTy == MVT::i16 && ST->hasSSE2()) || + (MScalarTy.isInteger() && ST->hasSSE41()) || + (MScalarTy == MVT::f32 && ST->hasSSE41() && + Opcode == Instruction::InsertElement); + }; + if (Index == 0) { // Floating point scalars are already located in index #0. // Many insertions to #0 can fold away for scalar fp-ops, so let's assume @@ -4337,6 +4346,20 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (ScalarType->isFloatingPointTy()) return RegisterFileMoveCost; + if (Opcode == Instruction::InsertElement && + isa_and_nonnull<UndefValue>(Op0)) { + // Consider the gather cost to be cheap. + if (isa_and_nonnull<LoadInst>(Op1)) + return RegisterFileMoveCost; + if (!IsCheapPInsrPExtrInsertPS()) { + // mov constant-to-GPR + movd/movq GPR -> XMM. + if (isa_and_nonnull<Constant>(Op1) && Op1->getType()->isIntegerTy()) + return 2 + RegisterFileMoveCost; + // Assume movd/movq GPR -> XMM is relatively cheap on all targets. + return 1 + RegisterFileMoveCost; + } + } + // Assume movd/movq XMM -> GPR is relatively cheap on all targets. if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) return 1 + RegisterFileMoveCost; @@ -4344,19 +4367,13 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, int ISD = TLI->InstructionOpcodeToISD(Opcode); assert(ISD && "Unexpected vector opcode"); - MVT MScalarTy = LT.second.getScalarType(); if (ST->useSLMArithCosts()) if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) return Entry->Cost + RegisterFileMoveCost; // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. - if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || - (MScalarTy.isInteger() && ST->hasSSE41())) - return 1 + RegisterFileMoveCost; - // Assume insertps is relatively cheap on all targets. - if (MScalarTy == MVT::f32 && ST->hasSSE41() && - Opcode == Instruction::InsertElement) + if (IsCheapPInsrPExtrInsertPS()) return 1 + RegisterFileMoveCost; // For extractions we just need to shuffle the element to index 0, which @@ -4383,7 +4400,8 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) RegisterFileMoveCost += 1; - return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1) + + RegisterFileMoveCost; } InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, @@ -5155,7 +5173,8 @@ X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, } // Add the final extract element to the cost. - return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, @@ -5455,7 +5474,8 @@ X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, } // Add the final extract element to the cost. - return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } /// Calculate the cost of materializing a 64-bit value. This helper diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 666789e160dc..c189e503f4e8 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -147,8 +147,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract); diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index e1b52aa2f80e..8ca422cfab9f 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -6745,9 +6745,24 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, // broadcast. assert(VecTy == FinalVecTy && "No reused scalars expected for broadcast."); - return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy, - /*Mask=*/std::nullopt, CostKind, /*Index=*/0, - /*SubTp=*/nullptr, /*Args=*/VL[0]); + const auto *It = + find_if(VL, [](Value *V) { return !isa<UndefValue>(V); }); + // If all values are undefs - consider cost free. + if (It == VL.end()) + return TTI::TCC_Free; + // Add broadcast for non-identity shuffle only. + bool NeedShuffle = + VL.front() != *It || !all_of(VL.drop_front(), UndefValue::classof); + InstructionCost InsertCost = + TTI->getVectorInstrCost(Instruction::InsertElement, VecTy, + /*Index=*/0, PoisonValue::get(VecTy), *It); + return InsertCost + (NeedShuffle + ? TTI->getShuffleCost( + TargetTransformInfo::SK_Broadcast, VecTy, + /*Mask=*/std::nullopt, CostKind, + /*Index=*/0, + /*SubTp=*/nullptr, /*Args=*/VL[0]) + : TTI::TCC_Free); } InstructionCost ReuseShuffleCost = 0; if (NeedToShuffleReuses) diff --git a/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll index 3e0f4c11aadf..1e96f97f16e9 100644 --- a/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll @@ -20,7 +20,7 @@ vector.body: ; preds = %vector.body, %vecto %5 = extractelement <2 x i64> %2, i32 1 %6 = getelementptr inbounds i32, ptr %A, i64 %5 %7 = load i32, ptr %4, align 4 - ;CHECK: cost of 1 {{.*}} insert + ;CHECK: cost of 0 {{.*}} insert %8 = insertelement <2 x i32> poison, i32 %7, i32 0 %9 = load i32, ptr %6, align 4 ;CHECK: cost of 1 {{.*}} insert diff --git a/llvm/test/Analysis/CostModel/X86/loop_v2.ll b/llvm/test/Analysis/CostModel/X86/loop_v2.ll index a9cbaaf2fd63..8f67b365ca9b 100644 --- a/llvm/test/Analysis/CostModel/X86/loop_v2.ll +++ b/llvm/test/Analysis/CostModel/X86/loop_v2.ll @@ -20,7 +20,7 @@ vector.body: ; preds = %vector.body, %vecto %5 = extractelement <2 x i64> %2, i32 1 %6 = getelementptr inbounds i32, ptr %A, i64 %5 %7 = load i32, ptr %4, align 4 - ;CHECK: cost of 1 {{.*}} insert + ;CHECK: cost of 0 {{.*}} insert %8 = insertelement <2 x i32> undef, i32 %7, i32 0 %9 = load i32, ptr %6, align 4 ;CHECK: cost of 1 {{.*}} insert diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll index 381e5b630812..897344d622d0 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll @@ -1907,7 +1907,7 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask2' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> poison, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind @@ -1966,7 +1966,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) { ; SSE2-LABEL: 'test_scatter_16i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> poison, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll index 2fa41968e807..5f22b2e39f94 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll @@ -1907,7 +1907,7 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask2' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind @@ -1966,7 +1966,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) { ; SSE2-LABEL: 'test_scatter_16i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> diff --git a/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll index 2296b3d5b0c4..e6a4de688186 100644 --- a/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll @@ -382,58 +382,58 @@ define i32 @insert_i64(i32 %arg) { define i32 @insert_i32(i32 %arg) { ; SSE2-LABEL: 'insert_i32' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SSE3-LABEL: 'insert_i32' ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SSSE3-LABEL: 'insert_i32' ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; @@ -664,100 +664,100 @@ define i32 @insert_i16(i32 %arg) { define i32 @insert_i8(i32 %arg) { ; SSE2-LABEL: 'insert_i8' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31 ; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31 -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32 -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63 </cut>

2 years, 7 months

1
0
0 0

[ACTIVITY] Report for week #2

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Fixed a regression found when preparing the new patches. Rebased on the current mainline branch and continued preparing patches for upstream submission. # Misc - Found a minor problem with a script in upstream GDB. Submitted and committed a quick patch¹ to fix it. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20230111174501.3699871-1-thiago.ba…

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 13 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - another round of patch review and a pull request * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - Made some useful progress with the FEAT_FGT implementation -- PMM

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending 8 Jan 2023

by Richard Henderson

* A couple of attempts at minimizing arm per-cpu init work. I've posted a short/medium-term solution for the lookup issue, so that we can re-apply Alex's CPUState unrealize patch. * TCG patch queue flushed, including call abi reorg. - Rebase TCGv_i128 patch set - Rebase goto_tb race condition patch set r~

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending Jan. 8 2023

by Alex Bennée

Project Stratos =============== vhost-device maintainer effort ([UM-196]) - a few version bump reviews Plugin register access ([QEMU-495]) =================================== - posted [PATCH v2 00/21] gdbstub: re-organise to for better compilation behaviour Message-Id: <20230105164320.2164095-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] docs: add some details about compilation units to coding style Message-Id: <20230103104758.767266-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: fix handling of HLT semihosting in system mode Message-Id: <20230105114304.2017493-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] testing: probe gdb for supported architectures ahead of time Message-Id: <20230105181533.2235792-1-alex.bennee(a)linaro.org> - posted [PATCH v2] scripts/ci: update gitlab-runner playbook to use latest runner Message-Id: <20230106152338.2599827-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [5/5] ======================= [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH v2] semihosting: add O_BINARY flag in host_open for NT compatibility Message-Id: <20230106102018.20520-1-eiakovlev(a)linux.microsoft.com> [PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64 Message-Id: <75da8346.1fd34.1856e0d08ef.Coremail.fanwj(a)mail.ustc.edu.cn> [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> Other ===== - bit of travel forecasting Current Review Queue ==================== TODO [RFC PATCH 00/40] Toward class init of cpu features Message-Id: <20230103181646.55711-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [RFC PATCH v6] virtio-video: Add virtio video device specification Message-Id: <20221208072325.2259940-1-acourbot(a)chromium.org> =================================================================================================================================== TODO [RFC PATCH kvmtool v1 00/32] Add support for restricted guest memory in kvmtool Message-Id: <20221202174417.1310826-1-tabba(a)google.com> =========================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 6 Jan

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] - Pretty much entirely trying to catch up with the code review backlog that had built up over the holidays. Got it down from 35 items to 7... Absences: * NB: I work a 4 day week, excluding Wednesdays * Apr 26 -- 28 : Linaro Connect (London) In office (provisional; let me know if you have preferences!): * week of the 9 Jan -- PMM

2 years, 7 months

1
0
0 0

[ACTIVITY] Report for week #52

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Identified a regression on systems that do not support SVE. Debugged it and now working on a fix. -- Thiago

2 years, 7 months

1
0
0 0

[ACTIVITY] Report for week #51

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished implementing the new approach of sending new XML target descriptions through the wire. - Fixed a couple of minor regressions I introduced and rebased the code on the current main branch. - Now preparing the patches for submitting upstream. # Community participation - Reviewed mailing list patch “[PATCH] [AArch64] Enable pointer authentication support for aarch64 bare metal/kernel mode addresses”. -- Thiago

2 years, 8 months

1
0
0 0

[ACTIVITY] week ending Dec. 25 2022

by Alex Bennée

Project Stratos =============== - started reviewing [PATCH v9 0/8] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221025151344.3784230-1-chao.p.peng(a)linux.intel.com> - trying to assess if user-space facing solution for memory sharing - writing up a [proposal for an API] [proposal for an API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> vhost-device maintainer effort ([UM-196]) - debugged regression in virtio-vsock and QEMU - should have some error message patches to post - QEMU 7.2 shipped with stubs for virtio-gpio and virtio-i2c [UM-196] <https://linaro.atlassian.net/browse/UM-196> Single Binary ([QEMU-487]) ========================== - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> Plugin register access ([QEMU-495]) =================================== - While experimenting with [the register API] ran into issues integrating to gdbstub - started a [re-factor] to make the process less painful - posted [PATCH v1 00/10] split user and system code in gdbstub Message-Id: <20221216112206.3171578-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> [the register API] <https://github.com/stsquad/qemu/tree/introspection/registers> [re-factor] <https://github.com/stsquad/qemu/tree/gdbstub/next> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 0/6] testing updates Message-Id: <20221221144019.2149905-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] gitdm metadata updates Message-Id: <20221219121914.851488-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [5/5] ======================= [QEMU][PATCH v2 00/11] Introduce xenpv machine for arm architecture Message-Id: <20221202030003.11441-1-vikram.garhwal(a)amd.com> [PATCH] configure: Fix check-tcg not executing any tests Message-Id: <20221207082309.9966-1-quic_mthiyaga(a)quicinc.com> [PATCH v4 00/27] tcg misc patches Message-Id: <20221213212541.1820840-1-richard.henderson(a)linaro.org> [PATCH v3 0/8] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221209051914.398215-1-richard.henderson(a)linaro.org> [PATCH-for-8.0 0/5] accel/tcg: Restrict page_collection structure to system TB maintainance Message-Id: <20221209093649.43738-1-philmd(a)linaro.org> Absences ======== Christmas holidays - merry Christmas! Current Review Queue ==================== TODO [RFC PATCH v6] virtio-video: Add virtio video device specification Message-Id: <20221208072325.2259940-1-acourbot(a)chromium.org> =================================================================================================================================== TODO [RFC PATCH kvmtool v1 00/32] Add support for restricted guest memory in kvmtool Message-Id: <20221202174417.1310826-1-tabba(a)google.com> =========================================================================================================================================== TODO [PATCH v10 0/9] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221202061347.1070246-1-chao.p.peng(a)linux.intel.com> ==================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 20 Dec

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - I'm now back on merging duty for the 8.0 release cycle, so some time spent on pull request processing - Sent pull requests with accumulated arm and reset-refactoring patches from the freeze period - Trying to cut down my code review backlog before the holidays -- PMM

2 years, 8 months

1
0
0 0

[ACTIVITY] Report for week #50

by Thiago Jung Bauermann

# [GNU-767] Support changing SVE vector length in remote debugging - Patches to gdbserver to support changing the SVE vector length: About halfway through implementing the new approach of sending new XML target descriptions through the wire. # Misc - Experimented with using a GDB wrapper to run the testsuite. Came up with a small patch that fixes the tests that fail when using the wrapper. -- Thiago

2 years, 8 months

1
0
0 0

[TCWG CI] Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.

by ci_notify＠linaro.org

Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 7572 # First few build errors in logs: # 00:10:43 drivers/gpu/drm/v3d/v3d_perfmon.c:57:1: internal compiler error: in decompose, at rtl.h:2288 # 00:10:44 make[5]: *** [scripts/Makefile.build:250: drivers/gpu/drm/v3d/v3d_perfmon.o] Error 1 # 00:10:53 make[4]: *** [scripts/Makefile.build:502: drivers/gpu/drm/v3d] Error 2 # 00:13:52 drivers/media/mc/mc-device.c:198:1: internal compiler error: in decompose, at rtl.h:2288 # 00:13:53 make[4]: *** [scripts/Makefile.build:250: drivers/media/mc/mc-device.o] Error 1 # 00:13:57 make[3]: *** [scripts/Makefile.build:502: drivers/media/mc] Error 2 # 00:15:27 make[2]: *** [scripts/Makefile.build:502: drivers/media] Error 2 # 00:17:50 make[3]: *** [scripts/Makefile.build:502: drivers/gpu/drm] Error 2 # 00:17:50 make[2]: *** [scripts/Makefile.build:502: drivers/gpu] Error 2 # 00:17:50 make[1]: *** [scripts/Makefile.build:502: drivers] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 8625 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-4618-g17ae956c0fa commit for tcwg_kernel: commit 17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 Author: Tamar Christina <tamar.christina(a)arm.com> Date: Mon Dec 12 15:18:56 2022 +0000 AArch64: Support new tbranch optab. This implements the new tbranch optab for AArch64. we cannot emit one big RTL for the final instruction immediately. The reason that all comparisons in the AArch64 backend expand to separate CC compares, and separate testing of the operands is for ifcvt. The separate CC compare is needed so ifcvt can produce csel, cset etc from the compares. Unlike say combine, ifcvt can not do recog on a parallel with a clobber. Should we emit the instruction directly then ifcvt will not be able to say, make a csel, because we have no patterns which handle zero_extract and compare. (unlike combine ifcvt cannot transform the extract into an AND). While you could provide various patterns for this (and I did try) you end up with broken patterns because you can't add the clobber to the CC register. If you do, ifcvt recog fails. i.e. int f1 (int x) { if (x & 1) return 1; return x; } We lose csel here. Secondly the reason the compare with an explicit CC mode is needed is so that ifcvt can transform the operation into a version that doesn't require the flags to be set. But it only does so if it know the explicit usage of the CC reg. For instance int foo (int a, int b) { return ((a & (1 << 25)) ? 5 : 4); } Doesn't require a comparison, the optimal form is: foo(int, int): ubfx x0, x0, 25, 1 add w0, w0, 4 ret and no compare is actually needed. If you represent the instruction using an ANDS instead of a zero_extract then you get close, but you end up with an ands followed by an add, which is a slower operation. gcc/ChangeLog: * config/aarch64/aarch64.md (*tb<optab><mode>1): Rename to... (*tb<optab><ALLI:mode><GPI:mode>1): ... this. (tbranch_<code><mode>4): New. * config/aarch64/iterators.md(ZEROM, zerom): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/tbz_1.c: New test. * gnu-master-aarch64-mainline-defconfig ** Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Reproduce current build: <cut> mkdir -p investigate-gcc-17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 cd investigate-gcc-17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 Author: Tamar Christina <tamar.christina(a)arm.com> Date: Mon Dec 12 15:18:56 2022 +0000 AArch64: Support new tbranch optab. This implements the new tbranch optab for AArch64. we cannot emit one big RTL for the final instruction immediately. The reason that all comparisons in the AArch64 backend expand to separate CC compares, and separate testing of the operands is for ifcvt. The separate CC compare is needed so ifcvt can produce csel, cset etc from the compares. Unlike say combine, ifcvt can not do recog on a parallel with a clobber. Should we emit the instruction directly then ifcvt will not be able to say, make a csel, because we have no patterns which handle zero_extract and compare. (unlike combine ifcvt cannot transform the extract into an AND). While you could provide various patterns for this (and I did try) you end up with broken patterns because you can't add the clobber to the CC register. If you do, ifcvt recog fails. i.e. int f1 (int x) { if (x & 1) return 1; return x; } We lose csel here. Secondly the reason the compare with an explicit CC mode is needed is so that ifcvt can transform the operation into a version that doesn't require the flags to be set. But it only does so if it know the explicit usage of the CC reg. For instance int foo (int a, int b) { return ((a & (1 << 25)) ? 5 : 4); } Doesn't require a comparison, the optimal form is: foo(int, int): ubfx x0, x0, 25, 1 add w0, w0, 4 ret and no compare is actually needed. If you represent the instruction using an ANDS instead of a zero_extract then you get close, but you end up with an ands followed by an add, which is a slower operation. gcc/ChangeLog: * config/aarch64/aarch64.md (*tb<optab><mode>1): Rename to... (*tb<optab><ALLI:mode><GPI:mode>1): ... this. (tbranch_<code><mode>4): New. * config/aarch64/iterators.md(ZEROM, zerom): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/tbz_1.c: New test. --- gcc/config/aarch64/aarch64.md | 33 ++++++++--- gcc/config/aarch64/iterators.md | 2 + gcc/testsuite/gcc.target/aarch64/tbz_1.c | 95 ++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 8 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 896b6a8ac79..d749c98eef6 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -947,12 +947,29 @@ (const_int 1)))] ) -(define_insn "*tb<optab><mode>1" +(define_expand "tbranch_<code><mode>3" [(set (pc) (if_then_else - (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r") - (const_int 1) - (match_operand 1 - "aarch64_simd_shift_imm_<mode>" "n")) + (EQL (match_operand:ALLI 0 "register_operand") + (match_operand 1 "aarch64_simd_shift_imm_<mode>")) + (label_ref (match_operand 2 "")) + (pc)))] + "" +{ + rtx bitvalue = gen_reg_rtx (<ZEROM>mode); + rtx reg = gen_lowpart (<ZEROM>mode, operands[0]); + rtx val = GEN_INT (1UL << UINTVAL (operands[1])); + emit_insn (gen_and<zerom>3 (bitvalue, reg, val)); + operands[1] = const0_rtx; + operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue, + operands[1]); +}) + +(define_insn "*tb<optab><ALLI:mode><GPI:mode>1" + [(set (pc) (if_then_else + (EQL (zero_extract:GPI (match_operand:ALLI 0 "register_operand" "r") + (const_int 1) + (match_operand 1 + "aarch64_simd_shift_imm_<ALLI:mode>" "n")) (const_int 0)) (label_ref (match_operand 2 "" "")) (pc))) @@ -963,15 +980,15 @@ { if (get_attr_far_branch (insn) == 1) return aarch64_gen_far_branch (operands, 2, "Ltb", - "<inv_tb>\\t%<w>0, %1, "); + "<inv_tb>\\t%<ALLI:w>0, %1, "); else { operands[1] = GEN_INT (HOST_WIDE_INT_1U << UINTVAL (operands[1])); - return "tst\t%<w>0, %1\;<bcond>\t%l2"; + return "tst\t%<ALLI:w>0, %1\;<bcond>\t%l2"; } } else - return "<tbz>\t%<w>0, %1, %l2"; + return "<tbz>\t%<ALLI:w>0, %1, %l2"; } [(set_attr "type" "branch") (set (attr "length") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d10cf93572e..a521dbde1ec 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1107,6 +1107,8 @@ ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) +(define_mode_attr ZEROM [(QI "SI") (HI "SI") (SI "SI") (DI "DI")]) +(define_mode_attr zerom [(QI "si") (HI "si") (SI "si") (DI "di")]) ;; Give the ordinal of the MSB in the mode (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") diff --git a/gcc/testsuite/gcc.target/aarch64/tbz_1.c b/gcc/testsuite/gcc.target/aarch64/tbz_1.c new file mode 100644 index 00000000000..39deb58e278 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tbz_1.c @@ -0,0 +1,95 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -std=c99 -fno-unwind-tables -fno-asynchronous-unwind-tables" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#include <stdbool.h> + +void h(void); + +/* +** g1: +** tbnz w[0-9]+, #?0, .L([0-9]+) +** ret +** ... +*/ +void g1(bool x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g2: +** tbz w[0-9]+, #?0, .L([0-9]+) +** b h +** ... +*/ +void g2(bool x) +{ + if (__builtin_expect (x, 1)) + h (); +} + +/* +** g3_ge: +** tbnz w[0-9]+, #?31, .L[0-9]+ +** b h +** ... +*/ +void g3_ge(int x) +{ + if (__builtin_expect (x >= 0, 1)) + h (); +} + +/* +** g3_gt: +** cmp w[0-9]+, 0 +** ble .L[0-9]+ +** b h +** ... +*/ +void g3_gt(int x) +{ + if (__builtin_expect (x > 0, 1)) + h (); +} + +/* +** g3_lt: +** tbz w[0-9]+, #?31, .L[0-9]+ +** b h +** ... +*/ +void g3_lt(int x) +{ + if (__builtin_expect (x < 0, 1)) + h (); +} + +/* +** g3_le: +** cmp w[0-9]+, 0 +** bgt .L[0-9]+ +** b h +** ... +*/ +void g3_le(int x) +{ + if (__builtin_expect (x <= 0, 1)) + h (); +} + +/* +** g5: +** mov w[0-9]+, 65279 +** tst w[0-9]+, w[0-9]+ +** beq .L[0-9]+ +** b h +** ... +*/ +void g5(int x) +{ + if (__builtin_expect (x & 0xfeff, 1)) + h (); +} </cut>

2 years, 8 months

1
0
0 0

[ACTIVITY] Report for week #49

by Thiago Jung Bauermann

# [GNU-767] Support changing SVE vector length in remote debugging - Patches to gdbserver to support changing the SVE vector length: There was an upstream discussion about whether changing the implementation from relying on expedited registers to relying on sending target descriptions over the wire was a better approach. Simon Marchi detailed his idea on how to do that and it does seem better. - Started implementing Simon's approach of sending target descriptions over the wire for each thread. # Misc - Sent and later committed a couple of patches¹ fixing whitespace issues in a Python script that generates a GDB source file. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221202192200.405379-1-thiago.bau…

2 years, 8 months

1
0
0 0

[ACTIVITY] Report for week #48

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - v2 of the gdbserver patches to support changing the SVE vector length was quickly reviewed by both Luis and Simon Marchi. I applied their review suggestions and I'm now working on fixing a bug with multi-threaded programs that they spotted. - Submitted a couple of small patches¹ fixing tab vs spaces issues in the gdbarch.py script that generates some source code in GDB. # Misc - Fixed problem in the tcwg-dev/start.sh script where asking docker to expose /dev/kvm to a dev container on a host which doesn't have KVM support causes docker to error out (reported by David Spickett). Sent Gerrit change request “42669: tcwg-dev: Add heuristic to check for KVM support on the host” to fix it. David reviewed and merged it. Thanks! -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221202192200.405379-1-thiago.bau…

2 years, 8 months

1
0
0 0

[ACTIVITY] Report for week #47

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Worked on v2 of the gdbserver patches improving SVE support. Found a couple of simplifications that could be made to the code. Rebased on current master branch and finished regression testing and patch preparation. Wrote the cover letter. - Finally posted the patch series upstream¹. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221126020452.1686509-1-thiago.ba…

2 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 25 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - More conversions of devices to 3-phase reset in pursuit of the interim goal of getting rid of device_class_set_parent_reset() - Investigated a regression in a TF-A workload: this was due to recent pagetable walk refactoring breaking debug accesses. - code review, etc; mostly this has been of for-8.0 material, as (other than the above mentioned ptw regression) there haven't been many release-worthy issues this freeze cycle. -- PMM

2 years, 9 months

1
0
0 0

[TCWG CI] 403.gcc failed to run after working-3971-g5f7f484ee54e: [AArch64] Add GPR rr instructions to isAssociativeAndCommutative

by Maxim Kuvyrkov

Hi David, Our CI flagged your commit; it seems it miscompiles 403.gcc from SPEC CPU2006 at -O3 -flto for aarch64-linux-gnu. Would you please investigate? Let me know if you need any assistance in reproducing this. Thanks! === After working-3971-g5f7f484ee54e commit 5f7f484ee54ebbf702ee4c5fe9852502dc237121 Author: David Green <david.green(a)arm.com> [AArch64] Add GPR rr instructions to isAssociativeAndCommutative the following benchmarks slowed down by more than 3%: - 403.gcc failed to run Configuration: - Benchmark: SPEC CPU2006 - Toolchain: Clang + Glibc + LLVM Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 -flto - Hardware: NVidia TX1 4x Cortex-A57 -- Maxim Kuvyrkov https://www.linaro.org

2 years, 9 months

2
2
0 0

[ACTIVITY] Report for week #46

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Working on v2 of the gdbserver patches improving SVE support. Found and fixed a memory leak in my code while preparing patches for upstream submission. Continuing preparing the patches. # [GNU-796] Stabilise GDB testsuite results in the CI - Analysed failures of “fast_check_gdb” CI jobs over the weekend. They were caused by unrelated build issues in GCC and libstdc++. -- Thiago

2 years, 9 months

1
0
0 0

[ACTIVITY] week ending Nov. 20 2022

by Alex Bennée

Project Stratos =============== - finished [blog post for virtio-camera] - now live [on web site] - did a review of [virtio-loopback] - started reviewing [PATCH v9 0/8] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221025151344.3784230-1-chao.p.peng(a)linux.intel.com> - trying to assess if user-space facing solution for memory sharing [blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> [on web site] <https://www.linaro.org/blog/the-challenges-of-abstracting-virtio/> [virtio-loopback] <https://git.virtualopensystems.com/virtio-loopback> vhost-device maintainer effort ([UM-196]) - debugged regression in virtio-vsock and QEMU - should have some error message patches to post [UM-196] <https://linaro.atlassian.net/browse/UM-196> Single Binary ([QEMU-487]) ========================== - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> - posted [PULL for 7.2 00/10] testing and doc updates Message-Id: <20221115133439.2348929-1-alex.bennee(a)linaro.org> - did a bunch of follow-up testing to shake out other console bugs - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> - posted [PATCH for 7.2? v1 0/2] Arm GICv2 patches Message-Id: <20221115134048.2352715-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - hackbox2 upgrade follow-up - health check content Completed Reviews [1/1] ======================= [PATCH] ci: replace x86_64 macos-11 with aarch64 macos-12 Message-Id: <20221116175023.80627-1-berrange(a)redhat.com> Absences ======== Current Review Queue ==================== TODO [PATCH v6 00/21] Drivers for gunyah hypervisor Message-Id: <20221026185846.3983888-1-quic_eberman(a)quicinc.com> ================================================================================================================== TODO [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> ======================================================================================================== TODO [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Message-Id: <20221111074101.2069454-1-richard.henderson(a)linaro.org> ===================================================================================================================================== -- Alex Bennée

2 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 18 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- the usual release cycle work. Looks relatively quiet this time around. -- taking the opportunity to try to catch up on some of the for-8.0 code review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] -- started thinking about how to implement FEAT_FGT. Looking at the code where this ought to go, I found a minor bug with how we implement the existing HSTR_EL2 traps, and a case where we trap AArch32 ATS12NSO* with the wrong syndrome. -- PMM

2 years, 9 months

1
0
0 0

[ACTIVITY] Report for week #45

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Working on v2 of the gdbserver patches improving SVE support. Tested new code for regressions in different systems and configurations and found none. Preparing new version of the patches for upstream submission. Will likely post them early next week. -- Thiago

2 years, 9 months

1
0
0 0

[ACTIVITY] week ending Nov. 13 2022

by Alex Bennée

Project Stratos =============== - finished [blog post for virtio-camera] - did a review of [virtio-loopback] [blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> [virtio-loopback] <https://git.virtualopensystems.com/virtio-loopback> vhost-device maintainer effort ([UM-196]) - review work Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - hackbox2 upgrade follow-up - health check content Completed Reviews [7/7] ======================= [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-1-richard.henderson(a)linaro.org> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH] Run docker probe only if docker or podman are available Message-Id: <20221030083510.310584-1-sw(a)weilnetz.de> [PULL 3/3] linux-test (tests/tcg/multiarch/linux-test.c) add check Message-Id: <1626902375-7002-4-git-send-email-tsimpson(a)quicinc.com> [PATCH v5 00/18] tests/qtest: Enable running qtest on Windows Message-Id: <20221006151927.2079583-3-bmeng.cn(a)gmail.com> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH RFC 0/1] tcg: add perfmap and jitdump Message-Id: <20221012051846.1432050-1-iii(a)linux.ibm.com> Absences ======== Current Review Queue ==================== TODO [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Message-Id: <20221111074101.2069454-1-richard.henderson(a)linaro.org> ===================================================================================================================================== TODO [PATCH v3 0/7] memory: prevent dma-reentracy issues Message-Id: <20221028191648.964076-1-alxndr(a)bu.edu> =========================================================================================================== TODO [QEMU][PATCH v2 0/5] Introduce Xilinx Versal CANFD Message-Id: <20221022054746.28217-1-vikram.garhwal(a)amd.com> ================================================================================================================== -- Alex Bennée

2 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 10 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- identified another piece of the reset mechanics that can be tractably cleaned up: I think we should be able to get everything (effectively) moved over to the 3-phase reset system -- sent out various for-8.0 patchsets that convert devices that were using device_class_set_parent_reset(), since getting rid of that function is step 1 of that cleanup -- code review etc -- PMM

2 years, 9 months

1
0
0 0

[ACTIVITY] Report for week #44

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Confirmed that gdbserver doesn't send a new XML target description over the wire when the vector length changes, so there's no impact of these patches on the amount of remote protocol traffic, which was a concern for GDB maintainers. - Started doing some up code cleanup and regression tests to prepare for submitting v2 of the patches. # [GNU-796] Stabilise GDB testsuite results in the CI - Committed Gerrit change request adding the new CI job¹ to run fast subset of GDB tests, which also has stable results. The list of tests comes from Sourceware's builder project. -- Thiago ¹ https://ci.linaro.org/view/tcwg_gnu_native/job/tcwg_gnu_native_fast_check_g…

2 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 4 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- investigated and thought a bit more about a race condition involving display devices. I know think I understand the problem but the best idea I could come up with for a solution is pretty painful... (Still hoping for feedback on whether I've missed something.) -- collated and sent out a pull request with various bug fixes for rc0 -- sent some more reset-cleanup patches (these will be for 8.0) -- PMM

2 years, 9 months

1
0
0 0

Virt meeting 2022-11-01

by Richard Henderson

Hi guys, I will attempt to join today, but we've been finding that connectivity is dependent on the number of rain drops and/or hail in between here and the mast. So I'm not overly hopeful for later this evening. Status report: - Fixed a failure in my x86 TARGET_TB_PCREL patches, which caused non-booting of some images (in today's tcg PR). - Revised the TCGv_i128 patch set (not yet posted). - Lots of work on accel/tcg/{cputlb,user-exec}.c, to honor atomicity requirements of FEAT_LSE2. Next up: Adding qemu_ld/st helpers and patterns for i128. r~

2 years, 9 months

1
0
0 0

[ACTIVITY] Report for week #43

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. Started checking changes for regressions. -- Thiago

2 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 28 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Cross-checked our boot.c code against the kernel's booting.rst, and sent patch fixing a few EL3 config bits we weren't setting - Sent out the minutes from QEMU Summit * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - Wrote and sent out patches to implement the extra traps required for FEAT_EVT -- PMM

2 years, 10 months

1
0
0 0

[ACTIVITY] Report for week #42

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilise GDB testsuite results in the CI - Reworked and committed Gerrit change request for jenkins-scripts adding a new CI job definition in tcwg_gnu-build.sh. - Also reworked and committed another one to the same script adding a default manifest file if one isn't specified on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Implemented Luis' suggestion of assuming that if ptrace can't read the SVE state, then SVE is disabled (which is what gdbserver does before my patches). It turns out that the only situation where this happens, gdbserver doesn't actually care about the target description. - Started exploring/implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. As Luis suggests, it may simplify the code. -- Thiago

2 years, 10 months

1
0
0 0

[ACTIVITY] week ending Oct. 23 2022

by Alex Bennée

Project Stratos =============== - wrote a [draft blog post for virtio-camera] [draft blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> vhost-device maintainer effort ([UM-196]) - review work [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: don't process FCSE translations on physical TLBs Message-Id: <20221021172338.2782240-1-alex.bennee(a)linaro.org> - posted [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: protect execlog's last_exec expansion Message-Id: <20221021164028.2757262-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: enable debug on CONFIG_DEBUG_TCG Message-Id: <20221021155146.2729598-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [4/4] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits Message-Id: <20221020123506.26363-1-ani(a)anisinha.ca> Other ===== - reviews and appraisals - members operational meeting - QEMU plans Absences ======== Current Review Queue ==================== TODO [PATCH 00/31] tcg: Support for Int128 with helpers Message-Id: <20221020115242.2301066-1-richard.henderson(a)linaro.org> ========================================================================================================================== TODO [PATCH v8 0/9] target/arm: pc-relative translation blocks Message-Id: <20221020030641.2066807-1-richard.henderson(a)linaro.org> ================================================================================================================================= TODO [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> ============================================================================================================================ -- Alex Bennée

2 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 21 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Spent a couple of days investigating a long-standing intermittent test case failure booting a kernel on the raspberry pi. This turned out to be caused by two linked bugs: - the test framework unhelpfully disconnects immediately from the guest serial console when the test ends, rather than staying connected until the QEMU process exits to capture all the output - QEMU's socket chardev loses data when the remote end closes the connection if the guest UART hasn't read all of it So the test was failing because the guest sometimes only saw the 'h' of the final 'halt' command the test sent... - Investigated and fixed a regression caused by some of last week's reset patches. (Turns out the patch to fix it had been sent back in 2021 but we accidentally dropped it on the floor. Oops.) thanks -- PMM

2 years, 10 months

1
0
0 0

[ACTIVITY] Report for week #41

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued incorporating suggestions from Luis' review of the patches. Working on a few regressions I introduced in the process. # [GNU-796] Stabilise GDB testsuite results in the CI - Started addressing Maxim's comments to my change requests for jenkins-scripts. -- Thiago

2 years, 10 months

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[ACTIVITY] week ending Oct. 16 2022

by Alex Bennée

Project Stratos =============== - virtio-camera discussion and prep vhost-device maintainer effort ([UM-196]) - more review, vsock merged \o/ [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - more leadership committee work - more member engagement on CCA/RME - posted [PATCH v1 0/4] testing/next hotfix (revert bios build, mingw) Message-Id: <20221011113417.794841-1-alex.bennee(a)linaro.org> - posted [PULL 0/1] testing: revert pc-bios build patch Message-Id: <20221011192858.956078-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/7] testing/next (configure, RUNC, win32|64) Message-Id: <20221013154705.1846261-1-alex.bennee(a)linaro.org> - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [2/2] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> Other ===== - reviews and appraisals - other admin Absences ======== - day off ill Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== -- Alex Bennée

2 years, 10 months

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[ACTIVITY] report week ending 14 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Started looking again at QEMU's rather messy set of reset related APIs. Dug out the half-a-plan I wrote up a long time back and refreshed my memory of what I was hoping we might be able to do. - As an initial step, wrote some patches to get rid of uses of several deprecated reset-related functions so that I only have to think about one set of functions and not two... -- PMM

2 years, 10 months

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[TCWG CI] Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses

by ci_notify＠linaro.org

Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 624 # First few build errors in logs: # 00:01:42 mm/slub.c:4428:5: error: virtual use of statement not up to date # 00:01:42 mm/slub.c:4428:5: internal compiler error: verify_ssa failed # 00:01:43 make[2]: *** [scripts/Makefile.build:250: mm/slub.o] Error 1 # 00:01:44 make[1]: *** [scripts/Makefile.build:500: mm] Error 2 # 00:01:56 make: *** [Makefile:1990: .] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 629 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-3219-g25413fdb2ac commit for tcwg_kernel: commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. * gnu-master-aarch64-next-allnoconfig ** Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Reproduce current build: <cut> mkdir -p investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 cd investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. --- gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c | 40 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c | 44 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c | 45 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c | 39 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c | 42 +++ gcc/tree-if-conv.cc | 313 ++++++++++++++++++-- gcc/tree-vect-data-refs.cc | 3 +- gcc/tree-vect-patterns.cc | 330 +++++++++++++++++++++- 14 files changed, 1079 insertions(+), 31 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c new file mode 100644 index 00000000000..01cf34fb444 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c @@ -0,0 +1,40 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define ELT0 {0} +#define ELT1 {1} +#define ELT2 {2} +#define ELT3 {3} +#define N 32 +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].i; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c new file mode 100644 index 00000000000..1a4a1579c14 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 0} +#define ELT1 {0x7FFFFFFFUL, 1} +#define ELT2 {0x7FFFFFFFUL, 2} +#define ELT3 {0x7FFFFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c new file mode 100644 index 00000000000..849f4a017e1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c @@ -0,0 +1,44 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" +#include <stdbool.h> + +extern void abort(void); + +typedef struct { + int c; + int b; + bool a : 1; + int d : 31; +} struct_t; + +#define N 16 +#define ELT_F { 0xFFFFFFFF, 0xFFFFFFFF, 0, 0x7FFFFFFF } +#define ELT_T { 0xFFFFFFFF, 0xFFFFFFFF, 1, 0x7FFFFFFF } + +struct_t vect_false[N] = { ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +struct_t vect_true[N] = { ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +int main (void) +{ + unsigned ret = 0; + for (unsigned i = 0; i < N; i++) + { + ret |= vect_false[i].a; + } + if (ret) + abort (); + + for (unsigned i = 0; i < N; i++) + { + ret |= vect_true[i].a; + } + if (!ret) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c new file mode 100644 index 00000000000..5bc9c412e96 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c @@ -0,0 +1,45 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 3, 0} +#define ELT1 {0x7FFFFFFFUL, 3, 1} +#define ELT2 {0x7FFFFFFFUL, 3, 2} +#define ELT3 {0x7FFFFFFFUL, 3, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c new file mode 100644 index 00000000000..1dc24d3eded --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 9; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c new file mode 100644 index 00000000000..7d24c299758 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 8; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c new file mode 100644 index 00000000000..19683d277b1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c @@ -0,0 +1,39 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].i = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].i != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c new file mode 100644 index 00000000000..d550dd35ab7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c new file mode 100644 index 00000000000..3303d2610ff --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c new file mode 100644 index 00000000000..fae6ea3557d --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 9; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c new file mode 100644 index 00000000000..99360c2967b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 8; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc index bac29fb5574..e468a4659fa 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -91,6 +91,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-pass.h" #include "ssa.h" #include "expmed.h" +#include "expr.h" #include "optabs-query.h" #include "gimple-pretty-print.h" #include "alias.h" @@ -123,6 +124,9 @@ along with GCC; see the file COPYING3. If not see #include "tree-vectorizer.h" #include "tree-eh.h" +/* For lang_hooks.types.type_for_mode. */ +#include "langhooks.h" + /* Only handle PHIs with no more arguments unless we are asked to by simd pragma. */ #define MAX_PHI_ARG_NUM \ @@ -145,6 +149,12 @@ static bool need_to_rewrite_undefined; before phi_convertible_by_degenerating_args. */ static bool any_complicated_phi; +/* True if we have bitfield accesses we can lower. */ +static bool need_to_lower_bitfields; + +/* True if there is any ifcvting to be done. */ +static bool need_to_ifcvt; + /* Hash for struct innermost_loop_behavior. It depends on the user to free the memory. */ @@ -1411,15 +1421,6 @@ if_convertible_loop_p_1 (class loop *loop, vec<data_reference_p> *refs) calculate_dominance_info (CDI_DOMINATORS); - /* Allow statements that can be handled during if-conversion. */ - ifc_bbs = get_loop_body_in_if_conv_order (loop); - if (!ifc_bbs) - { - if (dump_file && (dump_flags & TDF_DETAILS)) - fprintf (dump_file, "Irreducible loop\n"); - return false; - } - for (i = 0; i < loop->num_nodes; i++) { basic_block bb = ifc_bbs[i]; @@ -2899,18 +2900,22 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) class loop *new_loop; gimple *g; gimple_stmt_iterator gsi; - unsigned int save_length; + unsigned int save_length = 0; g = gimple_build_call_internal (IFN_LOOP_VECTORIZED, 2, build_int_cst (integer_type_node, loop->num), integer_zero_node); gimple_call_set_lhs (g, cond); - /* Save BB->aux around loop_version as that uses the same field. */ - save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; - void **saved_preds = XALLOCAVEC (void *, save_length); - for (unsigned i = 0; i < save_length; i++) - saved_preds[i] = ifc_bbs[i]->aux; + void **saved_preds = NULL; + if (any_complicated_phi || need_to_predicate) + { + /* Save BB->aux around loop_version as that uses the same field. */ + save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; + saved_preds = XALLOCAVEC (void *, save_length); + for (unsigned i = 0; i < save_length; i++) + saved_preds[i] = ifc_bbs[i]->aux; + } initialize_original_copy_tables (); /* At this point we invalidate porfile confistency until IFN_LOOP_VECTORIZED @@ -2922,8 +2927,9 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) profile_probability::always (), true); free_original_copy_tables (); - for (unsigned i = 0; i < save_length; i++) - ifc_bbs[i]->aux = saved_preds[i]; + if (any_complicated_phi || need_to_predicate) + for (unsigned i = 0; i < save_length; i++) + ifc_bbs[i]->aux = saved_preds[i]; if (new_loop == NULL) return NULL; @@ -2999,7 +3005,7 @@ ifcvt_split_critical_edges (class loop *loop, bool aggressive_if_conv) auto_vec<edge> critical_edges; /* Loop is not well formed. */ - if (num <= 2 || loop->inner || !single_exit (loop)) + if (loop->inner) return false; body = get_loop_body (loop); @@ -3260,6 +3266,201 @@ ifcvt_hoist_invariants (class loop *loop, edge pe) free (body); } +/* Returns the DECL_FIELD_BIT_OFFSET of the bitfield accesse in stmt iff its + type mode is not BLKmode. If BITPOS is not NULL it will hold the poly_int64 + value of the DECL_FIELD_BIT_OFFSET of the bitfield access and STRUCT_EXPR, + if not NULL, will hold the tree representing the base struct of this + bitfield. */ + +static tree +get_bitfield_rep (gassign *stmt, bool write, tree *bitpos, + tree *struct_expr) +{ + tree comp_ref = write ? gimple_assign_lhs (stmt) + : gimple_assign_rhs1 (stmt); + + tree field_decl = TREE_OPERAND (comp_ref, 1); + tree rep_decl = DECL_BIT_FIELD_REPRESENTATIVE (field_decl); + + /* Bail out if the representative is BLKmode as we will not be able to + vectorize this. */ + if (TYPE_MODE (TREE_TYPE (rep_decl)) == E_BLKmode) + return NULL_TREE; + + /* Bail out if the DECL_SIZE of the field_decl isn't the same as the BF's + precision. */ + unsigned HOST_WIDE_INT bf_prec + = TYPE_PRECISION (TREE_TYPE (gimple_assign_lhs (stmt))); + if (compare_tree_int (DECL_SIZE (field_decl), bf_prec) != 0) + return NULL_TREE; + + if (struct_expr) + *struct_expr = TREE_OPERAND (comp_ref, 0); + + if (bitpos) + *bitpos + = fold_build2 (MINUS_EXPR, bitsizetype, + DECL_FIELD_BIT_OFFSET (field_decl), + DECL_FIELD_BIT_OFFSET (rep_decl)); + + return rep_decl; + +} + +/* Lowers the bitfield described by DATA. + For a write like: + + struct.bf = _1; + + lower to: + + __ifc_1 = struct.<representative>; + __ifc_2 = BIT_INSERT_EXPR (__ifc_1, _1, bitpos); + struct.<representative> = __ifc_2; + + For a read: + + _1 = struct.bf; + + lower to: + + __ifc_1 = struct.<representative>; + _1 = BIT_FIELD_REF (__ifc_1, bitsize, bitpos); + + where representative is a legal load that contains the bitfield value, + bitsize is the size of the bitfield and bitpos the offset to the start of + the bitfield within the representative. */ + +static void +lower_bitfield (gassign *stmt, bool write) +{ + tree struct_expr; + tree bitpos; + tree rep_decl = get_bitfield_rep (stmt, write, &bitpos, &struct_expr); + tree rep_type = TREE_TYPE (rep_decl); + tree bf_type = TREE_TYPE (gimple_assign_lhs (stmt)); + + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Lowering:\n"); + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + fprintf (dump_file, "to:\n"); + } + + /* REP_COMP_REF is a COMPONENT_REF for the representative. NEW_VAL is it's + defining SSA_NAME. */ + tree rep_comp_ref = build3 (COMPONENT_REF, rep_type, struct_expr, rep_decl, + NULL_TREE); + tree new_val = ifc_temp_var (rep_type, rep_comp_ref, &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + if (write) + { + new_val = ifc_temp_var (rep_type, + build3 (BIT_INSERT_EXPR, rep_type, new_val, + unshare_expr (gimple_assign_rhs1 (stmt)), + bitpos), &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + gimple *new_stmt = gimple_build_assign (unshare_expr (rep_comp_ref), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + else + { + tree bfr = build3 (BIT_FIELD_REF, bf_type, new_val, + build_int_cst (bitsizetype, TYPE_PRECISION (bf_type)), + bitpos); + new_val = ifc_temp_var (bf_type, bfr, &gsi); + + gimple *new_stmt = gimple_build_assign (gimple_assign_lhs (stmt), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + + gsi_remove (&gsi, true); +} + +/* Return TRUE if there are bitfields to lower in this LOOP. Fill TO_LOWER + with data structures representing these bitfields. */ + +static bool +bitfields_to_lower_p (class loop *loop, + vec <gassign *> &reads_to_lower, + vec <gassign *> &writes_to_lower) +{ + gimple_stmt_iterator gsi; + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Analyzing loop %d for bitfields:\n", loop->num); + } + + for (unsigned i = 0; i < loop->num_nodes; ++i) + { + basic_block bb = ifc_bbs[i]; + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) + { + gassign *stmt = dyn_cast<gassign*> (gsi_stmt (gsi)); + if (!stmt) + continue; + + tree op = gimple_assign_lhs (stmt); + bool write = TREE_CODE (op) == COMPONENT_REF; + + if (!write) + op = gimple_assign_rhs1 (stmt); + + if (TREE_CODE (op) != COMPONENT_REF) + continue; + + if (DECL_BIT_FIELD_TYPE (TREE_OPERAND (op, 1))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + + if (!INTEGRAL_TYPE_P (TREE_TYPE (op))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NO OK to lower," + " field type is not Integral.\n"); + return false; + } + + if (!get_bitfield_rep (stmt, write, NULL, NULL)) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NOT OK to lower," + " representative is BLKmode.\n"); + return false; + } + + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\tBitfield OK to lower.\n"); + if (write) + writes_to_lower.safe_push (stmt); + else + reads_to_lower.safe_push (stmt); + } + } + } + return !reads_to_lower.is_empty () || !writes_to_lower.is_empty (); +} + + /* If-convert LOOP when it is legal. For the moment this pass has no profitability analysis. Returns non-zero todo flags when something changed. */ @@ -3270,12 +3471,16 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) unsigned int todo = 0; bool aggressive_if_conv; class loop *rloop; + auto_vec <gassign *, 4> reads_to_lower; + auto_vec <gassign *, 4> writes_to_lower; bitmap exit_bbs; edge pe; again: rloop = NULL; ifc_bbs = NULL; + need_to_lower_bitfields = false; + need_to_ifcvt = false; need_to_predicate = false; need_to_rewrite_undefined = false; any_complicated_phi = false; @@ -3291,16 +3496,42 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) aggressive_if_conv = true; } - if (!ifcvt_split_critical_edges (loop, aggressive_if_conv)) + if (!single_exit (loop)) goto cleanup; - if (!if_convertible_loop_p (loop) - || !dbg_cnt (if_conversion_tree)) + /* If there are more than two BBs in the loop then there is at least one if + to convert. */ + if (loop->num_nodes > 2 + && !ifcvt_split_critical_edges (loop, aggressive_if_conv)) goto cleanup; - if ((need_to_predicate || any_complicated_phi) - && ((!flag_tree_loop_vectorize && !loop->force_vectorize) - || loop->dont_vectorize)) + ifc_bbs = get_loop_body_in_if_conv_order (loop); + if (!ifc_bbs) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "Irreducible loop\n"); + goto cleanup; + } + + if (loop->num_nodes > 2) + { + need_to_ifcvt = true; + + if (!if_convertible_loop_p (loop) || !dbg_cnt (if_conversion_tree)) + goto cleanup; + + if ((need_to_predicate || any_complicated_phi) + && ((!flag_tree_loop_vectorize && !loop->force_vectorize) + || loop->dont_vectorize)) + goto cleanup; + } + + if ((flag_tree_loop_vectorize || loop->force_vectorize) + && !loop->dont_vectorize) + need_to_lower_bitfields = bitfields_to_lower_p (loop, reads_to_lower, + writes_to_lower); + + if (!need_to_ifcvt && !need_to_lower_bitfields) goto cleanup; /* The edge to insert invariant stmts on. */ @@ -3311,7 +3542,8 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) Either version this loop, or if the pattern is right for outer-loop vectorization, version the outer loop. In the latter case we will still if-convert the original inner loop. */ - if (need_to_predicate + if (need_to_lower_bitfields + || need_to_predicate || any_complicated_phi || flag_tree_loop_if_convert != 1) { @@ -3351,10 +3583,31 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) pe = single_pred_edge (gimple_bb (preds->last ())); } - /* Now all statements are if-convertible. Combine all the basic - blocks into one huge basic block doing the if-conversion - on-the-fly. */ - combine_blocks (loop); + if (need_to_lower_bitfields) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "-------------------------\n"); + fprintf (dump_file, "Start lowering bitfields\n"); + } + while (!reads_to_lower.is_empty ()) + lower_bitfield (reads_to_lower.pop (), false); + while (!writes_to_lower.is_empty ()) + lower_bitfield (writes_to_lower.pop (), true); + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Done lowering bitfields\n"); + fprintf (dump_file, "-------------------------\n"); + } + } + if (need_to_ifcvt) + { + /* Now all statements are if-convertible. Combine all the basic + blocks into one huge basic block doing the if-conversion + on-the-fly. */ + combine_blocks (loop); + } </cut>

2 years, 10 months

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[ACTIVITY] Report for weeks #37, #39 and #40

by Thiago Jung Bauermann

Hello, I haven't sent a report since week #36. For that reason, this report covers three weeks. # [GNU-796] Stabilise GDB testsuite results in the CI - Implemented CI job to run fast GDB tests based on the list from Sourceware's builder. Submitted Gerrit change requests for jenkins-scripts and ci/job/configs. - Posted Gerrit change request for jenkins-scripts with an improvement to tcwg_gnu-build.sh to use a default path for the artifacts file if one isn't given on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Started incorporating suggestions from Luis' review of the patches. # Community participation - Reviewed mailing list patch “[PATCH v3] gdb/arm: Handle lazy FPU register stacking” - Attended GNU Tools Cauldron 2022. -- Thiago

2 years, 10 months

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[ACTIVITY] week ending Oct. 9 2022

by Alex Bennée

Project Stratos =============== [UM-196] <https://linaro.atlassian.net/browse/UM-196> vhost-device maintainer effort ([UM-196]) - [review of vhost-sock for vhost-device] [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/54] testing, gdbstub, plugin and gitdm updates Message-Id: <20221004130138.2299307-1-alex.bennee(a)linaro.org> - took 3 attempts [PULL v3 00/52] testing, gdbstub, plugin and gitdm updates Message-Id: <20221006105556.3319342-1-alex.bennee(a)linaro.org> - leadership committee work - member engagement on CCA/RME [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH 00/20] Cross compilation changes for 7.2 Message-Id: <20220825222745.38779-13-pbonzini(a)redhat.com> [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Message-Id: <20221004141051.110653-4-richard.henderson(a)linaro.org> [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> Other ===== - reviews and appraisals Absences ======== Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org> =========================================================================================================================================================================== -- Alex Bennée

2 years, 10 months

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[ACTIVITY] report week ending Oct 7

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - miscellaneous upstream patch review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - sent out patchset implementing FEAT_GTG - sent out patch implementing FEAT_E0PD - code review of RTH's FEAT_HAFDBS patchset -- PMM

2 years, 10 months

1
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[ACTIVITY] report week ending 30 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out patch which adds a retry-on-EINTR loop to KVM_CREATE_VM ioctls - wrote up the draft of the minutes for the QEMU Summit for review - more code review and pullrequest collation (notably the Arm v8R support patchset) * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - read up on the remaining unimplemented features under this epic; closed out one we'd already implemented, and wrote up enough detail on the others to be happy with putting them all into the current sprint (they're all small features) - started looking at FEAT_GTG thanks -- PMM

2 years, 10 months

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[ACTIVITY] week ending Sep. 25 2022

by Alex Bennée

Project Stratos =============== - held poll for next meeting - started planning for virtio-camera/sensor QEMU Upstream Work ([UM-2]) =========================== - posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id: <CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com> - sadly one patch had to be reverted as it exposed another race - posted [PATCH v1 00/10] plugins/next (disas, monitor, docs, execlog) Message-Id: <20220921160801.1490125-6-alex.bennee(a)linaro.org> - posted [PULL 00/30] testing updates (docker, avocado, deprecate 32bit BE MIPS) Message-Id: <20220920171533.1098094-4-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Update docs - mention -d plugin - document features of tests/plugin plugins - clean up command lines to drop builddir KVM Forum ========= - Attended KVM forum, gave a talk, helper with another Completed Reviews [3/3] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> [RFC PATCH v2] gdbstub: only send stop-reply packets when allowed to Message-Id: <ba99db564c3aeb1812bdfbc9116849092334482f.1661362557.git.quic_mathbern(a)quicinc.com> [RFC 0/4] Support interactions between TCG plugins Message-Id: <20220901182734.2987337-1-fasano(a)mit.edu> Absences ======== Current Review Queue ==================== TODO [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [PATCH 00/51] tests/qtest: Enable running qtest on Windows Message-Id: <20220824094029.1634519-1-bmeng.cn(a)gmail.com> ======================================================================================================================== TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org> ======================================================================================================================================= -- Alex Bennée

2 years, 11 months

1
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[ACTIVITY] report week ending 23 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - attended KVM Forum - catching up with code review, email, etc... - sent out an Arm pullreq now 7.2 has opened up for development * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - diagnosed a regression caused by the recent FEAT_PMUv3p5 changes and sent out a fix KVM Forum trip highlights: * it was good to be able to meet people face-to-face again after several years * Cloud use of Arm hardware has now got to the point where big cloud companies are working through performance issues and then coming to present about it; e.g. Google did a talk about perf issues during migration on an Ampere Altra setup. The solutions seem to be a mix of "apply the lessons and fixes we already went through with x86" and "architecture fixes coming down the pipe" (in this case FEAT_TLBIRANGE and FEAT_BBM). * lots of Google talks about pKVM (using hypervisor hardware on Android to improve security). In fact lots of Google all over -- apparently they've made a big push to do more upstream kernel work and as a result a large chunk of the kernel KVM commits come from them... * talk from Xilinx (now with AMD) about doing co-simulation of QEMU and RTL -- basically (with the aid of a lot of non-upstream stuff) having QEMU talk to a SystemC environment so you can have eg an emulated ethernet card in FPGA that plugs into a QEMU VM. This kind of thing is a use-case which historically upstream have not really been interested in addressing. * Which brings me to the BoF session on emulation, perhaps the most interesting bit of the conference for me. There was a lot of discussion about whether QEMU might move closer to what I call the "bag of lego bricks" paradigm, where it provides device models and users might be able to configure it at runtime to stitch them together, perhaps adding out-of-tree devices of their own. There is clearly interest in this (eg from attendees from Xilinx and Qualcomm); the sticking point is that from upstream's perspective this seems like "you should do this thing that will benefit us and not you". My take is that whether this goes anywhere will depend on whether those who would like this are prepared to coordinate together to present themselves as a group who are willing to dig in to the necessary upstream refactoring and cleanup that would be a precondition for having something like this be anywhere near supportable, i.e. that they're a group who will come and help rather than merely consume... * There was also a shorter discussion in the BoF about the idea of "heterogenous CPU emulation", eg one QEMU model with both Arm and Microblaze CPUs. This is not conceptually controversial, it's just a lot of work. It seemed like maybe a few folk now care enough to have a go at it. -- PMM

2 years, 11 months

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[ACTIVITY] Report for week #36

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Made a few last-minute adjustments to the code and fixed a couple of regressions on x86_64-linux. Re-ran regression tests on x86_64-linux and aarch64-linux. Wrote cover letter and descriptions for all the patches. - Finally posted the patch series upstream¹. # [GNU-796] Stabilize GDB testsuite results in the Linaro CI - Started working on this issue. Currently adding a new CI job to run the same small subset of GDB testcases that Sourceware's buildbot runs. This subset runs quickly and has stable results so the job will be a good canary to check that the CI infrastructure is working correctly. -- Thiago ¹https://inbox.sourceware.org/gdb-patches/20220908064151.3959930-1-thiago.b…

2 years, 11 months

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[ACTIVITY] Report for week #35

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Cleaned up code for upstream submission, and divided it into patches. A couple of the patches affect other architectures and OSes, so made sure the code builds on as many combinations I can test, and now doing final regression testing on some of them. I'm hoping to finally send the patches upstream early next week. -- Thiago

2 years, 11 months

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[ACTIVITY] Report for week #34

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished fixing regressions in my changes to gdbserver for debugging an inferior which changes the SVE length. - Started cleaning up code for upstream submission and dividing it into patches. # Community participation - Reviewed mailing list patches: - [PATCH,v3] [aarch64] Fix removal of non-address bits for PAuth - [PATCH 1/2] gdb: Fix deleted thread when issuing next command - [PATCH 2/2] gdb: Improve the resuming of the stepped thread -- Thiago

2 years, 12 months

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[ACTIVITY] report week ending 25 Aug

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] - pretty much just tying up loose ends and doing other miscellaneous bits and pieces * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - respin, resend of PMUv3p5 series -- PMM

2 years, 12 months

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[ACTIVITY] Report for week #33

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - v2 of the patches fixing a small SVE bug when debugging in native mode an inferior which changes the SVE length was committed upstream. - Continued working on fixing regressions in my changes to gdbserver for debugging an inferior which changes the SVE length. -- Thiago

3 years

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