- linaro-toolchain - lists.linaro.org

by Andrew Stubbs

Hi All, Thanks for attending the call. I think we had some interesting discussions. I've posted the minutes from the call on the same page as before: https://wiki.linaro.org/AndrewStubbs/Sandbox/GCCoptimizations I'll try to get the audio posted somewhere for anybody that's interested. Andrew

14 years, 11 months

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GCC 4.6 BZR branch

by Andrew Stubbs

You may have noticed that I have created a new BZR/Launchpad branch for Linaro GCC 4.6: lp:gcc-linaro/4.6 https://code.launchpad.net/~linaro-toolchain-dev/gcc-linaro/4.6 Up until now, this has not been buildable due to unfixed bugs. However, upstream GCC have now straightened out the problems, so I have pushed a buildable version into the branch. I shall attempt to keep this branch as up-to-date as I can (at least, I will once the holiday season and January travel are over), but I'll only push updates if they build for me, so hopefully the branch should remain fairly stable, at least for our purposes. Note that so far I've only tested build-ability. Right now I'm not making any promises about the quality of the compiler. At some point, we'll want to use this branch to hold our own patches (both those that will never go upstream, and those that are queued for GCC 4.7), so it will diverge from upstream 4.6 a bit. For the moment, it's merely a mirror. Andrew

14 years, 11 months

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[ACTIVITY] Dec. 27 -- Jan. 2

by Zach Welch

== Last Week == * Got a new ARM-specific unwind test case working, so its integration with libunwind stands a marginally better chance of working (once it's finally finished). * Sent a ping to binutils mailing list about a patch to improve readelf that I had sent in at the beginning of December. Still no response. * Holidays and Vacation == This Week == * Try to finish libunwind integration, as my time with Linaro is nearly over. Update documentation on wiki to reflect current status. * Ping ltrace list about a new release. It seemed so close, then the list went abruptly silent. -- Zach Welch CodeSourcery zwelch(a)codesourcery.com (650) 331-3385 x743

14 years, 11 months

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[ACTIVITY] December 13th-January 4th

by Julian Brown

== Linaro GCC == * Continued looking at element/structure load/store intrinsics improvements. Some good initial results: it looks like the plan of using "extra-wide" vectors for returning struct results works fine (at least to a first approximation). Sent off WIP patch (internally to CS only, so far). Incidentally this looks like it'll be a good stepping-stone for the "RTL half" (vs. the "tree half") of the representation of element/structure loads/stores (e.g. vld2/vst2) also. The return type (for loads) and argument type (for stores) of the RTL patterns for such instructions is changed from the current wide-integer representation (OImode, etc.) to a suitable wide vector instead (e.g. V16QImode). This change might help lead to a more meaningful mapping from an equivalent tree form -- though we haven't quite got the whole picture yet, as the middle-end won't want to know about the ARM-specific and non-standard-named patterns for the element/structure loads/stores. (One might imagine a new standard-named RTL expander taking care of that though.) == Vacation == * Vacation Dec 20th-Jan 4th.

14 years, 11 months

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[ACTIVITY] Dec.27 -- Jan.02

by Chung-Lin Tang

== GCC issues == * PR44557, Thumb-1 ICE, looked at the ARM specific secondary reload parts, as well as some general reload internals context. Concluded that concerns on Thumb-2 about my submitted patch should be unneeded, as the reload_in/out patterns should never be used for Thumb-2. Also looked a bit on how we should upgrade ARM to use TARGET_SECONDARY_RELOAD. * PR45416, ARM code regression. Started working on this again, cleaning up patch to submit. * Had some email discussion with Revital Eres on Swing Modulo Scheduling (SMS) for ARM issues, mainly on how the doloop_end pattern should be done on ARM. * Submitted and committed an obvious small patch for a VFP testsuite case. == This week == * Continue on GCC issues. * Flying to Dallas on Sunday, prepare for trip.

14 years, 11 months

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[ACTIVITY] December 26-30

by Ira Rosen

Hi, * continued with my attempts to vectorize Viterbi: - finished implementation of conditional store sinking in cselim pass (I did only limited testing). - reconsidered the idea of safe load if-conversion if an adjacent field of the same structure is accessed unconditionally - this may be incorrect. Instead I tried the last, not yet committed, patch by Sebastian Pop that implements if-conversion for such cases of not-safe data accesses. His patch if-converts the loop in Viterbi, however, it also makes the loop not vectorizable - additional work should be done in the data-refs analysis and the vectorizer to make it work. Sebastian is working on the first part, and I'll help him with the vectorizer part if necessary. * analyzed EEMBC DenBench, couldn't find any action items for now. But vld/vst support of strided data accesses should be very useful for these benchmarks. * fixed GCC PR testsuite/47057 * looking into SLP of reduction as in PR 41881. I saw similar patterns several times in DenBench, but I'm not sure that SLP of reduction is enough to vectorize all of these cases. Happy New Year, Ira

14 years, 11 months

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[ACTIVITY] Dec. 20 -- Dec. 26

by Zach Welch

== Last Week == * Continue with libunwind. Wrote a new unit test for ARM-specific unwinding code to help debug that new code's problems. Almost got it working, which I hope means its integration with libunwind may be nearing completion. == This Week == * Try to finish ARM-specific improvements to libunwind. Famous Last Words. -- Zach Welch CodeSourcery zwelch(a)codesourcery.com (650) 331-3385 x743

14 years, 11 months

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[ACTIVITY] Dec.20 -- Dec.26

by Chung-Lin Tang

== GCC related == * Launchpad #693686, GCC ARM segfault ICE when building Chromium in V8. Spent some time reproducing; this ICE seems to be in the maverick gcc-4.5, at the vectorizer phase. As the ICE happens in tree-vect-stmts.c:supportable_widening_operation(), I'm suspecting (without further verification yet) this might be due to vmovn not backported? (Linaro 4.5 does has this ported I think) * PR44557, Thumb-1 ICE. Looking further after seeing Richard Earnshaw's comment on my patch. It would be nice if we could upgrade the entire secondary reload bits, looking into this. == This week == * Look into more GCC issues. * Get some backports done.

14 years, 11 months

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[ACTIVITY] Status Dec. 20th -- Dec. 26th

by Yao Qi

== Linaro GDB == * LP:615972 Get patch approved upstreams. Committed to FSF tree. Propose merge request to Linaro GDB tree. * LP:616003 gdb.mi/mi-var-display.exp failure Discussed in upstreams on how to handle fp in ARM/Thumb mode. Finally work out a one-line patch. Approved and committed to FSF tree. Propose merge request to Linaro GDB tree. Draft another patch to clean up ARM register alias. Pending on upstreams. * LP:616000 Handle -fstack-protector prologue code Revise patch per Joel's comments. Approved, and committed to FSF tree. Draft two patches to handle -fstack-protector prologue code on i386. Sent them out for review. Due to lack of knowledge on i386 prologue generate, not very confident on one of these patches. * LP:615980 Support displaced stepping on Thumb Get my test case to arm displaced stepping approved, and committed to FSF tree. A patch about supporting displace ARM insn in Thumb area is pending upstreams. Tried the 2nd approach since the 1st approach is not acceptable to upstreams reviewers. Without this patch, ARM displaced stepping doesn't work on Linaro. Support another three PC-related 16-bit Thumb insns (adr, ldr, and cbz), and add test cases for them accordingly. Spend some time splitting my big patch into three relatively small patches in order to make them easier to be reviewed. Patches on supporting Thumb 16-bit displaced stepping are sent out upstreams for review. == This Week == * Work from Mon. to Wed. ** Backport some approved upstreams patches to Linaro GDB ** Anything I should do for my pending patches. * Vacation on Thu. and Fri. 3rd Jan. is China public holiday. Back to work on 4th. Jan. -- Yao (齐尧)

14 years, 11 months

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Re: Linaro gcc ICE bug

by Ulrich Weigand

Khem Raj <raj.khem(a)gmail.com> wrote: > The bug http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46883 files > against GCC trunk also happens with linaro gcc 4.5 > My guess is that there is a backported patch from trunk into linaro > 4.5 tree thats causing this ICE > > This ICE does not happen on upstream gcc-4.5 branch Thanks for the bug report! > I havent figured out the commit yet. It looks like the regression was introduced by Bernd Schmidt's patch to improve zero-/sign-extensions (PR 42172), which we did indeed backport to Linaro GCC 4.5. (I've updated the PR 46883 bugzilla with more details.) > Should you need a bug in linaro > bug tracker I will be happy to file one Yes, please do so; this makes it easier to track the problem on the Linaro side. Thanks! Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 11 months

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[ACTIVITY] Dec 20 - Dec 23

by Ulrich Weigand

== GCC == * Checked in mainline fix for #617384 and submitted backport merge requests (.debug_line is wrong with -fpic) * Submitted backport merge requests for the fix for #662324 (Pointer type information lost in 4.5 debuginfo) * Checked in mainline fix for #693425 and submitted backport merge request (SPU back-end incompatible with extension elimination pass) Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 11 months

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[ACTIVITY] December 20-23

by Ira Rosen

Hi, I was on vacation on Sunday and starting from Tuesday stayed home with a sick child, so I only had a couple of days to work. * vectorization of Viterbi: - continued implementing conditional store sinking in cselim pass - made if-conversion to work on loads of structure fields if other field from the same structure is accessed unconditionally * fixed GCC PR 47001. Ira

14 years, 11 months

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[ACTIVITY] 2010-12-23

by David Gilbert

Continued looking at SPEC 2006. The two ICEs I mentioned last week are gone on the Natty version of the compiler, however the 4 programs that run and give the wrong results still happen with the Natty version and the latest version from bzr. The 4 failures are: h264ref - still fails on bzr 99447 with -O2 or -O0 sphinx3 - still fails on bzr 99447 with -O2 or -O0 gromacs - still fails on bzr 99447 with -O2 but works with -O1; I've followed this through and detailed it in bug 693502; it looks to me like a post-increment gone wrong (it's split so it's not actually a post increment and the original rather than post inc'd value gets used) zeusmp - this fails to load the binary; it's got a >1GB bss section. Interestingly it gets further on my beagle with less memory but a bit of swap, even though I think it's not really using all of the BSS in the config I'm using. I'm hoping to leave a 'ref' run going over the new year. The canis1 Orion board I was also running Spec on last weekend died during the run and hasn't come back. perf We now have silverberry using the -proposed kernel which has the fixed PERF_EVENT config, and perf seems to work fine. libffi I've started building the page https://wiki.linaro.org/WorkingGroups/ToolChain/FFIusers listing things that use FFI; (generated by a bit of apt wrangling). There are basically 3 sets: a) Apps that just use ffi for something specific b) Languages that then let the users of those languages have varying degrees of freedom in themselves c) Haskell - While some of the packages are actually probably ffi users, I think a lot of these are false dependencies; almost every haskell user seems to gain a dependency on libffi directly. I'm back on the 4th January. Dave

14 years, 11 months

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[ACTIVITY] December 12 - 16

by Ira Rosen

Hi, I continued looking into EEMBC benchmarks: - telecom fft is not vectorized because unknown number of iterations. It has both non-constant step and its loop bound may overflow. I think, the solution here could be loop versioning, but since versioning increases code size, this kind of optimization can be less beneficial. - telecom viterbi (vectorization potential gain is 4x) requires conditional store sinking and load hoisting to enable if-conversion. I worked on implementation of store sinking this week. Ira

14 years, 11 months

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Re: Extension elimination pass breaks SPU (Fw: spu gcc-4.5 linaro build failure)

by Ulrich Weigand

Ulrich Weigand/Germany/IBM wrote on 12/20/2010 06:01:21 PM: > Mark Mitchell <mark(a)codesourcery.com> wrote: > > On 12/20/2010 8:35 AM, Ulrich Weigand wrote: > > > Now, I guess there's two ways forward: either the outcome of the ongoing > > > discussions on gcc-patches is that it is in fact not a good idea to > > > generate such sets, and the EE pass is subsequently rewritten to avoid > > > them; or else, if those instructions are considered valid, I'll have to > > > extend the SPU move expander to handle them. Thoughts? > > > > I haven't participated in the upstream discussion -- I'm way behind on > > that list :-( :-( -- but I think such sets should be considered valid. > > OK, I'll have a look at fixing the SPU back-end then. I've now fixed this problem in the back-end upstream: http://gcc.gnu.org/ml/gcc-patches/2010-12/msg01694.html I've also created a back-port to Linaro GCC 4.5 and proposed the branch for merge; you can find the details at: https://bugs.launchpad.net/gcc-linaro/4.5/+bug/693425 Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 11 months

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[ACTIVITY] Dec. 13 -- Dec. 19

by Zach Welch

== Last Week == * Continued working on ARM unwinding in libunwind. Produced a draft write-up of my progress in the event that I don't finish this work before being swapped out of Linaro. * (Re-)submitted patches to fix ltrace test suite. Hopefully, these will be the last changes before the new release. == This Week == * Continue working on libunwind. -- Zach Welch CodeSourcery zwelch(a)codesourcery.com (650) 331-3385 x743

14 years, 12 months

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GCC for Android

by Patrik Ryd

Hi, We would like to build Android with the Linaro tool chain. Do any of you know what kind of work will be needed to adapt Linaro gcc to Android? Regards, Patrik

14 years, 12 months

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[ACTIVITY] Dec.13 -- Dec.19

by Chung-Lin Tang

== GCC related == * CS Issue #10201 / PR46883, unrecognizable insn ICE when compiling Samba. Fixed this by changing the predicates of two split patterns. Patch reviewed in CS internally and upstream, committed upstream, will backport to SG++ and Linaro soon. * LP:641397/PR46888: bitfield insert optimization. Andrew Pinski found a testcase that escapes the CSE patch gets handled by combine, and also found another bug with REG_EQUIV notes. Only looked at this minimally last week, will really work on this later. * LP:687406/PR46865, -save-temps creating different code. Backported and bzr-pushed the upstream fix by Jakub Jelinek. * PR45416, ARM code regression. Mostly can generate what I wanted by now, under ARM and x86, although patch is still not in a submittable state. * VFP index patch. Uncommitted GCC patch of mine from last year; added Thumb-2 bits and corrected some things in the testcase. Committed upstream. == This week == * Really get January travel stuff nailed. * Upstream patch review is probably going to start getting slow/suspended this week. Will probably do some study stuff on larger projects. * Continue to look at GCC issues.

14 years, 12 months

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[ACTIVITY] Dec. 13th -- Dec. 18th

by Yao Qi

== Linaro GDB == * LP:615972 Different output of 'info register' w/ and wo/ corefile. Understands gcore impl in gdb. Two patches are reviewed in upstreams. One is approved by Dan, and the other is still be reviewed. Evaluate the two approaches for NEON registers in corefile. Resume the discussion on kernel support for dumping NEON registers. Need a decision with kernel side, but no progress on it. * LP:685494 Revise patch per Pedro's suggestion. Waiting for someone to approve it. * LP:685702 Get it approved for FSF GDB 7.2 branch. Committed to both FSF 7.2 branch and Linaro tree. * LP:616003 gdb.mi/mi-var-display.exp failure GDB always assumes $fp is r11, even code is in thumb mode. Current GDB infrastructure can't handle mapping the same alias to two different registers. Proposed a new gdbarch took for this in upstreams, in order to increase the flexibility of GDB. No reply yet. * LP:616001 gdb.mi/mi-var-cmd.exp failure Ulrich pointed out it is caused by stack randomization. Confirmed this by setting "kernel.randomize_va_space" to zero. Figure out why this case passes on x86, because it is more restricted to turn on stack randomization on x86. * LP:615980 Support displaced stepping on Thumb Understands displaced stepping in GDB/ARM. Find a bug when GDB tries to execute ARM instruction in copy area, which is in Thumb mode (copy area starts from "_start + 4", and it is compiled in Thumb mode in Ubuntu). The fix is an one-line patch, which doesn't update status register when writing PC in displaced stepping. Write a test case for arm displaced stepping. Write code in ARM asm directly for the first time, which is very helpful to remember ARM asm instructions. Read ARM ARM and decode 16-bit thumb instructions in GDB for displaced stepping. It doesn't work so far because breakpoint instruction after instructions in copy area is still hard-coded to ARM breakpoint insn. == Misc == * Linaro GCC optimization meeting. == This Week == * LP:615980 Support displaced stepping on Thumb Send my fix and test case to upstreams for review. Make displaced stepping work on 16-bit instruction. * Ping other GDB patches. -- Yao (齐尧)

14 years, 12 months

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Re: Profile guided and string routines?

by Steven Bosscher

Mark Mitchell wrote: > > If Profile Guiding could spot that a particular callsite to say strlen() > > was often associated with strings > > of at least 'n' characters we could call a different implementation. > > I don't believe this is possible current profile-guided optimization, > but certainly it could be done. It looks to me like a case of value profiling, see tree-profile.c, for the various "stringops" optimizations. Unless I misunderstand David's idea here or missing something else, it seems that this kind of optimization should fit in the existing infrastructure without too much effort. Ciao! Steven

14 years, 12 months

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Profile guided and string routines?

by David Gilbert

Does anyone have any experience of what can be profiled in the profiled guided optimisations? One of the problems with some of the string routines is that you can write pretty neat fast routines that work well for long strings - but most of the calls actually pass short strings and the overhead of the fast routine means that for most cases you are slower than you would have been with a simple routine. If Profile Guiding could spot that a particular callsite to say strlen() was often associated with strings of at least 'n' characters we could call a different implementation. Dave

14 years, 12 months

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[ACTIVITY] 13th -18th December 2010

by Andrew Stubbs

* Linaro GCC lp:686381: C++ link failure on ARM Reproduced the bug and posted my findings to the bug report - user error. Changed the way the Linaro GCC version numbers are handled. Hopefully the new system should be less distasteful to Matthias. Updated the GCC release procedure document to match. Organised and chaired a meeting to discuss GCC optimization opportunities for ARM. It was well attended, and I think we had some useful discussion. Spend quite some time preparing beforehand, and writing it up afterwards. Next step is to come up with some actual plans to implement something. I imagine we can discuss this at the sprint in Dallas next month. See https://wiki.linaro.org/AndrewStubbs/Sandbox/GCCoptimizations * Upstream GCC My upstream patch to fix ARM smlabb has been approved and committed to GCC 4.6 (mainline). Only another three patches need approval now! Continued testing upstream GCC 4.6 with both cross and native builds. It appears to be in a buildable state now, with no extra patches required. I've updated the Linaro GCC 4.6 branch with the buildable state. * Other Updated my ESTA, and added my security details to the airline bookings. ------ Future availability 20th Dec .. 3rd Jan - Vacation/Holiday 4th Jan .. 8th Jan - Business as usual 9th Jan .. 14th Jan - Linaro Sprint, Dallas 15th Jan .. 21st Jan - CodeSourcery/Mentor Annual Meeting, Scottsdale 24th Jan onwards - normal service restored!

14 years, 12 months

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[ACTIVITY] 2010-12-17

by David Gilbert

Got SPEC2006 building on Silverbell (VExpress) and Canis1 (Orion). There are still some issues; The builds are still going (6 hours so far on a 1GHz A9 for a build and 'test' case), and the Silverbell one has hit an ICE on one of the tests that looks like 635409, and also looks like it needs some help getting Perl to work. The build on Canis has only just started, but hasn't got Fortran installed. (The SPEC2006 tools build also failed in the Perl testsuite on sprintf.t and sprintf2.t which seem to test integer overflow cases in sprintf % fields) Added a few of the kernel string/memory routines and bionic routines into my string/memory graphs and also ran the tests on the Orion board (similar to other A9 performance - no surprise). Wrote up a draft of an email to libffi-dev describing the varargs state; and as I was doing it realised that one of the ways didn't quite work and was more messy. Using rdepends to find all packages using ffi, need to figure out if any actually care about varargs. Dave

14 years, 12 months

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[ACTIVITY] Dec 13 - Dec 17

by Ulrich Weigand

== GCC == * Completed first successful bootstrap and regression test run of GCC mainline on my IGEPv2 board. * Worked on implementing fix for #617384 (.debug_line is wrong with -fpic) * Worked on backporting fix for #662324 (Pointer type information lost in 4.5 debuginfo) * Analyzed root cause of PR target/46883 (GCC ICE with error: unrecognizable insn) Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 12 months

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No meetings over the Christmas break

by Michael Hope

Hi there. I've cancelled the weekly and standup calls for the next two weeks. The next scheduled call is the standup call on Wednesday the 5th of January. Please attend if you can as it's our last one before the sprint. See you then! -- Michael

14 years, 12 months

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Topics for the sprint

by Michael Hope

Hi there. The sprint is just around the corner and it's a good time to think about how we can make best use of the week. I've put some topics up at: https://wiki.linaro.org/Events/2011-01-LinaroSprint/ToolChainWG Please feel free to add to it. Have a think about anything that's easier to do while everyone is in the same room - things like discussions, kicking off some work, a bit of pair programming on a problem, or anything that overlaps with another group or Ubuntu. -- Michael

14 years, 12 months

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[ACTIVITY] report week 50

by Peter Maydell

RAG: Red: Amber: Green: Milestones: | Planned | Estimate | Actual | finish virtio-system | 2010-08-27 | postponed | | get valgrind into linaro PPA | 2010-09-15 | 2010-09-28 | 2010-09-28 | complete a qemu-maemo update | 2010-09-24 | 2010-09-22 | 2010-09-22 | finish testing PCI patches | 2010-10-01 | 2010-10-22 | 2010-10-18 | Progress: * merge-correctness-fixes: ** Submitted patchset upstream to fix NaN propagation to follow ARM ARM rules rather than x87 semantics: http://patchwork.ozlabs.org/patch/75742/ http://patchwork.ozlabs.org/patch/75743/ * maintain-beagle-models: ** Finished implementation of the OMAP NAND prefetch/postwrite engine including its DMA support. Patches submitted to the qemu-maemo upstream tree and merged by Juha: http://meego.gitorious.org/qemu-maemo/qemu/merge_requests/1 ** Fixed the (cosmetic) bug https://bugs.launchpad.net/qemu-maemo/+bug/622408 where we were complaining about "Unknown CMD52" when Linux probed for the presence of SDIO cards. Fix merged into qemu-maemo: http://meego.gitorious.org/qemu-maemo/qemu/merge_requests/2 * qemu-continuous-integration: ** Discussion with Loic about setting up jobs on his Hudson instance for testing qemu against snapshots/hwpacks. * packageselection-arm-n-more-stable-vm-solution-for-arm ** Discussion about Ubuntu moving to using a qemu-maemo based qemu for ARM purposes. The Ubuntu blueprint is https://blueprints.launchpad.net/ubuntu/+spec/packageselection-arm-n-more-s… We need to come to agreement about what parts of this are going to be done by variously Linaro toolchain, Linaro foundations and Ubuntu. ** I'm going through doing another rebase-and-package of the Linaro qemu, and finishing off writing up the notes on the process: https://wiki.linaro.org/WorkingGroups/ToolChain/QemuReleaseProcess Meetings: toolchain, pdsw-tools, pdsw-tools xmas lunch :-) Issues: * a number of qemu patches in progress are logjammed behind the outstanding git pull request * the dbgsym debug packages for linaro kernels seem to have vanished: https://bugs.launchpad.net/linaro-images/+bug/691192 Absences: (complete to end of 2010) Fri 17 Dec - Tue 4 Jan inclusive. 2011: Dallas Linaro sprint 9-15 Jan. Holiday 22 Apr - 2 May.

14 years, 12 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, * I've spent some time for testing the patches that allow the GCC trunk to bootstrap again on ARM and posted the results to gcc-testresults * finally tested and posted the patch that optimizes the __sync_* builtins (#681138) on gcc-patches * investigated on the state of the crash utility on ARM (or rather its prerequisites like kexec) https://wiki.linaro.org/KenWerner/Sandbox/crash-utility * I'm on holiday now :) Regards Ken

14 years, 12 months

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Re: RFC: -mimplicit-it and GCC upstream

by Dave Martin

Hi, On Wed, Dec 15, 2010 at 1:44 AM, Michael Hope <michael.hope(a)linaro.org> wrote: > On Wed, Dec 15, 2010 at 1:05 PM, Steve Langasek > <steve.langasek(a)linaro.org> wrote: >> Hi Michael, >> >> On Wed, Dec 15, 2010 at 09:29:38AM +1300, Michael Hope wrote: >>> Hi Steve. I'd like to hand the rest of this over to you if that's OK. >> >> Yep, we can take it from here. To be clear, is this an additional change >> above and beyond what Matthias reports is currently in Ubuntu gcc >> (http://lists.linaro.org/pipermail/linaro-toolchain/2010-November/000441.html), >> and if so, in what version of Linaro GCC is it going to become effective? >> Do we have documentation of what the relevant failure modes caused by this >> change *look* like, so that we can at least be triaging them appropriately >> until there's some documentation on how to fix the resulting bugs? > > There will be many failures in many packages. The problem is when you > use conditional suffixes on instructions: previously the compiler > would insert an implicit instruction before that; now we have to be > explicit. > > The failures are easy to diagnose and fix. The build will fail with a > message from the assembler along the lines of 'xxx instruction outside > an IT block'. The fix is to find the inline assembly code, insert the > appropriate IT instruction, and re-build. The assembler will validate > the IT instruction against the following conditional instructions so > the change is quite safe. Did someone manage to find out which versions of binutils can silently accept the IT instructions when assembling for ARM? This affects what advice we should give on how to avoid breaking upstream with our additions. The safest approach is #ifdefs, but it will be better for maintenance if we can avoid this, since it will render the code very messy. Cheers ---Dave

15 years

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Blueprint changes

by Michael Hope

Hi there. Some of the tr-* blueprints had work items in them and this was interfering with the tools that the PM guys use. I've created new engineering blueprints, pulled the work items across into them, and added the new engineering blueprint as a dependency of the old TR. Sorry for the blueprint spam. In most cases the new blueprint has the same name and subject as the TR one, such as the TR: https://blueprints.launchpad.net/linaro/+spec/tr-toolchain-4.5-in-distros which is backed by the engineering blueprint: https://blueprints.launchpad.net/gcc-linaro/+spec/4.5-in-distros -- Michael

15 years

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RFC: -mimplicit-it and GCC upstream

by Dave Martin

Hi Richard, Recapping on this earlier conversation: http://lists.linaro.org/pipermail/linaro-toolchain/2010-July/000030.html http://lists.linaro.org/pipermail/linaro-toolchain/2010-July/000035.html Is it worth another attempt to make a case to upstream for supporting passing -mimplicit-it=thumb by default to gas? According to my understanding of this issue, my argument would go as follows: * gcc currently estimates the size of asm blocks, rather than determining the size accurately. * gcc cannot guarantee the right answer for asm block size when asm blocks contain directives etc., however use of directives in asm blocks is widespread * gcc cannot guarantee the right answer for asm block size in Thumb-2. gcc conservatively overestimates the size by assuming that each statement of the asm block expands to 4 bytes. * All of Ubuntu lucid and maverick has been built with -mimplicit-it=thumb passwd by default, with no known build or runtime failures arising from this (so size issues aside, we have confidence that the resulting code generation is sound) * -mimplicit-it=thumb -mthumb makes the asm block size estimation unsafe: the asm block can exceed the estimated size even in the absence of directives, which may lead to fixup range errors during assembly. * Following the principles already established for Thumb-2 in general the estimation can be made safe (or, as safe as the established Thumb-2 behaviour) by raising the assumed maximum statement expansion size for asm blocks to 6 bytes, since -mimplicit-it will add as most a single (16-bit) IT instruction to each statement. * The vast majority of all asm blocks are small (< 20 instructions, say), so the overall overestimate in sizes will generally be modest for any given compilation unit. * -mimplicit-it is already _required_ by the Linux kernel and possible other projects. ...so... * With -mimplicit-it=thumb and a 6-byte asm block statement expansion size estimate, we have toolchain behaviour which is as reliable, and as correct, as it is in upstream at present. * Layout of data in the compiler output will be more optimal in some cases, and less optimal in other cases, compared with the the current Thumb-2 behaviour, due to differing asm block size estimates. The exact behaviour will depend on the distribution of conditional instructions within asm blocks. * Taken over a whole compilation unit, the total code size overestimate (and therefore the impact on object layout) will normally be modest, due to the small typical size of asm blocks. * Behaviour for -marm will not be impacted at all. If gcc currently estimated asm block code size accurately, then I could understand upstream's objection; but as it stands it seems to me we wouldn't be making anything worse in practice with the proposed change; and there is no compatibility impact (other than positive impact). Of course, I may have some wrong assumptions here, or there may be some background I'm not aware of... Comments? Cheers ---Dave

15 years

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[ACTIVITY] December 6th-12th

by Julian Brown

== Linaro GCC == * Finish testing for big-endian/quad-word patch on mainline, and send upstream. Not yet reviewed by an ARM maintainer, but Joseph suggested tweaking DejaGnu's target-supports to better reflect the new capabilities of the vectorizer in big-endian mode. I've not looked into that yet. * Started looking at improving element/structure load/store intrinsics. Made it so that the structs used for loads/stores are created in the backend so that the types can be used directly by the builtins, but discovered that the front-end/middle-end would not play along with that plan as they are. Thought about ways to fix that. * Some time spent on other CodeSourcery stuff.

15 years

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Linaro GCC 4.4 and 4.5 2010-12 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the release of both Linaro GCC 4.4 and Linaro GCC 4.5. Linaro GCC 4.5 is the fifth release in the 4.5 series. Based off the latest GCC 4.5.1+svn167157, it includes many ARM-focused performance improvements and bug fixes. Linaro GCC 4.4 is the fifth release in the 4.4 series. Based off the latest GCC 4.4.5, it is a maintenance release that fixes one problem found through use. Interesting changes include: * A new performance focused extension elimination pass * Speed and size improvements when loading constants * Performance improvements on compound conditionals * A range of correctness improvements The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.5-2010.12-0 and https://launchpad.net/gcc-linaro/+milestone/4.4-2010.12-0 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro No changes have been committed to Linaro GDB 7.2 this month. -- Michael

15 years

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[ACTIVITY] 6th - 10th December

by Andrew Stubbs

* Linaro GCC 4.4/4.5 Merged the latest CS patches and Linaro merge requests into Linaro GCC (4.4 and 4.5). Ran regression tests. Yao's patch failed so I backed it out, and made the release tarballs. Uploaded the releases to Michael Hope for release. lp:686381: luatex fails to build with gcc-4.5 Fired off a test build to reproduce the problem. Will come back to this next week. * GCC 4.6/4.7 Posted my various queued patches up to gcc-patches(a)gcc.gnu.org for review. Looked at the state of the GCC 4.6 upstream build. There are currently two problems: 1. libquadmath must be disabled in a cross-build for the bootstrap phases. 2. libstdc++ doesn't build. There is a patch for it on the mail list, but it's not applied yet. Once gcc 4.6 builds cleanly, I shall update the Launchpad 4.6 branch, and declare that the baseline for our development. We'll then have somewhere to commit and track patches awaiting GCC stage 1 development. * Other Caught up with email following my holiday. Yet again, my IGEPv2 board suffered a corrupt file system. I've now upgraded the kernel and configured it to use an NFS root. The board is now somewhat less mobile, but should work more reliably. Continued organizing the a brain-storming session for GCC optimization improvements. Organised flights and hotel for both the Linaro Sprint and CodeSourcery annual meeting in January.

15 years

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[ACTIVITY] Dec. 06 -- Dec. 12

by Zach Welch

== Last Week == * Spent time tracking down a couple of regressions that appeared in the new ltrace release-candidate tree. Submitted a bunch of patches to fix the issues that were discovered during that process; most have been applied. * Finished writing fairly generic code for handling ARM-specific unwind tables, from lookup through decoding and dispatch. It uses a few definitions specific to libunwind, but those probably could be eliminated with more work. == This Week == * Integrate new ARM-specific bits into libunwind framework. * Rewrite part of a portability patch for ltrace and hope that those changes reflect the very last effort that will be required for that particular task. -- Zach Welch CodeSourcery zwelch(a)codesourcery.com (650) 331-3385 x743

15 years

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Re: Neon registers in core files

by Dave Martin

On Fri, Dec 3, 2010 at 9:06 AM, Yao Qi <yao.qi(a)linaro.org> wrote: > Hi, Kernel WG, > Can recent kernel handle NEON registers in corefiles? > > Seems we've had plan for this in "Ensure full NEON debug support" in > https://wiki.linaro.org/WorkingGroups/KernelConsolidation/Specs/BSPInvestig… > Any progress on this piece of work? We want to handle NEON registers in > corefiles from GDB, which required kernel dump them in corefile first. Hmmm, actually that bullet may have ended up in the wrong place ... since it's not a BSP-specific feature. Anyway, looking at the kernel code, it looks like the VFP/NEON state is not dumped into the core file. If it makes you feel better, the state of the obsolete FPE extension registers is dumped, if used :/ My guess is that it shouldn't be hard to dump the VFP/NEON state, but GDB and the kernel need to agree on the format. Rather that trying to hack the existing register dump format in a compatible way, I suggest it's simplest if the kernel creates an extra section in the dump containing something like: .long format_version /* reserved for future expansion - must be 0 */ .long FPSID .long FPSCR .long MVFR0 /* or 0 if not present in the hardware */ .long MVFR1 /* or 0 if not present in the hardware */ .long d0 .long d1 /* ... d2-d14 ... */ .long d15 If 32 D-registers in the hardware [ .long d16 .long d17 /* ... d18-d30 ... */ .long d31 ] I believe we don't need any extra flags to indicate whether the MVFRx fields are valid, since 0 in these registers indicates the VFPv2/legacy behaviour anyway. Note that some VFPv2 implementations (such as ARM1176) do provide these registers, and where the hardware has them, the kernel can fill them in when doing the coredump. We _should_ be prepared to ignore these fields (or interpret them differently) if a vendor-specific VFP subarchitecture is specified (by (FPSID & 0x4000) == 0x4000) The number of D-registers can be deduced from the FPSID and MVFRx registers, so we don't need to record it explicitly. When MVFRx are not present, there are 16 D-registers. When MVFRx are present, and (MVFR0 & 0xF) >= 2, there are 32 (or more) D-registers This is just a sketch -- the ARM ARM is the authoritative reference on the meanings of these bitfields. Any views on this? Cheers ---Dave > > _______________________________________________ > linaro-dev mailing list > linaro-dev(a)lists.linaro.org > http://lists.linaro.org/mailman/listinfo/linaro-dev >

15 years

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[ACTIVITY] Dec 6 - Dec 10

by Ulrich Weigand

== GCC == * Tracked down root cause of GCC mainline bootstrap failure on ARM (PR 46040 - "__DTOR_LIST__ undeclared"). == Miscellaneous == * Set up IGEP v2 board (w/ local disk, network, ...) as native GCC / GDB build environment. * Gave talk on Linaro at the "2010 Linux Community Event" at Siemens Munich (w/ Arnd Bergmann). Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

15 years

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Invitation: TWG GCC Optimization @ Wed 2010-12-15 9am - 10am (linaro-toolchain@lists.linaro.org)

by Andrew Stubbs

You have been invited to the following event. Title: TWG GCC Optimization Discuss ideas for improving GCC optimization for ARM. Open to anybody who wants to contribute. https://wiki.linaro.org/AndrewStubbs/Sandbox/GCCoptimizations International: +44 1452 567 588 UK: 0844 493 3801 Brazil: 08008912092 China: 108007121533 India: 0008001006354 Taiwan: 00801126472 United States: 18666161738 Conference code 2634417169# When: Wed 2010-12-15 9am – 10am London Where: Conference call code 263 441 7169 Calendar: linaro-toolchain(a)lists.linaro.org Who: * andrew.stubbs(a)linaro.org - creator * Ken Werner - optional * stevenb.gcc(a)gmail.com - optional * Michael Hope - optional * David Gilbert - optional * Peter Maydell - optional * ulrich.weigand(a)de.ibm.com - optional * Yao Qi - optional * Julian Brown - optional * paul(a)codesourcery.com - optional * Ira Rosen - optional * richard.earnshaw(a)arm.com - optional * Chung-Lin Tang - optional * mark(a)codesourcery.com - optional * linaro-toolchain(a)lists.linaro.org - optional * Richard Sandiford - optional * Marcin Juszkiewicz - optional * zwelch(a)codesourcery.com - optional Your attendance is optional. Event details: https://www.google.com/calendar/event?action=VIEW&eid=aXJlc2Z2bWZmZzQ5cGQ4b… Invitation from Google Calendar: https://www.google.com/calendar/ You are receiving this courtesy email at the account linaro-toolchain(a)lists.linaro.org because you are an attendee of this event. To stop receiving future notifications for this event, decline this event. Alternatively you can sign up for a Google account at https://www.google.com/calendar/ and control your notification settings for your entire calendar.

15 years

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[ACTIVITY] Dec.6th -- Dec.12th

by Chung-Lin Tang

== GCC related == * PR44557, Thumb-1 ICE: found two small needed corrections in the ARM backend to fix this. Sent patch upstream. * LP:641397/PR46888: bitfield insert optimization. Posted patch along with Andrew Stubbs' CSE patch upstream. The two-patch situation seemed to stir some discussion :) It seems both patches were deemed okay, though it would be better if there was some testcase that passed through unhandled by Andrew's CSE patch, but processed by my combine fix later in the pass pipeline. Both patches queued at GCC bugzilla page, to be handled in the next stage1. * LP:687406/PR46865, -save-temps creating different code. Analyzed problem, though slow to send fix upstream. Had some discussion on the list on how the fix should be like. * PR46667, section type conflicts. Tested and sent mail to gcc-patches. Jan Hubicka picked it up and pinged for an approval again. Hope this get resolved soon. * PR45416, ARM code regression. ARM considerations are mostly okay, main issue remaining is how to solve the x86 regression. The current expand code does a full DImode shift just to obtain a single bit, might be point of improvement to solve this. * LP:685534, ftbfs with gcc-linaro 4.5 on amd64. Found to be another erroneous inline asm case. Fixed and updated on LP. == This week == * More upstream and Linaro GCC issues. * Start dealing with January travel. * Think more about larger (Linaro) GCC optimization projects.

15 years

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[ACTIVITY] Dec 6th -- Dec 12th

by Yao Qi

== Linaro GDB == * LP:616000 Handle -fstack-protector prologue code Understand how frame affect expression validation in GDB. Improve i386 prologue parsing to handle 'and/add' sequence. Revise i386 prologue parsing for stack protector. Patch is not submitted since still lack of i386 prologue knowledge, and not very confident on that patch. Understand prologue-value used in ARM prologue parsing and relationship of symbol and frame in GDB. Make ARM prologue parsing understands stack protector code by identify the code sequence. Improve the patch by supporting ARM mode and ARMv5T, in order to make this patch accepted by upstreams. * LP:615972 gdb.base/gcore.exp failure. The failure is about "corefile restored general registers", which is not related to NEON register support in corefile. It is caused by inconsistent register types and names between tdesc and arm. The cause of this failure is found, but upstreams reviewer doesn't agree on one of my fix. As he suggested, arm-core.xml is modified to add "type=XXX", but get some errors when regenerate arm-with-iwmmxt.c. Filed GDB PR 12308. == GCC == * register rename improvements (LP:633243) Finally, got both middle-end part and ARM part approved. Committed to upstreams mainline. Some benchmarks in EEMBC shows 0.1%~0.2% code size reduction. == This Week == * Ping my GDB patches. * Fix GDB PR 12308, which blocks my fix for LP:615972. * Backport my approved patches to Linaro GDB if any. Fix other GDB bugs. * Pass one GCC patch in my queue to review, if I have extra time. == Vacation == Take vacation on Dec 30th and 31st. Travel to ChengDu, and back on 3rd Jan (It is public holiday in China). Back to work on 4th Jan. -- Yao (齐尧)

15 years

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[ACTIVITY] Weekly status

by Richard Sandiford

== This week == * Away Monday and Tuesday. * Very little the rest of the week due to other IBM commitments. I've just finished the main part of that work, so all being well, it should only need a bit of nannying next week. Most of the week should be Linaro. * Started trying to reproduce #641126, but realised that I'd need to set myself up for general Ubuntu cross package building first. Started to look at what's involved. == Next week == * Get stuck into #641126. * More STT_GNU_IFUNC and vectors. Richard

15 years

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[ACTIVITY] report week 49

by Peter Maydell

RAG: Red: Amber: Green: Milestones: | Planned | Estimate | Actual | finish virtio-system | 2010-08-27 | postponed | | get valgrind into linaro PPA | 2010-09-15 | 2010-09-28 | 2010-09-28 | complete a qemu-maemo update | 2010-09-24 | 2010-09-22 | 2010-09-22 | finish testing PCI patches | 2010-10-01 | 2010-10-22 | 2010-10-18 | Progress: * merge-correctness-fixes: ** I have sent out an updated ARM fixes pull request, all of whose components have been Reviewed-by: Nathan Froyd; I expect this to be merged shortly. ** vqshl(reg) patch posted to list; I have an update which also addresses vqshl{,u}(imm) which I'll send out as v2 once the first part has been reviewed. ** reviewed and retransmitted Wolfgang's semihosting commandline patches since he is having trouble sending unmangled mail to the list ** went through the monster qemu-maemo commit "Lots of ARM TCG changes" http://meego.gitorious.org/qemu-maemo/qemu/commit/3f17d4e1cb identifying what fixes it includes ** started looking at a VRSQRTS patch. This uncovered a number of qemu issues: NaN propagation is wrong, flush-to-zero handling is only flushing output denormals, not input denormals, and we don't handle the Neon "standard FPSCR value" but always use the real FPSCR. I have some preliminary patches for at least some of this, but since they affect a number of the same bits of code that are touched by existing not-yet-committed patches I'm waiting for those to be committed first. * verify-emulation: ** wrote a README for risu and made it public at http://git.linaro.org/gitweb?p=people/pmaydell/risu.git;a=summary * maintain-beagle-models: ** the ubuntu maverick netbook image doesn't boot on qemu because it uses the OMAP NAND prefetch/DMA, which isn't modelled https://bugs.launchpad.net/qemu-maemo/+bug/645311 I've started on this and am perhaps halfway through (basic prefetch code implemented, but DMA and debugging still to go) * other: ** took part in an OBS mini-sprint where we were walked through how the OBS buildsystem works and can be used to do test rebuilds of Meego with new versions of the toolchain. Meetings: toolchain, pdsw-tools Plans: * finish omap NAND prefetch engine work * make sure ARM changes get committed to qemu... Absences: (complete to end of 2010) Fri 17 Dec - Tue 4 Jan inclusive. 2011: Dallas Linaro sprint 9-15 Jan. Holiday 22 Apr - 2 May.

15 years

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[ACTIVITY] weekly status

by Ken Werner

Hi, * created custom kernel deb packages from the linaro-linux tree in order to * test the various ftrace tracers and profilers available on ARM * results at: https://wiki.linaro.org/KenWerner/Sandbox/ftrace * started to look into crash (kexec, kdump) but wasn't able to generate a kernel dump yet Regards Ken

15 years

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Perfromance Test Results using gcc-linaro-4.5-2010.11-1

by Prashanth S

Dear All Our team in Samsung collected some performance metrics for the following 3 GCC cross compilers 1.. Gentoo Complier(part of Chrome OS Build Environment) 2.. GCC 4.4.1 (Code Sourcery). 3.. Linaro (gcc-linaro-4.5-2010.11-1) Flags used to Build Linaro Tool chain used Michael Hope Script .Just modified "GCCFLAGS = --with-mode=thumb --with-arch=armv7-a --with-float=softfp --with-fpu=neon --with-fpu=vfpv3-d16" a.. Using the above three tool chains we compiled the kernel of Chrome OS and did Coremark Performance test.(With same optimisation flag mentioned in the attachment) b.. Test Environment for all the three are the same. My Questions 1.. Is there any build options that I am missing while I am building the Cross Compiler? 2.. Else is this performance degradation is a know issue and is the tool chain group working on it?.(If so whom to contact?) Any Pointers from you would be of great help to me. If you need any further details also do ping me Regards Prashanth S

15 years

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GCC Optimization Brain Storming Session

by Andrew Stubbs

Hi All, As we discussed on Monday, I think it might be helpful to get a number of knowledgeable people together on a call to discuss GCC optimization opportunities. So, I'd like to get some idea of who would like to attend, and we'll try to find a slot we can all make. I'm on vacation next week, so I expect it'll be in two or three week's time. Before we get there, I'd like to have a list of ideas to discuss. Partly so that we don't forget anything, and partly so that people can have a think about them before the day. I'm really looking for bigger picture stuff, rather than individual poor code generation bugs. So here's a few to kick off: * Costs tuning. - GCC 4.6 has a new costs model, but are we making full use of it? - What about optimizing for size? - Do the optimizers take any notice? [1] * Instruction set coverage. - Are there any ARM/Thumb2 instructions that we are not taking advantage of? [2] - Do we test that we use the instructions we do have? [3] * Constant pools - it might be a very handy space optimization to have small functions share one constant pool, but the way the passes work one function at a time makes this hard. (LP:625233) * NEON - There's already a lot of work going on here, and I don't want it to hog all our time, but it might be worth touching on. What else? I'm not the most experienced person with GCC internals, and I'm relatively new to the ARM specific parts of those, so somebody else must be able to come up with something far more exciting! So, please, get brain-storming! Andrew [1] We discovered recently that combine is happy to take two insns and combine them into a pattern that matches a splitter that then explodes into three insns (partly due to being no longer able to generate pseudo-registers). [2] For example, I just wrote a patch to add addw and subw support (not yet submitted). [3] LP:643479 is an example of a case where we don't.

15 years

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[ACTIVITY] 2010-12-09

by David Gilbert

Mostly more working with libffi; swapping some ideas back and forwards with Marcus Shawcroft and it looks like we have a good way forward. Got an armhf chroot going, libffi built. Got a testcase failing as expected. Trying to look at other processors ABIs to understand why varargs works for anyone else. Cut through one layer of red tape; can now do the next level of comparison in the string routine work. Started looking at SPEC; hit problems with network stability on VExpress (turns out to be bug 673820) long long weekend; short weeks=2; Back in on Tuesday. Dave

15 years

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Silverbell

by David Gilbert

Hi, Those of you use silverbell may be glad to know it's back up. Be a little careful, if you shovel large amounts of stuff over it's network the network tends to disappear. (Not sure if this is hardware or driver) Dave

15 years

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Hard float chroot

by David Gilbert

Hi, As mentioned on the standup, I just got an armhf chroot going, thanks to markos for pointing me at using multistrap I put the following in a armhfmultistrap.conf and did multistrap -f armhfmultistrap.conf Once that's done, chroot in and then do dpkg --configure -a it's pretty sparse in there, but it's enough to get going. Dave ============================================== [General] arch=armhf directory=/discs/more/armhf cleanup=true noauth=true unpack=true explicitsuite=false aptsources=unstable unreleased bootstrap=unstable unreleased [unstable] packages= source=http://ftp.de.debian.org/debian-ports/ keyring=debian-archive-keyring suite=unstable omitdebsrc=true [unreleased] packages= source=http://ftp.de.debian.org/debian-ports/ keyring=debian-archive-keyring suite=unreleased omitdebsrc=true

15 years

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risu instruction set test harness now publicly available

by Peter Maydell

Hi. As part of my work on qemu I've written a simplistic random instruction sequence generator and test harness. To quote the README: risu is a tool intended to assist in testing the implementation of models of the ARM architecture such as qemu and valgrind. In particular it restricts itself to considering the parts of the architecture visible from Linux userspace, so it can be used to test programs which only implement userspace, like valgrind and qemu's linux-user mode. I don't particularly expect this tool to be of much general interest outside people developing either qemu or valgrind or similar models, but I have in any case made it publicly available now: http://git.linaro.org/gitweb?p=people/pmaydell/risu.git;a=tree -- PMM

15 years

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RFC: Dynamic hwcaps

by Dave Martin

Hi all, I'd be interested in people's views on the following idea-- feel free to ignore if it doesn't interest you. For power-management purposes, it's useful to be able to turn off functional blocks on the SoC. For on-SoC peripherals, this can be managed through the driver framework in the kernel, but for functional blocks of the CPU itself which are used by instruction set extensions, such as NEON or other media accelerators, it would be interesting if processes could adapt to these units appearing and disappearing at runtime. This would mean that user processes would need to select dynamically between different implementations of accelerated functionality at runtime. This allows for more active power management of such functional blocks: if the CPU is not fully loaded, you can turn them off -- the kernel can spot when there is significant idle time and do this. If the CPU becomes fully loaded, applications which have soft-realtime constraints can notice this and switch to their accelerated code (which will cause the kernel to switch the functional unit(s) on). Or, the kernel can react to increasing CPU load by speculatively turn it on instead. This is analogous to the behaviour of other power governors in the system. Non-aware applications will still work seamlessly -- these may simply run accelerated code if the hardware supports it, causing the kernel to turn the affected functional block(s) on. In order for this to work, some dynamic status information would need to be visible to each user process, and polled each time a function with a dynamically switchable choice of implementations gets called. You probably don't need to worry about race conditions either-- if the process accidentally tries to use a turned-off feature, you will take a fault which gives the kernel the chance to turn the feature back on. Generally, this should be a rare occurrence. The dynamic feature status information should ideally be per-CPU global, though we could have a separate copy per thread, at the cost of more memory. It can't be system-global, since different CPUs may have a different set of functional blocks active at any one time -- for this reason, the information can't be stored in an existing mapping such as the vectors page. Conversely, existing mechanisms such sysfs probably involve too much overhead to be polled every time you call copy_pixmap() or whatever. Alternatively, each thread could register a userspace buffer (a single word is probably adequate) into which the CPU pokes the hardware status flags each time it returns to userspace, if the hardware status has changed or if the thread has been migrated. Either of the above approaches could be prototyped as an mmap'able driver, though this may not be the best approach in the long run. Does anyone have a view on whether this is a worthwhile idea, or what the best approach would be? Cheers ---Dave

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