Upstream Work ([VIRT-109])
==========================
- spent ages tracking down 64-on-32 cputlb errors which led to:
- adding x86_64 support to TCG system tests
- {PATCH v1 0/4} softmmu de-macro fix with tests Message-Id:
<20190605162326.13896-1-alex.bennee(a)linaro.org>
- {PATCH} cputlb: cast size_t to target_ulong before using for
address masks Message-Id:
<20190606154310.15830-1-alex.bennee(a)linaro.org>
- took over maintainership of orphaned gdbstub
- posted {PULL 00/52} testing, gdbstub and cputlb fixes Message-Id:
<20190607090552.12434-1-alex.bennee(a)linaro.org>
- problems on hackbox lead to {PATCH} tests/vm: favour the locally
built QEMU for bootstrapping Message-Id:
<20190607185337.14524-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other Tasks
===========
- Did some initial reading on RPMB
- Half day fire training
Absences
========
- May 27th is a Bank Holiday
- May 31st working on train in the afternoon
Current Review Queue
====================
* {Qemu-devel} {PATCH v4 00/39} tcg: Move the softmmu tlb to CPUNegativeOffsetState
Message-Id: <20190604203351.27778-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH v2} target/arm: Vectorize USHL and SSHL
Message-Id: <20190603232209.20704-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH resend} test-thread-pool: be more reliable
Message-Id: <20190530093417.23370-1-pbonzini(a)redhat.com>
* {PATCH 0/4} tests/docker: add podman support
Message-Id: <20190523234011.583-1-marcandre.lureau(a)redhat.com>
* {Qemu-devel} {PATCH 0/2} Implement PowerPC FPSCR flag Fraction Rounded
Message-Id: <20190525022008.24788-1-programmingkidx(a)gmail.com>
* {Qemu-devel} {PATCH for-4.1 v2 00/36} tcg: Move the softmmu tlb to CPUNegativeOffsetState
Message-Id: <20190328230404.12909-1-richard.henderson(a)linaro.org>
--
Alex Bennée
[LLVM-122] BTI and PAC support
Committed the LLD work. Modulo bugs this should now be done.
[LLVM-542] LLVM/GCC code size investigation
- Revisited my Zephy build with clang patches and updated so that it
works with trunk.
- Work out next steps of work.
- Work out to build an embedded gcc toolchain using the linaro infrastructure.
[Misc]
Reported bug in gold whereupon it would generate v4t veneers for v8-a CPUs
Still waiting for TK-1 board to finish building clang so that it can
run the testsuite. Hopefully finished over the weekend.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ Got the VFP decodetree conversion patchset out for review
(42 patches, 8 files changed, 3024 insertions(+), 1476 deletions(-))
+ sent a patchset which does the (easy) first step in my plan
for converting QEMU's documentation to Sphinx; sadly all the other
steps are much trickier...
thanks
-- PMM
== Progress ==
* FDPIC
- GCC: No progress, still waiting for feedback
* GCC upstream validation:
- reported a few regressions.
* GCC:
- UBSAN/bare-metal: added sync primitives implementation for low-end
cores (eg cortex-m0) Seems OK
- noinit attribute: started work
* Infra
- Fixed Dejagnu configuration issue in ABE which prevented us from
using target variant specifications
- Investigated problems with ABE and failure to cross-build "recent"
glibc (trouble with C++ compiler detection). ABE patches under review.
- Reduced load on APM machines to avoid depending on them too much
== Next ==
GCC:
- handle feedback on FDPIC patches
- noinit attribute
- UBSAN/bare-metal: do more testing
Hi,
Food for thought for today's sync up. I've been writting QEMU plugins to
exercise the plugin system and see what sort of useful information you
can extract when you can control the instruction stream.
For example I now have a plugin that can break down instruction counts
for any given run, for example a kernel boot:
Instruction Classes:
Class: UDEF not counted
Class: SVE (68 hits)
Class: Reserved (0 hits)
Class: PCrel addr (4589078 hits)
Class: Add/Sub (imm,tags) (0 hits)
Class: Add/Sub (imm) (26832113 hits)
Class: Logical (imm) (74304974 hits)
Class: Move Wide (imm) (10933759 hits)
Class: Bitfield (71470957 hits)
Class: Extract (85655 hits)
Class: Data Proc Imm (0 hits)
Class: Cond Branch (imm) (37227632 hits)
Class: Exception Gen (6 hits)
Class: NOP not counted
Class: Hints (244825554 hits)
Class: Barriers (1668558 hits)
Class: PSTATE (202144 hits)
Class: System Insn (7132992 hits)
Class: System Reg (2268308 hits)
Class: Branch (reg) (6280976 hits)
Class: Branch (imm) (18347905 hits)
Class: Cmp & Branch (180167025 hits)
Class: Tst & Branch (4092972 hits)
Class: Branches (0 hits)
Class: AdvSimd ldstmult (0 hits)
Class: AdvSimd ldstmult++ (0 hits)
Class: AdvSimd ldst (0 hits)
Class: AdvSimd ldst++ (0 hits)
Class: ldst excl (160861365 hits)
Class: Prefetch (0 hits)
Class: Load Reg (lit) (12828544 hits)
Class: ldst noalloc pair (0 hits)
Class: ldst pair (60381349 hits)
Class: ldst reg (0 hits)
Class: Atomic ldst (0 hits)
Class: ldst reg (reg off) (0 hits)
Class: ldst reg (pac) (0 hits)
Class: ldst reg (imm) (119597941 hits)
Class: Loads & Stores (0 hits)
Class: Data Proc Reg (113586343 hits)
Class: Scalar FP (0 hits)
Class: Unclassified (0 hits)
You can break down each class to individual instructions. For example
the Hints are mostly:
Individual Instructions:
Instr: wfe (132400072 hits) (op=0xd503205f/ Hints)
Instr: sevl (66433640 hits) (op=0xd50320bf/ Hints)
Instr: yield (29619246 hits) (op=0xd503203f/ Hints)
Instr: wfi (2865 hits) (op=0xd503207f/ Hints)
So I'm looking for a similar experiment that would be useful for the
memory sub-system. When I chatted to Maxim we thought maybe a simplified
cache line simulator might be useful. The aim wouldn't be to simulate
what a real cache might do but to be useful say for identifying regions
of code which might be susceptible to cache line bouncing. So as
compiler writers what sort of run time memory behaviour would you like
to track? What sort of information would be useful to extract with such
a tool?
I'm open to ideas ;-)
--
Alex Bennée
Four day week.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390 fp vector patch set.
Posted v16 rx. This seemed so close to being ready
last week, but now I don't know. I think I should
quit pushing it myself and let Yoshinori do more of
the lifting here.
Reviewed avr v20 patch set.
Reviewed Alex's testing patch set.
Submitted patches to constify upstream capstone
(500k from .data to .rodata).
r~
Short week (off Thursday/Friday)
== Progress ==
* FDPIC
- GCC: No progress, still waiting for feedback
* GCC upstream validation:
- reported a few regressions / fixed some testcases
* GCC:
- UBSAN/bare-metal: added sync primitives implementation for low-end
cores (eg cortex-m0) Seems OK
* Infra
- cleanup
- handling some problems with boards upgrades and crashes
== Next ==
FDPIC:
- GCC: handle feedback
UBSAN/bare-metal: do more testing
== This Week ==
* PR88837 (7/10)
- Addressed all upstream suggestions.
- Found a (hackish) way to test patch with qemu (multiple issues).
- Sorting thru "strange" testsuite fallout most of which seems
unrelated to my patch.
* PR88833 (2/10)
- Looking at fwprop pass
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks.
(Short week, three days.)
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ continuing with the conversion of the VFP decoder to 'decodetree'.
With some useful advice from RTH I have now got a big chunk of
it done, and it looks like this will provide:
- better places to put "UNDEF if CPU doesn't have double support" checks
- checks of "VFP enabled?" only after all UNDEF checks have happened
- cleanup of a lot of code that uses some TCG globals cpu_F0 and cpu_F1,
which is weird ancient style and overdue for a cleanup
- a VFP decoder which isn't a single thousand-line function with multiple
nested switch statements
thanks
-- PMM
3 day week.
[LLVM-122] BTI and PAC support in lld, llvm-readobj, llvm-objdump
- Now in upstream review. Most of the week spent writing and updating tests.
Some time reviewing some asm goto patches patches.
Planned absences:
Holiday Friday 31st May.
== Progress ==
* Out of office 22 & 24 May
* [GlobalISel] Refactor CallLowering [LLVM-568]
- In progress, likely going to take a while
- Found a minor bug in the lowering for AArch64 (I can get it to
crash on some edge case), not sure if it's worth fixing independently
since it gets fixed anyway with the refactoring that I have in
progress
- Trying to understand an AMDGPU failure
== Plan ==
* Out of office 29 May - 10 June
* More of the same
o LLVM
* 8.0.1-rc1 ARM and AArch64 Binaries uploaded.
* Buildbots: One fixe committed upstream.
* Machine outliner:
- Fixed liveness issue.
- Preparing pat6ch for re-submission
o Misc
* Various meetings and discussions.
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ]
Merged!
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Started dusting off and rebasing wip.
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ]
Started reviewing the kernel patch set for this feature.
[VIRT-327 # Richard's upstream QEMU work ]
PR for tcg gvec work.
PR for Sato-san's RX target.
Patch set to update capstone and enable s390x.
GSOC: Review v3 of Jan's enable risu for x86 patch set.
[Other]
Travel arrangements for Xilinx meeting in San Jose, June 13.
Will need to pick Peter's brain re m-profile before then.
r~
== This Week ==
* PR88833 (4/10)
- Started investigating the issue, it seems one of the code-movement
RTL passes like cse2
do not remove identical register copies resulting in extra register move.
* PR88837 (5/10)
- Patch almost approved offline by Richard, suggested me to move
discussion upstream.
- Observed "strange" issue with return value vectors on qemu for
run-time tests for fixed-length vectors. Turned out due to mismatch
in vector-length at compile and run time -;)
- Trying to run SVE tests with qemu.
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
[LLVM-122] BTI and PAC support in LLD
Implementation now working, have written BTI tests, next step is
finishing off PAC tests.
[Misc]
Helped out debugging an asm-goto problem on ARM targets.
Investigated a GNU ld LMA overlap when VMA and LMA got out of sync.
Helped out with CMSIS use of ld scripts when using a fast-model,
needed to get LMA == VMA for program header covering BSS.
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- synced up with Emilio, will take over branch and submit
- latest branch is [plugins/plugins-v3]
- will peel off simple clean-ups and tweaks next week
- then need to split up some more and better separate code
- exposed plugin_disas to for "howvec" instruction counter
- some [example] [output] while booting kernel
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
[plugins/plugins-v3]
https://github.com/stsquad/qemu/tree/plugins/plugins-v3
[example] http://ix.io/1JXC
[output] http://ix.io/1JXl
GSoC Mentoring ([VIRT-348])
- planning for start of coding next week
[VIRT-348] https://projects.linaro.org/browse/VIRT-384
Upstream Work ([VIRT-109])
==========================
- prepared [testing/next] for PR
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[testing/next] https://github.com/stsquad/qemu/tree/testing/next
Completed Reviews [3/3]
=======================
{RISU v3 00/11} Support for i386/x86_64 with vector extensions
Message-Id: <20190523204409.21068-1-jan.bobek(a)gmail.com>
{PATCH v10 00/20} gdbstub: Refactor command packets handler
Message-Id: <20190521095948.8204-1-arilou(a)gmail.com>
- CLOSING NOTE [2019-05-24 Fri 17:30]
awaiting re-spin with tags applied.
{RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
- CLOSING NOTE [2019-05-24 Fri 17:47]
taking over the tree
Absences
========
- May 27th is a Bank Holiday
- May 31st working on train in the afternoon
Current Review Queue
====================
* {PATCH 0/5} tests/vm: Python 3, improve image caching, and misc
Message-Id: <20190329210804.22121-1-wainersm(a)redhat.com>
* {Qemu-devel} {PATCH for-4.1 v2 00/36} tcg: Move the softmmu tlb to CPUNegativeOffsetState
Message-Id: <20190328230404.12909-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {RFC v4 0/7} Baby steps towards saner headers
Message-Id: <20190523081538.2291-1-armbru(a)redhat.com>
* {Qemu-arm} {PATCH v2 0/4} hw/arm/boot: handle large Images more gracefully
Message-Id: <20190516144733.32399-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH v12 00/12} Add RX archtecture support
Message-Id: <20190514061458.125225-1-ysato(a)users.sourceforge.jp>
* {PATCH 00/13} target/arm/kvm: enable SVE in guests
Message-Id: <20190512083624.8916-1-drjones(a)redhat.com>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ sent patchset fixing a handful of simple GICv3 bugs
+ usual codereview work
+ sent out a sketch of how we can transition our documentation
from the current texinfo manual to a set of sphinx manuals
+ had a look at the practicalities of converting our hand-written
VFP decoder to 'decodetree' -- this may be the easiest way to
support FPU configs which only support single-precision, like Cortex-M33
thanks
-- PMM
== Progress ==
* FDPIC
- GCC: Updated patch 03/21 with changes in the handling of -static
according to feedback. Pinged the whole series.
* GCC upstream validation:
- reported a couple of regressions
* Infra
- [stalled] working on adding binutils regression testing to round-robin jobs
- cleanup
- handling some problems with boards upgrades and crashes
== Next ==
FDPIC:
- GCC: handle feedback
UBSAN/bare-metal: look at how to make it easier to use on CPUs that
lack sync primivites (eg cortex-m0)
== This Week ==
* PR88837 (9/10)
- Tweaked patch to handle few more special cases with suggestions from
Richard.
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
o LLVM
* 8.0.1-rc1 Started Binaries build.
* Buildbots babysitting:
- Two fixes committed upstream
* Machine outliner:
- Liveness informations are not accurate after FrameLowering,
investigation on-going.
o Misc
* Various meetings and discussions.
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ]
Posted v7 and v8. I think this is now ready for merge,
but I said that last week as well. :-P
[VIRT-327 # Richard's upstream QEMU work ]
More gvec work, some of which applies to target/arm,
and some to tcg/aarch64/, but all of which is in support
of David's target/s390x work. Should be coming to a
close on that soon.
Posted v7 of my do_syscall split.
Reviewed v13 of the RX target, adjusted it slightly for
my tlb_fill changes. I think this now ready to merge.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ finally managed to complete review of Damien's reset handling rework
+ rolled v2 of patchset to support booting large kernel images
+ sent a cleanup patchset to rename arm.h to boot.h
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ working on making the CPU model configurable without FPU or DSP,
so that we can correctly model the Musca-A and MPS2-AN521 boards as
not having FPU or DSP on CPU #0.
thanks
-- PMM
== Progress ==
* FDPIC
- GCC: sent updated patch series (v5). Received feedback about -static
support vs dynamic-linkker need. Discussing options.
* GCC upstream validation:
- reported a couple of regressions
- found a bug in qemu while testing v4.0.0, preparing a reproducer
* Infra
- [stalled] working on adding binutils regression testing to round-robin jobs
- cleanup
== Next ==
FDPIC:
- GCC: handle feedback
UBSAN/bare-metal: look at how to make it easier to use on CPUs that
lack sync primivites (eg cortex-m0)
== Progress ==
* [GlobalISel] Add support for integers > 32 bits wide [LLVM-310]
- While looking into this I found and fixed a bug in the generic
part of IRTranslator, which reduced the number of fallbacks on the ARM
test-suite by about 20%
- Currently working on lowering function calls etc for 64-bit types
* [GlobalISel] Refactor CallLowering [LLVM-568]
- The CallLowering interface really needs a cleanup before I
continue with LLVM-310
- This has been discussed upstream in the past and would benefit all
targets, so I'm going to give it a shot
* SVE2 code reviews
== Plan ==
* More of the same
* Out of office 29 May - 10 June
== Progress ==
* Out of office on Friday (sick)
* [GlobalISel] Better support for small types [LLVM-553]
- Committed upstream
* GlobalISel
- quickfix for a DBG_VALUE-related bug
- code reviews
* SVE code reviews
* Catching up on Connect / EuroLLVM
== Plan ==
* More of the same
* Out of office end of May - beginning of June
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ]
Posted v4, v5, v6. I think this is now ready for merge.
[VIRT-327 # Richard's upstream QEMU work ]
Posted v3 of the CPUNegativeOffset patch set.
Posted v2, v3, and a pull request for the tlb_fill patch set.
Debugged one more fix for Sparc testthreads.
Reposted some long dormant linux-user fixes.
Started reviving the do_syscall split patch set,
since Laurent asked after it.
r~
o 4 days week.
o LLVM
* Machine outliner:
- Fixed LR save issue, when saved into a register.
- Dealing with LR save/restore when outlined region is a
pop{...,PC} tail-call.
- Investigating potential issue with condition flags.
o Misc
* Various meetings and discussions.
[LLVM-158] buildbot maintenance
- Increased timeouts on some libfuzzer tests, aarch64 full bots should
fail less frequently under load.
[LLVM-534] -n -N support in LLD (needed for Linux kernel allyesconfig
CI with LLD on AArch64)
Rewrote using a different approach after upstream comments
[LLVM-122] BTI and PAC support in LLD
Wrote an implementation, it compiles, but completely untested as of today.
(short week: 3 days)
Brief writeup of a pair of talks I attended on Tuesday at the
Cambridge University Computer Lab by some people from Amazon:
Diana Popa talked about Amazon's new "Firecracker" VMM (virtual
machine monitor -- the userspace component that uses the kernel's KVM
APIs to create and control virtual machines; kvmtool and QEMU are both
VMMs). Their use case is the AWS Lambda service, where VMs are
generally fairly short-lived (on the order of hours), startup time
matters a lot, and the VMs typically don't need very much CPU/RAM
resource. Firecracker is written in Rust, and provides a very simple
guest device model (virtio block and network devices), booting a
kernel that knows it is virtualized. It boots the kernel directly,
without running a BIOS. It has a memory footprint of less than 5MB and
a boot time of 125ms. They are currently working on Arm support (they
have it booting, but some bits still need work, eg the VM doesn't get
the right time because there is no RTC device exposed to the guest).
My feeling was that this shows an advantage of the KVM design: the
kernel/userspace split makes it easy to replace the userspace VMM
part with something customised for the task at hand if you don't
need a full-fat all-bells-and-whistles general-purpose solution.
Andreea Florescu talked next, about the "rust-vmm" libraries. This is
a set of open-source Rust crates which are intended to abstract out
some of the common building blocks for VMMs. Firecracker started as a
fork of Google's crosvm project, but since the use-case requirements
for the two projects are markedly different the code diverged fairly
rapidly. rust-vmm is intended to allow the projects to share code for
things like "nice Rust interfaces to the KVM ioctls" and
"implementations of virtio devices". The project is still in quite an
early stage of development -- they have a few crates that have made it
to the "stable, published on crates.io" phase, but most are either in
"being developed" or still just "planned/proposed/discussed". It's
currently Apache-2.0 licensed, but they are planning to dual-license
to Apache-2.0 | 3-BSD because Apache-2.0 isn't GPL-2.0 compatible, and
they have had some interest in being able to experiment with using
these crates with QEMU. (That sounds a bit outlandish but it's
actually something I'm planning to look into myself -- the nice thing
about Rust is that you can potentially incrementally add it to an
existing C codebase without requiring a ground-up rewrite, so allowing
security hardening of the more "risky" parts. This is very definitely
all still just "exploratory prototyping" though.)
Progress:
* just miscellaneous upstream stuff
thanks
-- PMM
* 1 day off (public holiday)
== Progress ==
* FDPIC
- rebased GCC FDPIC patches. Fixing conflict with fstack-protector.
* GCC upstream validation:
- Fixed ST internal validation broken since GCC bumped to version 10.
Still some spurious failures probably caused by NFS. Testing
workarounds.
- reported a couple of regressions
* GCC
- ubsan on bare-metal toolchain: no news.
* Infra
- [stalled] working on adding binutils regression testing to round-robin jobs
== Next ==
FDPIC:
- GCC: fix problems with fstack-protector
UBSAN/bare-metal: look at how to make it easier to use on CPUs that
lack sync primivites (eg cortex-m0)
o 4 days week.
o LLVM
* Machine outliner:
- Identified an issue related to LR saving inside an outlined
chunk, working on a proper fix.
o Misc
* Various meetings and discussions.
[VIRT-327 # Richard's upstream QEMU work ]
Review Mark's target/ppc getVSR patch set.
Two rounds of "tcg vector improvments"; hopefully that's
ready to go in on Monday.
More work on "bit select" and "compare select" primitives.
I can now vectorize Neon VSHL/VSHR variable shift (where
positive values are left shift and negative values are
right shift). Waiting on posting this while previous tcg
vector patch set is still in flight.
Review Alex's demacrofy v5. Wrote a boot.S for Alpha.
Review David's latest target/s390 vector patch set.
Review Sato-san's target/rx v8. Played around with a few
disassembler improvements, but I'll not confuse the review
process by posting them now.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ pushed QEMU 4.0 out the door
+ code review:
- RTH's patchset that cleans up the softmmu TLB structs
- Nios2 nommu and semihosting patchset from codesourcery
- cleanup series removing a "bucket of random stuff" header file
- RTH's patchset adding BTI support for linux-user mode
- RTH's patchset cleaning up the tlb_fill API
- RTH's patchset implementing Cortex-A73, A75, A76
- "SBSA reference platform" new board model
- patchset adding Netduino Plus 2 board model
- linux-user patch to correctly handle loading ELF segments which
have no file data (ie only bss)
- patch adding the RTC device to the ASpeed board models
- patchset fixing various minor problems preventing QEMU building
cleanly for Windows-on-Arm
- started looking at Damian's patchset that overhauls how we do
device reset; this is good work that's long overdue, but reviewing
it requires me to wrap my head around the problem space...
+ sent out v2 versions of a few minor patches that needed respins
+ wrote email to qemu-devel asking for volunteers to help with
QEMU release work so it's not only me doing this every cycle
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ FPU support now upstream
+ a few loose ends remain to be tidied up, but this epic is
now essentially complete
NB: out of office Tues 7th afternoon to attend a couple of lectures
at the CL by people from Amazon on their virtualization stack written
in Rust (http://talks.cam.ac.uk/talk/index/119491 and
http://talks.cam.ac.uk/talk/index/121069)
thanks
-- PMM
[LLVM-158] Buildbot monitoring duty
- Reported bug that libc++ when built as part as libfuzzer is not
built with PIC or PIE, yet some tests for non-x86 force PIE which then
fails at link-time.
- Reported bugs in libstdc++ and clang where exception specifications
didn't match due to extra parentheses. libstdc++ now fixed to not have
any discrepancy, clang bug for not ignoring the extra parentheses
still active.
- Investigated libfuzzer intermittent failures, 2 look like timeouts
not being long enough, submitted patch to get this increased.
[LLVM-122] BTI/PAC Started prototyping an implementation based on top
of the yet to land LLD patch for Intel CET.
Think about how to add crypto extensions without overriding
architecture in a complex build system.
Review comments for LLD and compiler-rt, and mailing list proposal for
something similar to __attribute__((at(address))).
* 1 day off (public holiday)
== Progress ==
* FDPIC
- Looked at gdbserver memory consumption increased since release 7.5.
Found similar results to Prathamesh. On arm-linux-gnueabihf with a
sample test program, gdbserver memory usage increased from ~500kB to
~1.5MB. But that should not prevent execution on board (which has
16MB); maybe memory fragmentation?
- rebased GCC FDPIC patches. There's a regression since Thomas
committed fixes to fstack-protector.
* GCC upstream validation:
- ST internal validation broken since GCC bumped to version 10. I was
using an old glibc. Upgrading glibc proved to be painful (requiring
new versions of make, bison, python....). Still using RH6 servers.
* GCC
- ubsan on bare-metal toolchain: Sent an email to llvm-dev list,
requesting help in how-to-cross-build runtime libs in clang/llvm. No
response so far....
* Infra
- [stalled] working on adding binutils regression testing to round-robin jobs
- fixed legacy binutils regression testing by switching to new slaves
- sent patches to support new slave (tcwg-lc-01)
- sent ABE patches to support new gcc9 config, and update to latest-rel config
== Next ==
FDPIC:
- GCC: fix problems with fstack-protector
UBSAN/bare-metal: look at how to make it easier to use on CPUs that
lack sync primivites (eg cortex-m0)
Infra:
- Fix ST internal validation
== Progress ==
* Out of office 1 day (public holiday)
* [GlobalISel] Better support for small types [LLVM-553]
- Fixed the bug that I'd been looking into
- Committed support for several instructions, only 3 left to commit next week
* IR SVE Reviews [LLVM-545]
- Looked into the patches for stack management
* GlobalISel code review
- Currently looking into an unpleasant patch adding a new opcode
* Catching up on Connect / EuroLLVM
== Plan ==
* More of the same
* Out of office end of May - beginning of June
[VIRT-327 # Richard's upstream QEMU work ]
Another round on launchpad 1824853, TB overflow.
This time handling relocation overflow. Which would
not be seen on an x86 host (2GB displacement), but
would affect some of the risc hosts.
Reviewed Peter's v7m fpu patches.
Another round on util/path.c, fixing the startup loop
that we get into for using a full chroot for -L.
Poked my nose into Alex's cputlb demacrofy patch set.
Hopefully the feedback was helpful...
First two pull requests for 4.1.
r~
[PR40542] Sent patch for -n and -N support in LLD for upstream review
[LTO]
Investigated problems when using -Os -Oz with LTO, raised 2 PRs
- error if clang linker invocation uses -Os and -Oz
- strange error message when .bc used as a file extension for a
separate compile and link step
Crash in GNU ld when linking LLVM lto via the gold plugin. Looks like
a memory access/corruption problem in the conversion from .bc to bfd.
Other miscellaneous reviews for some linker script support in LLD.
Investigation into why ld.bfd with NOLOAD on the .gnu.build-id section
corrupts debug information.
== This Week ==
* PR88837 (7/10)
- Discussed and finalized algorithm for vector construction with Richard.
* GNU-606 (1/10)
- Experimented gdbserver memory consumption with docker.
* Public Holiday (2/10)
== Next Week ==
- Continue ongoing tasks.
== Progress ==
* Short week (Out of office 22 - 24 April)
* [GlobalISel] Better support for small types [LLVM-553]
- Investigated my bug some more, it doesn't seem to be related to my
recent patches but rather an existing issue which is exposed because
we select more functions now
- Might be related to LLVM-456 (Fix frame index sizes for i<32)
* Catching up on Connect / EuroLLVM
== Plan ==
* Try to confirm root cause of LLVM-553 issue
