Upstream Work ([VIRT-109])
==========================
- need to finish the re-work of [system test and misc arch] tests
:todo
- will be useful for test cases for plugins
- also more test cases queued up for system tests
- posted userspace CPUID access patches Message-Id:
<20190128173940.25813-1-alex.bennee(a)linaro.org>
- spent some time debugging PAuth kernel boot regression
- rth posted a fix for the regression Message-Id:
<20190129143511.12311-1-richard.henderson(a)linaro.org>
Other Tasks
===========
- rebuilt Zen after the /home SSD failed
- fortunately the backup drive had all the work in progress source
code
- moved to Debian Buster while I'm at it
- need to regenerate my images and foundation/FVP setup
- and realise quite how many tweaks I had baked into the old system
Completed Reviews [2/2]
=======================
{Qemu-devel} {PATCH 00/11} Enable build and install of our rST docs
Message-Id: <20190201145035.22739-1-peter.maydell(a)linaro.org>
{RFC PATCH 0/3} lm32: convert to new common tcg infrastructure
Message-Id: <20190131215611.29341-1-michael(a)walle.cc>
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {PATCH v2 00/18} OpenBSD: Enable qtesting
Message-Id: <20190129175403.18017-1-philmd(a)redhat.com>
* {PATCH v11 00/25} Fixing record/replay and adding reverse debugging
Message-Id: <20190131131520.23264.75724.stgit@pasha-VirtualBox>
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code
Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH v3 0/4} tcg: support heterogenous CPU clusters
Message-Id: <20190121152218.9592-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH RFC 00/11} Add Renesas RX archtecture
Message-Id: <20190121131602.55003-1-ysato(a)users.sourceforge.jp>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ got the "use Sphinx for documentation" patchset to a point where I
think we could plausibly commit it to master; sent out for review
+ two arm pull requests
+ sent patches fixing decode errors for FCMLA
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ AN521 model is now in upstream QEMU
thanks
-- PMM
== Progress ==
* FDPIC
- (GNU-411) GDB: debugging problems with FDPIC support.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, still
- qemu-3.1: switched to it this week
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. No progress.
- minor testsuite fixes
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- debugging new benchmarking round-robin jobs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Infra:
- benchmarking jobs
== Progress ==
* Out of office on Friday
* [Thumb GlobalISel] Support divisions [LLVM-516]
- Committed upstream
* [Thumb GlobalISel] Support G_GEP [LLVM-532]
- Ready to commit next week
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Posted binaries for rc1
- Created a bug report for a MSan failure on AArch64
* Use new version of GCC on buildbots [LLVM-515]
- Ready to use in production
== Plan ==
* More GlobalISel
* Patch up the Jenkins release job [LLVM-533]
== Progress ==
* FDPIC
- (GNU-411) GDB: debugging problems with FDPIC support.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, still
- qemu-3.1: plan to switch to it this week
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. No progress.
- minor testsuite fixes
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- experimenting with new build servers
- started looking at new benchmarking round-robin jobs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
== This Week ==
* SVE ACLE (8/10)
- WIP patch for svlsl
* Validation (1/10)
- Upsteam monitoring job based on round-robin.
- abe bug with make install
* Meetings (1/10)
== Next Week ==
- Continue ongoing tasks.
== Progress ==
* SVE ACLE
- Revised and reviewed svbic main briant svbic_z for bool
* Fixing uninit warning suppression from tree-ch pass
- Implemented a patch to handle this and regression test is fine.
Will post for review once stage 1 opens
* tree-reassoc improvements
- Looking at possible data structures to best represent
== Plan ==
* Continue with SVE ACLE
* Continue with tree-reassoc
[VIRT-294 # ARMv8.3-PAuth, Pointer Authentication ]
Finished up the linux-user emulation, and posted.
Reviewed a patch set from Huawei also touching PAuth.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed riscv decodetree v4 patchset.
Partial review of new target/rx patchset. It is confusing enough
to make me want to tackle the variable-length decodetree problem.
Reviewed softtlb resize v7 patchset; ported that to the remaining
tcg backends.
Part way through reviewing Peter's MPS2 patch set.
r~
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- started reviewing {RFC v2 00/38} Plugin support Message-Id:
<20181209193749.12277-1-cota(a)braap.org>
- some bitrot when applied to current tree :/
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- respin {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.bennee(a)linaro.org>
- re-based [v3 branch] - I think the id reg stuff is now addressed
by rth's fixes
- still need to address other review comments
- posted {RFC PATCH 0/3} vmbuild tweaks for BSD targets Message-Id:
<20190121171543.32422-1-alex.bennee(a)linaro.org>
- posted {PATCH v3 00/11} current fpu/next queue (tests & build fix)
Message-Id: <20190122215016.18697-12-alex.bennee(a)linaro.org>
- finally solved the weird endianess issue
- merged in {PULL v2 00/11} check-softfloat, fp-bench and clang
compile fixes Message-Id:
<20190123114220.16972-1-alex.bennee(a)linaro.org>
- posted {PATCH v1 00/14} testing/next (binfmt_misc, vm-build and BSD
CI) Message-Id: <20190125140017.6092-1-alex.bennee(a)linaro.org>
- also did some work on [the linux-user multiarch but it is not
ready yet]
- need to finish the re-work of [system test and misc arch] tests
:todo
- will be useful for test cases for plugins
- also more test cases queued up for system tests
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[v3 branch]
https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3
[the linux-user multiarch but it is not ready yet]
https://github.com/stsquad/qemu/tree/testing/next-with-linux-user
[system test and misc arch]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2
Completed Reviews [2/2]
=======================
{PATCH 00/18} Acceptance Tests: target architecture support
Message-Id: <20190117185628.21862-1-crosa(a)redhat.com>
- CLOSING NOTE [2019-01-25 Fri 19:33]
Still a few edge cases to work out
{PATCH 0/2} contrib: gitdm: Some updates
Message-Id: <1547807155-4526-1-git-send-email-aleksandar.markovic(a)rt-rk.com>
- CLOSING NOTE [2019-01-25 Fri 19:33]
Queued to my tree
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code
Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH v3 0/4} tcg: support heterogenous CPU clusters
Message-Id: <20190121152218.9592-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH RFC 00/11} Add Renesas RX archtecture
Message-Id: <20190121131602.55003-1-ysato(a)users.sourceforge.jp>
* {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI
Message-Id: <20190110121736.23448-1-richard.henderson(a)linaro.org>
* {PATCH v5 00/73} per-CPU locks
Message-Id: <20181213050453.9677-1-cota(a)braap.org>
--
Alex Bennée
Majority of the week spent preparing for Fosdem talk on LLD:
- Built Chrome for Arm and AArch64 to investigate link time
performance on non-X86 platforms
-- Both gold and bfd take a considerable amount of time to produce
stubs/veneers/errata fixes
-- AArch64 link time is comparable to X86
- LLD gets more usage out of multithreading than gold
- Studied Gold and BFD structure to compare to LLD
- About half of slides written.
Some minor involvement with some investigations for ClangBuiltLinux.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ code review:
- 'SBSA reference' model (now quite close to being in shape to go in)
- RTH's BTI patchset
- RTH's patchset adding TBI support to user-mode emulation
+ sent patches fixing the last lot of clang
-Waddress-of-packed-member warnings
+ had another look at the prototype work I did to use Sphinx
for QEMU's documentation -- updated the patchset and started
looking at how to tie it into our makefiles.
+ sent patches fixing a handful of underdecodings in our A64 decoder,
where we should have UNDEFed but did not
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ sent out v1 of the patchset implementing the SSE-200 and MPS2 AN521 model
+ read through the Musca-B1 docs to confirm what we can easily
put into an initial implementation of a model
thanks
-- PMM
== Progress ==
* Out of office on Monday
* [Thumb GlobalISel] Support G_SHL, G_ASHR, G_LSHR [LLVM-517]
- Committed upstream
* [Thumb GlobalISel] Support G_SDIV and G_UDIV [LLVM-516]
- Most of the work done, ready to commit next week
* LLVM 8.0 Release for ARM & AArch64 [LLVM-526]
- Started a few jobs, but ran into some trouble with our containers
- Will look more into it next week
* Use new version of GCC on buildbots [LLVM-515]
- Got it to work and committed patch; we have 2 silent bots running with GCC-7
- Will keep monitoring the bots and if they seem stable we can merge
to tcwg-llvmprod next week
== Plan ==
* Test LLVM 8.0.0 RC1
* Commit LLVM-516
* More GlobalISel
* Out of office on Friday
Hi Martin and Linaro-toolchain team,
We want to use 4.8.5 cross compile toolchain to build ko.
But we can't find such version on the release site[1].
Is there a 4.8.5 cross compile toolchain?
[1] https://releases.linaro.org/components/toolchain/gcc-linaro/
Best,
Xinliang
== Progress ==
* SVE ACLE
- Committed patches for
* svabs, svneg, svnot and svsqrt series
* svdiv series
* svmulh series
* svand, svorr, and sveor series
* svdot series
- Working on svbic and svbic_b variants
* Others
- Looking into tree-reassoc improvements for next stage1
- Looked into kernel plugin issue for arm
== Plan ==
* Continue with SVE ACLE
* Continue with tree-reassoc
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Posted v1.
[VIRT-327 # Richard's upstream QEMU work ]
Posted v6 of linux-user split. Based on Laurent's feedback,
I'm running LTP myself this time, at least for a few guests.
r~
Upstream Work ([VIRT-109])
==========================
- posted {PULL 0/5} gitdm updates with final 2018 stats Message-Id:
<20190114160956.7513-1-alex.bennee(a)linaro.org>
- posted {PULL 00/21} misc testing fixes for Travis and docker
Message-Id: <20190114150129.1013-1-alex.bennee(a)linaro.org>
- we have gone green again
- posted {PULL 0/7} check-softfloat, fp-bench and clang compile fixes
Message-Id: <20190117132703.17790-1-alex.bennee(a)linaro.org>
- some alt-OS issues and a weird failure on s390x
- spent some time getting a working s390x setup to investigate
- posted {PATCH} target/s390x: define TCG_GUEST_DEFAULT_MO for MTTCG
Message-Id: <20190118171848.27332-1-alex.bennee(a)linaro.org>
- need to investigate why s390x breaks so weirdly
- messed around with a little [CONFIG_TCG type cleanups]
- need to finish the re-work of [system test and misc arch] tests
:todo
- will be useful for test cases for plugins
- also more test cases queued up for system tests
- respin {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.bennee(a)linaro.org> :todo
- in branch [v3 branch]
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[CONFIG_TCG type cleanups]
https://github.com/stsquad/qemu/tree/misc/config-tcg-cleanups
[system test and misc arch]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2
[v3 branch]
https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3
Other Tasks
===========
- wrote up and submitted abstract for Connect
- I still hope to the history of TCG for TCWG room as well
Completed Reviews [4/4]
=======================
{Qemu-devel} {PATCH} .cirrus.yml: basic compile and test for FreeBSD
Message-Id: <CAPyFy2Dw2F3ks_5f8cvWjrsOTS0_Ybr5kELUpyHQmOQWUaeuFg(a)mail.gmail.com>
- CLOSING NOTE [2019-01-16 Wed 15:01]
Adds FreeBSD testing, yet another CI system
{PATCH v2} softfloat: enforce softfloat if the host's FMA is broken
Message-Id: <20181225070305.18221-1-cota(a)braap.org>
- CLOSING NOTE [2019-01-16 Wed 15:03]
Queued to my tree
{PATCH v6 0/3} Dynamic TLB sizing
Message-Id: <20190114165017.27298-1-cota(a)braap.org>
- CLOSING NOTE [2019-01-17 Thu 10:53]
Found a few issues.
{PATCH v7 0/3} Dynamic TLB sizing
Message-Id: <20190116170114.26802-1-cota(a)braap.org>
- CLOSING NOTE [2019-01-18 Fri 16:54]
Looks good to me now.
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {PATCH 0/2} contrib: gitdm: Some updates
Message-Id: <1547807155-4526-1-git-send-email-aleksandar.markovic(a)rt-rk.com>
* {PATCH 00/18} Acceptance Tests: target architecture support
Message-Id: <20190117185628.21862-1-crosa(a)redhat.com>
* {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI
Message-Id: <20190110121736.23448-1-richard.henderson(a)linaro.org>
* {PATCH v5 00/73} per-CPU locks
Message-Id: <20181213050453.9677-1-cota(a)braap.org>
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code
Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org>
--
Alex Bennée
[LLVM-521] LLD and taking the address of an ifunc
Went through the possible combinations (pic, pie, non-pic, exec,
shared,...) found one relocation that gcc uses that clang doesn't,
hence mc and LLD don't support. Raised upstream pr. Also found that
clang's code-sequence for -fpie doesn't seem to guarantee ifunc
pointer equivalence when linking -fpie (non-got generating sequence
used when ifunc is in same translation unit). Will need some further
investigation to confirm.
[LLVM-499] Support for linking the linux kernel
Committed -pic-veneer support and associated overflow fix, now merged
to 8.0 branch.
Other:
- Started work on Fosdem presentation on LLD performance. Studying
ld.bfd and ld.gold source code to look for structural differences
between them and LLD.
- Submitted presentation for next Linaro Connect
- Review for comdat group and unused section elimination.
- On buildbot duty.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ some code review, and another arm pull-request (including
RTH's pointer auth work)
+ sent patch fixing a bug in the gdbstub memory access path that
meant it was always making accesses as NonSecure even if the
guest CPU was currently Secure
+ sent patch fixing checkpatch to not wrongly complain about
block comments starting "/**"
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ I have a model of the SSE-200 subsystem used by the Musca board,
and a model of the MPS2 AN521 FPGA image which uses it. (Since it is
basically "our existing MPS2 AN505 model, but with SSE-200 rather than
IoTKit" it's a useful stepping stone to the Musca board.) There are
still some bugs and missing features, but it seems to mostly be
functional (it can run the ARM Trusted Firmware M test binary.)
thanks
-- PMM
== Progress ==
* FDPIC
- (GNU-411) GDB: gdbserver did not start because of a qemu-user
feature. Worked around it.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, still
- qemu-3.1 memory consumption. Got some clarifications from IT team
about LSF reports.. It seems qemu-3.1 consumes more memory in some
cases, though.
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. No progress.
- (GNU-597) Fixed arm testcase.
- PR 85596 committed doc fix
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- dealing with nasty ST-internal infrastructure problems
- (GNU-592): improved benchmarking scripts
- experimenting with new build servers
- ran Linaro binary toolchain tests on gcc-arm release, filled a few bug reports
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Validation:
- isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for
aarch64-linux target
== Progress ==
* [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491]
- Committed upstream
* [ARM & Thumb GlobalISel] Support calls to vararg functions [LLVM-490]
- This gets rid of all the fallbacks in the test-suite related to
calls to printf (which is a lot)
- Committed upstream
* Use new version of GCC on buildbots [LLVM-515]
- Fiddled with this a bit, but couldn't test much due to dockerd
being broken for a couple of days
- Manual installation of g++-7 from PPA works, but when trying the
same steps in the dockerfile it keeps restarting; need to investigate
why
== Plan ==
* More of the same
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2019.01 snapshot of the Linaro GCC 7 source package.
The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
This snapshot1 is based on FSF GCC 7.4+svn267072 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2019.01 stable2 periodic release.
Interesting changes in this GCC source package snapshot include:
Updates to GCC 7.4+svn267072
Linaro bug 4007: “Internal compiler error with -mcpu=thunderx2t99” is fixed
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development.
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development mailing list:
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at #linaro-tcwg
* Bug reports should be filed in Bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at Linaro support:
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
== Progress ==
* SVE ACLE
- Revised svmla, svmls, svmad and svmsb and committed after getting ACK
- Revised again posted for review
* svabs, svneg, svnot and svsqrt series
* svdiv series
* svmulh series
* svand, svorr, and sveor series
* svdot series
== Plan ==
* Contine with sve acle
[LLVM-520] LLD Fix movt/movw relocation overflow
Now committed upstream.
[LLVM-521] Taking the address of an ifunc in AArch64
Prompted by a bug report and comment about pointer equivalence, spent
some time looking into gold, lld and bfd behaviour to ensure that LLD
is at least correct.
Other
Some investigation into LLD non-support of common-page-size and
whether this is significant for code-size. Used in response to query
about whether LLD should change default value of max-page-size.
Thoughts about whether a linker must generate cantunwind .ARM.exidx
sections for code sections missing a .ARM.exidx section. If C++ code
with exceptions is interleaved with some assembly code without
.ARM.exidx sections then the assembly code can match the address range
of the C++ code that precedes it.
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ rth's pointer-auth emulation patchset
+ more devices for the microbit board model
+ support for u-boot "noload" image type
+ gdbstub multiprocess extension support for use when the board
model has multiple asymmetric clusters (like Xilinx Zynq boards)
- finished debugging patch for aarch64 host linux-user to distinguish
SEGV on read from SEGV on write by looking at the ESR context struct
from the kernel rather than by looking at the faulting insn; sent it.
- sent patch to fix linux-user pread64/pwrite64 with NULL buffer and 0 length
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
- Sent out patchset fixing heterogenous CPU support (required a lot
of thought about what we might need to fix and not all that much
code, in the end)
- Started work on refactoring our IoTKit model to also support
the extra pieces required by the SSE-200 subsystem used in the Musca
thanks
-- PMM
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v1 0/6} current fpu/next queue Message-Id:
<20190108162154.22259-1-alex.bennee(a)linaro.org>
- posted {PATCH v1 0/3} gitdm updates Message-Id:
<20190107111129.2087-2-alex.bennee(a)linaro.org>
- posted {PATCH v1 00/19} testing/next queue for travis and docker
Message-Id: <20190110174516.21586-1-alex.bennee(a)linaro.org>
- also managed to trigger two of the occasional Travis failures
locally
- one is a segfault in mcount (gprof/RCU related)
- the other seems to be a O_NONBLOCK/make interaction (using eBPF
to track it)
- did a little more on re-work of [system test and misc arch] tests
- will be useful for test cases for plugins
- respin {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.bennee(a)linaro.org> :todo
- in branch [v3 branch]
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[system test and misc arch]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2
[v3 branch]
https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3
Completed Reviews [2/2]
=======================
{PATCH v3 0/2} tests: Reorganize MIPS TCG directories and files
Message-Id: <1546621859-28227-1-git-send-email-aleksandar.markovic(a)rt-rk.com>
- CLOSING NOTE [2019-01-07 Mon 11:23]
A few notes about keeping makefile
{PATCH 00/13} Misc fixes / improvements for the docker and travis configs
Message-Id: <20190109163114.17010-1-berrange(a)redhat.com>
- CLOSING NOTE [2019-01-10 Thu 12:34]
Queued a chunk of these into testing/next
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI
Message-Id: <20190110121736.23448-1-richard.henderson(a)linaro.org>
* {PATCH v9 00/21} Fixing record/replay and adding reverse debugging
Message-Id: <154703587757.13472.3898702635363120794.stgit@pasha-VirtualBox>
* {Qemu-devel} {PATCH 0/4} tcg: support heterogenous CPU clusters
Message-Id: <20190108163008.7006-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH v3 00/31} target/arm: Implement ARMv8.3-PAuth
Message-Id: <20190108223129.5570-1-richard.henderson(a)linaro.org>
* {Qemu-arm} {PATCH 0/3} target/arm: Vector expansion improvments.
Message-Id: <20190106225035.5671-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH} configure: Force the C standard to gnu11
Message-Id: <1546857926-5958-1-git-send-email-thuth(a)redhat.com>
--
Alex Bennée
== Progress ==
* FDPIC
- (GNU-499) GCC: wait for feedback on v4 patches, but GCC just entered
stage4, so it's probably too late for gcc-9 :-(
- (GNU-411) GDB: hacked to build gdbserver, but the resulting binary
does not start.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, still
- qemu-3.1.0-rc3, memory consumption: more experiments under LSF show
"random" reports for memory consumption. It seems qemu-3.1 consumes
more memory in some cases, though.
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- dealing with nasty ST-internal infrastructure problems
- (GNU-592): improved benchmarking scripts
- (TCWG-1501) looking at new build servers configs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Validation:
- isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for
aarch64-linux target
== Progress ==
* [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491]
- Negative constants in particular cause a lot of fallbacks in the
test-suite/selfhost
- Need to help TableGen produce code for MOVi32imm
- Ready to commit next week
- Looked a bit into enabling MVNi as well, but that seems to require
more effort
* Use new version of GCC on buildbots [LLVM-515]
- Talked to doko and got a different PPA
- Didn't get a chance to test it yet, will do next week
* Sanity checks for docker builbbot containers
- Sent a quick patch to check slavenames and compatibility between
slave and image when starting a bot container
* Investigated some buildbot failures
- Marked 2 sanitizer tests as unsupported on ARM
- Need to investigate further so we can re-enable them
- I've been emailing the author, hopefully he can help debug
== Plan ==
* More of the same
[VIRT-294 # ARMv8.3-PAuth, Pointer Authentication ]
Posted v3 based on feedback.
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ]
Posted "v1" to qemu-devel, rebased on v3 pauth
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Progressed to the "write a standalone test case" stage for linux-user. I'll
need to discuss address space stuff w/ PMM for system mode. Discovered while
writing a test case for this that my document and gas do not agree on the
instruction encodings. Putting this on hold until query about document
revision numbers is answered.
Posted pieces of this implementing TBI for aarch64-linux-user.
[VIRT-327 # Richard's upstream QEMU work ]
Fixed alpha-linux-user fpcr initialization.
Fixed alpha-softmmu double-increment of SIGILL address.
Sent v2 patchset for target/arm use of gvec minmax routines.
r~
The Linaro Binary Toolchain
============================
The Linaro GCC 6.5-2018.12 Release is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release packages from:
(sources) http://releases.linaro.org/components/toolchain/gcc-linaro/6.5-2018.12/
(binaries) http://releases.linaro.org/components/toolchain/binaries/6.5-2018.12/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.5-2018.12
http://releases.linaro.org/components/toolchain/gcc-linaro/6.5-2018.12/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (users/linaro/binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.2 (gdb-8.2-branch)
https://lists.gnu.org/archive/html/info-gnu/2018-09/msg00001.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.5-2018.12)
==============================================
* Runtest and gdbserver are no longer installed in the toolchain bin/
directory. Binary releases no longer include runtest at all, and
gdbserver is a target tool; it is now shipped in the sysroot under
usr/bin/.
LDTS case #2211: gdbserver and runtest in GCC binary release are in
the wrong place or have the wrong name
* Gdbserver is no longer linked statically, because this is currently
unsupported.
Linaro bugzilla #3344: gdbserver broken in Linaro 2017.02
https://bugs.linaro.org/show_bug.cgi?id=3344
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.1 to 8.2.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06, Linaro
GCC 6.4-2017.07, Linaro GCC 6.4-2017.08, Linaro GCC 6.4-2017.09,
Linaro GCC 6.4-2017.10, Linaro GCC 6.4-2018.04 and Linaro GCC
6.5-2018.11.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2018.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.5-2018.11/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
This seems like a tricky extension to deploy to the operating system.
What is the proposed interface for setting GP on application pages? There are
several things that seem plausible to me, and I wondered how far planning has
gotten.
An mmap/mprotect flag?
An ELF program header PT_ARM_BTI (a-la PT_GNU_RELRO) to direct the loader to
set said flag when mapping binaries? Or equivalently, a PF_MASKOS bit that
could be set on the normal PT_LOAD header.
An ELF section flag set by the compiler for sections that use -mbti, which are
then collected into the PT_GNU_BTI segment by the linker?
That seems like the most plausible way to indicate on a per-binary basis that
it has been compiled with the BTI hints in place. But probably there are other
ways that make an equal amount of sense.
Is there any coordination going on with Intel wrt their similar gadget
protection scheme(s)?
r~
== This Week ==
* SVE ACLE (8/10)
- Addressing comments by Richard for svlsl_wide
- Created patch for svcls / svclz
* Validation (2/10)
- WIP hcqc wrapper script
== Next Week ==
- Continue ongoing tasks
(Short week, 2 days)
Progress:
* VIRT-65 [QEMU upstream maintainership]
- catching up on email/review backlogs from the holidays
- investigating a weird failure where running 'make check' in a loop
would cause make to complain "make: write error: stdout". This seems
to be because one or two of our test cases would put stdin/stdout
into O_NONBLOCK, which then made make's output routines fall over...
thanks
-- PMM
== This Week ==
* SVE ACLE (8/10)
- WIP patches for svlsl_wide, integer comparisons and cls/clz.
* Public holiday (2/10)
== Next Week ==
- Continue ongoing tasks
[VIRT-327 # Richard's upstream QEMU work ]
Some tcg-op-gvec work in support of MCA's target/ppc AltiVec work.
But in the process filled in the blanks for target/arm to take
advantage of the new entry points.
Rebased my August linux-user split work, reorg'ed for advice, and
posted v5.
Reviewing Cota's dynamic sized tlb patch set. TODO: I want to update
the aarch64 backend for this before finalizing a data structure layout.
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ]
Posted v1. We'll not talk about mailing lists any further. :-P
Merry Christmas, all!
r~
== Progress ==
* FDPIC
- (GNU-499) GCC: wait for feedback on v4 patches
- (GNU-411) GDB: it seems qemu's gdbstub needs patches to support
packets needed by fdpic. Tried to build gdbserver for fdpic, but the
code base changed a lot since our original port.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, still
- qemu-3.1.0-rc3, memory consumption: no time to really look at the
problem. Unable to match time's figures with LSF's
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. Using gcc-built
libubsan worked with an in-house llvm-based toolchain. POC is OK, but
a clean implementation is still far.
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- dealing with nasty ST-internal infrastructure problems
- (GNU-592): improved benchmarking scripts
- looking at new build servers configs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Validation:
- isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for
aarch64-linux target
Posting this to an internal list because v8.5 is still NDA.
There are a lot of holes to be filled wrt the user-level ABI.
In the meantime, I have a cpu property to turn on GP for all
pages. Which means that to test it, I provide a complete
statically linked program, so that nothing uses indirect
branches except that the ones I use myself.
r~
Richard Henderson (11):
target/arm: Introduce isar_feature_aa64_bti
target/arm: Add PSTATE.BTYPE
target/arm: Add BT and BTYPE to tb->flags
target/arm: Record the GP bit for a page in MemTxAttrs
target/arm: Default handling of BTYPE during translation
target/arm: Reset btype for direct branches and syscalls
target/arm: Set btype for indirect branches
target/arm: Add guarded_pages cpu property for user-only
target/arm: Enable BTI for -cpu max
linux-user/aarch64: Reset btype for signal handlers
tests/tcg/aarch64: Add bti smoke test
include/exec/memattrs.h | 2 +
target/arm/cpu.h | 22 +++-
target/arm/internals.h | 6 +
target/arm/translate.h | 9 ++
linux-user/aarch64/signal.c | 4 +
target/arm/cpu64.c | 24 ++++
target/arm/helper.c | 28 +++--
target/arm/translate-a64.c | 196 +++++++++++++++++++++++++++++-
tests/tcg/aarch64/bti-1.c | 61 ++++++++++
tests/tcg/aarch64/bti-crt.inc.c | 51 ++++++++
tests/tcg/aarch64/Makefile.target | 7 +-
11 files changed, 399 insertions(+), 11 deletions(-)
create mode 100644 tests/tcg/aarch64/bti-1.c
create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
--
2.17.2
=== Work done during the last week ===
* LLVM-432 (Support arithmetic on FileCheck regex variable): in progress
+ finished cleaning up code
+ rebase on top of trunk
+ fix all issues discovered with check-all
+ add detection of conflict between numeric variable and pattern variable
+ add memory management (yay for shared_ptr)
* GNU-593 (Tied softfloat mul and div): upstream review
+ search for a non-elf arm target
-> none seems supported
* Fix issues with -mslow-flash-data: committed
+ finish testing patch for big endian and respond to upstream comments
* GNU-598 (Do not select hardfloat when targeting Thumb-1 with mfpu
set): upstream review
+ write and test patch, submit upstream
* GNU-597 (pr77904.c test failure): upstream review
+ Investigate whether code added for PR77904 should be kept
+ test and submit patch for external review
=== Plan for week 51 ===
* DSGHACK-25 (Support arithmetic on FileCheck regex variable):
+ extend testcase coverage (add tests for latest syntax change and
add more negative testing)
+ clean up the code written last week
+ improve documentation
* Tied softfloat mul and div:
+ get it committed
* GNU-598 (Do not select hardfloat when targeting Thumb-1 with mfpu set):
+ get it committed
* GNU-597 (pr77904.c test failure):
+ get it committed
* Try to reproduce perf issue mentioned in week #30's weekly report on
latest perf
o 4 days week.
o GNU releases:
* Gave support for 6.5-2018.12-rc1
o LLVM
* Tested and uploaded 7.0.1-rc3 ARM and AArch64 binaries
* Machine Outliner on ARM prototype:
- Fixed a bug in tailcall handling on ARM
- Working on an issue with outlined calls through function pointers
o Misc
* Various meetings and discussions.