Progress:
[VIRT-246 # ARMv8.1-LOR Limited Ordering Regions ]
Merged to target-arm.next.
[VIRT-294 # ARMv8.3-PAuth, Pointer Authentication ]
Posted v2.
Now booting Will's kernel, which properly detects and enables support.
Once that gets to mainline I'll add the prctl to linux-user/.
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ]
Started.
[VIRT-327 # Richard's upstream QEMU work ]
Put the ool softmmu patch set on hold for now, as that is not
clearly ready when development opens again. Rebased all of the
other queued tcg patch sets around that. Generated pull request.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
- QEMU 3.1.0 finally released
- sent out a couple of pull requests
- some easy patches fixing more clang warnings about taking the
address of a member in a packed struct
- read through the Memory Tagging extension specification
(and a bunch of arm-internal meetings etc this week)
thanks
-- PMM
[TCWG-1492] Add timeout and retry to git fetches in Linaro ci infrastructure.
[LLVM-505] LLD implement --pic-veneer for AArch32 linux kernel (pr39886)
In upstream review
[LLVM-509] Add support for v6m range extension thunks to LLD
In upstream review
pr34928 fixed undefined weak reference handling for AArch64
Spent quite a bit of time revisiting cross-compilation of compiler-rt
after helping out on llvm-dev. Posted a review D55709 to improve the
documentation.
Planned Absences
Next 3 weeks on Christmas holiday back Monday 7th January
== Progress ==
GlobalISel support for Thumb2:
# [LLVM-506] G_LOAD, G_STORE
# [LLVM-500] G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR
# [LLVM-516] G_SEXT, G_ZEXT, G_ANYEXT, G_TRUNC
# G_INTTOPTR, G_PTRTOINT
- Committed upstream
# [LLVM-518] Support G_CONSTANT for Thumb
- Started adding tests
== Plan ==
# [LLVM-518] Support G_CONSTANT for Thumb
== Progress ==
* FDPIC
- (GNU-499) GCC: wait for feedback on v4 patches
- (GNU-411) GDB: will try to keep as much as possible in common with frv
* GCC upstream validation:
- reported a few regressions, helped testing some patches
- dealing with some random results, still
- qemu-3.1.0-rc3, memory consumption: no time to really look at the
problem. Unable to match time's figures with LSF's
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. Trying to build an LLVM
toolchain to see how to properly apply my patches: still trying,
thanks to Peter Smith for the support!
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- ran Spec2006 on aarch32 using gcc-8.2 sysroot, on cortex-a57,
results match the
previous ones, so the improvements are only imputable to the compiler.
1 regression on gobmk (created GNU-596 to look at this)
- dealing with nasty ST-internal infrastructure problems
- (GNU-141) noinit/persistent attributes: they are already supported
by GCC for TI msp430. The patches are small, plus one libgloss patch.
- (GNU-592): started improving benchmarking scripts
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Validation:
- isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for
aarch64-linux target
Misc:
GNU-592
[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 6.5-2018.12-rc1
The Linaro Binary Toolchain
============================
The Linaro GCC 6.5-2018.12-rc1 Release-Candidate is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release-candidate packages from:
(sources) http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.5-2018.12-rc1/
(binaries) http://snapshots.linaro.org/components/toolchain/binaries/6.5-2018.12-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and AArch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.5-2018.12-rc1
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.5-2018.12-rc1/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (users/linaro/binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 8.2 (gdb-8.2-branch)
https://lists.gnu.org/archive/html/info-gnu/2018-09/msg00001.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.5-2018.12-rc1)
==================================================
* Runtest and gdbserver are no longer installed in the toolchain bin/
directory. Binary releases no longer include runtest at all, and
gdbserver is a target tool; it is now shipped in the sysroot under
usr/bin/.
LDTS case #2211: gdbserver and runtest in GCC binary release are in
the wrong place or have the wrong name
* Gdbserver is no longer linked statically, because this is currently
unsupported.
Linaro bugzilla #3344: gdbserver broken in Linaro 2017.02
https://bugs.linaro.org/show_bug.cgi?id=3344
* Previous MinGW hosted version of Linaro GCC C preprocessor failed to
convert character set used for string, character constants, etc. This
is fixed in this release.
Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8.
https://bugs.linaro.org/show_bug.cgi?id=3040
* The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code
option to ARMv7-M and ARMv8-M targets. This option ensures functions
are put into sections that contain only code and no data.
* The GDB version was upgraded from GDB 8.1 to 8.2.
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC
6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06, Linaro
GCC 6.4-2017.07, Linaro GCC 6.4-2017.08, Linaro GCC 6.4-2017.09,
Linaro GCC 6.4-2017.10, Linaro GCC 6.4-2018.04 and Linaro GCC
6.5-2018.11.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2018.04/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.5-2018.11/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
Mark Murray Staff Software Engineer | Arm
. . . . . . . . . . . . . . . . . . . . . . . . . . .
p: +44 1223 405082
arm.com <http://www.arm.com>
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
=== Work done during last week ===
* DSGHACK-25 (Support arithmetic on FileCheck regex variable):
+ simplifies how numeric expression are matched and checked, easier
to explain too
+ start code cleanup and increasing testing, ETA: end of next week
* Line management.
=== Plan for week 50 ===
* DSGHACK-25 (Support arithmetic on FileCheck regex variable):
+ extend testcase coverage (add tests for latest syntax change and
add more negative testing)
+ finish cleaning up the code
+ improve documentation
* Try to reproduce perf issue mentioned in week #30's weekly report on
latest perf
* Line management
o 4 days week.
o LLVM
* Machine Outliner on ARM prototype:
- Rebased on upstream Machine Outliner developments
- Still working on LLVM bootstrap failures in ARM mode
o Misc
* Various meetings and discussions.
[VIRT-246 # ARMv8.1-LOR Limited Ordering Regions ]
Posted v3.
[VIRT-294 # ARMv8.3-PAuth, Pointer Authentication ]
Implemented. Posted v1. I can sort of guarantee that it doesn't work in
system mode yet, cause I spotted a bug by eye yesterday.
In the meantime, Peter via Will Deacon added me to the cc list for the in
development kernel patches. I'll review v5 shortly.
r~
Upstream Work ([VIRT-109])
==========================
- reviewed {Qemu-devel} {PATCH for-4.0 v2 00/37} tcg: Assorted
cleanups Message-Id:
<20181123144558.5048-1-richard.henderson(a)linaro.org>
- looked at common part of {Qemu-devel} {PATCH 2 00/39} Windbg
supporting Message-Id:
<154401431697.8440.845616703562380651.stgit(a)Misha-PC.lan02.inno>
- finished review of {PATCH v6 00/13} hardfloat Message-Id:
<20181124235553.17371-1-cota(a)braap.org>
- 2-3x speed-ups for FPU heavy workloads!
- finished prototype of [enabling tcg system tests]
- includes some more userspace tests as well
- just missed posting RFC, will post next week
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[enabling tcg system tests]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v1
Other Tasks
===========
- debugged compiler failures on SynQuacer
- turned out it was dodgy RAM *slot layout* - system now stable
again
- did some bug triage/tagging in QEMU bug database
- update JIRA tickets as per QEMU initiative thread Message-Id:
<87wop4gezg.fsf(a)linaro.org> :todo
Completed Reviews [3/3]
=======================
{PATCH v3 00/16} tcg: Assorted cleanups
Message-Id: <20181130215221.20554-1-richard.henderson(a)linaro.org>
- CLOSING NOTE [2018-12-03 Mon 10:46]
Easier review with the re-org of removal and clean-up patches
{Qemu-devel} {PATCH for-4.0 v2 00/37} tcg: Assorted cleanups
Message-Id: <20181123144558.5048-1-richard.henderson(a)linaro.org>
- CLOSING NOTE [2018-12-03 Mon 10:47]
Got part way through, subset reposted and reviewed. Some questions
remain on the efficiency of ool softmmu w.r.t various
micro-architectures.
{PATCH v6 00/13} hardfloat
Message-Id: <20181124235553.17371-1-cota(a)braap.org>
- CLOSING NOTE [2018-12-05 Wed 12:48]
Looking good. I've proposed myself as another maintainer for FPU
emulation and will handle the pull request once the tree opens.
Absences
========
- Christmas Holidays
- Connect BKK19 (1-5th April 2019)
Current Review Queue
====================
* {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code
Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org>
* {Qemu-arm} {PATCH 00/13} Support disabling TCG on ARM
Message-Id: <20181113165247.4806-1-sameo(a)linux.intel.com>
* {PATCH for-4.0 0/5} tcg/i386: Improve guest_base handling
Message-Id: <20181203160840.15115-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH for-4.0 00/71} qtest: qgraph driver framework
Message-Id: <1543851204-41186-1-git-send-email-pbonzini(a)redhat.com>
* {Qemu-arm} {PATCH v7 00/16} gdbstub: support for the multiprocess extension
Message-Id: <20181123091729.29921-1-luc.michel(a)greensocs.com>
* {PATCH 0/7} Acceptance Tests: basic architecture support
Message-Id: <20181004151429.7232-1-crosa(a)redhat.com>
--
Alex Bennée
[LLVM-499] LLD support for linking the linux kernel
- [LLVM-504] Support for linker script symbol assignment to an alias.
-- Diagnosed problem and made reproducer on PR.
-- Reviewed the upstream patch.
- [LLVM-503] Support for discarding .dynamic, .dynstr and .dynsym
-- Reviewed upstream patch and proposed testcase that is
representative of the kernel use case.
Some revisiting of scripts and advice on how to cross compile clang
libraries. Looks like I have some updates to do to the documentation
for some configurations I haven't tried before.
- 2 days at ARM internal Codegen conference. Really good event,
standard of work was very high, left enthused.
Planned absences:
Christmas Holiday from 17th December to 4th January
== Progress ==
* FDPIC
- GCC: no feedback yet on v4 patches
- GDB: did not decide yet how/if to commonalize with frv code. Asked
for advise on the gdb list.
* GCC upstream validation:
- reported a few regressions, helped testing some patches
- dealing with some random results, still
- trying qemu-3.1.0-rc3, memory consumption problems with
aarch64-linux. LSF reports (cgroup-based) do not seem consistent with
time --verbose.
* GCC:
- rebased ubsan / bare-metal patches. Trying to build an LLVM
toolchain to see how to properly apply my patches
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- ran Spec2006 on aarch32 using gcc-8.2 sysroot, results match the
previous ones, so the improvements are only imputable to the compiler.
- dealing with nasty ST-internal infrastructure problems
- trying to look at noinit/persistent attributes provided by other
toolchains, need a windows machine :(
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Benchmarks:
- collect results
Validation:
- isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for
aarch64-linux target
Progress:
* VIRT-65 [QEMU upstream maintainership]
- release work (we needed an rc4, and then an rc5 due to a
late-breaking security bug)
- wrote a patch which I hope will fix synchronization of system
register state to KVM for a case where QEMU code wants to change
the register values, which it does when QEMU is arranging to inject
an exception into the guest
- catching up on patch review and assembling target-arm.next
ready for when the tree reopens
- some simple patches fixing minor memory leaks spotted by clang LeakSanitizer
- sent a patch for a race condition that meant we would sometimes ignore
a guest-requested system reset or otherwise get confused by it
thanks
-- PMM
== Progress ==
# [LLVM-492] [Thumb GlobalISel] Lower parameters for Thumb functions
- Committed upstream
# [LLVM-500] [Thumb GlobalISel] Support G_ADD, G_SUB, G_MUL
- Started working on this but it became apparent that the existing
tests would be easier to reuse if we had support for G_LOAD first
# [LLVM-506] [Thumb GlobalISel] Support G_LOAD and G_STORE
- Investigated whether we could get TableGen to select G_LOADs and
G_STOREs by porting ComplexPattern
- Unfortunately that is not enough, and even AArch64 has
hand-written code for it in the instruction selector
- Will handle it the ugly way next week
== Plan ==
# LLVM-506, LLVM-500
Greetings,
I’m trying to have the Aarch64 gcc optimize a single function using the O3 optimization in this manner:
void __attribute__ ((optimize ("-O3", "-ftree-vectorize" )))
However, when examining the assembler code, there is no trace of any optimization beyond the project default.
The only way to successfully enforce the optimization is using -O3 in the gcc command line. Then the compiler produces ARM neon instructions.
Do you know any issues regarding function level optimizations and the Aarch64 gcc?
Regards
[Upstream]
Posted a patch set aimed at register allocation vs function calls. It does
reduce code size by a percent or two. Emilio did some benchmarking and found
that it does help a bit, but does not completely eliminate the effect of the
call+ret overhead on the most modern of x86 implementations.
Reviewed v2 of tcg/riscv. Still a lot of work to be done, I think.
Cleanup of all tcg backends vs re-translation, which is no longer a thing.
Cleanup of tcg/i386 vs scratch registers.
[Other]
Updated the mustang to ubuntu 18.10. I was seeing some weirdness
that I'm hoping I can blame on the bionic 4.15 kernel and will be
gone with the cosmic 4.18 kernel. Fingers crossed...
r~
o 4 days week.
o LLVM
* 7.0.1-rc2:
- Miscompare on AArch64:
No luck with Sanitizers enabled, still digging.
* Machine Outliner on ARM prototype:
- Fixed Pic code issue.
- llvm bootstrap in thumb mode gives 4% code size reduction.
- Investigating new issues
o Misc
* Various meetings and discussions.
=== Work done during the past 2 weeks ===
* GNU-296 (Fix stack protector on ARM): committed!
* LLVM-432 (Support arithmetic on FileCheck regex variable):
+ finished reworking parsing code to be separate from evaluation and support
more complex expression
+ fix compile errors and bugs found when running tests added to check feature
* Write patch to diagnose error when compiling Armv8-M Baseline CMSE
code with -mfpu
-> as unintended consequence, needs rewrite
* Wrote and committed patch to improve comments for some data structure in ld
* Misc:
+ various meeting about my departure from Arm & Linaro
=== Plan for week 49 ===
LLVM-432 (Support arithmetic on FileCheck regex variable):
+ extend testcase coverage (add tests for latest syntax change and
add more negative testing)
+ clean up the code
+ improve documentation
* Try to reproduce perf issue mentioned in week #30's weekly report on
latest perf
* Line management:
+ continue progress on rotations
== Progress ==
* FDPIC
- GCC: no feedback yet on v4 patches
- GDB: started looking at the patches, some parts are very similar to
FRV, maybe worth commonalization.
* GCC upstream validation:
- reported a few regressions, helped testing some patches
- dealing with some random results, still
- trying qemu-3.1.0-rc1, memory consumption problems with
aarch64-linux. Could not properly test cortex-m0 support yet, because
building gcc --with-cpu=cortex-m0 currently fails.
* GCC:
- bug report on aarch64 about misaligned accesses. I do not have
access to LHG gerrit, Maxim will look at isolating the problem.
- rebased ubsan / bare-metal patches. Really need to look at how to
merge them into LLVM
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- ran Spec2006 on aarch64 using gcc-8.2 sysroot, results match the
previous ones, so the improvements are only imputable to the compiler.
Started the same experiment on aarch32
- some Jira/goals discussions
- dealing with nasty ST-internal infrastructure problems
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Benchmarks:
- collect results
Validation:
- isolate why qemu-3.1.0-rc1 consumes much more memory for aarch64-linux target
Progress:
* VIRT-65 [QEMU upstream maintainership]
- release work (it is looking like we'll need an rc4 next week)
- worked out some patches which hopefully will fix running
QEMU on OSX Mojave (testing still required)
- code review
- sent a cleanup patchset that removes the load_image()
function (which is not possible to use safely and which we
marked as deprecated way back in 2008!)
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
- implemented test case which demonstrates that we incorrectly share
translated code between heterogenous CPUs and behave wrongly as a
result (using the existing xlnx-zcu102 board)
thanks
-- PMM
[LLVM-493] LLD link failure on KASLR for AArch64 Linux kernel
The linux kernel can build in an ASLR mode that is currently causing LLD
some problems. There are a few oddities in the kernel that aren't quite
right but there are some problems in LLD that need resolving as well. has
been a couple of interesting days trying to work out why some strange
options have been used.
[LLVM-484] LLD combination of dynamic relocs into a single section
Committed upstream
[LLVM-486] Error if user code defines _GLOBAL_OFFSET_TABLE_
Committed upstream
[LLVM-489] Measure (cross) linking of performance of LLD on Chrome
Performance of linking AArch64 matches X86, roughly twice as fast as
ld.gold and five times faster than ld.bfd.
[TCWG-1492] Investigated why git-clone and git-fetch might hang/deadlock.
Back up might be to put a timeout/retry.
[Other]
Submitted LLVM team goals for the TCWG team
Wrote up how TCWG use Jenkins and CI, now in Confluence.
Planned Absences:
ARM internal Compiler conference 4th/5th December
Christmas holiday 17th December - 4th January
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- reviewed Emilio's {RFC 00/48} Plugin support Message-Id:
<20181025172057.20414-1-cota(a)braap.org>
- looks like a good basis for going forward if we can work out the
kinks
- port my example tools to his framework :todo
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- did a quick pass at [enabling system tests in check-tcg]
- started reviewing {Qemu-devel} {PATCH for-4.0 v2 00/37} tcg:
Assorted cleanups Message-Id:
<20181123144558.5048-1-richard.henderson(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[enabling system tests in check-tcg]
https://github.com/stsquad/qemu/tree/tests/enable-system-tests
Testing and CI
==============
[VIRT-2] https://projects.linaro.org/browse/VIRT-2
KVM CI Loop ([VIRT-2])
- The [LKFT team] are working with gregkh to ensure -stable is tested
for KVM regressions
- wrote up the State of testing for KVM Message-Id:
<874lc14194.fsf(a)linaro.org>
- look at example regression to see what would have caught the failure
:todo
- look at kselftest and understand it's place :todo
[VIRT-2] https://projects.linaro.org/browse/VIRT-2
[LKFT team] https://lkft.linaro.org/
Other Tasks
===========
- need to concluded actions from The QEMU initiative thread
Message-Id: <87wop4gezg.fsf(a)linaro.org> :todo
Completed Reviews [2/2]
=======================
{RFC 00/48} Plugin support
Message-Id: <20181025172057.20414-1-cota(a)braap.org>
- CLOSING NOTE [2018-11-28 Wed 14:13]
Hashed out a number of things. Emilio will look at a single-pass
option and it makes things easier or not. It was also suggested we
could move instruction fetch to helpers outside of the individual
front-ends to keep the plugin call points in the core translator and
avoid having to tweak each front-end for support. A number of
pre-requisites were discussed including some de-macrofication work
to make the code easier to follow and instrument.
{PATCH 0/4} xxhash patches for 4.0
Message-Id: <20181123230206.12629-1-cota(a)braap.org>
- CLOSING NOTE [2018-11-28 Wed 15:09]
Clean-up to xxhash to match original and handle expanded hashes
Absences
========
- Christmas Holidays
- Connect BKK19 (1-5th April 2019)
Current Review Queue
====================
* {Qemu-devel} {PATCH for-4.0 v2 00/37} tcg: Assorted cleanups
Message-Id: <20181123144558.5048-1-richard.henderson(a)linaro.org>
* {PATCH v6 00/13} hardfloat
Message-Id: <20181124235553.17371-1-cota(a)braap.org>
* {Qemu-arm} {PATCH v7 00/16} gdbstub: support for the multiprocess extension
Message-Id: <20181123091729.29921-1-luc.michel(a)greensocs.com>
* {Qemu-arm} {PATCH 00/13} Support disabling TCG on ARM
Message-Id: <20181113165247.4806-1-sameo(a)linux.intel.com>
* {PATCH 0/7} Acceptance Tests: basic architecture support
Message-Id: <20181004151429.7232-1-crosa(a)redhat.com>
* {PATCH v7 00/19} Fixing record/replay and adding reverse debugging
Message-Id: <20181010133333.24538.53169.stgit@pasha-VirtualBox>
--
Alex Bennée
o 4 days week.
o LLVM
* 7.0.1-rc2:
- Miscompare on AArch64 is related to host compiler, still digging.
* Machine Outliner on ARM prototype:
- IR Outliner experiments:
Commented upstream, and reducing problematic test case.
o Misc
* Various meetings and discussions.
Four day week (Happy Thanksgiving, all you Europeans)
[Upstream]
Posted patches making bswap during qemu_ld/st optional. The prompt was
reviewing the tcg/riscv/ patch set, but I've wanted to do this for ages.
This should avoid the need for reservation of scratch registers on some hosts
that can ill afford it -- in particular i386 and aa32.
In the process I ran into two other places that x86 used those scratch
registers: stores from non-q-registers and bsd-user.
I included patches for both of those (freebsd only; net/openbsd will work so
long as guest_base == 0 and will abort at runtime otherwise).
I still need to audit the other hosts before dropping the call-clobbering from
user-only within tcg.c.
r~
== Progress ==
* FDPIC
- Cortex-M uClibc-ng patch merged
- GCC: no feedback yet on v4 patches
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, again
- trying qemu-3.1.0-rc1, maybe some memory consumption problems, tbc
* GCC:
- bug report on aarch64 about misaligned accesses. I do not have
access to LHG gerrit, Maxim will look at isolating the problem.
- rebased ubsan / bare-metal patches. Really need to look at how to
merge them into LLVM
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- ran Spec2006 using gcc-8.2 sysroot, to avoid differences caused by
glibc versions. Fortran benchmarks could not run when compiled with
gcc-5/gcc-6 because libgfortran changed .so version compared to gcc-8.
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- uclibc-ng: look at how to test fdpic mode with openadk
Benchmarks:
- collect results
Validation:
- check if qemu-3.1.0-rc1 is OK for my GCC validations
[LLVM-486] Error id user defines _GLOBAL_OFFSET_TABLE_ (upstream review)
[LLVM-484] Fix linker script dynamic relocations combination into a single
output section (upstream review)
[LLVM-483] cortex-a53 erratum fix interaction with TLS relaxation (upstream
review)
[LLVM-489] Measure (cross) linking performance of LLD for AArch64 and Arm.
Looking for large projects that I can build for Arm and AArch64
- Firefox seems to have some ARM Android cross build support but it does
not appear to be working too well.
- Chrome can cross build to ARM and AArch64 Android. Have been able to
build AArch64 so far.
Notably both projects don't support building natively on AArch64, there are
quite a few build dependencies for which only x86 support is available.
Raised Jira tickets for recent PRs fixed
2019 Planning
- Drafted objectives document for LLVM team
- Drafted some Jira suggestions for TCWG
QEMU Tooling ([VIRT-252])
=========================
[VIRT-252] https://projects.linaro.org/browse/VIRT-252
QEMU plugin support ([VIRT-280])
- continued reviewing Emilio's {RFC 00/48} Plugin support Message-Id:
<20181025172057.20414-1-cota(a)braap.org>
- port my example tools to his framework :todo
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- finished reviewing {RFC PATCH v2 00/23} KVM: arm64: Initial support
for SVE guests Message-Id:
<1538141967-15375-1-git-send-email-Dave.Martin(a)arm.com>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other Tasks
===========
- started The QEMU initiative thread Message-Id:
<87wop4gezg.fsf(a)linaro.org> for JIRA discussion
Completed Reviews [3/3]
=======================
{RFC PATCH v2 00/23} KVM: arm64: Initial support for SVE guests
Message-Id: <1538141967-15375-1-git-send-email-Dave.Martin(a)arm.com>
- CLOSING NOTE [2018-11-22 Thu 15:36]
My only major concern is if the query API is too gold plated.
{RFC PATCH 0/2} docker: Add gentoo-mipsr5900el-cross image
Message-Id: <20181118203312.5376-1-f4bug(a)amsat.org>
{PATCH} docker: dockerfile for openSUSE Leap
Message-Id: <87k1lai2vo.fsf(a)linaro.org>
Absences
========
- Christmas Holidays
- Connect BKK19 (1-5th April 2019)
Current Review Queue
====================
* {RFC 00/48} Plugin support
Message-Id: <20181025172057.20414-1-cota(a)braap.org>
* {Qemu-devel} {PATCH for-4.0 v2 00/37} tcg: Assorted cleanups
Message-Id: <20181123144558.5048-1-richard.henderson(a)linaro.org>
* {Qemu-arm} {PATCH v5 00/16} gdbstub: support for the multiprocess extension
Message-Id: <20181110081147.4027-1-luc.michel(a)greensocs.com>
* {Qemu-arm} {PATCH 00/13} Support disabling TCG on ARM
Message-Id: <20181113165247.4806-1-sameo(a)linux.intel.com>
* {PATCH 0/7} Acceptance Tests: basic architecture support
Message-Id: <20181004151429.7232-1-crosa(a)redhat.com>
* {PATCH v7 00/19} Fixing record/replay and adding reverse debugging
Message-Id: <20181010133333.24538.53169.stgit@pasha-VirtualBox>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
- release work
- code review
- sent patch fixing Coverity issue in Xen PCI device passthrough
(this was our last outstanding issue with no patch on the list!)
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
- some initial investigation of what changes are going to be needed
for heterogenous-cpu support in QEMU
- started on a test case using the existing xnlx-zcu102 board (which
has a heterogenous config that works only by accident)
thanks
-- PMM
== Progress ==
# Monday off
# [LLVM-479] Check current status of GlobalISel
- Looked into new patterns that can be selected by TableGen and
forked LLVM-481 and LLVM-482 out of that
- Ran a test-suite and a selfhost with GlobalISel and had a look at
the fallbacks
# [LLVM-481] [ARM GlobalISel] Test BFC
- Committed upstream
# [LLVM-482] [ARM GlobalISel] Enable CLZ
- Most of the work is done, ready to commit next week
== Plan ==
Wrap up LLVM-482 and LLVM-479
Fork more stories out of LLVM-479
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2018.11 snapshot of Linaro GCC 6 source package.
o This Linaro GCC 6 snapshot[1] is based on FSF GCC 6.5+svn265890 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot will be part of the final maintenance release,
as the upstream GCC 6 branch is at the end of its maintenance lifespan.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.5-2018.11/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn265890
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Mark Murray Staff Software Engineer | Arm
. . . . . . . . . . . . . . . . . . . . . . . . . . .
p: +44 1223 405082
arm.com <http://www.arm.com>
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
o 4 days week.
o LLVM
* 7.0.1-rc2:
- Uploaded ARM and AArch64 binaries
- Investigating miscompare on AArch64
* Machine Outliner on ARM prototype:
- IR Outliner experiment gave interesting code size reduction
o Misc
* Various meetings and discussions.
* CI patch reviews
Three day week.
[GNU-180 # Fix gcov crash on program exit]
Fiddled around with TI-RTOS for a while before I realized that was sort of
beside the point. Gave the reporter a method do avoid dumping during the
global destructors. Still need to look into where the reported stack space
problem might be.
[Upstream]
Out-of-line softmmu patches got some work. Added ppc64 support. Fixed a race
and a code removal crash. Emilio verified -5% aa64 boot+shutdown time, but it
performed less well on spec2006.
Reviewed risc-v host patch set.
r~
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- started reviewing Emilio's {RFC 00/48} Plugin support Message-Id:
<20181025172057.20414-1-cota(a)braap.org>
- port my example tools to his framework :todo
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- started looking at {RFC PATCH v2 00/23} KVM: arm64: Initial support
for SVE guests Message-Id:
<1538141967-15375-1-git-send-email-Dave.Martin(a)arm.com>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other Tasks
===========
- [Video for KVM Forum QEMU status report] is up
- the rest of the [sessions are here]
- posted {PULL for 3.1 0/2} Testing tweaks Message-Id:
<20181114131008.27599-1-alex.bennee(a)linaro.org>
[Video for KVM Forum QEMU status report]
https://www.youtube.com/watch?v=GZBd3jt5iA8
[sessions are here]
https://www.youtube.com/channel/UCRCSQmAOh7yzgheq-emy1xA/videos
Completed Reviews [3/3]
=======================
{PATCH} tests/tcg/multiarch: fix 32bit linux-test on 64bit host
Message-Id: <20181113175437.26492-1-laurent(a)vivier.eu>
{Qemu-devel} {PATCH} hax: Support for Linux hosts
Message-Id: <20181114130428.32326-1-asanchez(a)kryptoslogic.com>
{Qemu-devel} {PATCH} target: hax: replace g_malloc with g_malloc0
Message-Id: <1542261954-4060-1-git-send-email-liq3ea(a)gmail.com>
Absences
========
- Christmas Holidays
- Connect BKK19 (1-5th April 2019)
Current Review Queue
====================
* {RFC PATCH v2 00/23} KVM: arm64: Initial support for SVE guests
Message-Id: <1538141967-15375-1-git-send-email-Dave.Martin(a)arm.com>
* {Qemu-arm} {PATCH v5 0/4} target/arm: KVM vs ARMISARegisters
Message-Id: <20181113180154.17903-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH for-4.0 00/17} tcg: Move softmmu out-of-line
Message-Id: <20181112214503.22941-1-richard.henderson(a)linaro.org>
* {Qemu-arm} {PATCH 00/13} Support disabling TCG on ARM
Message-Id: <20181113165247.4806-1-sameo(a)linux.intel.com>
* {Qemu-devel} {PATCH for-4.0 00/17} tcg: Move softmmu out-of-line
Message-Id: <20181112214503.22941-1-richard.henderson(a)linaro.org>
* {Qemu-arm} {PATCH v5 00/16} gdbstub: support for the multiprocess extension
Message-Id: <20181110081147.4027-1-luc.michel(a)greensocs.com>
--
Alex Bennée
LLD bug fixing and triage
pr39678 Calculation of DT_PLTRELSZ with strange linker script.
pr39662 Request to add more emulations
pr39634 LTO and references from inline symbols
D54474 Fix for incorrect relocation span out of ifunc review
D54624 Redefinition of _GLOBAL_OFFSET_TABLE_
=== Work done during the past 2 weeks ===
* Resurrect code size optimization for fmul/dmul from Tony Wang: bootstraping
+ rework slightly to better deal with switch of section and deal with
several possible section layout
+ start anew with a new approach based on symbol visibility
-> works without -gc-sections and does not rely on section layout
* Fix -mslow-flash-data: ready to upstream on Monday
+ some more cleanup and code improvement
* LLVM-432 (Support arithmetic on FileCheck regex variable):
+ started reworking parsing code to be separate from evaluation and support
more complex expression
* Infrastructure code review
=== Plan for week 47 ===
* LLVM-432 (Support arithmetic on FileCheck regex variable):
+ extend testcase coverage (add tests for latest syntax change and
add more negative testing)
+ finish cleaning up the code
* Try to reproduce perf issue mentioned in week #30's weekly report on
latest perf
* Line management.
Progress:
* VIRT-251 [AArch32 Hyp/running microvisors]
- fixes to the issues running L4Re/Fiasco have now been committed
to QEMU master for the 3.1 release
- some minor remaining missing functionality not needed for these guests
has been recorded as subtasks of VIRT-65
- this Epic is now closed!
* VIRT-65 [QEMU upstream maintainership]
- release work
- looked again at automation of uploads to the Coverity Scan service
(last try was last year); sent out revised patchset
- code review:
+ "sbsa reference board" model
+ LOR, HPD, AA32HPD extension support (rth)
+ Minimize TLB flushing for ASID changes (rth)
+ Support for loading uboot "noload" uimage files
+ better PMUv3 emulation
+ micro:bit SoC device models
thanks
-- PMM
== Progress ==
* FDPIC
- Cortex-M uClibc-ng patch still pending
- GCC: updated patches and sent v4
Tried to isolate the regressions observed on xtensa uclinux
toolchain with my patches.
Built a qemu-system-arm -based platform to run tests involving the
kernel. Built and ran a few LTP tests.
Unfortunately, LTP has dropped/is dropping support for uclinux
configs, for lack of interest
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, again
* GCC:
- bug report on aarch64 about misaligned accesses. Waiting for more
details to reproduce the problem.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- uclibc-ng: look at how to test fdpic mode with openadk
== Progress ==
* Catch up on things
- Remind myself what a laptop looks like, install updates etc etc
- Figure out new links, machines etc
- Clean up inbox
* [LLVM-59] Small changes to the LLVM helper scripts
- Had a look at all the remaining issues and closed them as obsolete
or already implemented
* [LLVM-479] Check current status of GlobalISel
- Read the mailing list to see what I’ve missed
- Started looking at the code
- Trying to run the test-suite on a TK1
* Misc
- Fixed a simple buildbot breakage
- Meetings
== Plans ==
* LLVM-479
== This Week ==
* GNU-405: Implement division using vrecpe/vrecps (1/10)
- Committed patch
* SVE ACLE (2/10)
- Continue work on shift intrinsics
* PR83750 (1/10)
- Addressing upstream comments
* Holidays (6/10)
- Diwali festival
== Next Week ==
- Continue working on SVE ACLE and PR83750
o 4 days week.
o LLVM
* 7.0.1-rc2:
- Built ARM and AArch64 binaries
- Investigating miscompare on AArch64
* Machine Outliner on ARM prototype:
- Investigating issues in PIC mode
- Testing IR Outliner
o Misc
* Various meetings and discussions.
[VIRT-241 # QEMU ARMv8.x support ]
The new ARM ARM was released (DDI0487 D_a) including ARMv8.4.
Add jira cards for all of the v8.4 features. Rearrange all of
the stories into a hierarchy so that it's easier to track which
cards belong to which architecture revision.
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Working my way through this rather large extension:
* Cleanup (most) direct uses of hcr_el2.
* Add new hypervisor virtual timer.
* Add contextidr_el2 and use it in breakpoint matching.
* Add system register aliasing and redirection.
* Added a new mmu_idx for the NS EL2&0 regime;
working through all the places that should be handled.
[Upstream]
Posted kvm-vs-idregs patch set v3.
r~
== Progress ==
* FDPIC
- Cortex-M uClibc-ng patch still pending
- GCC: handling feedback on v3 patches.
Managed to build/check xtensa uclinux toolchain with my patches.
Largely better, but a few new failures.
- working on kernel + qemu-system env to run more tests. Got help from
Nicolas Pitre.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, again
* GCC:
- bug report on aarch64 about misaligned accesses. Waiting for more
details to reproduce the problem.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
== Next ==
FDPIC:
- GCC: followup v3 patches
- uclibc-ng: look at how to test fdpic mode with openadk
- use qemu-system mode to run more tests
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review
+ more microbit device models
+ some raspi device model improvements
- sent patches for more Coverity issue fixes
- put together a list of source files still with legacy
non-QOM device models (about 60 files total)
- tagged QEMU 3.1.0 rc0
* VIRT-251 [aarch32 Hyp/running microvisors]
- tracked down a regression affecting L4Re guest: we had
misimplemented HCR.{VI,VF}. Sent patchset reverting the
broken version and implementing the correct semantics.
- finally tracked down why the 32-bit version of L4Re/Fiasco was
crashing -- we were incorrectly implementing Hyp mode as having
a banked r14, but it shares that register with User and System modes.
- These patches fix all the known issues with these guests.
thanks
-- PMM
=== Work done during the past week ===
* Resurrect code size optimization for fmul/dmul from Tony Wang:
+ clean up new testsuite directive andd testcases
* Fix -mslow-flash-data:
+ resurrect / rebase Arm internal patch to fix -mslow-flash-data
once and for all
+ many fixes to make it pass all testsuite with -mslow-flash-data without ICE
* Line management.
=== Plan for week 45 ===
* LLVM-432 (Support arithmetic on FileCheck regex variable):
+ extend testcase coverage (add tests for latest syntax change and
add more negative testing)
+ finish cleaning up the code
* Try to reproduce perf issue mentioned in week #30's weekly report on
latest perf
o Two days off.
o LLVM
* Machine Outliner on ARM prototype:
- catch-up after vacation
- re-based prototype branch on upstream
- Investigating issues in PIC mode
== This Week ==
* PR83750: CSE erf/erfc pair (6/10)
- Submitted patch upstream
* SVE ACLE (2/10)
- Started working on shift intrinsics
* GNU-235 (1/10)
- Cancelled card after I realized vrp does not support floating point ranges -:/
* Misc (1/10)
- Meetings
== Next Week ==
- PR83750: Address upstream comments
- GNU-405: Benchmark patch to provide more evidence to make it acceptable.
- SVE ACLE: Continue work on shift intrinsics.