- linaro-toolchain - lists.linaro.org

[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.5-2017.10-rc1

by Mark Murray

[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.5-2017.10-rc1 The Linaro Binary Toolchain ============================ The Linaro GCC 5.5-2017.10-rc1 Release-Candidate is now available. Notice: All Linaro GCC 5 series toolchain users should migrate to the latest version of the Linaro GCC 5 toolchain in order to mitigate potential security exposure to CVE-2015-7547. See the NEWS section below for details. Download release-candidate packages from: (sources) http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.5-2017.10-rc1/ (binaries) http://snapshots.linaro.org/components/toolchain/binaries/5.5-2017.10-rc1/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 5.5-2017.10-rc1 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.5-2017.10-rc1/ Linaro glibc 2.21 (linaro/2.21) https://lists.gnu.org/archive/html/info-gnu/2015-02/msg00001.html Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch) https://sourceware.org/ml/newlib/2013/msg01128.html Linaro binutils 2.25 (linaro_binutils-2_25-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… FSF GDB 7.12 (gdb-7.12-branch) https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 5 (as of Linaro GCC 5.5-2017.10-rc1) ================================================== * Include GCC fix for Linaro bugzilla #2575: ICE: declaration and definition of function with __attribute__((target("thumb"))) and inlined assembler, with debug symbols enabled https://bugs.linaro.org/show_bug.cgi?id=2575 * Include GCC fix for Linaro bugzilla #2575: Internal compiler error using -mtune=cortex-a57.cortex-a53. https://bugs.linaro.org/show_bug.cgi?id=2785 * The soft-float targeted toolchains have now been configured to generate code using -mfloat-abi=soft. This makes arm-linux-gnueabi and armeb-linux-gnueabi toolchains use the “soft” FP ABI instead of “softfp”. Historically, TCWG’s toolchains provided both “soft” and “softfp” multilibs, but when switching from crosstool-ng to cbuildv2/abe (which support a single multilib) “softfp” multilib was choosen. Using “-mfloat-abi=soft” is a better choice for a gnueabi toolchain, since it doesn’t require cores to have a floating-point unit. This change should not break compatibility for toolchain users since the ABI will stay the same. The compiler and glibc libraries will not refernce FP instructions. * Include GCC fix for Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of strong when called through pointer https://bugs.linaro.org/show_bug.cgi?id=2562 * Include GCC fix for Linaro bugzilla #1925: [regression] FAIL: libgomp.fortran/retval1.f90 -O1 execution test https://bugs.linaro.org/show_bug.cgi?id=1925 * Include GCC fix for Linaro bugzilla #2185: aarch64-linux-gnu-g++ internal compiler error: in curr_insn_transform https://bugs.linaro.org/show_bug.cgi?id=2185 * Backported glibc patch to simplify static malloc interposition [BZ #20432] to correct user identified issue. commit 058b5a41d56b9a8860dede14d97dd443792d064b Author: Florian Weimer Date: Fri Aug 26 22:40:27 2016 +0200 malloc: Simplify static malloc interposition [BZ #20432] * Host binaries for x86_64 linux hosts now have symbols and debug information stripped in order to reduce the size of the toolchain binary archives. This reduces the archive size from 1.1G to 580M for aarch64-linux-gnu target with the gcc-5-branch. * Removed .la files from binary toolchain archive as these files break autotools builds. https://bugs.linaro.org/show_bug.cgi?id=2764 * The mingw toolchains are now archived using the rsync -L option in order to avoid problems with Windows extractors and symbolic links. https://review.linaro.org/#/c/16415/ This resolves the following user bugs: https://bugs.linaro.org/show_bug.cgi?id=2684 https://bugs.linaro.org/show_bug.cgi?id=2192 https://bugs.linaro.org/show_bug.cgi?id=2762 * Copy the libwinpthread DLL into the bin directories so it gets into the tmp directory before tar is run. https://review.linaro.org/#/c/13723/ * Increment binutils release date to 2016_02 to reflect the most recent commit: commit ef90a4718f535cbe6345b4e7168baea7b1972abf Author: Matthew Wahab <matthew.wahab(a)arm.com> Date: Tue Jan 12 16:35:30 2016 +0000 [ARM] Support ARMv8.2 RAS extension. * Baremetal sysroot names now contain 'newlib' rather than 'glibc'. * Manifests now contain relative paths rather than absolute paths. * Now generating proper manifest files. * Fixed pi requeue support in glibc 2.21 while allowing the existing 2.21 minimum kernel default setting. This was checked into the linaro/2.21/master branch. commit a68cafa11c500d8a49a3014c43c5152859d037ae Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Tue May 17 10:16:39 2016 -0300 Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463) commit 6e5cb616b5b442ce8b2664ad673c0acf42a490ac Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Mon May 16 19:01:10 2016 -0300 Remove __ASSUME_SET_ROBUST_LIST commit 9ac61c0047295696cbcdbc26bdc174c7bd25a3c8 Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Mon May 16 10:35:25 2016 -0300 Remove __ASSUME_FUTEX_LOCK_PI * Backported support into GCC for Cortex-A32, Cortex-A35, and Cortex-R8. * Applied fix for CVE-2015-7547 - A stack-based buffer overflow in glibc's getaddrinfo() was corrected in glibc 2.23 and backported into glibc 2.21. https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html * ARMv8.1 Instruction Support - ARMv8.1 instructions support was checked into GCC and binutils. It has been backported into Linaro GCC 5.3 and Linaro binutils 2.25. * Backported -Bsymbolic-functions into Linaro binutils 2.25. * Performance related backports from Linaro GCC 5.2-2015.11, Linaro GCC 5.2-2015.12, and Linaro GCC 5.3-2016.01-1, Linaro GCC 5.3-2016.02, Linaro GCC 5.3-2016.03, Linaro GCC 5.3-2016.04, Linaro GCC 5.4-2016.06, Linaro GCC 5.4-2016.10, Linaro GCC 5.4-2016.12, Linaro GCC 5.4-2017.02, GCC 5.4-2017.04 and Linaro GCC 5.5-2017.10 have been included. See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.03 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.04 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.06 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.10 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.12 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2017.02 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2017.04 http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.5-2017.10 Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org

8 years, 1 month

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Does Linaro GCC 5.4 fully support ARMv8.2-A

by Vincent Chen

Hi, We are evaluating LInaro GCC5.4 readiness for ARMv8.2-A extension support but can't find direct answer if all the features has been supported/backported. Can you point me to the answer? Thanks, Vincent ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. -----------------------------------------------------------------------------------

8 years, 1 month

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[ACTIVITY] Week 42

by Yvan Roux

== Progress == o Linaro GCC/Validation * Releases handover - Monthly snapshots for GCC 6 and 7 deployed - GCC 5 final release handled by Mark * Branch merge done * Tarball and release ready to be deployed * RC1 planned for w43 o LLVM * Continue ramp-up * Working on upstream bug 32999: [ARM] Missed vpadd combine opportunity o Misc * Various meetings and discussions. == Plan == o Continue release handover and LLVM ramp-up

8 years, 1 month

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[ACTIVITY] 16 - 20 October 2017

by Prathamesh Kulkarni

== This Week == * TCWG-1234 (4/10) - Patch inhibits if-conversion for couple of tests. * TCWG-1253 (3/10) - Fixed regressions with the patch * Took Monday off for recovering from travel (2/10) * Misc (1/10) - Meetings == Next Week == - TCWG-1234, TCWG-1253, TCWG-319

8 years, 1 month

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[ACTIVITY] Oct. 16 -- Oct 20

by Yao Qi

# Progress # * TCWG-1040, [4/10] Update my patches to remove the last use of MAX_REGISTER_SIZE. Before I send them upstream, I find some bits that I can improve, but finally, many things are changed. Need to get them in shape, and think about the design again. * TCWG-1125, [4/10] ARMv8 tagged address support in GDB. GDB/GDBserver needs to remove the top one byte of virtual address before pass it to kernel. Patch v1 was reviewed, and GDB internal caching needs updated for tagged address, because tagged address and non-tagged address should be mapped to the same cache entry in GDB. * GDB flexible target description conversion [1/10] Finished the conversion for tic6x and nios2. To be posted. * ILP32 GDB branch. [1/10] Got Steve Ellcey's patches, one bfd patch and one gdb patch. No GDBserver patches. Will create branch with them. # Plan # * ILP32 GDB branch. * ARMv8 tagged address support in GDB. * Update my patches to remove the last use of MAX_REGISTER_SIZE. -- Yao Qi

8 years, 1 month

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[ACTIVITY] 16-20 October 2017

by Christophe Lyon

== Progress == * GCC - FDPIC: started reading docs - testsuite cleanup * GCC upstream validation: - reported 2 bugs in qemu-armeb - noise reduction: polishing dejagnu local patches - since ubsan merge with upstream, validation of arm targets is now much longer (typically 1h30 to 6h), leading to timeouts most of the time * Infrastructure: - improved GCC bisect job/scripts - updated ABE to allow overriding cpu/fpu/tune/arch etc... * misc (conf-calls, meetings, emails, ....) == Next == * GCC upstream validation * GCC/ubsan * GCC/FDPIC

8 years, 1 month

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[ANNOUNCE] Linaro GCC 6 and 7 2017.10 source snapshots

by Mark Murray

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.10 snapshot of Linaro GCC 6 and 7 source packages. o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 For an explanation of the changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn253626 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2017.11 stable[2] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 7.2+svn253626 o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn253668 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the next maintenance release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 6.4+svn253668 o Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed. [2]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

8 years, 1 month

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[ACTIVITY] Week 41

by Yvan Roux

== Progress == o Linaro GCC/Validation * Continue releases handover - Branch merges done - Monthly snapshots about to be deployed o LLVM * Jira cards review * Checked/updated cards related to upstream BZ * Continue ramp-up o Misc * Various meetings and discussions. == Plan == o Continue release handover and LLVM ramp-up

8 years, 1 month

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[ACTIVITY] 9 - 13 October 2017

by Prathamesh Kulkarni

== This Week == * TCWG-1234 (5/10) - Posted analysis upstream with a test-case. - Have a workaround that disables hoisting when only single stmt is to be hoisted. - Investigating solution to limit distance between hoisted def. and it's uses. * TCWG-1005 (2/10) - Did changes based on upstream feedback from Honza, validated patch. - Waiting for final approval from Honza before committing. * Sick leave (2/10) * Misc (1/10) - Meetings == Next Week == - TCWG-1234, TCWG-1005

8 years, 1 month

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[ACTIVITY] 9-13 October 2017

by Christophe Lyon

== Progress == * GCC - sent final patch for deprecated IT blocks - updated PR 71233 (missing AdvSIMD intrinsics) * GCC upstream validation: - reported a couple of regressions/new failures, found bugs in qemu (need to report them) - noise reduction: will report randomly killed processes as "untested" making it easier to ignore them - buildbot discussion * Infrastructure: - improved GCC bisect job/scripts * misc (conf-calls, meetings, emails, ....) - Connect feedback (internal) == Next == * GCC upstream validation * GCC/ubsan

8 years, 2 months

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[ACTIVITY] Week 40

by Yvan Roux

* One day off after Connect == Progress == o Linaro GCC/Validation * Handover releases to ARM on-going. o LLVM * Continue ramp-up o Misc * Various meetings and discussions. * Debrief Connect inside ST == Plan == o Continue release handover o LLVM Jira card: cleanup and find first tasks to do

8 years, 2 months

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[ACTIVITY] 2nd Oct - 6th Oct 2017

by Prathamesh Kulkarni

== This Week == * TCWG-1234: code-hoisting regression (3/10) - Have a workaround that fixes the particular regression (but may introduce another) - Trying to cross build benchmarks - Investigating PRE and code-hoisting optimizations * TCWG-1005: malloc attr propagation (3/10) - Iteration based on upstream feedback. * TCWG-1253 (1/10) - Committed patch last week to add patterns for div and cmp against 0. - Patch to transform rshift and cmp against 0 to cmp between operands in upstream review. * Public Holiday (2/10) * Misc (1/10) - Meetings == Next Week == - TCWG-1234, TCWG-1005

8 years, 2 months

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[ACTIVITY] 25 September-6 October 2017

by Christophe Lyon

== Connect == * Various discussions on GNU toolchain roadmap == Progress == * GCC - committed fix for PR71727 (strict-align bug on aarch64), backported to gcc-7-branch - small fixes in the testsuite * GCC upstream validation: - problems with internal infrastructure, but validation results OK - reported a couple of regressions/new failures - ran validations for a couple of tentative patches - noise reduction: looking at how to report randomly killed processes * misc (conf-calls, meetings, emails, ....) - Connect feedback (internal) == Next == * GCC upstream validation * GCC/ubsan * GCC/deprecated-IT blocks

8 years, 2 months

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[ACTIVITY] 02-06 Oct 2017

by Yao Qi

# Progress # * GDB SVE patches review. [4/10] Finished my patches to remove the last use of MAX_REGISTER_SIZE. Send them to Alan to review. * GDB flexible target description follow-up. [4/10] Committed some patches to improve GDB build, so that we can easily share code of target description between GDB and GDBserver. Done. * File Linaro Connect expense, and misc. [2/10] # Plan # * On holiday, Mon - Thu. * Either GDB target description work,or ILP32 GDB branch. -- Yao Qi

8 years, 2 months

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Re: GCC generates unaligend memory access code

by Christophe Lyon

On 24 July 2017 at 18:38, Christophe Lyon <christophe.lyon(a)linaro.org> wrote: > > > Le 24 juil. 2017 18:30, "Ard Biesheuvel" <ard.biesheuvel(a)linaro.org> a écrit > : > > On 18 July 2017 at 13:54, Christophe Lyon <christophe.lyon(a)linaro.org> > wrote: >> On 13 July 2017 at 13:50, Christophe Lyon <christophe.lyon(a)linaro.org> >> wrote: >>> On 12 July 2017 at 19:33, Ard Biesheuvel <ard.biesheuvel(a)linaro.org> >>> wrote: >>>> On 12 July 2017 at 18:27, Alexei Fedorov <Alexei.Fedorov(a)arm.com> wrote: >>>>> >>>>> Christophe, Leif, Ard, Ryan at al. >>>>> >>>>> >>>>> We are observing unaligned memory access fault with UEFI code compiled >>>>> by >>>>> Linaro GCC 6.3.1 & 7.1.1 using -O3 optimisation option. >>>>> >>>>> The fault occures at the very early stage of UEFI boot with MMU not >>>>> being >>>>> enabled yet. >>>>> >>>>> The failing function is CalculateSum8() from >>>>> edk2\MdePkg\Library\BaseLib\CheckSum.c: >>>>> >>>>> >>>>> UINT8 >>>>> EFIAPI >>>>> CalculateSum8 ( >>>>> IN CONST UINT8 *Buffer, >>>>> IN UINTN Length >>>>> ) >>>>> { >>>>> UINT8 Sum; >>>>> UINTN Count; >>>>> >>>>> ASSERT (Buffer != NULL); >>>>> ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1)); >>>>> >>>>> for (Sum = 0, Count = 0; Count < Length; Count++) { >>>>> Sum = (UINT8) (Sum + *(Buffer + Count)); >>>>> } >>>>> >>>>> return Sum; >>>>> } >>>>> >>>>> & the instruction which causes the exception is "ldr q1, [x1], 16" >>>>> which >>>>> accesses Buffer = 0xE0000048 pointed by X1 register, see the part of >>>>> generated assembly code: >>>>> >>>>> >>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:49: for (Sum = 0, Count >>>>> = 0; >>>>> Count < Length; Count++) { >>>>> .loc 1 49 0 is_stmt 1 >>>>> cbz x19, .L10 // Length, >>>>> .L4: >>>>> sub x0, x19, #1 // tmp150, Length, >>>>> cmp x0, 14 // tmp150, >>>>> bls .L11 //, >>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:42: { >>>>> .loc 1 42 0 >>>>> movi v0.4s, 0 // vect_Sum_19.24 >>>>> lsr x2, x19, 4 // bnd.18, Length, >>>>> mov x1, x20 // ivtmp.29, Buffer >>>>> mov x0, 0 // ivtmp.28, >>>>> .LVL4: >>>>> .p2align 3 >>>>> .L7: >>>>> // r:\edk2\MdePkg\Library\BaseLib\CheckSum.c:50: Sum = (UINT8) (Sum >>>>> + >>>>> *(Buffer + Count)); >>>>> .loc 1 50 0 discriminator 3 >>>>> ldr q1, [x1], 16 // vect__6.23, MEM[(const UINT8 >>>>> *)vectp_Buffer.21_38] >>>>> add x0, x0, 1 // ivtmp.28, ivtmp.28, >>>>> cmp x0, x2 // ivtmp.28, bnd.18 >>>>> add v0.16b, v0.16b, v1.16b // vect_Sum_19.24, vect_Sum_19.24, >>>>> vect__6.23 >>>>> bcc .L7 //, >>>>> >>>>> ... >>>>> >>>>> Although all AARCH64 code is compiled with "-mstrict-align" option >>>>> which >>>>> according to GCC 3.18.1 AArch64 Options: >>>>> >>>>> "-mstrict-align >>>>> >>>>> Avoid generating memory accesses that may not be aligned on a natural >>>>> object >>>>> boundary as described in the architecture specification." >>>>> >>>>> >>>>> the generated code doesn't comply with this description. In this case >>>>> X1 = >>>>> Buffer @0xE0000048 and is not aligned to 16 bytes boundary. >>>>> >>>>> The similiar code is generated by GCC 6.3.1-2017.05 but 5.3.1-2016.05 >>>>> compiler produces only 16 bytes aligned memory accesses when loading Q1 >>>>> register. >>>>> >>>>> >>>>> I attached the simple test file which can be compiled by running GCC >>>>> compilation with >>>>> >>>>> -c test.c -O3 -mstrict-align -save-temps >>>>> >>>>> to see the difference between code generated by 7.1.1 & 5.3.1 GCC >>>>> versions. >>>>> >>>>> It seems that 5.3.1 ignores "-mstrict-align" option at all and always >>>>> generates aligned pointers for loading Q1 register, 7.1.1 & 6.3.1 also >>>>> ignore the option but generate slighly different code with unaligned >>>>> access >>>>> enabled. >>>>> >>>>> >>>>> Please share your thoughts regading this issue. >>>>> >>>> >>>> Hello Alexei, >>>> >>>> This does look like a compiler bug to me. 'Buffer' is a pointer to >>>> unsigned char, and so the compiler should never emit the ldr >>>> instruction under -mstrict-align. >>>> >>>> In the mean time, we could work around this with adding >>>> -mgeneral-regs-only in all places where -mstrict-align is being >>>> passed. In general, I don't really see the point of supporting the use >>>> of FP/ASIMD registers in UEFI beyond ensuring that our builds are >>>> compatible with 3rd party binaries that do use them. >>>> >>> >>> Hello Alexei, >>> >>> I agree with Ard: it looks like a compiler bug, I'm looking at it. >>> >>> And indeed in the mean time, using -mgeneral-regs-only should >>> workaround your problem. >>> >> >> Hello, >> >> As a follow-up, I've posted a patch: >> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01063.html >> >> We'll see if maintainers agree. >> > > Thanks. By the looks of it, nobody cared to respond, right? > > > Not yet and we are used to slow response. > > In addition I'm on holidays until Aug 21st so I won't ping until then. > > Hi all, My patch was finally accepted last week and committed. I also backported it to the gcc-7-branch, so that the problem will be fixed in the next gcc-7 release (either FSF or Linaro). Thanks, Christophe

8 years, 2 months

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[ACTIVITY] 18-22 September, 2017

by Christophe Lyon

== Progress == * GCC upstream validation: - PR82120: experimenting with -mbranch-cost option - still working on further reducing false alams (catching killed processes) - problems with internal infrastructure * GCC - investigating portability of ubsan to bare-metal targets - 'ARMv8 deprecated IT blocks' followup patch ongoing * misc (conf-calls, meetings, emails, ....) == Next == * Connect

8 years, 2 months

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[ACTIVITY] Sep 18th -- Sep 22nd

by Yao Qi

# Progress # * Flexible GDB target description work. [5/10] As we'll add more and more files, need to clean up GDB build first. Patch is OK, but need to reduce the duplication first. Yet another clean up. Start to think about the design of removing last usage of MAX_REGISTER_SIZE. Still ongoing. * Misc, [5/10] ** File cauldron expense. ** Improve gdb_mbuild.sh to build GDB for different supported targets. # Plan # * Connect. -- Yao Qi

8 years, 2 months

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[ACTIVITY] Week 37

by Yvan Roux

== Progress == o Linaro GCC/Validation * Completed backports and branch merges * Delivered 7.2 and 6.4 monthly source snapshots * Reviewed infra patches * Still some patches pending on upstream reviews o LLVM * Still learning o Misc * Various meetings and discussions. == Plan == o Close remaining GCC tasks

8 years, 2 months

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[ACTIVITY] Sep 04th -- Sep 15th

by Yao Qi

Two weeks * GNU Cauldron and vacation, [12/20] # Progress # * TCWG-1159, New design of GDB/GDBserver target description. [4/20] Commit my patches, and fix some build failures. Done. * Cauldron presentation and Linaro Connect SFO17 presentation. [3/20] Done. * Misc, catch up email, [1/20] # Plan # * Prepare a prototype about regcache, and compare with Alan's implementation. * Continue my target description work, for other non-actively-maintained target descriptions. -- Yao Qi

8 years, 3 months

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[ACTIVITY] 11-15 September 2017

by Christophe Lyon

== Progress == * Infrastructure: - patch reviews * Benchmarking: - minor bug fixes * Snapshots/releases - branch merge reviews * GCC upstream validation: - PR82120: adding a -mbranch-cost option to the arm backend does not help with pr81588.c test failing on cortex-a5 - incorrectly reported a regression due to bisect problems (worth 100% chocolate ;-) - still working on further reducing false alams - problems with internal infrastructure * binutils/gdb upstream validation: - gdbserver build fixed by Yao * GCC - investigating portability of ubsan to bare-metal targets - 'ARMv8 deprecated IT blocks' patch finally committed. Will look at the remaining warnings. * misc (conf-calls, meetings, emails, ....) - Connect preparation (slides, ...) == Next == * GCC upstream validation * GCC/ubsan * GCC/deprecated-IT blocks

8 years, 3 months

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[ANNOUNCE] Linaro GCC 6 and 7 2017.09 source snapshots

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.09 snapshot of Linaro GCC 6 and 7 source packages. o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 For an explanation of the changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn252337 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2017.11 stable[2] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.09/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 7.2+svn252337 * Backports from mainline: - Backport of [Bugfix] [AArch32] PR target/77308 surprisingly large stack usage for sha512 on arm - Backport of [AArch32] Fix ldrd offsets - Backport of [AArch32] Remove %? string from some Advanced SIMD patterns - Backport of [AArch64] Add optimized implementation of mersenne twister - Backport of [AArch64] Add RDMA support to falkor port - Backport of [AArch64] Fix big endian float immediate moves - Backport of [AArch64] Fix missing optimization for CMP+AND - Backport of [AArch64] Fix pattern guard relaxations that are allowing more constants than they should - Backport of [AArch64] Fix ThunderX fp vectorizer cost model - Backport of [AArch64] Generate MLA when multiply + add vector by scalar - Backport of [AArch64] Implement ALU_BRANCH fusion - Backport of [AArch64] Improve aarch64 conditional compare usage - Backport of [AArch64] Improve thunderx_vect_cost some more - Backport of [AArch64] Move the check for any_condjump_p from sched-deps to target macros - Backport of [AArch64] Only allow 0s unconditionally for floating point values - Backport of [AArch64] Optimize float immediate moves-HF/DF/SF mode - Backport of [AArch64] Optimize float immediate moves-infrastructure - Backport of [AArch64] Optimize float immediate moves-testsuite - Backport of [AArch64] Optimize integer immediate moves with partial masks - Backport of [Tesstuite] Fix dg-require-stack-check - Backport of [Testsuite] [AArch32] Add -mfloat-abi=hard to arm_neon_ok - Backport of [Testsuite] [AArch64] Fix dbl_mov_immediate_1.c test - Backport of [Testsuite] [AArch64] gcc.target/aarch64/ccmp_2.c: New test - Backport of [Cleanup] [AArch32] PR target/68535 arm.c: 5 * set but not used - Backport of [Doc] [AArch64] Clean up AArch64 options o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn252072 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the next maintenance release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.09/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 6.4+svn252072 o Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed. [2]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

8 years, 3 months

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[ANNOUNCE] Linaro Binary ILP32 Preview Toolchain

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce our first preview-grade ILP32 binary cross-toolchain. Linaro is supporting AArch64 community effort to introduce ILP32 ABI for AArch64 Linux, and TCWG will be providing preview-grade ILP32 binary cross-toolchains alongside our normal release candidates. These toolchains will be built using community-supported branches for ILP32 ABI of Linux kernel and Glibc. This first delivery is based on Linaro GCC 7.1-2017.08-rc1 sources and available at: http://snapshots.linaro.org/components/toolchain/binaries/7.1-2017.08-rc1/a… Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org

8 years, 3 months

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[ACTIVITY] 4-8 September 2017

by Christophe Lyon

== Progress == * Infrastructure: - patch reviews * Benchmarking: - more experiments to reduce noise. - board reboot + several iterations + use of only 1 core seems to give manageable results, at the expense of execution time - old 'deprecated IT blocks' patch benchmarked again with this setup, seems ok * GCC upstream validation: - further reduced noise ("random" pass/failures) - reported a few regressions, looking at improving some testcases related to branch-cost on arm * binutils/gdb upstream validation: - gdbserver build broken on trusty, sent an email to Yao * GCC - investigating portability of ubsan to bare-metal targets * misc (conf-calls, meetings, emails, ....) == Next == * Benchmarking * GCC upstream validation * GCC/ubsan

8 years, 3 months

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[ACTIVITY] Week 36

by Yvan Roux

== Progress == o Linaro GCC/Validation * Working on release process * Reviewed infra patches * Still some patches pending on upstream reviews o LLVM * Familiarizing with LLVM environment o Misc * Various meetings and discussions. * Booked everything for SFO17 == Plan == o Backports for 2017.09 snapshot

8 years, 3 months

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[ACTIVITY] Week 35

by Yvan Roux

* 3 days off == Progress == o Linaro GCC/Validation * Investigating upstream bugzilla PR81863 * Other patches are still pending on upstream reviews * Working on release process o Misc * Various meetings and discussions. == Plan == o PR81863, ...

8 years, 3 months

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[ACTIVITY] 28 August - 1st September 2017

by Prathamesh Kulkarni

== This Week == * Type promotion (6/10) - Benchmarking on ARM and AArch64 - Experimenting with pass order to reduce redundancies - Preparing the patch to send upstream * PR78809 (2/10) - Prototype patch done - Working through testsuite fallout * PR78736 (1/10) - Iteration on upstream feedback. Waiting for approval from Fortran maintainers for libgfortran changes * Misc (1/10) - Submitted https://review.linaro.org/#/c/21111/ - Meetings == This Week == - Submit patch fo type promotion upstream. - GNU Cauldron 2017

8 years, 3 months

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[ACTIVITY] Aug 21st -- Sep 01st

by Yao Qi

Status of two weeks. * Bank holiday on Monday and I am off on Tue and Wed. [6/20] # Progress # * TCWG-1159, New design of GDB/GDBserver target description. [4/20] Post my target description v4 patches. They should be ready to check in, however, I am sidetracked by GNU Cauldron presentation. * Cauldron presentation. [5/20] Write the presentation for my target description work above. Ongoing. latex+beamer+tikz is quite powerful to make presentation. * My Linaro Connect SFO17 presentation is accepted. Need to write it in google doc later. * Review Alan H.'s patches. [2/20] * Misc [3/20] # Plan # * Finish my Cauldron presentation, * Commit my target description v4 patches, if time allows, * Off on Wed, and fly to Prague. Back to office on 14th Sep. -- Yao Qi

8 years, 3 months

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Re: [hpc-sig-devel] GCC extensions for `hcqc'

by Kugan Vivekanandarajah

Hi, On 26 August 2017 at 18:10, Pinski, Andrew <Andrew.Pinski(a)cavium.com> wrote: >> However there might be pushback from upstream maintainers as this makes the structure bigger >> by adding a field. This could have implications for memory usage of the compiler. > > I looked into the structure, adding this field is not going to make the structure bigger for either ILP32 or LP64 targets. If you want, you use bit-fields; there is one bool already there which means you can fit 8 bits in the same area as currently taken up by that one. Yes. I should have checked the mem_attrs structure. This does have at least a byte left unlike some other tightly packed structures (gimple and some tree structures in gcc). Thanks, Kugan >> Alternatively, we maybe able to get this info from dwarf info when we compile with -g ? > > I doubt you can. He wants to know if an instruction is a spill location. The location of a variable might be recorded in -g (if it was an user variable) but not that does present the data for all temps being spilled. > > I think the patch is actually a good one in general just needs some cleanup. > > As for these comments: >>> For example, GCC calls `output_asm_insn' directly from the `define_insn' >>> definition in the aarch64.md file without an insn object(`output_asm_insn' >>> calls `output_asm_operand_names'). >>> This occurs in "*cb<optab><mode>1" and >>> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult". > > Spills in GCC will always be via the mov* patterns (they are special). > Now really *aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult should be fixed for a different reason; it does unneeded work. The fix would be something like (untested): > { > operands[2] = GEN_INT (aarch64_fpconst_pow_of_2 (operands[2])); > return "fcvtz<su>\t%<GPI:w>0, %<GPF:s>1, %2"; > } > > Thanks, > Andrew > > > -----Original Message----- > From: linaro-toolchain [mailto:linaro-toolchain-bounces@lists.linaro.org] On Behalf Of Kugan Vivekanandarajah > Sent: Saturday, August 26, 2017 12:40 AM > To: Renato Golin <renato.golin(a)linaro.org> > Cc: Jim Wilson <jim.wilson(a)linaro.org>; hpc-sig-devel(a)linaro.org; Linaro Toolchain <linaro-toolchain(a)lists.linaro.org> > Subject: Re: [hpc-sig-devel] GCC extensions for `hcqc' > > Hi, > > On 26 August 2017 at 04:04, Renato Golin <renato.golin(a)linaro.org> wrote: >> +linaro-toolchain, hoping to get more eyes into it. >> >> cheers, >> --renato >> >> On 25 August 2017 at 17:59, Masaki Arai <masaki.arai(a)linaro.org> wrote: >>> Hi, >>> >>> I extended GCC 7.1(or GCC 7.2) for `hcqc'. >>> I would be grateful if you could give me a comment about whether this >>> extension is acceptable and whether this extension should be pushed >>> upstream. > > I think this is a useful info. However there might be pushback from upstream maintainers as this makes the structure bigger by adding a field. This could have implications for memory usage of the compiler. > Alternatively, we maybe able to get this info from dwarf info when we compile with -g ? Jim may have some input here (cc ing him). > > Thanks, > Kugan > >>> >>> The extended GCC's output using the option ` -fverbose-asm' is as >>> follows: >>> >>> ldr w0, [x29,48] // tmp433, j(8-byte Folded Spill) >>> ^^^^^^^^^^^^^^^^^^^ This >>> code shows that this instruction accesses a memory area for spill >>> codes. >>> I made the following changes to GCC 7.1(or GCC 7.2). >>> The related files are under `hcqc/patch/gcc-7.1.0-add'. >>> >>> (1) rtl.h >>> >>> I added flag information to `struct mem_attrs' that means whether it >>> is a spill memory area or not. >>> >>> + >>> + /* True if the MEM is for spill. */ >>> + bool for_spill_p; >>> >>> Also, I added an access macro for this additional field. >>> >>> + /* For a MEM rtx, true if its MEM is for spill. */ #define >>> + MEM_FOR_SPILL_P(RTX) (get_mem_attrs (RTX)->for_spill_p) >>> + >>> >>> (2) emit-rtl.c >>> >>> I added a code to turn on flags for spill memory area in function >>> `set_mem_attrs_for_spill'. >>> >>> + attrs.for_spill_p = true; >>> >>> (3) final.c >>> >>> I added code to print that information in function >>> `output_asm_operand_names' >>> if the memory is a spill memory area, >>> >>> + >>> + if (MEM_P (op) && MEM_FOR_SPILL_P (op)) >>> + { >>> + HOST_WIDE_INT size = MEM_SIZE (op); >>> + fprintf (asm_out_file, " (" HOST_WIDE_INT_PRINT_DEC "-byte >>> + Folded >>> Spill)", size); >>> + } >>> >>> The above changes are implemented similarly as Clang/LLVM. >>> Unfortunately, it is difficult for GCC to print the above "(?-byte >>> Folded Spill)" >>> for memory access instructions only in the same manner as Clang/LLVM. >>> The reason is that GCC executes the above `output_asm_operand_names' >>> even in situations where any instruction object(insn) does not exist >>> when outputting assembly code. >>> For example, GCC calls `output_asm_insn' directly from the `define_insn' >>> definition in the aarch64.md file without an insn object(`output_asm_insn' >>> calls `output_asm_operand_names'). >>> This occurs in "*cb<optab><mode>1" and >>> "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult". >>> >>> From this fact, `hcqc' extracts and accumulates memory access >>> instructions from the assembly code with the comment "(?-byte Folded >>> Spill)". >>> >>> The above extensions are commonly available on almost any architecture. >>> Also, these extensions do not affect the execution of the resulting >>> assembly code since additional outputs are only in comments. >>> >>> Best regards, >>> -- >>> -------------------------------------- >>> Masaki Arai >>> >> _______________________________________________ >> linaro-toolchain mailing list >> linaro-toolchain(a)lists.linaro.org >> https://lists.linaro.org/mailman/listinfo/linaro-toolchain > _______________________________________________ > linaro-toolchain mailing list > linaro-toolchain(a)lists.linaro.org > https://lists.linaro.org/mailman/listinfo/linaro-toolchain

8 years, 3 months

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[ACTIVITY] Week 34

by Yvan Roux

== Progress == o Linaro GCC/Validation * Delivered monthly source snapshots * Released GCC 6 and 7 2017.08 binary releases * Completed PR 80287: - Added new testcase on trunk and GCC 7 branch. - Fix backported on gcc-6-branch. * Investigating upstream bugzilla PR81863 * Other patches are still pending on upstream reviews o Misc * Various meetings and discussions. == Plan == o Off until Aug 31th o PR81863, ...

8 years, 3 months

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[ANNOUNCE] Linaro Binary Toolchain Release GCC 7.1-2017.08

by Yvan Roux

The Linaro Binary Toolchain ============================ The Linaro GCC 7.1-2017.08 Release is now available. *Notice*: GCC 7.1 ABI change for arm*-*-* targets, and note for aarch64*-*-* targets >From GCC 7.1 release notes: On ARM targets (arm*-*-*), a bug introduced in GCC 5 that affects conformance to the procedure call standard (AAPCS) has been fixed. The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. This is an ABI change. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 GCC 5 and GCC 6 releases will continue to be affected by the ABI bug, since changing ABI in these releases is not practical. A warning enabled by -Wpsabi option was added to GCC 5 and GCC 6 toolchains to diagnose codebases that might be affected by the ABI bug. Additionally, this same bug was present in AArch64 backend in development versions of GCC 7. There was no releases of GCC with this bug present in AArch64 backend, therefore the release notes does not mention this. However, be advised that any code bases built with development versions of GCC 7 need to be recompiled with released version of GCC 7 to conform to ABI. For an explanation of GCC 7 series changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html For help in porting to GCC 7 please see the following explanation: https://gcc.gnu.org/gcc-7/porting_to.html Download release packages from: (sources) http://releases.linaro.org/components/toolchain/gcc-linaro/7.1-2017.08/ (binaries) http://releases.linaro.org/components/toolchain/binaries/7.1-2017.08/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 7.1-2017.08 http://releases.linaro.org/components/toolchain/gcc-linaro/7.1-2017.08/ FSF glibc 2.25 (release/2.25) https://lists.gnu.org/archive/html/info-gnu/2017-02/msg00002.html Newlib 2.5 (newlib-2_5_0 tag) https://sourceware.org/ml/newlib/2016/msg01191.html GNU Binutils 2.28 (linaro-local/linaro_binutils-2_28-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… FSF GDB 8.0 (gdb-8.0-branch) https://sourceware.org/ml/gdb-announce/2017/msg00003.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 7 (as of Linaro GCC 7.1-2017.08) ============================================== * The Linaro GCC 7.1-2017.07 snapshot added prefetching configuration improvement for AArch64 targets and laid groundwork to enabling prefetching in more cases. * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * Performance related backports from the following snapshots have been included: Linaro GCC 7.1-2017.05, Linaro GCC 7.1-2017.06 and Linaro GCC 7.1-2017.07. See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.05/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.07/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org

8 years, 3 months

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[ANNOUNCE] Linaro Binary Toolchain Release GCC 6.4-2017.08

by Yvan Roux

The Linaro Binary Toolchain ============================ The Linaro GCC 6.4-2017.08 Release is now available. The GCC 6 Release series has significant changes from the GCC 5 release series. For an explanation of the changes please see the following website: https://gcc.gnu.org/gcc-6/changes.html For help in porting to GCC 6 please see the following explanation: https://gcc.gnu.org/gcc-6/porting_to.html Download release packages from: (sources) http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/ (binaries) http://releases.linaro.org/components/toolchain/binaries/6.4-2017.08/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 6.4-2017.08 http://releases.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/ Linaro glibc 2.23 (linaro/2.23/master) https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html Linaro newlib 2.4-2016.03 (linaro_2.4-branch) https://sourceware.org/ml/newlib/2016/msg00370.html Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… Linaro GDB 8.0 (gdb-8.0-branch) https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 6 (as of Linaro GCC 6.4-2017.08) ============================================== * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code option to ARMv7-M and ARMv8-M targets. This option ensures functions are put into sections that contain only code and no data. * The GDB version was upgraded from GDB 8.0. * Previous versions of the Linaro GCC 6 toolchain, when -static -E/—dynamic-list are passed to the linker, might create executables with dynamic sections which aren’t supported by run-time. This was exhibited in Perf Tools build system and has been fixed upstream and backported into Linaro Binutils 2.27 branch. Linaro bugzilla #2926 : Perf tools compiled statically for AArch64 with Linaro release 6.1 and later ones was not statically linked. https://bugs.linaro.org/show_bug.cgi?id=2926 * The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS, exception handling, …) and these have been incorporated into this release. * Previous versions of the Linaro GCC 6 toolchain were incorrectly generating floating-point code for soft-float Linux targets (arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection until recently because the soft-float targeted toolchains were configured to use general-purpose registers for passing floating-point values (which is what you would expect for soft-float toolchains) and the intra-routine floating-code was not noticed. The issue would only show up on targets that were run on hardware that truly didn't have floating-point hardware where the kernel did not trap and emulate floating-point routines. This has been solved in Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using --with-float=soft) to generate code without any floating-point instructions at all (-mfloat-abi=soft). https://review.linaro.org/#/c/16968/2 This change should not break compatibility between existing binaries compiled with these toolchains since the float-point parameter passing ABI is still the same. * A bug/regression in the compiler has been identified whereby the target function that is invoked when calling a "weak" function directly is the "strong" override, whereas when calling the function via a pointer the "weak" implementation is used. This would be noticed as inconsistent function invocation when invoking directly vs. invoking via function pointer. This issue only affected 32-bit arm targets. This regression has been fixed upstream and backported into Linaro GCC 6.3-2017.02-rc2. GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function instead of strong when called through pointer. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253 Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of strong when called through pointer https://bugs.linaro.org/show_bug.cgi?id=2562 * MS Windows does not support symlinks and the MS Windows archive extractor does not properly deep copy the symlink target files/directories into the symlinked directory structure when unpacking the toolchain archive. This causes problems with missing dependencies when using the Linaro mingw toolchains, as identified in the following bugs: https://bugs.linaro.org/show_bug.cgi?id=2684 https://bugs.linaro.org/show_bug.cgi?id=2192 https://bugs.linaro.org/show_bug.cgi?id=2762 This has been solved by copying files rather than using symlinks when the mingw targetted toolchain archives are created. https://review.linaro.org/#/c/16415/ * Users of Linaro's toolchain have encountered problems when building projects with Autotools (specifically libtool): https://bugs.linaro.org/show_bug.cgi?id=2764 The Linaro binary toolchain release contained files with a .la suffix as artifacts of the toolchain build process. These .la files are helper files for libtool, but unlike a gcc install tree, they are not position independent and contain full paths. Since these artifacts contain absolute paths they can actually mislead user invocation of libtool into not finding required libraries (because they reference the build tree, not the install location) and hence breaking Autotools builds. These *.la file artifacts have been removed from Linaro toolchain binaries because they are unnecessary for users. * The Linaro GCC 6.3-2017.01 snapshot added further enablement for ARMv8-M and these have been incorporated into this release. * Compiling and statically linking some SPEC2006int tests against tcmalloc have been failing due to a problem with glibc's memory allocator function overrides. This was fixed upstream: https://sourceware.org/bugzilla/show_bug.cgi?id=20432 Backported into Linaro glibc 2.23: commit 058b5a41d56b9a8860dede14d97dd443792d064b Author: Florian Weimer <fweimer(a)redhat.com> Date: Fri Aug 26 22:40:27 2016 +0200 malloc: Simplify static malloc interposition [BZ #20432] * Host binaries for x86_64 linux hosts now have symbols and debug information stripped in order to reduce the size of the toolchain binary archives. This reduces the archive size from 1.5G to 600M for aarch64-linux-gnu target with the gcc-6-branch. * The GDB version was upgraded from GDB 7.11 in the Linaro GCC 6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release. * The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2 and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes merged from FSF GCC 6.2. This is available in the binary toolchain as of Linaro GCC 6.2-2016.11. * Basic tuning support for the Qualcomm qdf24xx was added to the Linaro GCC 6.2-2016.10 snapshot and is available in the binary toolchain as of Linaro GCC 6.2-2016.11. * IFUNC was disabled for baremetal targets, as it was causing test-suite failures, and is presently a Linux only feature. * The gold linker was added to this binary release. * Backported malloc_lock fix into Linaro newlib 2.4. commit 2665915cfc46aa6403bb2efd473c523d3167e0cb Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com> Date: Thu Jun 16 12:23:51 2016 +0100 Re-enable malloc_lock for newlib-nano * Backported rawmemchr patch into Linaro newlib 2.4. commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5 Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com> Date: Thu May 12 16:16:58 2016 +0000 Add rawmemchr * Backported strlen fix when using Thumb-2 and -Os -marm into Linaro newlib 2.4. commit 5c02bcc086a96b174e1b9e1445a4a1770070107a Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com> Date: Wed May 11 17:18:48 2016 -0400 Fix strlen using Thumb-2 with -Os -marm * Backported fix for semihosting ARM when heapinfo not provided by debugger into Linaro newlib 2.4. commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7 Author: David Hoover <spm2(a)dangerous.li> Date: Thu Apr 21 07:12:24 2016 +0200 Fixed semihosting for ARM when heapinfo not provided by debugger. * Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23. * Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch. commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Tue May 17 10:16:39 2016 -0300 Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463) * Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23 branch. commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1 Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Mon May 16 19:01:10 2016 -0300 Remove __ASSUME_SET_ROBUST_LIST * Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23 branch. commit e48b4e7fed0de06dd7832ead48bea8ebc813a204 Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Mon May 16 10:35:25 2016 -0300 Remove __ASSUME_FUTEX_LOCK_PI * Merged latest FSF binutils-2_27-branch into linaro_binutils-2_27-branch. * The libwinpthread DLL is now copied into the host bin directory to satisfy mingw package dependencies. * Backported GNU Linker fix. commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59 Author: Nick Clifton <nickc(a)redhat.com> Date: Tue Aug 23 09:45:11 2016 +0100 Fix seg-fault in ARM linker when trying to parse a binary file. * Backported GNU Assembler fix for PR 20364 commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd Author: Nick Clifton <nickc(a)redhat.com> Date: Fri Aug 5 10:37:57 2016 +0100 Fix the generation of alignment frags in code sections for AArch64. https://sourceware.org/bugzilla/show_bug.cgi?id=20364 * Performance related backports from the following snapshots have been included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC 6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01, Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC 6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06 and Linaro GCC 6.4-2017.07 . See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org

8 years, 3 months

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[ACTIVITY] 21 - 25 August 2017

by Prathamesh Kulkarni

== This Week == * Type promotion (4/10) - Looking at perf regressions on ppc64 - Enabling at -O2 with vrp removes some perf regressions - Did benchmarking for code-size - Issues with benchmarking for performance * PR78809 (2/10) - WIP patch * PR78736 (1/10) - Updated patch based on upstream feedback * Public Holiday (2/10) * Misc (1/10) - Meetings == Next Week == - type-promotion, PR78736, PR78809

8 years, 3 months

1
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Re: [hpc-sig-devel] GCC extensions for `hcqc'

by Renato Golin

+linaro-toolchain, hoping to get more eyes into it. cheers, --renato On 25 August 2017 at 17:59, Masaki Arai <masaki.arai(a)linaro.org> wrote: > Hi, > > I extended GCC 7.1(or GCC 7.2) for `hcqc'. > I would be grateful if you could give me a comment about whether > this extension is acceptable and whether this extension should be > pushed upstream. > > The extended GCC's output using the option ` -fverbose-asm' is > as follows: > > ldr w0, [x29,48] // tmp433, j(8-byte Folded Spill) > ^^^^^^^^^^^^^^^^^^^ > This code shows that this instruction accesses a memory area > for spill codes. > I made the following changes to GCC 7.1(or GCC 7.2). > The related files are under `hcqc/patch/gcc-7.1.0-add'. > > (1) rtl.h > > I added flag information to `struct mem_attrs' that means whether > it is a spill memory area or not. > > + > + /* True if the MEM is for spill. */ > + bool for_spill_p; > > Also, I added an access macro for this additional field. > > + /* For a MEM rtx, true if its MEM is for spill. */ > + #define MEM_FOR_SPILL_P(RTX) (get_mem_attrs (RTX)->for_spill_p) > + > > (2) emit-rtl.c > > I added a code to turn on flags for spill memory area in function > `set_mem_attrs_for_spill'. > > + attrs.for_spill_p = true; > > (3) final.c > > I added code to print that information in function > `output_asm_operand_names' > if the memory is a spill memory area, > > + > + if (MEM_P (op) && MEM_FOR_SPILL_P (op)) > + { > + HOST_WIDE_INT size = MEM_SIZE (op); > + fprintf (asm_out_file, " (" HOST_WIDE_INT_PRINT_DEC "-byte Folded > Spill)", size); > + } > > The above changes are implemented similarly as Clang/LLVM. > Unfortunately, it is difficult for GCC to print the above "(?-byte Folded > Spill)" > for memory access instructions only in the same manner as Clang/LLVM. > The reason is that GCC executes the above `output_asm_operand_names' > even in situations where any instruction object(insn) does not exist when > outputting assembly code. > For example, GCC calls `output_asm_insn' directly from the `define_insn' > definition in the aarch64.md file without an insn object(`output_asm_insn' > calls `output_asm_operand_names'). > This occurs in "*cb<optab><mode>1" and > "*aarch64_fcvt<su_optab><GPF:mode><GPI:mode>2_mult". > > From this fact, `hcqc' extracts and accumulates memory access > instructions from the assembly code with the comment "(?-byte Folded > Spill)". > > The above extensions are commonly available on almost any architecture. > Also, these extensions do not affect the execution of the resulting assembly > code since additional outputs are only in comments. > > Best regards, > -- > -------------------------------------- > Masaki Arai >

8 years, 3 months

2
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[ANNOUNCE] Linaro GCC 6 and 7 2017.08 source snapshots

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.08 snapshot of Linaro GCC 6 and 7 source packages. o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 For an explanation of the changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.2+svn251138 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2017.11 stable[2] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.08/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 7.2+svn251138 * Backports from mainline: - [Bugfix] [AArch32] PR target/79665: Improve Cortex-A53 shift bypass - [Bugfix] PR lto/69866 lto1: internal compiler error: in add_symbol_to_partition_1, at lto/lto-partition.c:158 - [AArch32] Improve Cortex-A53 FP scheduler - [AArch64] Add rcpc extension - [AArch64] Do not increase data alignment at -Os and with -fconserve-stack. - [AArch64] Emit SIMD moves as mov - [AArch64] Enable software prefetching (-fprefetch-loop-arrays) for ThunderX 88xxx - [AArch64] Fix atomic_cmp_exchange_zero_reg_1.c with +lse - [AArch64] Fix failing lrint inline tests on bare-metal - [AArch64] Fix ILP32 memory access - [AArch64] Improve/correct ThunderX 1 cost model for Arith_shift - [AArch64] Improve dup pattern - [AArch64] Inline calls to lrint when possible - [AArch64] Literal vector construction through vcombine is poor - [Misc] Fold (A / (1 << B)) to (A >> B) - [Testsuite] [AArch32] Allow arm_arch_*_ok to test several macros - [Testsuite] [AArch32] Make gcc.target/arm/its.c more robust - [Testsuite] [AArch32] Require arm_arch_v8a_ok for sdiv_costs_1.c - [Testsuite] [AArch32] sdiv_costs_1.c: Disable on softfloat - [Testsuite] [AArch32] sdiv_costs_1.c: Require arm_v8_vfp_ok - [Testsuite] [AArch32] sdiv_costs_1.c: Use dg-add-options - [Cleanup] [AArch64] Rearrange the processors in aarch64-cores.def - [Cleanup] Update comment about is_leaf - [Doc] [AArch64] Document RcPc extension o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn251111 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the next maintenance release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 6.4+svn251111 o Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed. [2]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

8 years, 3 months

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[ACTIVITY] 14 - 18 Aug

by Yao Qi

* Mon - Wed off [6/10] # Progress # * TCWG-1159,New design of GDB/GDBserver target description. [3/10] Commit another three patches, about GDBserver unit tests. Rebase patches, and prepare series v4. * Misc, [1/10] # Plan # * TCWG-1162, triage the aarch64-elf GDB test result with QEMU. * TCWG-1159, rebase my GDB target description patches, and post v4. -- Yao Qi

8 years, 3 months

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[ACTIVITY] Week 33

by Yvan Roux

== Progress == o Linaro GCC/Validation * Completed 6.4 and 7.2 branch merges * Snapshots delayed due to gerrit config upgrade issues * Investigating upstream bugzilla PR81863 * Other patches are still pending on upstream reviews o Misc * Various meetings and discussions. == Plan == o Complete monthly snapshot and binary releases o PR81863, ...

8 years, 3 months

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[ACTIVITY] 14 - 18 August 2017

by Prathamesh Kulkarni

== This Week == * type promotion (7/10) - Refactored patch - Resolved all functional regressions on arm, aarch64, ppc64. * PR78809 (1/10) * Misc (2/10) - pinged patches for malloc propagation and PR78736 - Public holiday == Next Week == - Validation and Benchmarking of type-promotion pass - PR78809

8 years, 3 months

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Q: reasons for lack of support for C++ in OP-TEE?

by Godmar Back

In a recent github thread <https://github.com/OP-TEE/optee_os/issues/1708#issuecomment-320245973> it was suggested that I ask this list about what the exact reasons for the lack of C++ support are, and how/if they break down by C++ feature so as to gauge a possible investment in remedying this situation at least partially. In other words, suppose I changed the build process to include libstdc++, libgcc, and libgcc_eh (and/or other runtime support commonly linked with C++ programs), what features of C++ would work/still fail? And what implementation work would be required to implement the missing features? On a related note, are there intrinsic properties of the secure environment that may conflict with running C++ code, if any? Thank you. - Godmar

8 years, 4 months

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[ACTIVITY] Week 32

by Yvan Roux

== Progress == o Linaro GCC/Validation * Delivered GCC 6 and 7 2017.08 release candidates binaries * Preparing backports for 2017.08 source snapshots * reviewed infra patches o Misc * Various meetings and discussions. == Plan == o Complete backports and branch merges for snapshots o Tuesday off

8 years, 4 months

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[ACTIVITY] 07/08 - 11/08

by Yao Qi

# Progress # * TCWG-1159,New design of GDB/GDBserver target description. [3/10] Split the patch series, and post unrelated stuff first. Patches will be easily reviewed in this way. * TCWG-561, Handle unavailable memory during frame unwinding. [2/10] Committed the first 4 patches, and leave the rest 4 patches for review. * TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [4/10] Resolved the newlib issue. Get my first newlib patch merged. Successfully run GDB testsuite with QEMU system mode. It should be similar to running with OpenOCD. * Upstream review. [1/10] ** Review some memory leaks fixes. ** One patch about armv8.3 pointer authentication. Next week: * On holiday, and back on Thu. * TCWG-1162, triage the aarch64-elf GDB test result with QEMU. * TCWG-1159, rebase my GDB target description patches, and post v4. -- Yao Qi

8 years, 4 months

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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 6.4-2017.08-rc1

by Yvan Roux

The Linaro Binary Toolchain ============================ The Linaro GCC 6.4-2017.08-rc1 Release-Candidate is now available. The GCC 6 Release series has significant changes from the GCC 5 release series. For an explanation of the changes please see the following website: https://gcc.gnu.org/gcc-6/changes.html For help in porting to GCC 6 please see the following explanation: https://gcc.gnu.org/gcc-6/porting_to.html Download release-candidate packages from: (sources) http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08-rc1/ (binaries) http://snapshots.linaro.org/components/toolchain/binaries/6.4-2017.08-rc1/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 6.4-2017.08-rc1 http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.08-rc1/ Linaro glibc 2.23 (linaro/2.23/master) https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html Linaro newlib 2.4-2016.03 (linaro_2.4-branch) https://sourceware.org/ml/newlib/2016/msg00370.html Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… Linaro GDB 8.0 (gdb-8.0-branch) https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 6 (as of Linaro GCC 6.4-2017.08-rc1) ================================================== * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code option to ARMv7-M and ARMv8-M targets. This option ensures functions are put into sections that contain only code and no data. * The GDB version was upgraded from GDB 8.0. * Previous versions of the Linaro GCC 6 toolchain, when -static -E/—dynamic-list are passed to the linker, might create executables with dynamic sections which aren’t supported by run-time. This was exhibited in Perf Tools build system and has been fixed upstream and backported into Linaro Binutils 2.27 branch. Linaro bugzilla #2926 : Perf tools compiled statically for AArch64 with Linaro release 6.1 and later ones was not statically linked. https://bugs.linaro.org/show_bug.cgi?id=2926 * The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS, exception handling, …) and these have been incorporated into this release. * Previous versions of the Linaro GCC 6 toolchain were incorrectly generating floating-point code for soft-float Linux targets (arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection until recently because the soft-float targeted toolchains were configured to use general-purpose registers for passing floating-point values (which is what you would expect for soft-float toolchains) and the intra-routine floating-code was not noticed. The issue would only show up on targets that were run on hardware that truly didn't have floating-point hardware where the kernel did not trap and emulate floating-point routines. This has been solved in Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using --with-float=soft) to generate code without any floating-point instructions at all (-mfloat-abi=soft). https://review.linaro.org/#/c/16968/2 This change should not break compatibility between existing binaries compiled with these toolchains since the float-point parameter passing ABI is still the same. * A bug/regression in the compiler has been identified whereby the target function that is invoked when calling a "weak" function directly is the "strong" override, whereas when calling the function via a pointer the "weak" implementation is used. This would be noticed as inconsistent function invocation when invoking directly vs. invoking via function pointer. This issue only affected 32-bit arm targets. This regression has been fixed upstream and backported into Linaro GCC 6.3-2017.02-rc2. GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function instead of strong when called through pointer. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253 Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of strong when called through pointer https://bugs.linaro.org/show_bug.cgi?id=2562 * MS Windows does not support symlinks and the MS Windows archive extractor does not properly deep copy the symlink target files/directories into the symlinked directory structure when unpacking the toolchain archive. This causes problems with missing dependencies when using the Linaro mingw toolchains, as identified in the following bugs: https://bugs.linaro.org/show_bug.cgi?id=2684 https://bugs.linaro.org/show_bug.cgi?id=2192 https://bugs.linaro.org/show_bug.cgi?id=2762 This has been solved by copying files rather than using symlinks when the mingw targetted toolchain archives are created. https://review.linaro.org/#/c/16415/ * Users of Linaro's toolchain have encountered problems when building projects with Autotools (specifically libtool): https://bugs.linaro.org/show_bug.cgi?id=2764 The Linaro binary toolchain release contained files with a .la suffix as artifacts of the toolchain build process. These .la files are helper files for libtool, but unlike a gcc install tree, they are not position independent and contain full paths. Since these artifacts contain absolute paths they can actually mislead user invocation of libtool into not finding required libraries (because they reference the build tree, not the install location) and hence breaking Autotools builds. These *.la file artifacts have been removed from Linaro toolchain binaries because they are unnecessary for users. * The Linaro GCC 6.3-2017.01 snapshot added further enablement for ARMv8-M and these have been incorporated into this release. * Compiling and statically linking some SPEC2006int tests against tcmalloc have been failing due to a problem with glibc's memory allocator function overrides. This was fixed upstream: https://sourceware.org/bugzilla/show_bug.cgi?id=20432 Backported into Linaro glibc 2.23: commit 058b5a41d56b9a8860dede14d97dd443792d064b Author: Florian Weimer <fweimer(a)redhat.com> Date: Fri Aug 26 22:40:27 2016 +0200 malloc: Simplify static malloc interposition [BZ #20432] * Host binaries for x86_64 linux hosts now have symbols and debug information stripped in order to reduce the size of the toolchain binary archives. This reduces the archive size from 1.5G to 600M for aarch64-linux-gnu target with the gcc-6-branch. * The GDB version was upgraded from GDB 7.11 in the Linaro GCC 6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release. * The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2 and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes merged from FSF GCC 6.2. This is available in the binary toolchain as of Linaro GCC 6.2-2016.11. * Basic tuning support for the Qualcomm qdf24xx was added to the Linaro GCC 6.2-2016.10 snapshot and is available in the binary toolchain as of Linaro GCC 6.2-2016.11. * IFUNC was disabled for baremetal targets, as it was causing test-suite failures, and is presently a Linux only feature. * The gold linker was added to this binary release. * Backported malloc_lock fix into Linaro newlib 2.4. commit 2665915cfc46aa6403bb2efd473c523d3167e0cb Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com> Date: Thu Jun 16 12:23:51 2016 +0100 Re-enable malloc_lock for newlib-nano * Backported rawmemchr patch into Linaro newlib 2.4. commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5 Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com> Date: Thu May 12 16:16:58 2016 +0000 Add rawmemchr * Backported strlen fix when using Thumb-2 and -Os -marm into Linaro newlib 2.4. commit 5c02bcc086a96b174e1b9e1445a4a1770070107a Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com> Date: Wed May 11 17:18:48 2016 -0400 Fix strlen using Thumb-2 with -Os -marm * Backported fix for semihosting ARM when heapinfo not provided by debugger into Linaro newlib 2.4. commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7 Author: David Hoover <spm2(a)dangerous.li> Date: Thu Apr 21 07:12:24 2016 +0200 Fixed semihosting for ARM when heapinfo not provided by debugger. * Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23. * Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch. commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Tue May 17 10:16:39 2016 -0300 Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463) * Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23 branch. commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1 Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Mon May 16 19:01:10 2016 -0300 Remove __ASSUME_SET_ROBUST_LIST * Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23 branch. commit e48b4e7fed0de06dd7832ead48bea8ebc813a204 Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> Date: Mon May 16 10:35:25 2016 -0300 Remove __ASSUME_FUTEX_LOCK_PI * Merged latest FSF binutils-2_27-branch into linaro_binutils-2_27-branch. * The libwinpthread DLL is now copied into the host bin directory to satisfy mingw package dependencies. * Backported GNU Linker fix. commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59 Author: Nick Clifton <nickc(a)redhat.com> Date: Tue Aug 23 09:45:11 2016 +0100 Fix seg-fault in ARM linker when trying to parse a binary file. * Backported GNU Assembler fix for PR 20364 commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd Author: Nick Clifton <nickc(a)redhat.com> Date: Fri Aug 5 10:37:57 2016 +0100 Fix the generation of alignment frags in code sections for AArch64. https://sourceware.org/bugzilla/show_bug.cgi?id=20364 * Performance related backports from the following snapshots have been included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC 6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01, Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03, Linaro GCC 6.3-2017.04, Linaro GCC 6.3-2017.05, Linaro GCC 6.3-2017.06 and Linaro GCC 6.4-2017.07 . See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org

8 years, 4 months

1
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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 7.1-2017.08-rc1

by Yvan Roux

The Linaro Binary Toolchain ============================ The Linaro GCC 7.1-2017.08-rc1 Release-Candidate is now available. *Notice*: GCC 7.1 ABI change for arm*-*-* targets, and note for aarch64*-*-* targets >From GCC 7.1 release notes: On ARM targets (arm*-*-*), a bug introduced in GCC 5 that affects conformance to the procedure call standard (AAPCS) has been fixed. The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. This is an ABI change. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 GCC 5 and GCC 6 releases will continue to be affected by the ABI bug, since changing ABI in these releases is not practical. A warning enabled by -Wpsabi option was added to GCC 5 and GCC 6 toolchains to diagnose codebases that might be affected by the ABI bug. Additionally, this same bug was present in AArch64 backend in development versions of GCC 7. There was no releases of GCC with this bug present in AArch64 backend, therefore the release notes does not mention this. However, be advised that any code bases built with development versions of GCC 7 need to be recompiled with released version of GCC 7 to conform to ABI. For an explanation of GCC 7 series changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html For help in porting to GCC 7 please see the following explanation: https://gcc.gnu.org/gcc-7/porting_to.html Download release-candidate packages from: (sources) http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.08-rc1/ (binaries) http://snapshots.linaro.org/components/toolchain/binaries/7.1-2017.08-rc1/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 7.1-2017.08-rc1 http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.08-rc1/ FSF glibc 2.25 (release/2.25) https://lists.gnu.org/archive/html/info-gnu/2017-02/msg00002.html Newlib 2.5 (newlib-2_5_0 tag) https://sourceware.org/ml/newlib/2016/msg01191.html GNU Binutils 2.28 (linaro-local/linaro_binutils-2_28-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… FSF GDB 8.0 (gdb-8.0-branch) https://sourceware.org/ml/gdb-announce/2017/msg00003.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 7 (as of Linaro GCC 7.1-2017.08-rc1) ===========================[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 7.1-2017.08-rc1======================= * The Linaro GCC 7.1-2017.07 snapshot added prefetching configuration improvement for AArch64 targets and laid groundwork to enabling prefetching in more cases. * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * Performance related backports from the following snapshots have been included: Linaro GCC 7.1-2017.05, Linaro GCC 7.1-2017.06 and Linaro GCC 7.1-2017.07.

8 years, 4 months

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[ACTIVITY] 31/07 - 04/08

by Yao Qi

# Progress # * TCWG-1159,New design of GDB/GDBserver target description. [3/10] Patches are still not reviewed. Keep going to change x86 target descriptions. Post two patches to clean up them first. * TCWG-561, Handle unavailable memory during frame unwinding. [3/10] Patches are posted. * PR 21818, GDB crashes with executable for armv5te. [1/10] Patch is tested, and to be posted. * Upstream review, [2/10] ** ADI patches review, advice on how to match the output in gdb tests, ** Some disassembly regression caused by my previous patches, ** Help people to triage their GDB issues because I don't have the env to reproduce them. * Misc, [1/10] # Plan # * TCWG-1162, Test GDB+OpenOCD with AArch64 boards. Post my newlib patches upstream, and continue to test with QEMU and OpenOCD respectively. * TCWG-1159, New design of GDB/GDBserver target description -- Yao Qi

8 years, 4 months

1
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[ACTIVITY] Week 31

by Yvan Roux

o Back from vacation Wednesday. == Progress == o Linaro GCC/Validation * Discussed/checked needs for newlib and binutils to include in binaries * Preparing RCs (release notes, ...) * pinged my unreviewed upstream patches * reviewed infra patches o Misc * Various meetings and discussions. == Plan == o 2017.08 GCC 6 and 7 release candidates, backports, ...

8 years, 4 months

1
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[ACTIVITY] 31st July - 4th August 2017

by Prathamesh Kulkarni

== This Week == * malloc propagation (2/10) - Submitted patch upstream * type promotion (4/10) - Verified ppc64 miscompilation with memcpy-bi.c is a latent issue. - Investigating another miscompilation on ppc64 with patch. - Experimenting with pass placement. * bugs (3/10) - PR78736: pinged upstream. - PR78888: submitted patch upstream. - Started looking at PR78809. - Committed patch add include-guard to tree-vrp.h. * Misc (1/10) - Meetings == Next Week == - Type promotion, PR78809, malloc propagation

8 years, 4 months

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[ACTIVITY] 24 - 28 July 2017

by Prathamesh Kulkarni

== This Week == * malloc propagation (4/10) - Resolved bootstrap comparison failure - Patch passes validation with and without LTO. - Working on handling indirect calls. * type promotion (3/10) - Created patche for resolving ICE with armv3/armv5t. - Have got a hack-ish patch to address interference between type promotion and widening_mul/bswap optimizations, but needs improvement. * Misc (3/10) - Meetings - Visa interview == Next Week == - Continue with malloc propagation, type promotion

8 years, 4 months

1
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[ACTIVITY] 24 - 28 July

by Yao Qi

# Progress # * TCWG-1159,New design of GDB/GDBserver target description. [3/10] Looks people who can review my patches is on holiday, so I committed 7 patches and leave the rest 19 patches there. Need to think about how to make people more confident on these patches. * PR 21717, PR 21555, fixed. Pushed to master and 8.0 branch. [1/10] * TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [3/10] I can run gdb regression tests with OpenOCD on HiKey. After I power cycle the board, the first several tests can run, but the following tests failed because the board goes to an odd state. Something wrong in OpenOCD side. Try GDB aarch64 bare-metal debugging with QEMU, and then find a bug in newlib which doesn't initialize FPU, so some FPU instruction will trigger und exception. * TCWG-561, Handle unavailable memory during frame unwinding. [2/10] Lear C++ move assignment and move constructor. Finish the code, and testing the patches. * Send my GDB target description talk abstract to Linaro SFO17. * Misc [1/10] # Plan # * Mon and Tue off. * TCWG-561, TCWG-1159. -- Yao Qi

8 years, 4 months

1
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Problems with Aarch64 vmull_p64 and vmull_high_p64

by Jeffrey Walton

Hi Everyone, I'm working on a early LeMaker HiKey with GCC 4.9.2. I believe everything is fully patched. I'm using the builtin's because the intrinsics are missing. I lifted it from https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01976.html. Any ideas on this issue? hikey$ g++ -march=armv8-a test.cxx -c test.cxx: In function ‘poly128_t VMULL_P64(poly64_t, poly64_t)’: test.cxx:10:1: error: unrecognizable insn: } ^ (insn 9 8 12 2 (set (reg:TI 73 [ D.17869 ]) (unspec:TI [ (reg:DI 75) (reg:DI 76) ] UNSPEC_PMULL)) test.cxx:9 -1 (nil)) test.cxx:10:1: internal compiler error: in extract_insn, at recog.c:2202 Please submit a full bug report, Thanks in advance. Jeff ********** hikey:cryptopp-fork$ cat test.cxx #include <arm_neon.h> #include <arm_acle.h> #define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) #if (GCC_VERSION >= 40800) && (GCC_VERSION < 50000) inline poly128_t VMULL_P64(poly64_t a, poly64_t b) { return __builtin_aarch64_crypto_pmulldi_ppp (a, b); } inline poly128_t VMULL_HIGH_P64(poly64x2_t a, poly64x2_t b) { return __builtin_aarch64_crypto_pmullv2di_ppp (a, b); } #else # define VMULL_P64(a, b) vmull_p64(a, b) # define VMULL_HIGH_P64(a, b) vmull_high_p64(a, b) #endif int main(int argc, char* argv[]) { const poly64_t a1={0x9090909090909090}, b1={0xb0b0b0b0b0b0b0b0}; const poly8x16_t a2={0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xa0,0xa0,0xa0,0xa0,0xa0,0xa0,0xa0,0xa0}, b2={0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0}; const poly128_t r1 = VMULL_P64(a1, b1); const poly128_t r2 = VMULL_HIGH_P64((poly64x2_t)(a2), (poly64x2_t)(b2)); return 0; } ********** $ cat /proc/cpuinfo Processor : AArch64 Processor rev 3 (aarch64) processor : 0 processor : 1 processor : 2 processor : 3 processor : 4 processor : 5 processor : 6 processor : 7 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: AArch64 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 3 Hardware : HiKey Development Board ********** $ gcc --version gcc (Debian/Linaro 4.9.2-10) 4.9.2 Copyright (C) 2014 Free Software Foundation, Inc. $ lsb_release -a No LSB modules are available. Distributor ID: Debian Description: Debian GNU/Linux 8.9 (jessie) Release: 8.9 Codename: jessie

8 years, 4 months

2
3
0 0

[ACTIVITY] 24 - 28 July

by Peter Smith

4 day week. [TCWG-614] Range Extension Thunks - Rebased due to upstream refactoring - Pinged but no upstream review progress [Compiler-rt] Clang no longer always uses base PCS for all the builtins it expands such as the _Complex helpers. - Added tests to make sure RTABI 4.1.2 Floating Point helpers all use softfp in Clang D35538 and llvm D35904. - Reviewer pointed out useful script update_llc_test_checks.py that can simplify writing of llc tests. Well worth checking out [LLD] Looks like lld use in Android may be becoming more likely, major blocking feature is lack of Cortex-A53 erratum fix 843419. - I've commented on the upstream PR https://bugs.llvm.org/show_bug.cgi?id=33463 - I've written some test cases and have started a prototype implementation Submitted Linaro Connect presentation proposal for Functional Safety and Development tools. Plans: In priority order: - range extension thunks - Cortex-A53 843419 - Compiler-rt

8 years, 4 months

1
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[ACTIVITY] 24 - 28 July 2017

by Diana Picus

== Progress == * TCWG-1205 - Minor tweaks to Jenkins LLVM jobs [1/10] - Sent a few patches to make the Jenkins jobs more friendly and/or fix them for new changes in the upstream release script * TCWG-1206 - Investigate timeouts on buildbots [1/10] - Had some mysterious timeouts on some of the buildbots - Didn't manage to reproduce, will keep an eye out in case it happens again * TCWG-1199, 1200 - LLVM 5.0.0 for ARM and AArch64 [1/10] - RC1 is out, there are some failures in some libunwind and sanitizer tests; reported upstream * TCWG-1194 - [ARM GlobalISel] Support simple, static globals [4/10] - Committed some simple stuff and sent a patch for upstream review * TCWG-1209 - [MIR] Print ARM constant pools [1/10] - Printing target-specific constant pools is trivial, but testing is a bit problematic - All current MIR tests read in and then print out the same MIR, which means that we'd have to add support for target-specific constant pools in the parser as well - This is complicated by the fact that at a first glance the parser doesn't seem to handle any other target-specific stuff and I'm not sure it's ok to pull ARMConstantPool into it * Misc [2/10] - Mailing lists, code reviews, meetings == Plan == * Figure out what to do about TCWG-1209 * More code reviews and global isel

8 years, 4 months

1
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