== This Week ==
* TCWG-1005 (4/10)
- Made some improvements to analysis, which increased candidates for
malloc functions in gcc source.
- Patch review from Kugan
* PR78736 (2/10)
- Submitted upstream for review
* PR80613 (2/10)
- Submitted patch but was rejected by Richard
- "Fixed" the bug by partially reverting the commit that caused it.
* Validation (1/10)
- Committed patch to tcwg-buildapp for adding python source.
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1005, GCC bugs, validation
The Linaro Binary Toolchain
============================
The Linaro GCC 6.3-2017.05-rc1 Release-Candidate is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release-candidate packages from:
(sources)
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05-rc1/
(binaries)
http://snapshots.linaro.org/components/toolchain/binaries/6.3-2017.05-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and Aarch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.3-2017.05-rc1
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.05-rc1/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro-local/linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 7.12 (gdb-7.12-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.3-2017.05-rc1)
==================================================
* Previous versions of the Linaro GCC 6 toolchain, when -static
-E/—dynamic-list are passed to the linker, might create executables
with dynamic sections which aren’t supported by run-time. This was
exhibited in Perf Tools build system and has been fixed upstream and
backported into Linaro Binutils 2.27 branch.
Linaro bugzilla #2926 : Perf tools compiled statically for AArch64
with Linaro release 6.1 and later ones was not statically linked.
https://bugs.linaro.org/show_bug.cgi?id=2926
* The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS,
exception handling, …) and these have been incorporated into this
release.
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, Linaro GCC 6.3-2017.01,
Linaro GCC 6.3-2017.02, Linaro GCC 6.3-2017.03 and Linaro GCC
6.3-2017.04.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
# Progress #
* TCWG-1050, GDB 8.0 release. [4/10]
** Fix the new fails about the size of wchar_t on aarch64, by setting
it to 4 in default. Patch is pushed to master and 8.0 branch.
** Intel btrace python api patches are ready to commit. No idea why
he doesn't push yet.
* TCWG-1040, Review SVE patches. [4/10]
** Review some SVE GDB patches, and approved part of them. Leave the
controversial part there. Some of them are blocked by my Class-fy
regcache patches.
** Class-fy regcache. Patches are approved. Will push them in later.
Then, I'll update my unit test to value/register conversion gdbarch
hooks, and post them next week.
** GDB target description change, the preparation for adding more
hardware features, like PAUTH and SVE, and their arbitrary
combinations.
GDB side changes are done, and take i386-linux as an example to
demonstrate the the benefit of the changes.
* Misc, [2/10]
** Rebase my GDB disassembler patch, which unify the disassembler
selection in both gdb and objdump.
** Explain the GDB behavior to Linaro kernel guy who is working on
single-step in kgdb.
** Read some paper on dynamic slicing, and think about how to do it on
GDB for aarch64/arm.
# Plan #
* Holiday on Monday.
* Review kernel-awareness patches,
* Upstream my patches about unit test to value/register conversion
gdbarch hooks.
* Post my GDB target description change as an RFC, collect comments,
and think about the changes in GDBserver side (which is harder).
--
Yao Qi
* Day off (2/10)
== Progress ==
o Linaro GCC/Validation (5/10)
* Release Automation:
- 5.4 2017.05 RC1: Done
- 6.3 2017.05 RC1: still on-going
- Re-worked publication part of the process
* Debug Binutils instablities
* Reviews, backport, ...
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o Complete 6.3 RC1
o Make Linaro GCC 7 RC
o Continue release automation
== Progress ==
* [ARM GlobalISel] Support div [TCWG-1103] [1/10]
- Committed upstream
* [ARM GlobalISel] Fix fallback path [TCWG-1110] [2/10]
- Fixed and committed another issue
* [ARM GlobalISel] Fix loading i<32 from the stack [TCWG-1065] [2/10]
- Committed upstream
* Remove environment variables [TCWG-1114] [1/10]
- Committed a first patch towards fixing this
* Misc [4/10]
- Meetings, mailing lists, code reviews
- Minor GlobalISel cleanups
- Put up a cron job on llvm-tk1-test-02 to track GlobalSel
TableGen'erated code for ARM and AArch64
== Plan ==
* Out of office on Monday
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037]
* [ARM GlobalISel] Add support for struct / array args [TCWG-1033]
* Maybe finish TCWG-1114
* Two days off, Mon and Tue [4/10]
# Progress #
* TCWG-1050, GDB 8.0 release. [2/10]
8.0 branch is created. Intel btrace python api patches are almost OK
push to master and 8.0 branch. Patches should be pushed in soon.
* TCWG-1040, Review SVE patches. [3/10]
Write unit test to value/register conversion gdbarch hooks. C++-fy
regcache so that I can easily verify the result in unit test. Still
some fails, need to investigate further. They are needed to prove SVE
changes are correct.
* Upstream patches review [1/10]
** arm software single step patch review. There is still an open
issue that the author didn't realize, that is, GDB has to understand
there may be different kind of breakpoints on the same address.
* Propose deprecate arm fpa support in GDB. I need to post the
proposal in gdb-announce(a)sourceware.org this week, according to the
deprecation process.
# Plan #
* Finish my unit test and post them for review (with regcache C++-fy
patch).
* Other issues on 8.0 release if any.
--
Yao Qi
* Public Holiday (2/10)
== Progress ==
o Linaro GCC/Validation (5/10)
* Release Automation:
- Deployed job to create snapshots/releases tags
- Working on the missing jobs to complete automation process
* GCC 7 preview release:
- Mingw builds fixed after revert
- Merged upstream GCC 7 and built binaries
- Preapring Linaro GCC 7 branch
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o Finalized 2017.05 RCs
o Continue release automation
== Progress ==
* Out of office on Monday [2/10]
* [ARM GlobalISel] Investigate divmod [TCWG-1086]
- Broke this up into several smaller stories
* [ARM GlobalISel] Support sub and mul [TCWG-1104] [1/10]
- Committed upstream
* [ARM GlobalISel] Support trunc [TCWG-1109] [1/10]
- Committed upstream
* [ARM GlobalISel] Support div [TCWG-1103] [2/10]
- Mostly done, will upstream next week
* [ARM GlobalISel] Fix fallback path [TCWG-1110] [2/10]
- Oliver from ARM has started running csmith with GlobalISel and is
finding several issues
- Fixed one of them and committed upstream
- Will commit another one next week
* Misc [2/10]
- Meetings, mailing lists, code reviews, buildbots
- Minor cleanup in the ARM backend (renamed a subtarget feature to
avoid future misuse)
== Plan ==
* [ARM GlobalISel] Fix fallback path [TCWG-1110]
* [ARM GlobalISel] Support div [TCWG-1103]
* Resume [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037]
3 day week,Monday and Tuesday off
Achievements:
[TCWG-614] Range Thunks
- No review progress, blocked on a request for some refactoring to
unify the address allocation.
- Reworked my downstream patch stack in light of TCWG-1088 below.
- Spent some time refactoring the code to try and make it easier to follow.
[TCWG-1088] Refactoring of address assignment
- Committed first patch reviewed last week
- Sent out first couple of patches, no response from upstream, I'm
hoping this is due to maintainers being on Easter holiday.
Some upstream review on ILP32 patches.
Plans for next week:
- 2 day week, at ACCU2017 conference Wednesday to Friday.
- Respond to any upstream review comments.
- Find some small tasks to do to fit in the remainder of the time.
Planned Absences
- ACCU2017 next week (Wednesday to Friday)
I'm working on my HiKey. I'm trying to enable CRC extension on ARMv8
in the assembler regardless of the way GCC was built, and regardless
of the user's CFLAGS and CXXFLAGS. I'm encountering an assembler
error: "unknown pseudo-op: `.arch_extension'".
According to [1], I can use ".arch_extension" to enable it. According
to [2], ".arch_extension" is available in GCC 4.6 and GAS 2.21. My
version of Linaro provides GCC 4.9.2 and GAS 2.25.90. I can also
duplicate the issue on GCC113 (compiel farm), which provides GCC 4.8
and GAS 2.24.
The test program is below. Trying to compile it results in:
$ g++ test.cxx -c
/tmp/ccVZ6hiq.s: Assembler messages:
/tmp/ccVZ6hiq.s:24: Error: unknown pseudo-op: `.arch_extension'
/tmp/ccVZ6hiq.s:25: Error: selected processor does not support `crc32b w1,w0,w0'
Trying to compile without ".arch_extension" results in:
$ g++ test.cxx -c
/tmp/cci4wu6d.s: Assembler messages:
/tmp/cci4wu6d.s:24: Error: selected processor does not support `crc32b w1,w0,w0'
Its almost as if ".arch_extension" is not being properly recognized or consumed.
Any ideas what might be going wrong here?
**********
The program:
$ cat test.cxx
#include <arm_neon.h>
#define GCC_INLINE_ATTRIB __attribute__((__gnu_inline__,
__always_inline__, __artificial__))
#if defined(__GNUC__) && !defined(__ARM_FEATURE_CRC32)
__inline unsigned int GCC_INLINE_ATTRIB
CRC32B(unsigned int crc, unsigned char v)
{
unsigned int r;
asm (" \n"
".arch_extension crc \n"
"\t" "crc32b %w2, %w1, %w0 \n"
: "=r"(r) : "r"(crc), "r"((unsigned int)v));
return r;
}
#else
// just use the instrinsic
# define CRC32B(a,b) __crc32b(a,b)
#endif
int main(int argc, char* argv[])
{
return CRC32B(argc, argc);
}
**********
Versions...
$ gcc --version
gcc (Ubuntu/Linaro 4.8.4-2ubuntu1~14.04.3) 4.8.4
$ as -v
GNU assembler version 2.24 (aarch64-linux-gnu) using BFD version (GNU
Binutils for Ubuntu) 2.24
$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 14.04.5 LTS
Release: 14.04
Codename: trusty
[1] https://sourceware.org/binutils/docs/as/AArch64-Directives.html#AArch64-Dir…
[2] https://gcc.gnu.org/ml/gcc-help/2012-07/msg00180.html
* Child care (2/10)
== Progress ==
o Linaro GCC/Validation (5/10)
* Released GCC 5 and 6 Linaro source sanpshots
* Progressing on release automation
* Preparing GCC 7 preview release:
- found a build issue for mingw toolchains
- proposed a fix upstream, discussion on-going.
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o Continue release on automation and prepare 2017.05 RC
== Progress ==
* Validation
- kernelci/lava-ci scripts update broke my prototype. We need more
discussion at this point.
- benchmarking scripts, debugging with Jenkins
- reviews
* GCC
- reported a regression on trunk after an LRA fix, now fixed by Vladimir.
- bootstrapping gcc-5 on armv7 (using present continuous because
it's taking so long)
- Linaro bugzilla
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation?
* Benchmarking: debug scripts/jenkins/board setup
* Off Monday 17th
[TCWG-614] Range Thunks
- No review progress, blocked on a request for some refactoring to
unify the address allocation.
[TCWG-1088] Refactoring of address assignment
- Found out that linker scripts can break ARM exceptions in the same
way as they can break the thunk insertion
- Made a prototype of unified address allocation that is good enough
for the current interworking range thunks. This passes the existing
test case that I made to show that linker scripts could break the Mips
LA25 thunk placement.
[TCWG-1089] Fixed problem with ARM exceptions and identical code folding
Plans for next week:
On Holiday Tuesday
[TCWG-1088] Polish up patches and send for review.
Planned Absences:
Tuesday 18th April
Wednesday - Friday 27 - 29 April ACCU 2017
# Progress #
* TCWG-1050, GDB 8.0 release. [4/10]
Release branch is not created, but a lot of C++
patches are posted, and massively change the code even when release
is coming.
** Fix PR 19942, patch v2 is OK. Committed.
** Intel btrace python interface. Intel people posted patches to
adjust the interface as I requested. Reviewing them. They look
much better.
* TCWG-1040, Review SVE patches. [4/10]
SVE patches review. Read Alan's patches and various GDB backends,
like mips, xtensa, and ia64. Feel nervous to approve them because we
have no way testing them. Figure out a unit test to related methods,
and it works well if I build GDB with ASAN. This unit test does find
some existing issues, and patches are posted. In order to make the
test more useful, need to C++-fy regcache, not a small piece of work.
* Upstream reviews [2/10]
** Software single-step on arm-non-eabi. Convince the author that his
patch will break GDB's default behavior, and give some thoughts on
fixing it.
** Propose to deprecate ARM FPA in GDB.
So far, I am not clear what is the "right" process to deprecate
features in GDB. (I know how to deprecate ports and commands).
** Some one complains GDB can't unwind from arm64 kernel irq vector,
which is hand written asm. The fix should be using .cfi directives
to annotate them, however, they want GDB to error out if it can't
unwind. I am suggested to ask in linux-arm-kernel(a)lists.infradead.org
about the expected behavior. Will do next week.
# Plan #
* Mon and Tue off.
* Figure out more ways to test code touched by SVE patches. Convert
regcache to class if necessary.
--
Yao Qi
== Progress ==
* Out of office on Friday [2/10]
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039] [2/10]
- Committed G_FPOW and G_FADD upstream
- Most of the other soft float libcalls are just a matter of boilerplate
* [GlobalISel] Investigate divmod [TCWG-1086] [5/10]
- Working on a patch to support G_(S|U)REM in GlobalISel
- Found an inconsistency in DAGISel, sent a patch upstream
* Misc [1/10]
- Mailing lists, meetings
- Buildbot monitoring (did a bisection, reverted a few patches)
== Plan ==
* Out of office on Monday
* Send patch for TCWG-1086
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.04 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.3+svn246668 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246668
* Backport of [Bugfix] [AArch32] PR target/71436: Restrict
*load_multiple pattern till after LRA
* Backport of [Bugfix] [AArch32] PR target/79911: Invalid vec_select arguments
* Backport of [Bugfix] [AArch64] PR target/79889: Error message on
target attribute on aarch64
* Backport of [Bugfix] [AArch64] PR target/79913: VEC_SELECT bugs in
aarch64 patterns
* Backport of [Bugfix] [AArch64] PR target/79925: tweaks to quoting in
error messages
* Backport of [AArch32] Fix small multiply feature
* Backport of [AArch64] Enable AES fusion with -mcpu=generic
* Backport of [AArch64] Fix bootstrap due to wide_int .elt (0) uninit warning
* Backport of [AArch64] Fix incorrect INS in SIMD mov pattern
* Backport of [AArch64] Fix search_line_fast for aarch64/ILP32
* Backport of [AArch64] Fix typo in aarch64.opt (dummping -> dumping)
* Backport of [AArch64] Improve cost model for ThunderX2 CN99xx
* Backport of [AArch64] Improve generic branch cost
* Backport of [AArch64] more poly64 intrinsics and tests
* Backport of [AArch64] Use 'x' constraint for vector HFmode
multiplication by indexed element instructions
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn246667 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the next
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2017.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.4+svn246667
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1] Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2] Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [4/10] Release branch is not created,
but test result
looks good.
** Fix PR 19942, patch v2 is OK. Need to fix some nits before check
in.
** Intel btrace python interface discussion. Good to see that Intel
people accept my suggested new interface, and finalize the details of
the new interface.
* TCWG-1040, Review SVE patches. [4/10]
The overall goal is to remove MAX_REGISTER_SIZE.
Reviewed some Alan's patches, and wrote two patches to remove
MAX_REGISTER_SIZE in frame.c and regcache.c.
* Misc, meeting, [2/10]
~ Plan ~
* More remote tests for GDB 8.0 release.
* SVE patches review, and start to think about GDB target description
changes for SVE.
* Public holiday on Friday and next Monday.
--
Yao Qi
== Progress ==
[TCWG-614] Long Range Thunks
- Posted for upstream review. I may have to do some refactoring of the
address allocation first to unify the linker-script and non
linker-script cases.
- Started work on a prototype that fabricates linker script commands
for the default non linker-script case. Failing 7 tests of 1007 and it
is a mess so some work to do here.
[TLS] Fixed recent breakage in ARM TLS caused by change in the way
that values are written to the GOT.
== Plans ==
Progress the prototype address allocation far enough to post upstream
for comment, I think that this is likely to take a few iterations to
get right.
== Planned Absences ==
ACCU 2017 27-29 April
== This Week ==
* TCWG-1005 (6/10)
- All ICE's resolved with firefox -;)
- Few improvements still left - handling indirect calls, handle cases
when return value from malloc'd function has more than single use.
* Validation (1/10)
- patch for adding --set buildconfig option to abe
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Get back to TCWG-1010 (bitwise-dce)
- Validation
== Progress ==
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][3/10]
- Ran more tests and reported the results upstream
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
- Started supporting G_FREM and G_FPOW, which are already handled by
the target-independent code
- Committed G_FREM upstream, G_FPOW is ready to commit first thing next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Moved llvm-helper-scripts
* Misc [3/10]
- Mailing lists, code reviews, meetings
== Plan ==
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
=== This Week ===
GDB Kernel Awarenes - Kernel Dump setup for ARM [9/10]
-- Background study on kdump and try to find working steps for QEMU ARM.
-- There is a problem with kdump-tools install script with QEMU
-- Tried building kernel for Raspberry Pi2 and Pi3 with kdump, no
success so far.
-- Setup B2260 with debian and try kdump setup
-- Setup and kernel config successful but kdump couldn't configure
-- Tried the same with HiKey board
Miscellaneous Activities [1/10]
-- Meetings, Emails etc.
=== Next Week ===
GDB Kernel Awarenes
-- Start merging Peter's and IBM patches
-- Look around for help on Kdump setup.
== This Week ==
* TCWG-1005 (6/10)
- Fixed firefox ICE
- Unfortunately that gives rise to another ICE with ipa-icf pass :(
Investigating if this
caused by the patch or a latent bug in ipa-icf.
- Builds well with chromium
* Validation (1/10)
- abe/extraconfig patches
- backport review
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
~ Progress ~
* TCWG-1050, GDB 8.0 release. [7/10]
** Fix PR 19942, but looks my patch is completely wrong as I fully
misunderstood the "reference count" in GDB. Writing the v2.
** Intel btrace python interface discussion, a marathon discussion
about both the interface and implementation. Good thing is that we
agree that we need to change the interface. This takes most of my
time this week.
* TCWG-1040, Review SVE patches. [2/10]
Some discussions on avoid copying register contents to a local buffer
again, which is from my review comments to Alan's patch and my
suggested patch. Spend some time on understanding the zero
initialization of union in C++. I'll update my suggested patch.
* Update AArch32 GDB buildbot option, so we can get more reasonable
test result. [1/10]
~ Plan ~
* More remote tests for GDB 8.0 release.
* Fix PR 19942.
* One day off on Thu.
--
Yao Qi
[Eurollvm]
Attended, we have recorded our thoughts in EuroLLVM 2017 Recap doc
[TCWG-614] Range extension thunks
- I've finished my downstream implementation, and have written almost
all the lld tests I'd like to write
- Still need to test on real large programs such as libclang.so
- Made a start at breaking down the implementation into smaller
patches that can be sensibly upstreamed
Plans for next week
[TCWG-614]
- Aiming to start upstreaming on Monday, I'm expecting this to be
quite a drawn out process
- Continue testing on ARM Linux
Planned Absences
ACCU conference 2017 27-29 April
== Progress ==
* Validation
- helped with new llvm build scripts and jobs
- improvements to container scripts to cope with llvm's higher needs
in resources
- improved tcwg-regression tests
- various to remove dependencies on env variables
- comparison script now reports the associated .exp file name,
making it easier to reproduce a regression
- experimented with lava
- started work on benchmarking scripts
* GCC
- keeping an eye on trunk regressions
- update to qemu-2.8.0 introduced regressions in validation for
armeb on some atomic tests
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation:
- hopefully nothing :)
* Benchmarking:scripting
== Progress ==
* EuroLLVM trip [6/10]
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][2/10]
- Apple wants to switch the default O0 to GlobalISel for AArch64, so
we need to run tests and gather metrics
- I'm running the test-suite and selfhost with GlobalISel to see how
it performs
* Misc [2/10]
- Mailing list, code reviews, meetings, herding GlobalISel cats
(we're trying to open more communication channels with Apple so we can
unblock progress)
== Plan ==
* Wrap up TCWG-1074
* Learn more TableGen and do more code review
Hello all,
I've been using GCC 4.9.4 for a while now (arm-linux-gnueabi-gcc (Linaro
GCC 4.9-2017.01) 4.9.4), and I found this strange behavior:
In the library header (libm5op.h):
-----
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run);
#ifdef __cplusplus
}
#endif
-----
In the library C file (m5op_arm_.c):
-----
#include "stdio.h"
#include <stdlib.h>
#include "libm5op.h"
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run)
{
// Code here using args
}
-----
The code above is in
/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ and compiled as a
library with GCC 6.3.1 and is ok:
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -O3
-fno-optimize-sibling-calls -c m5op_arm_.c -o m5op_arm_.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c m5op_arm.S -o m5op_arm.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-ar
rcs libm5op32.a m5op_arm_.o m5op_arm.o
The library is used in a source code compiled with the GCC 4.9.4 describe
at the begining.
In the C file:
-----
#include <libm5op.h>
S_regmatch(pTHX_ regnode *prog)
{
warm_and_run_(161, 818);
// Code continues
}
------
This source is compile with:
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c -o regexec.o -DSPEC_CPU -DNDEBUG -DPERL_CORE -static -marm
-march=armv7-a - mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat-abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/ SPEC_CPU2006v1.1-aarch64/m5op/
-DGEM5_ARM32=1 -DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 regexec.c
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-static -marm -march=armv7-a -mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat- abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ -DGEM5_ARM32=1
-DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 av.o deb.o doio.o doop.o
dump.o globals.o gv.o hv.o locale.o mg.o numeric.o op.o pad.o perl.o
perlapi.o perlio.o perlmain.o perly.o pp.o pp_ctl.o pp_hot.o pp_pack.o
pp_sort.o pp_sys.o regcomp.o regexec.o run.o scope.o sv.o taint.o toke.o
universal.o utf8.o util.o xsutils.o Base64.o Cwd.o Dumper.o HiRes.o IO.o
Peek.o attrs.o poll.o stdio.o DynaLoader.o MD5.o Storable.o Parser.o
specrand.o Hostname.o Opcode.o -lm -lm5op32 -lm5op32 -o
perlbench
Finally, the assembled code of S_regmatch has:
-----
af2d0: e3a000a1 mov r0, #161 ; 0xa1
af2d4: e3001332 movw r1, #818 ; 0x332
af2d8: e58d3018 str r3, [sp, #24]
af2dc: e58d2028 str r2, [sp, #40] ; 0x28
af2e0: fa02615c blx 147858 <warm_and_run_>
-----
So, this means that warm_and_run_ is assumed by GCC 4.9.4 to have 32 bits
arguments, while they are indeed 64 bits. This seems to be a bug for me.
The code in the library is correctly allocating 2*32 bits regs for each
argument.
For now, I'm using int32_t, and I just thought it could be useful to
feedback you guys.
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
== Progress ==
* Validation
- finally merged most of work of the past weeks
- main jobs are now using start-container scripts
- helped with new llvm build scripts and jobs
- abe initial config for gcc7: need to investigate a binutils build
problem in a trusty container
- improved tcwg-regression tests, identified a regression for bug-2123
- many validation-related patches to review
* GCC
- reported a regresion upstream
* misc (conf-calls, meetings, emails, ....)
- started discussing benchmarking
== Next ==
* Validation:
- a few patches pending review (to improve reports, debug-ability of
containers, ...)
- work on a new proposal to upgrade our qemu
- probably more cleanup needed in the jobs (slaves, basedir scm option, ...)
- improve tcwg-regression
- boot kernel after build
* Benchmarking: start to contribute
== Progress ==
o Linaro GCC/Validation (6/10)
* Validation/Infra patch reviews
* Upstream monitoring job
* Release automation:
- Reworking tcwg-release.sh
o Misc (4/10)
* Various meetings and discussions.
== Plan ==
o Focusing on release automation and validation
Achievements:
[TCWG-614] Range extension Thunks
- About 3 hours in total of rebasing due to upstream refactoring
- Have finished the non-linkerscript tests and fixed all the bugs
detected by them
- Started the linkerscript tests, no problems found so far
[TLS]
- Some explanation to upstream of how ARM TLS works
- Discovered that upstream have broken TLS global-dynamic for
executables, I have a fix but will need to write a test case.
Plans for next week:
- Euro LLVM Monday, Tuesday
- Continue with TCWG-614
-- Try and link clang (> 30 Mb) to test range thunks on some real programs
-- Aim to get something ready for upstream review by end of week, may
slip to beginning of next week depending on if I find any hard to
debug problems.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [6/10]
** Pushed a fix to AArch64 process record bug on PRFM instruction.
AArch64 native test looks good now.
** Start to look at ARM native test, triage the fails in
watch-bitfields.exp. Test doesn't fail on old Linux kernel, likely
a kernel bug. Further analysis is needed.
** Request reverting Intel btrace python interface before release, as
they are too btrace-specific.
** Fixing a bug about thread_info refcount issue. Testing the patch.
* Discussion on RTOS awareness in debugging. OpenOCD people want GDB
aware more about different RTOSes. [1/10]
* TCWG-1040, SVE patches review, [2/10]
* Misc, [1/10]
~ Plan ~
* Take a look at native ARM testing, and cross testing.
* Post my fix to thread_info refcount issue.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037] [3/10]
- Got some patches ready but they depend on the TableGen support for
predicates, which has not been committed upstream yet
* [GlobalISel] Use proper calling conv for calls [TCWG-1051] [1/10]
- Patch accepted upstream, will commit next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Started migrating tcwg-release-tools to Python 3, still in progress
* Misc [5/10]
- Mailing lists, code reviews, buildbot monitoring, catching up after Connect
- LLVM social in Stockholm
- Fiddling with the new container for our LLVM buildmasters
== Plan ==
* Commit TCWG-1051, maybe TCWG-1037 too depending on upstream progress
* More GlobalISel code reviews
* TCWG-896
* Out of office for EuroLLVM (24 - 29 March)
[TCWG-614] Range extension Thunks
Worked all week on this. I've got a prototype that is nearly feature
complete. It passes the existing tests when run in a single pass. I'm
now trying to get it to run in multiple passes.
Plans
[TCWG-614] Range extension Thunks
Start adding tests for the new functionality and doubtless spending a
lot of time fixing problems. If I'm lucky I may have something that I
can at least in part send upstream for review by the end of the week.
~ Progress ~
* Three days off [6/10]
* TCWG-1050, GDB 8.0 release. [2/10]
Pushed in some patches fixing ARM reverse debugging bug.
Investigating a GDB internal error.
Review Python btrace stuff, still trying to make it more generic.
* Misc, [2/10], catch up emails
~ Plan ~
* TCWG-1050.
* Review IBM linux kernel awareness patches.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.03 snapshot of the Linaro GCC 6 source package.
This monthly snapshot[1] is based on FSF GCC 6.3+svn246148 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246148
* Backport of [Bugfix] [AArch64] PR target/71112 ICE with -fpie on
aarch64 ILP32 big-endian
* Backport of [Bugfix] [AArch64] PR target/71727 -O3 -mstrict-align
produces code which assumes unaligned vector accesses work
* Backport of [Bugfix] [AArch64] PR target/78382 ICE when compiling on
aarch64 in ILP32 mode with traditional thread local storage and pic
* Backport of [AArch32] Add vfpv2 and neon-vfpv3
* Backport of [AArch32] Fix assembly comment syntax in -mprint-tune-info
* Backport of [AArch64] Add commandline support for -march=armv8.3-a
* Backport of [AArch64] Expand DImode constant stores to two SImode
stores when profitable
* Backport of [AArch64] Fix aarch64 PGO bootstrap
* Backport of [AArch64] Fix exception handling for ILP32 aarch64
* Backport of [AArch64] Have the verbose cost model output output be
controllable
* Backport of [AArch64] Implement popcount pattern
* Backport of [AArch64] Optimized implementation of search_line_fast
for the CPP lexer
* Backport of [AArch64] Use new target pass registration framework for
FMA steering pass
* Backport of [Testsuite] [AArch32] Add Cortex-A15 tuning to
gcc.dg/uninit-pred-8_a.c
* Backport of [Testsuite] [AArch32] Skip optional_mthumb tests if GCC
has a default mode
* Backport of [Testsuite] [AArch32] Updating testcase unsigned-extend-2.c
* Backport of [Testsuite] [AArch64] Fix
gcc.dg/torture/float32-builtin.c with RTL checking
* Backport of [Testsuite] [AArch64] PR middle-end/78142 more registers
to be used for on gcc.target/aarch64/vector_initialization_nostack.c
* Backport of [Cleanup] [AArch32] Define arm_arch_core_flags in a single file
* Backport of [Cleanup] [AArch32] Remove unimplemented option -macps-float
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
* 2 days out of office (Thursday & Friday)
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
- Committed support for GEPs and 32-bit constants, which enables us
to put call parameters on the stack
- Proposed a fix for an AArch64 issue where the size of the stack
was computed incorrectly if the last parameter was sign- or
zero-extended into a stack slot
* Misc
- Mailing list etc.
== Plan ==
* Connect
2 day week:
== Activity ==
[TCWG-617] Range extension thunks
- rebased patch after coming back from holiday, took some time as
quite a bit had changed, patch still in upstream review.
- Have downstream patches to make inline thunks work with linker
scripts, will post for review next week.
== Plan ==
At linaro connect all next week
== Planned absences ==
Euro LLVM 27-28 March
~ Progress ~
* GDB 8.0 release, TCWG-1050, [5/10].
Release branch will be created on March 15th.
Fixed some instruction decoding in reverse debugging. Tested.
Added a unit test for arm process recording for some instructions.
To be posted upstream.
PR gdb/21165 is fixed.
* SVE GDB patches review, TCWG-1035, [3/10]
SVE patches review. One of Alan's patch is to remove some lines of
code written 19 years ago, which was to fix a bug at that moment.
A lot of archeology. Hopefully the author is still in RedHat, and
get more information on the fix. Alan's patch is correct.
* Upstream patches review. [2/10]
** Some python bindings on intel btrace. Make it more portable,
hopefully these python apis can be used for CoreSight in the
future.
~ Plan ~
* Linaro Connect.
* March 13th -- 15th, holiday.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Fix atomic loads/stores after r294993 [TCWG-1041] [1/10]
- For the moment we just bail out if we have any atomic loads /
stores. This is better than silently replacing them with non-atomic
operations.
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038] [6/10]
- Committed support for calls with args/returns in registers (ints,
pointers, floating point)
- Found and reported a bug in the AArch64 backend
- Working on lowering stack arguments: committed support for stores,
still working on adding support for GEPs and constants so we can
actually compute the addresses that we have to store to
* Misc [3/10]
- Meetings, mailing lists, code reviews
- Connect slides
- Buildbots (reverted patches with flaky tests, fixed mips-specific
test to run only when mips is built)
== Plan ==
* Out of office on Thursday and Friday
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
== Progress ==
* Validation
- more work on use of containers, ssh-agent & jenkins problems
- added an experimental job to prepare the migration to
the new scripts
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Holidays next week
* Connect
