== This Week ==
* ipa mod/ref analysis (2/10)
- Prototype patch now detects modifications to reference parameters
- Working on mod/ref analysis of global variables.
* PR35691 (2/10)
- Patch iterations based on upstream review
* PR35503 (2/10)
- Patch approved by Jason
- Building kernel with patch resulted in two warnings.
* Public Holidays (4/10)
== Next Week ==
- IPA mod/ref prototype
- Bugs
-- Activity --
[TCWG-683] Branch to undefined weak on aarch64 and arm
Fix in upstream review, looks pretty close to being accepted.
[TCWG-828] TLS support for static linking
In upstream review but no comments as yet
[TCWG-829] IFunc support
In upstream review, but will probably need to be rewritten after some
upstream refactoring has finished
[TCWG-911] eglibc requires a SHT_ARM_ATTRIBUTES section for dlopen to work
I have a quick hack to work round this on my Chromebook but a full fix
will take some time as lld doesn't understand build attributes right
now.
[TCWG-901] Investigate lld as a system linker
With downstream fixes, using lld as the system linker on a Chromebook I can :
- Build llvm, lld and run the regression tests successfully
- Use lld as the linker in the lnt tests successfully
- Using lld to build the shared objects used by lnt's python C
extensions was less successful. I have some interesting debugging to
do.
-- Plan --
Debug the python extension problems
Respond to upstream review comments
More use of lld as system linker
== Progress ==
* [ARM] Investigate switching from itineraries to schedule models
[TCWG-824] [4/10]
- Looked at the sched model as well as the old instruction itinerary
interfaces
- There aren't many tests that are specifically testing the scheduler,
but lots of tests break if you make enough changes to it (it's unclear
which of these are breaking intentionally and which are just poorly written)
- First step is probably to try and complete the sched model (TCWG-543),
then hunt down any differences between what we get using itineraries and
what we get with the new model
* Rewrite llvm-projs in Python [TCWG-833] [3/10]
- Reorganized the repo so we can have a separate tests directory
- Added support for parsing command line options
- Almost ready for review
* Misc [2/10]
- Catching up after vacation
- LLVM GitHub move survey
== Plan ==
* Wrap up TCWG-833
* Migrate scripts to Python 3 (TCWG-896)
* Maybe start TCWG-543 as the first step in TCWG-824
# Progress #
* TCWG-547, Change software_single_step interface to return a vector
of address. [3/10]
Patches are reviewed. V2 are posted and committed. Follow-up
patches are being tested.
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode. [3/10]
Clean up val_print, remove one redundant parameter. Patches are
being tested.
* Maintain upstream GDB, patches review, [2/10]
* OpenOCD. [2/10] Various IRC chats with maintainer about
** multi-thread support in RTOS, and multi-thread debugging,
** Release 0.10.0 and aarch64 patches merging,
** Understand aarch64 OpenOCD reads DSPSR (32-bit), so don't have to
update GDB target description now.
* Short chat with Peter Griffin on thread ids in linux-kthread.
# Plan #
TCWG-547, TCWG-333.
--
Yao Qi
# Progress #
* Fix GDBserver build on aarch64_be. [1/10]
Done. Patch is pushed in to master and 7.12 branch.
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode. [4/10]
Get anther patch and fix all regressions. In the discussion
with ppc64 and mips people on my approach.
* TCWG-518, Range stepping in arm-linux. Done. [1/10]
After pending for several months, patches are approved. Pushed
them in!
* Reproduce the GCC dwarf generation regression. [1/10]
Reported to GCC and Jakub fixed it.
* Sort out the license issue of new OCaml debugging support in gdb.
Help to clarify a little bit. [1/10]
* Discuss with OpenOCD people on supporting thread awareness for
RTOS. [1/10]
* Misc, meeting. [1/10]
# Plan #
* TCWG-333, TCWG-547
* Add new aarch64 target description for 64-bit xPSR.
--
Yao Qi
o 2 days off (4/10)
== Progress ==
o Linaro GCC/Validation (4/10)
* ABE and validation jobs reviews
* Investigating binary tarballs size reduction
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on validation
o Complete 4.9 branch merge
* TCWG-72 (2/10)
- Committed to trunk finally!
* ipa mod/ref analysis (6/10)
- Prototype in progress based on Muchnik's text
* Misc (2/10)
- Committed a trivial patch to use VAR_P in arm.c.
- Background reading on paper about virtual-ssa.
- Meetings
== Next Week ==
- Continue with mod/ref analysis
- TCWG-319
- Ping patch for GCC PR35503.
# Progress #
TCWG-845 Static linking missing linker defined symbols
- Now upstream
TCWG-829 Support for ifunc
- Patch sent upstream for review, no feedback yet. This is a bit messy
as ARM is different to other architectures so I expect this to need
reworking several times.
TCWG-828 Static linking and TLS
- Downstream patch implemented and tested, will send upstream after ifunc
TCWG-683 Support for branches to undefined weak references
- Downstream patch implemented and tested
Other:
- Downloaded and built Mozilla and Chromium so I can use them as
performance tests for lld (initially for x86_64).
- Wrote some scripts to make using lld in place of gnu ld a bit more convenient.
# Plan #
- Upstream static linking changes
- Work some infrastructure to test lld more widely on ARM.
o 2 days off (4/10)
== Progress ==
o Linaro GCC/Validation (4/10)
* Completed GCC 5 and 6 branch merges
* Released source 2016.10 snapshots
o Upstream GCC (1/10)
* Investigate PR #78020 (vzip, vuzp implementation).
o Misc (1/10)
* Various meetings and discussions.
== Plan ==
o Two more days off
o Back on 4.9 branch merge and validation.
The Linaro Binary Toolchain
============================
The Linaro GCC 6.2-2016.11-rc1 Release-Candidate is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release-candidate packages from:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11-rc1/http://snapshots.linaro.org/components/toolchain/binaries/6.2-2016.11-rc1/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.2-2016.11-rc1
Linaro glibc 2.23 (linaro/2.23/master)
https://www.sourceware.org/ml/libc-alpha/2016-08/msg00212.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
Linaro binutils 2.27 (linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 7.12 (gdb-7.12-branch)
https://sourceware.org/ml/gdb/2016-08/msg00000.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 6.2-2016.11-rc1
====================================
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and will appear in this release.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was also added to this binary releases (for linux
targets).
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 022bd2995640626d9efb6a839884c5e1c7c5e133
Author: Christophe Lyon <christophe.lyon(a)linaro.org>
Date: Wed Oct 19 14:11:50 2016 +0200
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit 5357441171f2409fb759112bc6a00d3e672374d9
Author: Christophe Lyon <christophe.lyon(a)linaro.org>
Date: Wed Oct 19 14:09:51 2016 +0200
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit f194ff4d5e1e304ac2a8d438d7abcbffd2dba757
Author: Christophe Lyon <christophe.lyon(a)linaro.org>
Date: Wed Oct 19 14:05:23 2016 +0200
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit bda499cb9d2b97075f74df9bfb38b23ff4d12ac2
Author: Christophe Lyon <christophe.lyon(a)linaro.org>
Date: Wed Oct 19 13:59:52 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Added __ASSUME_REQUEUE_PI support to Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Added __ASSUME_SET_ROBUST_LIST support to Linaro glibc 2.23 branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Added __ASSUME_FUTEX_LOCK_PI support to Linaro glibc 2.23 branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* Include GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Copy the libwinpthread DLL into the bin directories so it gets into
the tmp directory before tar is run.
https://review.linaro.org/#/c/13723/
* Include GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from Linaro GCC 6.1-2016.06, Linaro GCC
6.1-2016.07, Linaro GCC 6.1-2016.08, Linaro GCC 6.2-2016.09, and
Linaro GCC 6.2-2016.10 have been included.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
== Progress ==
LTO/IPA
- Committed propagation of nonnull attribute and optimizations
- Committed patch to infer noonull from ADDR_EXPR
- Working on a patch to improve ipa-cp unary expressions pass
through jump-function
* LTO bootstrap is failing in streaming but normal bootstrap working
* Looking into it
== Next ==
- Commit pending patches
- Start LTO benchmarking and analysis
== This Week ==
* TCWG-72 (2/10)
- Updated patch based on Jeff's suggestions.
* Folding optimizations (2/10)
a) PR53979 - fix committed to trunk
b) PR71636 - fix committed to trunk
* TCWG-665 (2/10)
- Rebased patch and done few modifications
- Trying to look for a better solution to workaround a memory leak
issue with patch
with -ffat-lto-objects
* PR35503 (1/10)
- Rebased patch on top of Marek's changes to c-common.c and pinged upstream.
* Validation (1/10)
- Added spec2k and spec2k6 to tcwg-buildapp
- Fixed abe bug 1439
* Misc (2/10)
- Reading up on mod/ref analysis.
- Meetings
== Next Week ==
- TCWG-72, TCWG-665, TCWG-125
- Look into changing user to "benchmark" for tcwg-buildapp job.
== Progress ==
TCWG-610 ARM Exceptions support
Now fully committed upstream. We should now have support for
exceptions in Shared Objects and Executables.
I've diagnosed problems when static linking after staring at a
disassembly for most of a day. With some hacks I've managed to get a
static link working using a recent Linaro sysroot. Next task is to
resolve these in a more principled way.
TCWG-845 Static linking missing linker defined symbols
- lld doesn't use a built in linker script so we need to add in
symbols that libc.a is expecting the default linker script to
generate.
- lld is defining __tls_get_addr as it expects all TLS to be relaxed,
this isn't the case for ARM or Mips so we need to not define it.
TCWG-829 Support for ifunc
For some annoying reason that I can't work out why, ARM requires the
R_ARM_IRELATIVE relocations to be in the .rel.dyn and not .rel.plt
like all the other targets that lld supports including AArch64
TCWG-828 Static linking and TLS
When static linking the TLS dynamic relocations in the .got must be
resolved statically.
- The other architectures that lld supports have the thread control
block (tcb) after the data so the initial-exec relocations don't need
to add the tcb size to the value put into the .got.
- The module index dynamic relocation needs to be 1 and not 0 (LLD
assumes general dynamic is relaxed away at static link-time).
TCWG-683 Support for branches to undefined weak references
LLD doesn't resolve these to the next instruction so they just hang at runtime.
Some feedback and review for Linaro LLVM team processes.
== Plans ==
Work out a proper solution for TCWG-828 then start upstreaming.
TCWG-683 can be worked around by providing an empty definition of the
function, all the others need to be fixed to get a static libc to
link.
# Progress #
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode. [4/10]
Get review comments and suggestions. Tried to do what they suggested,
but it doesn't work well due to some reasons. Preparing the the reply to
address their comments.
* TCWG-416, Improve GDB performance in remote debugging. [2/10]
Patches for ARM and AArch64 are ready. Need to measure the
performance improvement.
* OpenOCD. [2/10]
Chat with people working on AArch64 support on irc. Help him
understanding GDB and GDB remote protocol. Patches are there, but
need to figure out how to help to get these patches merged.
* Misc, [2/10]
Meeting, and various discussions.
# Plan #
* Continue all above.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.10 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn241214 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.11
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.2+svn241214
* Backport of [Bugfix] PR libgcc/77519: Correct libgcc complex
multiply excess precision handling
* Backport of [Bugfix] PR target/63250: Enable HCmode multiply and
divide (mulhc3/divhc3)
* Backport of [AArch32/AArch64] Add qdf24xx base tuning support
* Backport of [AArch32] [ARMv8.2] 1/17 Add ARMv8.2-A command line
option and profile
* Backport of [AArch32] [ARMv8.2] 2/17 [testsuite] Add a selector for
ARM FP16 alternative format support.
* Backport of [AArch32] [ARMv8.2] 3/17 [testsuite] Add ARM support for
ARMv8.2-A with FP16 arithmetic instructions
* Backport of [AArch32] [ARMv8.2] 4/17 Define feature macros for FP16
* Backport of [AArch32] [ARMv8.2] 5/17 Enable HI mode moves for
floating point values
* Backport of [AArch32] [ARMv8.2] 6/17 Add data processing intrinsics
for float16_t
* Backport of [AArch32] [ARMv8.2] 7/17 Add FP16 data movement instructions
* Backport of [AArch32] [ARMv8.2] 8/17 Add VFP FP16 arithmetic instructions
* Backport of [AArch32] [ARMv8.2] 9/17 Add NEON FP16 arithmetic instructions
* Backport of [AArch32] [ARMv8.2] 10/17 Refactor support code for NEON builtins
* Backport of [AArch32] [ARMv8.2] 11/17 Add builtins for VFP FP16 intrinsics
* Backport of [AArch32] [ARMv8.2] 12/17 Add builtins for NEON FP16 intrinsics
* Backport of [AArch32] [ARMv8.2] 13/17 Add VFP FP16 instrinsics
* Backport of [AArch32] [ARMv8.2] 14/17 Add NEON FP16 instrinsics
* Backport of [AArch32] [ARMv8.2] 15/17 Add tests for ARMv8.2-A FP16 support
* Backport of [AArch32] [ARMv8.2] 16/17 Add tests for VFP FP16 ACLE instrinsics
* Backport of [AArch32] [ARMv8.2] 17/17 Add tests for NEON FP16 ACLE intrinsics
* Backport of [AArch32] [ARMv8.2] Delete one redundant word in
target-supports.exp comment
* Backport of [AArch32] [ARMv8.2] Enable mov[hsd]i_movw tests on ARM
and big endian
* Backport of [AArch32] [ARMv8.2] Fix invalid instructions generated
for data movement.
* Backport of [AArch32] [ARMv8.2] Fix invalid instructions generated
for data movement.
* Backport of [AArch32] [ARMv8.2] Fix new constraints and attributes
of SI/HI data movement patterns
* Backport of [AArch32] [ARMv8-M] Add support for ARMv8-M
* Backport of [AArch32] [ARMv8-M] Add support for CB(N)Z and (U|S)DIV
to ARMv8-M Baseline
* Backport of [AArch32] [ARMv8-M] Add support for MOVT/MOVW to ARMv8-M Baseline
* Backport of [AArch32] [ARMv8-M] Check CLZ availability with ISA
support and architecture level macros
* Backport of [AArch32] [ARMv8-M] Enable atomics for ARMv8-M Mainline
* Backport of [AArch32] [ARMv8-M] Factor out MOVW/MOVT availability
and desirability checks
* Backport of [AArch32] [ARMv8-M] Fix indentation of FL_FOR_ARCH*
definition after adding support for ARMv8-M
* Backport of [AArch32] [ARMv8-M] Fix pr42574.c selector syntax error
* Backport of [AArch32] [ARMv8-M] Fix Thumb-1 only == ARMv6-M &
Thumb-2 only == ARMv7-M assumptions
* Backport of [AArch32] Fix RTL checking failure in Thumb mode
* Backport of [AArch64] Add __artificial__ attribute to Aarch64 NEON intrinsics
* Backport of [AArch64] Add missing attributes to arm_neon.h
* Backport of [AArch64] Add more NEON intrinsics vmaxnm_f64,
vminnm_f64, vmax_f64, vmin_f64
* Backport of [AArch64] Add tunning of ldpw for THunderX
* Backport of [AArch64] Fix __builtin_aarch64_fmindf
* Backport of [AArch64] [ARMv8.2] 1/4 ARMv8.2-A FP16 testsuite selector
* Backport of [AArch64] [ARMv8.2] 2/4 ARMv8.2-A testsuite for new data
movement intrinsics
* Backport of [AArch64] [ARMv8.2] 3/4 ARMv8.2-A testsuite for new
vector intrinsics
* Backport of [AArch64] [ARMv8.2] 4/4 ARMv8.2-A testsuite for new
scalar intrinsics
* Backport of [Misc] Allow simple register subregs in noce_convert_multiple_sets
* Backport of [Misc] Fix native_encode_real for HFmode constants
* Backport of [Misc] Modify extend_mask to extend bits based on signop
* Backport of [Testsuite] [AArch32] Fix prototype in vst1Q_laneu64-1.c
* Backport of [Testsuite] [AArch32] neon-testgen.ml removal
* Backport of [Cleanup] Fix typo in comment in tree-ssa-strlen.c
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn241215 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.11
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.4+svn241215
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Hi all.
I've incorrectly reported a build failure in the support system.
<https://support.linaro.org/hc/en-us/requests/1876>
-But I'm posting a copy to this list, in order to follow Victor's advice.
I've suggested a couple of changes, which makes ABE a little more compatible.
Though I can still not build the toolchain on my PowerBook G4, I think that my two modifications might ease building on Intel based Macs and perhaps other architectures in addition.
In short:
* Use getconf instead of /proc/cpuinfo (you're already using getconf in configure.ac).
* By default use twice as many cores for -jN as usual. (If you have 2 cores, use -j4)
* Change the architecture from 'Power Macintosh' (which contains an offending space) to 'powerpc'.
...And here's "configure.ac.patch":
---8<-----8<-----8<-----
diff --git a/configure.ac b/configure.ac
index 1bf3593..8cc4986 100644
--- a/configure.ac
+++ b/configure.ac
@@ -49,9 +49,10 @@ AC_SUBST(DBPASSWD)
DBHOST=${dbhost}
AC_SUBST(DBHOST)
-CPUS="`grep -c proces /proc/cpuinfo`"
+
+let CPUS=2*`getconf _NPROCESSORS_ONLN`
AC_SUBST(CPUS)
-CORES="`grep cores /proc/cpuinfo | tail -1 | cut -d ' ' -f 3`"
+#CORES="`grep cores /proc/cpuinfo | tail -1 | cut -d ' ' -f 3`"
AC_SUBST(CORES)
LIBC="`getconf GNU_LIBC_VERSION`"
AC_SUBST(LIBC)
@@ -59,6 +60,7 @@ KERNEL="`uname -r`"
AC_SUBST(KERNEL)
BUILDHOST="`${srcdir}/config.guess`"
BUILD_ARCH="`uname -m`"
+[[ "`uname -s`" == "Darwin" ]] && BUILD_ARCH="`uname -p`"
AC_SUBST(BUILD_ARCH)
AC_SUBST(BUILDHOST)
HOSTNAME="`uname -n`"
--->8----->8----->8-----
Apart from that, I'd like to report a successful build on Cubieboard2 running Armbian.
I built for the aarch64 architecture, and I'm currently attempting to build Armbian for beelink GT1 using the new shiny Linaro toolchain. :)
...and what a pleasure, there's no fan-noise when building on the Cubieboard2!
Love
Jens
Just been trying to build the Linaro toolchain from source on RHEL 6.5. The ABE configure script fails to detect the packaging system on RHEL as it looks like RPM will only be detected if it's running on a Fedora system. This patch will instead detect RPM if the rpm binary is available (and it's not Debian/Ubuntu), like the test for Arch/pacman.
diff --git a/configure b/configure
index 42f787e..52ddd42 100755
--- a/configure
+++ b/configure
@@ -3639,7 +3639,6 @@ fi
# Figure out which packaging system is in use. Since it's possible to
# install both on a system.
-rpm="`uname -a | grep -ic '\.fc[0-9].\.'`"
deb="`uname -a | grep -ic 'ubuntu'`"
deb=$(($deb + `uname -a | grep -ic 'debian'`))
@@ -3672,7 +3671,9 @@ $as_echo "yes" >&6; }
### RPM Packages ###
else
-if test ${rpm} -eq 1; then
+rpm="`which rpm 2> /dev/null`"
+result=$?
+if test ${result} -eq 0; then
packages="${packages} ncurses-devel python-devel"
for i in ${packages}; do
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if $i is installed" >
Regards,
Scott.
Hi Christophe,
Here are the commits, in order, that Adhemerval did to support 48-bit
VMA on AArch64.
r275792: [asan] Enable 48-bit VMA support on aarch64
r277137: tsan: Enable 48-bit VMA support on aarch64
r279752: msan: Enable 48-bit VMA support on aarch64
r279753: dfsan: Enable 48-bit VMA support on aarch64
Currently, all sanitiser tests pass on Ubuntu Xenial on the LLVM side.
cheers,
--renato
== Progress ==
LTO/IPA
- Committed ipa-vrp and early-vrp improvements
- Patches for propagation of nonnull and optimization are accepted;
Will commit after testing (once again)
- Noticed some improvements but full benchmarking not yet done
- Setting up the benchmarking infrastructure
== Next ==
- Commit pending patches
- Start LTO benchmarking and analysis
== Progress ==
o Linaro GCC/Validation (7/10)
- Completed backports for monthly snapshots (dependency tracking).
- Prepared branch merges for branches 5 and 6
- ABE reviews
- New jenkins job to compare toolchains
(goal is to use it for development and to refactor current jobs).
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o Release 2016.10 snapshots
o On Vacation from Thu 20th to Tue. 24th.
== This Week ==
* TCWG-72 (3/10)
- Committed patch to remove optab functions for [us]divmod_optab after
Bernd's approval.
- My assumption that __udivmoddi4 is generically available is perhaps
wrong, call to __udivmoddi4
generates undefined reference error on aarch64-linux-gnu. To be
safe, I dropped generating call
to __udivmoddi4.
- Patch posted upstream
* TCWG-834 / PR71636 (1/10):
- Patch posted upstream.
* Misc (2/10)
- PR35503: Changes to C++FE approved by Jason, waiting for approval to
C, C-family changes.
- Posted patch upstream to add reverse keyword to genmatch
- Posted patch for abe bug 1439
- Meetings
* Public Holidays (4/10)
== Next Week ==
- TCWG-72, TCWG-665, TCWG-319
- Add support to tcwg-buildapp for SPEC2000 and SPEC2006.
== Progress ==
* Test GlobalISel on AArch64 Linux [TCWG-825]
- Got the existing tests to work on Linux - luckily this only required
changes to the tests and not to GlobalISel itself; committed these changes
upstream
- Ran the test-suite with GlobalISel and with the fallback to the old DAG
ISel enabled; only 57 object files can be compiled with GlobalISel only,
the others need the fallback to the old ISel; also, there are crashes in
over 500 of the tests
* Rewrite llvm-projs in Python [TCWG-833]
- Rewrote the core functionality of the script and added tests
- Still have to implement the command line interface
* Handle special cases in AArch64InstrInfo::GetInstSizeInBytes [TCWG-757]
- Committed upstream
* [AArch64] CMP + label arithmetic not supported [TCWG-710]
- Committed upstream
* Misc
- Upstream code review
- Linaro annual performance review
- Had a quick look at a hanging check-all in one of the AArch64
buildbots; I identified the hanging test as one of the TSAN tests, but I
didn't manage to reproduce the issue locally (since the tests run in
parallel, it's possible that there's a subtle interaction between them);
I've seen other buildbots (PowerPC) similarly hanging every now and then,
but I'm not sure it's the same issue; will keep an eye on it though.
== Plan ==
* 2 weeks off
# Progress #
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode. [4/10]
Finish the patch, tested it on arm and ppc64. Post patches for
review.
* TCWG-556, aarch32 GDB buildbot slave. In progress. [1/10]
Sergio needs to adjust buildbot setting to customize my buildslave.
* TCWG-547, [2/10]
Ping the patch series, and commit some obvious ones.
* Misc, [3/10]
** Ask two people about using OpenOCD with AArch64 board.
** Review kernel patch to fix kernel limitation of byte address select.
Patches look good, but GDB needs to detect that such limitation is
removed.
** Read "C++ Primer". Need more knowledge on C++.
# Plan #
* Other thing on OpenOCD,
* TCWG-167, TCWG-416,
--
Yao Qi
* 3 days off
* Connect week
== Progress ==
* Validation
- patch reviews (jenkins jobs, abe)
* GCC
- reported a few regressions on trunk, helped validating fixes
- ran benchmarks with "deprecated IT blocks" patch.
A few regressions, need to reproduce on other HW
* Binutils
- fixed https://sourceware.org/bugzilla/show_bug.cgi?id=20608
"Relocation truncated to fit: R_ARM_THM_JUMP24 for relocation to PLT entry"
- requested backport approval for branches 2.26 and 2.27, but
no answer so far
* misc (conf-calls, meetings, emails, ....)
== Next ==
* (try to) handle backlog of GCC trunk regressions
* ABE patches reviews and bug fixes
* backports/reviews
* GCC: run benchmarks on other HW
o Two days off post-connect (4/10)
== Progress ==
o Linaro GCC/Validation (3/10)
- Restart work on 4.9.4 branch merge.
- Restart backport activity.
- Investigate binary release size issue (Lin. bug #2544)
o Misc (3/10)
* Various meetings and discussions.
* Reviewing release tools branch
== Plan ==
o Continue on-going tasks (backports, 4.9.4 merge, release tools)
o ABE bugzillas
== This Week ==
* TCWG-807 (2/10)
- Upstream patch iterations with Honza and Martin.
- Committed to trunk as r240898.
* TCWG-779 (1/10)
- Changed %Z specifier to take int*, unsigned len args instead of vec<int>
for easier format checking.
- Committed diagnostic.c and diagnostic-core.h changes.
- Waiting for approval for other parts of the patch.
* Misc (1/10)
- Committed patch to fix typo in bits propagation
- Committed patch for freeing m_vr and bits in ipcp_transform_function
* Holidays (6/10)
== Next Week ==
- Abe bug 1439
- Extend tcwg-buildapp to include SPEC2000
- Address reviews for TCWG-779
- Look at checked exceptions nothrow propagation.
- TCWG-319
== Activity ==
- AFDS and AFDS review comments
LLD:
- Have nudged the ARM exceptions story in lld along a bit, I've had
one patch accepted, but not the most important one.
- Updated the Linaro TCWG jira issues post Connect
- Worked on static linking and ifunc support. I have managed to get
ifunc working for dynamic linking and static linking working for an
old ARM only sysroot. The latest Linaro linux-gnueabi-hf sadly
segfaults in __libc_init_first -> __ctype_init, with what looks like
stack corruption of the return address. I at least have a good idea of
what needs to be done to make static linking work.
Other LLVM:
Some upstream review comments for ILP32 support and others.
== Plans ==
On holiday all week. Will attempt to continue upstreaming lld work
that I already have patches and tests for.
# Progress #
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode.
[3/10] Recall some discussions on it in GNU Cauldron, and
dig into GDB source. Unfortunately, GDB decides to track
function address rather than function pointer in 2001, which
makes harder to fix it. Still thinking about it.
* TCWG-556, aarch32 GDB buildbot slave. [2/10]
Build GDB and test cases in arm on an aarch64 machine. There are
1000+ test fails, but not triaged yet. Discussed upstream on how to
set up buildbot slave with special configuration option and test
board file. Ongoing.
* TCWG-685, GDB 7.12 release, and patches review. [1/10].
All blocking issues are gone. 7.12 should be released soon.
* Clean up arm xml files. Done. [3/10]
* Misc, meetings. [1/10]
# Plan #
* TCWG-333, TCWG-556.
* As 7.12 goes out, ping my pending patches on TCWG-518, and TCWG-547
--
Yao Qi
== Progress ==
* [Lab] ASAN test fails with glibc 2.23 [TCWG-811]
- Recommitted upstream after discussing with Adhemerval at Connect
(thanks, Adhemerval)
- The bot is now upstream
* Add worktree module to tcwg-release-tools [TCWG-783]
- In review. Trying to use it in our llvm-projs helper script
* Investigate buildbot failure on clang-native-arm-lnt [TCWG-832]
- Found and reverted the offending patch
- Ran a pre-commit test on the second version of the patch
* [Lab] Xenial Stage1 test failure: std::length_error [TCWG-821]
- Couldn't use gdb on this, so I had to manually find the call that
throws the exception; the code seems to be doing the right thing, and
in addition selfhosting works, so we're suspecting either some
undefined behaviour or a bug in the g++ toolchain on the bot
- Neither ubsan nor clang-tidy had much to complain about the code,
so this will require more investigation
* Misc
- Upstream code reviews, meetings etc
== Plan ==
* [Lab] Xenial Stage1 test failure: std::length_error [TCWG-821]
* [ARM] Switch from itineraries to schedule models [TCWG-824]
== Progress ==
* [Lab] ASAN test fails with glibc 2.23 [TCWG-811] [4/10]
- This issue is keeping us from moving one of the TK1 bots into production
- Committed a patch upstream, but it broke on an x86_64 bot when
compiling with -m32
- I tracked the problem to the wrong glibc function being used when
-fsanitize=address is provided on the command line
- Reported the problem on the mailing list
* Add worktree module to tcwg-release-tools [TCWG-783] [4/10]
- Made good progress on this, should be ready for review soon
* Misc [2/10]
- Code reviews, preparing for Connect
== Activity ==
Exceptions.
Another attempt at ARM exceptions support. I did get some more fine
grained comments back which have been addressed, but no approval to
commit yet.
Some follow up over whether ld -r support for merging output sections
is necessary, answer seems to be yes as kernel modules depend on it.
I've volunteered to post a simpler patch without ld -r support as this
is a very niche use case. Not had any feedback yet so will just post
it next week.
TLS
Fixed TLS support in lld so that it does not attempt to follow lld's
generic relaxation model, which can't be implemented in ARM. Still
some work to do for static linking.
== Next Week ==
Out of office at Linaro Connect in Las Vegas
== Planned Absences ==
Holiday 10th to 14th October
* Two days off [4/10]
# Progress #
* TCWG-685, GDB 7.12 release. [2/10]
Patch "keep RES0 bits in CPSR" is pushed into mainline and 7.12.
Find a GDBserver bug, and open PR 20627. It is target independent,
but may block the release. :(
* TCWG-518, Range stepping in ARM. [3/10]
Regression test is done. Find some other issues exposed by my
patches, and fix them. Need to post patches upstream for review.
* Misc [1/10]
Close gdbserver in mi_gdb_exit. The bug breaks the aarch64 multi-arch
testing. Patch is pushed in.
File expense for GNU Cauldron travel.
# Plan #
* Linaro Connect.
--
Yao Qi
Hello,
I'm using Linaro GCC 4.9-2015.01-3 for AArch64, and trying to disable the
generation of guarded instructions. More specifically, I'd like not to see
instructions such as 'cset', 'csinc', 'ccmp', 'fccmp', etc.
So far, it seemed that the flag '-fno-if-conversion2' could do the job, but
I still see those instructions in my disassembled program functions (I
guess that it may not be possible to remove them from standard libs).
My command line:
aarch64-linux-gnu-gcc -static -march=armv8-a -O3 -fno-strict-aliasing
-fno-if-conversion2
I also tried '-fno-if-conversion' and both '-fno-if-conversion
-fno-if-conversion2' without success.
Regards,
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
o Travel from Cauldron (2/10)
o One day off (2/10)
== Progress ==
o Linaro GCC/Validation (7/10)
- Started backports for 2016.10
- Investigating 4.9.4 branch marge validation issues
- Extended validation monitoring, tried to reproduce an OOM issue.
o Misc (3/10)
* Various meetings and discussions.
* Connect preparation
== Plan ==
o Tuesday off
o Continue on-going tasks and travel to LAS16
== Progress ==
* Validation
- patch reviews (Jenkins jobs, abe)
* GCC
- reported a few regressions on trunk
- looked at making reporting scripts more robust
at handling DejaGnu errors that could otherwise
be un-noticed
* Binutils
- backported a fix from trunk to linaro-2.27 branch, to close bug
2518 (linker SEGV)
- investigating https://sourceware.org/bugzilla/show_bug.cgi?id=20608
"Relocation truncated to fit: R_ARM_THM_JUMP24 for relocation to PLT entry"
* misc (conf-calls, meetings, emails, ....)
- Connect preparation
== Next ==
- monitor GCC trunk regressions
- release scripts/abe
- backports/reviews
- Binutils bug 20608
== Progress ==
* Validation
- patch reviews (Jenkins jobs, abe)
- helped on release infra/scripts
* GNU Cauldron
- useful discussion with several maintainers
* GCC
- progress on PR 67591 (ARM v8 Thumb IT blocks deprecated)
First patch posted, I will need benchmark results.
* misc (conf-calls, meetings, emails, ....)
== Progress ==
- Connect slides
- Return jump function - working on prototype
- Revised and posted early-vrp
- Revised and posted patch for PR72835
== Next ==
- Work on IPA/LTO improvements
- Wrap-up connect slides
- Follow up on pending patches
== This Week ==
* TCWG-807 (4/10)
- Wrote patch for extending ipa-bits-cp with pointer alignment propagation,
* TCWG-779 (2/10)
- Removed obstack for fmt building and added %I to pp_format for
printing vec<int>
- Posted patch upstream for feedback
* TCWG-319 (1/10)
- Tried random hacks to lib/target-supports.exp, none of which worked :(
* TCWG-72 (1/10)
- Upstream discussion about optab_libfunc() issue with
Richard Sandiford and Richi
* Misc (2/10)
- Travel from Cauldron
- Meetings
- Lava job #1118698 failed with infrastructure error: "Unable to download",
restarted as #1123350
== Next Week ==
- Prepare slides for connect
- Continue ongoing tasks
== Progress ==
* [AArch64] Support for label arithmetic in the assembler [TCWG-710]
- 2 patches in upstream review
* Handle special cases in AArch64InstrInfo::GetInstSizeInBytes [TCWG-757]
- Committed a patch for stackmap / patchpoint sizes
- Since this was a bit cumbersome to test otherwise, I had to add
unit tests for it, which took a bit of CMake plumbing because these
are the first target-specific unit tests in LLVM
* Add worktree module to tcwg-release-tools [TCWG-783]
- Started working on it
* Misc
- Helped test/setup the new TK1 buildbots
== Plan ==
* Add worktree module to tcwg-release-tools [TCWG-783]
* Help get the TK1 buildbots into a stable state
* Ping upstream patches
* Off on Mon and Tue. [4/20]
# Progress #
* Range stepping in ARM. TCWG-518 [5/20]
The thread starvation is fixed by randomly
selecting pending events among threads. Being regression tested.
* GDB 7.12 release. TCWG-685. [4/20]
Due to the recent kernel change, single step in GDBserver stops
working, because new kernel becomes sensitive on writing RES0
bits in CPSR. Fixed in GDB side.
* GNU Cauldron. [7/20]
Discussed with GDB people on the projects we are
working on. Got some agreement on the general direction of some
projects. Discussed with the possible GDB changes to handle
variable length registers, such as SVE. Agreed to move ptrace-test
from sourceware to kernel tree. Sync on 7.12 release. Discussed on
AArch64 TLS var debug information, looks it is less complex than
expected.
# Plan #
* Off on Mon and Tue.
* TCWG-685, TCWG-518
* Prepare for the US travel.
--
Yao Qi
== Activity ==
Exceptions support in LLD; 3rd try at an implementation that will be
accepted upstream. Now implementation complete and passing my existing
tests but needs some more cases checked.
Helped track down an intermittent build bot failure to an ld stub
generation problem
Some upstream patch review
== Next Week ==
Add more test cases and send exceptions support upstream
Use some of the Cauldron slides to replace existing LLD ones in the
Connect presentation.
== Planned Absences ==
Holiday 10th - 14th October
Hi,
As painfully found out by mono team, if big/little cores have
different cache line sizes, __clear_cache doesn't work as expected.
This affects any home-grown cache flushing mechanism as well.
http://www.mono-project.com/news/2016/09/12/arm64-icache/
protip, if you suspect your application issues might related to
big.LITTLE, use taskset(1) or hwloc-bind(1) to tie the process to
either big or little cluster (or just a single core).
== Progress ==
- Still trying to get support for .ARM.exidx into upstream LLD, looks
like more changes are needed by the owners, but I think I should be
able to get this by the next report.
- LLVM Cauldron on Thursday. Trip report sent separately
- Holiday on Friday
== Next week ==
Planned:
- ARM Exceptions support in lld
- Further lld porting work
== Progress ==
- Connect slides
- Analyzed IPA-VRP performance for slides
- Started working on return jump function
- Reading C++ ABI and other documents referred in Honza's blog to
understand the C++ related issues in IPA/LTO
= Next ==
- Work on IPA/LTO improvements
- Benchmarking
- Follow up on pending patches
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.09 snapshot of the Linaro GCC 6 source package.
This monthly snapshot[1] is based on FSF GCC 6.2+svn239654 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.11
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/
Interesting changes in this GCC source package snapshot include:
* Backport of [Bugfix] [AArch32] PR target/53440 Handle generic thunks
better for TARGET_32BIT
* Backport of [Bugfix] [AArch32] PR target/59833 ARM soft-float
extendsfdf2 fails to quiet signaling NaN
* Backport of [Bugfix] [AArch32] PR target/70473 Reduce size of
Cortex-A8 automaton
* Backport of [Bugfix] [AArch32] PR target/71061 length pop* pattern
in epilogue correctly
* Backport of [Bugfix] [AArch32] PR target/77281 Fix an invalid check
for vectors of the same floating-point constants.
* Backport of [Bugfix] [AArch64] PR 64971 Convert function pointer to
Pmode when emit call.
* Backport of [Bugfix] [AArch64] PR 70904 Relax the restriction on
subreg reload for wide mode
* Backport of [Bugfix] [AArch64] PR target/63596 Honor tree-stdarg
analysis result to improve VAARG codegen
* Backport of [Bugfix] [AArch64] PR target/63874 vtable address
generation goes through memory
* Backport of [Bugfix] PR 70751 Correct the cost for spilling
non-pseudo into memory
* Backport of [Bugfix] PR 77421 Redundant second assignment of bb_copy
= NULL in free_original_copy_tables
* Backport of [Bugfix] PR middle-end/37780 Conditional expression with
__builtin_clz() should be optimized out
* Backport of [Bugfix] PR middle-end/68217 Wrong constant folding
* Backport of [Bugfix] PR middle-end/71700 zero-extend sub-word value
when widening constructor element
* Backport of [Bugfix] PR rtl-optimization/66940 Avoid signed overflow
in noce_get_alt_condition
* Backport of [Bugfix] PR rtl-optimization/71150 Guard in_class_p with
REG_P check
* Backport of [Bugfix] PR rtl-optimization/71295
* Backport of [Bugfix] PR rtl-optimization/71594 ICE in
noce_emit_cmove due to mismatched source modes
* Backport of [Bugfix] PR rtl-optimization/71878
* Backport of [Bugfix] PR tree-optimization/61839 More optimize
opportunity for VRP
* Backport of [Bugfix] PR tree-optimization/71818 ICE in as_a, at
is-a.h:192 w/ -O2 -ftree-vectorize
* Backport of [AArch32] Keep ctz expressions together until after reload
* Backport of [AArch32] Add fcsel to Cortex-A57 scheduler
* Backport of [AArch32] Add initial support for Cortex-A73
* Backport of [AArch32] Add support for overflow add, sub, and neg operations
* Backport of [AArch32] Add support for some ARMv8-A cores to driver-arm.c
* Backport of [AArch32] arm_neon.h: s/__FAST_MATH/__FAST_MATH__/g
* Backport of [AArch32] Emit vmov.i64 to load 0.0 into FP reg when neon enabled.
* Backport of [AArch32] Enable __fp16 as a function parameter and return type
* Backport of [AArch32] Fix aprofile multilib mappings
* Backport of [AArch32] Fix predicable_short_it attribute for arm_movqi_insn
* Backport of [AArch32] genmultilib: improve error reporting for MULTILIB_REUSE
* Backport of [AArch32] improve Cortex-A53 integer scheduler
* Backport of [AArch32] Model CSEL instruction in Cortex-A57 scheduling model
* Backport of [AArch32] no-data-is-text-relative & msingle-pic-base
* Backport of [AArch32] Refactor MOVW/MOVT fusion logic to allow extension
* Backport of [AArch32] Replace uses of int_log2 by exact_log2
* Backport of [AArch32] Update documentation for ARM architecture
* Backport of [AArch32] Use a MULTILIB_REQUIRED approach for aprofile multilib
* Backport of [AArch64] 1/2 Add support INS (element) instruction to
copy lanes between vectors
* Backport of [AArch64] 2/2 (Re)Implement vcopy<q>_lane<q> intrinsics
* Backport of [AArch64] 1/2 Improve zero extend
* Backport of [AArch64] 2/2 Improve zero extend
* Backport of [AArch64] 1/3 Migrate aarch64_add_constant to new
interface & kill aarch64_build_constant
* Backport of [AArch64] 2/3 Optimize aarch64_add_constant to generate
better addition sequences
* Backport of [AArch64] 3/3 Migrate aarch64_expand_prologue/epilogue
to aarch64_add_constant
* Backport of [AArch64] 1/6 Reimplement scalar fixed-point intrinsics
* Backport of [AArch64] 2/6 Reimplement vector fixed-point intrinsics
* Backport of [AArch64] 3/6 Reimplement frsqrte intrinsics
* Backport of [AArch64] 4/6 Reimplement frsqrts intrinsics
* Backport of [AArch64] 5/6 Reimplement fabd intrinsics & merge rtl patterns
* Backport of [AArch64] 6/6 Reimplement vpadd intrinsics & extend rtl
patterns to all modes
* Backport of [AArch64] Accept vulcan as a cpu name for the AArch64 port of GCC
* Backport of [AArch64] Add ANDS pattern for CMP+ZERO_EXTEND
* Backport of [AArch64] Add commit message
* Backport of [AArch64] Add initial support for Cortex-A73
* Backport of [AArch64] Add legitimize_address_displacement hook
* Backport of [AArch64] Add more choices for the reciprocal square
root approximation
* Backport of [AArch64] Add rtx_costs routine for vulcan
* Backport of [AArch64] Add some more missing intrinsics
* Backport of [AArch64] Add ThunderX vector cost model
* Backport of [AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP
* Backport of [AArch64] Canonicalize Cortex core tunings
* Backport of [AArch64] Cleanup -mpc-relative-loads
* Backport of [AArch64] Define WORD_REGISTER_OPERATIONS to zero and comment why
* Backport of [AArch64] Emit division using the Newton series
* Backport of [AArch64] Emit square root using the Newton series
* Backport of [AArch64] Enable tree-stdarg pass for AArch64 by
defining counter fields
* Backport of [AArch64] Fix typo in aarch64_legitimize_address
* Backport of [AArch64] Fixup to fcvt patterns added in r237200
* Backport of [AArch64] Fix vld2/3/4 on big endian systems
* Backport of [AArch64] Give some new costs for Cortex-A53
floating-point operations
* Backport of [AArch64] Give some new costs for Cortex-A57
floating-point operations
* Backport of [AArch64] Handle AND+ASHIFT form of UBFIZ correctly in costs
* Backport of [AArch64] Handle iterator definitions with conditionals
in geniterator.sh
* Backport of [AArch64] Improve aarch64_modes_tieable_p
* Backport of [AArch64] Increase code alignment
* Backport of [AArch64] Keep CTZ components together until after reload
* Backport of [AArch64] Optimize prolog/epilog
* Backport of [AArch64] Remove aarch64_cannot_change_mode_class
* Backport of [AArch64] Remove spurious attribute __unused__ from NEON intrinsic
* Backport of [AArch64] Renaming ARMv8.1 to ARMv8.1-A in comments and
documentations
* Backport of [AArch64] Replace insn to zero up SIMD registers
* Backport of [AArch64] update vulcan L1 cacheline size
* Backport of [ARMv8.2] [AArch64] 10/10 ARMv8.2-A FP16 lane scalar intrinsics
* Backport of [ARMv8.2] [AArch64] 1/10 ARMv8.2-A FP16 data processing intrinsics
* Backport of [ARMv8.2] [AArch64] 2/10 ARMv8.2-A FP16 one operand
vector intrinsics
* Backport of [ARMv8.2] [AArch64] 3/10 ARMv8.2-A FP16 two operands
vector intrinsics
* Backport of [ARMv8.2] [AArch64] 4/10 ARMv8.2-A FP16 three operands
vector intrinsics
* Backport of [ARMv8.2] [AArch64] 5/10 ARMv8.2-A FP16 lane vector intrinsics
* Backport of [ARMv8.2] [AArch64] 6/10 ARMv8.2-A FP16 reduction vector
intrinsics
* Backport of [ARMv8.2] [AArch64] 7/10 ARMv8.2-A FP16 one operand
scalar intrinsics
* Backport of [ARMv8.2] [AArch64] 8/10 ARMv8.2-A FP16 two operands
scalar intrinsics
* Backport of [ARMv8.2] [AArch64] 9/10 ARMv8.2-A FP16 three operands
scalar intrinsics
* Backport of [ARMv8.2] [AArch64] ARMv8.2 command line and feature
macros support
* Backport of [Misc] 1/2 Move choose_mult_variant declaration and
dependent declarations to expmed.h
* Backport of [Misc] 2/2 Hook up mult synthesis logic into
vectorisation of mult-by-constant
* Backport of [Misc] Append "evaluates to 0" for Wundef diagnostic
* Backport of [Misc] Avoid unnecessary peeling for gaps with LD3
* Backport of [Misc] Check for POINTER_TYPE_P before accessing
SSA_NAME_PTR_INFO in tree-inline
* Backport of [Misc] Disable ifunc on *-musl by default
* Backport of [Misc] Disable setting param of __builtin_constant_p to null
* Backport of [Misc] Don't count spilling cost for it offmemok
* Backport of [Misc] Don't use section anchors for declarations that
don't fit in a single anchor range
* Backport of [Misc] Fix ChangeLog entry
* Backport of [Misc] Fix GROUP_GAP for single-element interleaving
* Backport of [Misc] Fix unused variable warning in
simplify_cond_clz_ctz on some targets
* Backport of [Misc] Increase alignment of global structs in
increase_alignment pass
* Backport of [Misc] Latent alignment bug in tree-ssa-address.c
* Backport of [Misc] Report supported function classes correctly on *-musl
* Backport of [Testsuite] 29_atomics/atomic/65913.cc: require
atomic-builtins rather than specific target
* Backport of [testsuite] [AArch32] Add missing guards to fp16 AdvSIMD tests
* Backport of [Testsuite] [AArch32] Fix, add tests for FP16 aapcs
* Backport of [Testsuite] [AArch32] Fix dg-do and dg-skip order
* Backport of [Testsuite] [AArch32] gcc.target/arm/pr37780_1.c: Use
arm_arch_v6t2 effective target and options
* Backport of [Testsuite] [AArch32] Make arm_neon_fp16 depend on arm_neon_ok
* Backport of [Testsuite] [AArch32] Selectors and options directives
for ARM VFP FP16 support
* Backport of [Testsuite] [AArch64] Ensure vrnd* tests run on ARMv8 cores
* Backport of [Testsuite] Add testcases
* Backport of [testsuite] asan/clone-test-1.c: Handle clone() failure
* Backport of [Testsuite] Fix testcases
* Backport of [Testsuite] Use setrlimit for testing libstdc++ in cross
toolchains
* Backport of [Cleanup] [AArch32] 2/4 Replace casts of 1 to
HOST_WIDE_INT by HOST_WIDE_INT_1 and HOST_WIDE_INT_1U
* Backport of [Cleanup] [AArch32] 3/4 Cleanup casts from INTVAL to
[unsigned] HOST_WIDE_INT
* Backport of [Cleanup] [AArch32] 4/4 Simplify checks for CONST_INT_P
and comparison against 1/0
* Backport of [cleanup] [AArch32] Delete thumb_reload_in_h
* Backport of [Cleanup] [AArch32] Remove non-existent extern
declarations in arm.h
* Backport of [Cleanup] [AArch64] aarch64_elf_asm_named_section:
Remove declaration.
* Backport of [Cleanup] [AArch64] Clean up parentheses and use
GET_MODE_UNIT_BITSIZE in a couple of patterns
* Backport of [Cleanup] [AArch64] Remove static variable
all_extensions from aarch64.c
* Backport of [Cleanup] Cleanup frame push/pop code
* Backport of [Cleanup] rtlanal.c: Convert conditional compilation on
WORD_REGISTER_OPERATIONS
* Backport of [Debug] ifcvt: Print name of noce trasform that
succeeded in dump file
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[1]. Source package snapshots are defined when the compiler is only
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[2]. Stable source package releases are defined as releases where the
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