Hi
I have a question about the impact of a binutils bug to do with parsing the .align assembler directive, which may appear soon in a Linaro GCC release. The bug was first discovered by Jérôme Forissier when building ARM Trusted Firmware with a non-Linaro toolchain:
https://lists.linaro.org/pipermail/linaro-toolchain/2016-June/005768.html
As Jim Wilson helpfully noted later in that thread:
> This patch isn't present in the binutils-2.25 that tcwg is using. The patch is present in binutils-2.26.
The bug is now fixed in binutils mainline:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=7ea12e5…
But this was too late to be in the binutils-2_27 tag (3rd August)
I'm concerned that this bug may appear in the upcoming Linaro GCC 6 stable release, which may have a significant lifetime. Can anyone comment on the binutils version to be used in the Linaro GCC 6 release? If a binutils version containing the bug is used, is it possible for this to be patched with the fix? I need to know whether we need to provide an interim solution in ARM Trusted Firmware.
Regards
Dan.
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Hello linaro experts!
I'm using the stable version(gcc-linaro-4.9-2014.11) recommended on
https://wiki.linaro.org/WorkingGroups/ToolChain. I downloaded the
binary fromhttps://releases.linaro.org/14.11/components/toolchain/binaries/arm-lin….
But I found there is no libstdc++.so.6. Is that library missing in
that version?
What I need is just a tested stable version for an industry iot
project and the stability is the most important thing. And due to app
back-compatibility, I can not use hardware-float feature. So any
recommendation for a tested stable version of
_gcc-linaro-xxx-arm-linux-gnueabi_ toolchain?
Thanks!
dlw
o One day off (2/10)
== Progress ==
o Upstream GCC (3/10)
- AArch64 and ARM backend cleanup w/r to reload remaining hooks
rebasing and validation on-going
- Investigate guality test failures
o Misc (5/10)
* Various meetings and discussions.
* Catch up with mail/irc/upstream dev after holidays
== Plan ==
o Continue on-going tasks
== This Week ==
* LTO (5/10)
a) TCWG-666 (4/10)
- RFC Patch submitted upstream
- Committed r239212 to make extend_mask, extend bits based on sign.
- Addressed patch reviews
b) TCWG-548 (1/10)
- Resolved issue with chromebook
- Benchmarking with SPEC2k doesn't show much perf improvement.
* Bugs (3/10)
- Fixed regressions caused by my commits for PR70920 and PR71078
- PR57371: Submitted patch upstream
* Misc (2/10)
- UK visa application and appointment
== Next Week ==
- Continue with TCWG-666, TCWG-72, TCWG-548
# Progress #
* TCWG-685, GDB 7.12 release. [5/10]
Release branch is created. Finished the test and triage for aarch64
native.
Tests are good. Two patches are committed. Running regression tests
for cross for arm and aarch64.
Upgrade the native compiler to gcc mainline, and run aarch64 tests
with the new compiler.
* OpenOCD for aarch64. [3/10]
Investigate OpenOCD support for aarch64. There was an openocd patch
for aarch64 posted in Feb 2015, but never merged.
* Misc, [2/10]
# Plan #
* TCWG-685.
* Finish OpenOCD investigation.
* US visa interview on Wed.
--
Yao
== Progress ==
* LLVM 3.9.0 Release for AArch64 [TCWG-696] [3/10]
- Ran the tests on one of our APM boards
- Fixed an issue with some tests that are only supposed to be run
for the x86 target but were accidentally running for other targets too
- Wrote up some release notes for AArch64
* Enable MLx Expansion pass for non-Cortex-A9 targets [TCWG-674] [3/10]
- Did a few runs of the test-suite on one of our chromebooks (Cortex-A15)
- The pass is expanding > 2000 MLx instructions in the test-suite, so it
looks like we can use it for evaluation
* [AArch64] Keep merging consecutive stores in store sequences [TCWG-704] [2/10]
- When merging stores, we always start looking from the end of the store
sequence, and if the last store cannot be merged we stop; we should instead
keep looking through the rest of the sequence to see if we can merge any of
the previous stores
- Working on a fix
* Refactor SelectionDAGBuilder::visitInlineAsm [TCWG-643] [2/10]
- Made it shorter by about 100 LOC; it could still use some cleanup, but I've
sent the patch upstream to get an initial round of feedback
== Plan ==
* LLVM 3.9.0 Release for AArch64 [TCWG-696]
- Wait for the next release candidate
* [AArch64] Keep merging consecutive stores in store sequences [TCWG-704]
== Progress ==
* Validation
- reviews in Jenkins jobs/ABE
- checked that the new xenial builder works as expected
* GCC
- PR 67591 (ARM v8 Thumb IT blocks deprecated)
* misc (conf-calls, meetings, emails, ....)
- catching up after holidays
- Cauldron and Connect: booked flights and hotels
== Next ==
On holidays until Aug 22nd
== This Week ==
* LTO (4/10)
a) TCWG-666 (3/10)
- No idea where data corruption happens in ltrans with my patch,
tree value in ipa_bits gets corrupted for some reason.
- Started over with widest_int representing value and mask
- WIP new prototype patch:
http://people.linaro.org/~prathamesh.kulkarni/ipa-bits-0_1.diff
b) TCWG-548 (1/10)
- Benchmarking fails on my chromebook, input/output error,
no idea why.
* TCWG-72 (2/10)
- Rebased patch on trunk, bootstrapped on x86_64, cross tested on arm*-*-*
- Addressed comments from Ramana
- Strange issue with armv8l-unknown-linux-gnu which has hardware div
but produced call to __aeabi_idiv, maybe I screwed sth during the build.
Building from scratch doesn't reproduce the issue and patch does not
regress armv8l-unknown-linux-gnueabihf.
* Misc (4/10)
- PR70920: Fix committed upstream.
- PR71078: Fix committed upstream.
- Committed r238874 to restrict pr70929-4.c for lp64 targets to avoid
fallout caused by the test-case on ilp32 targets.
- Submitted RFC patch to warn for dead calls, rejected due
to potentially false positives.
- WIP patch to fold strlen (s) eq/ne 0 to *s eq/ne 0
== Next Week ==
- Continue with TCWG-72, TCWG-548 and TCWG-666
Hi Everyone,
I'm having trouble finding vreinterpretq_u64_p128 (and friends) to
help convert a polynomial. I can't find it in arm_neon.h or
arm_acle.h:
$ grep p128 /usr/lib/gcc/aarch64-linux-gnu/4.9/include/arm_acle.h
$ grep p128 /usr/lib/gcc/aarch64-linux-gnu/4.9/include/arm_neon.h
$ grep p64 /usr/lib/gcc/aarch64-linux-gnu/4.9/include/arm_acle.h
$ grep p64 /usr/lib/gcc/aarch64-linux-gnu/4.9/include/arm_neon.h
vmull_p64 (poly64_t a, poly64_t b)
vmull_high_p64 (poly64x2_t a, poly64x2_t b)
$
An RPI-3 with ARMv8/Aarch32 and GCC 4.9.2 has it in arm_neon.h:
$ cat /usr/lib/gcc/arm-linux-gnueabihf/4.9.2/include/arm_neon.h | grep
-A 4 vreinterpretq_u64_p128
vreinterpretq_u64_p128 (poly128_t __a)
{
return (uint64x2_t)__builtin_neon_vreinterpretv2diti
((__builtin_neon_ti) __a);
}
Is there another file that should be included for it? Or is there
something else I should be doing when I want to convert from a
polynomial to a type like uint64x2_t?
Thanks in advance.
Jeff
Hi Everyone,
I have a HiKey running Linaro. I'm trying to build out a test case
which tests Aarch32 on Aarch64.
When I attempt to build an Aarch32 binary I experience the compile
error below. The GCC folks helped me with the Aarch32 CFLAGS, so I
believe they are correct.
$ gcc -march=armv8-a+crc -mtune=cortex-a53
-mfpu=crypto-neon-fp-armv8 -mfloat-abi=hard test.cc -o test.exe
gcc: error: unrecognized command line option ‘-mfpu=crypto-neon-fp-armv8’
gcc: error: unrecognized command line option ‘-mfloat-abi=hard’
Trying an -m32:
$ gcc -march=armv8-a+crc -mtune=cortex-a53
-mfpu=crypto-neon-fp-armv8 -mfloat-abi=hard -m32 test.cc -o test.exe
gcc: error: unrecognized command line option ‘-mfpu=crypto-neon-fp-armv8’
gcc: error: unrecognized command line option ‘-mfloat-abi=hard’
gcc: error: unrecognized command line option ‘-m32’
And without the -mtune:
$ gcc -march=armv8-a+crc -mfpu=crypto-neon-fp-armv8
-mfloat-abi=hard test.cc -o test.exe
gcc: error: unrecognized command line option ‘-mfpu=crypto-neon-fp-armv8’
gcc: error: unrecognized command line option ‘-mfloat-abi=hard’
I'm obviously suffering a disconnect. I may have more problems after
the build when attempting to run the program, but I'll cross that
bridge when I encounter it.
How does one build an Aarch32 program on Aarch64?
Thanks in advance.
== Progress ==
* PR24234 - [AArch64] error in backend: fixup value out of range
[TCWG-681] [5/10]
- Wrong instruction size computed for TLS accesses
- Accepted upstream, will commit first thing next week
* [AArch64] Register all AArch64 passes [TCWG-687] [3/10]
- Cleanup that should enable us to run AArch64 passes in llc (incidentally,
this was useful for testing TCWG-681)
- Accepted upstream, will commit first thing next week
* Enable MLx Expansion pass for non-Cortex-A9 targets [TCWG-674] [2/10]
- Started playing with a code snippet so I can understand the pass better
== Plan ==
* Enable MLx Expansion pass for non-Cortex-A9 targets [TCWG-674]
- Brush up the code snippet and do some runs on a Cortex-A15 to see how it
behaves there
* Pick up another AArch64 bug from TCWG-678
* Off on Tue and Wed [4/10]
# Progress #
* TCWG-655, workaround ARM linux kernel ptrace bug on setting VFP
registers. Pedro isn't happy about the workaround, and inclined to
upgrade kernel.
* TCWG-685, GDB 7.12 release. [4/10]
Fix a bug on threads are disappeared when gdb detach. GDB gets
odd task state (disk sleep) from /proc/<pid>/status, and takes some
time understanding what does "disk sleep" mean for a thread to be
exited. Patch is being tested.
* US visa. [1/10]
Get the visa photo, finish the DS-160 form, and make an interview
appointment.
* Misc, [1/10]
# Plan #
* TCWG-685, GDB 7.12 release. More testing on aarch32.
* TCWG-655.
--
Yao
The Linaro Binary Toolchain
============================
The Linaro GCC 5.3-2016.05 Release is now available.
Notice: All Linaro GCC 5 series toolchain users should migrate to the
latest version of the Linaro GCC 5 toolchain in order to mitigate
potential security exposure to CVE-2015-7547. See the NEWS section
below for details.
Download release packages from:
http://releases.linaro.org/components/toolchain/gcc-linaro/5.3-2016.05/http://releases.linaro.org/components/toolchain/binaries/5.3-2016.05/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 5.3-2016.05
Linaro glibc 2.21 (linaro/2.21)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.25 (linaro_binutils-2_25-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 5.3-2016.05
================================
* Increment binutils release date to 2016_02 to reflect the most recent
commit:
commit ef90a4718f535cbe6345b4e7168baea7b1972abf
Author: Matthew Wahab <matthew.wahab(a)arm.com>
Date: Tue Jan 12 16:35:30 2016 +0000
[ARM] Support ARMv8.2 RAS extension.
* Baremetal sysroot names now contain 'newlib' rather than 'glibc'.
* Manifests now contain relative paths rather than absolute paths.
* Now generating proper manifest files.
* Fixed pi requeue support in glibc 2.21 while allowing the existing
2.21 minimum kernel default setting. This was checked into the
linaro/2.21/master branch.
commit a68cafa11c500d8a49a3014c43c5152859d037ae
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
commit 6e5cb616b5b442ce8b2664ad673c0acf42a490ac
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
commit 9ac61c0047295696cbcdbc26bdc174c7bd25a3c8
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Backported support into GCC for Cortex-A32, Cortex-A35, and Cortex-R8.
* Applied fix for CVE-2015-7547 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
glibc 2.21.
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* ARMv8.1 Instruction Support - ARMv8.1 instructions support was checked
into GCC and binutils. It has been backported into Linaro GCC 5.3
and Linaro binutils 2.25.
* Backported -Bsymbolic-functions into Linaro binutils 2.25.
* Performance related backports from Linaro GCC 5.2-2015.11, Linaro GCC
5.2-2015.12, and Linaro GCC 5.3-2016.01-1, Linaro GCC 5.3-2016.02,
Linaro GCC 5.3-2016.03, and Linaro GCC 5.3-2016.04 have been included.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.03http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.04
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
T: +1-612-424-1861 <+16124241861>
== Progress ==
* IPA VRP and Early VRP
- Posted patch series and revised based on review
- Few patches are accepted; others are waiting for re-review
* Tree VRP
- Converted to use allocpool
* Committed upstream tree-reassoc patch for missed optimization due to
factoring out CONVERT_EXPR in phiopt.
== Plan ==
- Follow upon remaining upstream patches
- IPA VRP
== This Week ==
* TCWG-666 (2/10)
- Working through bootstrap and regtest failures
* TCWG-548 (1/10)
- Running benchmarks on chromebook (cortex-a15)
* Bugs (5/10)
- PR71947: Richard committed fix in vrp which solves this at -O2.
- PR70920: Patch passes bootstrap+test.
- Wrote patch to make ipa-pure-const pass warn for unused return values
- PR71315: Verified works on trunk, exposed another bug in tree-ssa-strlen
* Misc (2/10)
- Recovery from sprint
== Next Week ==
- Continue with TCWG-666 and TCWG-548
- Bugs
# Progress #
* TCWG-518, ARM range stepping patches. [2/10]
The last one is approved, and all patches are committed! Need to
enable range stepping and collect the performance data. Range
stepping should speed up remote debugging.
* TCWG-655, Workaround ARM linux kernel ptrace bug on setting VFP
registers. No response from upstreams.
* TCWG-333, Thumb mode function pointer assignment in GDB. [3/10]
Try a different approach, still causes regressions. I'll ask upstream
how to do it.
* TCWG-547, Change software_single_step interface to return a vector of
address. [4/10].
Patches are done, but need to figure out how to hook them together.
* TCWG-685, GDB 7.12 release. [1/10]
The release will be in Sep, and hopefully it can be done before the
Linaro Connect. Discuss on how/when to pick up 7.12 in Linaro
toolchain release. I am inclined to upgrade GDB in linaro release
from 7.11 to 7.12 in fall or winter.
# Plan #
* Off on Tue and Wed.
* GDB 7.12 release testing for ARM and AArch64.
* US visa application.
--
Yao
== Progress ==
TCWG-680 Some analysis on what non-compiler support would be required
for an llvm based EBC (UEFI) toolchain.
TCWG-612 ARM TLS support in LLD: Initial support and tests for
standard model upstreamed. There is still some work to be done for
corner cases where LLD's relaxations will cause assertion failures.
Static linking also needs some work as the TLS module index needs to
be written into the GOT without a dynamic relocation. I have a
prototype fix that needs cleaning up and tests written.
Did some experiments with static linking and TLS to work out what I'll
need to look at next. Discovered GNU ifunc support when static linking
is not working.
Did some thinking about what would be needed to support C++ exceptions
in LLD for ARM. This is probably the next major chunk of work as
supporting exceptions is needed when static linking against the C
library startup code.
== Plans ==
Plans for next 4 weeks:
On Sabbatical back on the 22nd August. Will probably have limited
access to email if there is anything urgent.
Peter
== Progress ==
* ARM: Different ABI functions based on optimization level [TCWG-669]
- Patch committed upstream
* PR26038 - inline assembly assertion building ARM linux kernel
[TCWG-590] [2/10]
- Patch committed upstream
* PR24234 - [AArch64] error in backend: fixup value out of range
[TCWG-681] [5/10]
- Started investigating
* AArch64 Bugzilla scrub [2/10]
- Closed a couple of bugs that couldn't be reproduced
- Added a few interesting bugs to TCWG-678
* Minor updates to the helper scripts [TCWG-630, TCWG-649] [1/10]
== Plan ==
* PR24234 - [AArch64] error in backend: fixup value out of range [TCWG-681]
- Looks like a tough one :)
Hi Everyone,
I'm looking at the features of a BeagleBone Black. Its /proc/cpuinfo is below.
I think vfpd32 cpu flag means I have 32 D-registers. The cpu flags
neon and vfpv3 flags means I want something more than -mfpu=neon-fp16,
but I'm not sure what that is.
My question is, what GCC ARM option is used when we encounter the
neon, vfpv3 and vfpd32 flags?
Thanks in advance.
**********
$ cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 2 (v7l)
BogoMIPS : 996.14
Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc08
CPU revision : 2
Hardware : Generic AM33XX (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
Hi Everyone,
I'm having trouble with ARMv8/Aarch64. One is an early Mustang server
board (without CRC or Crypto), and the other is a LeMaker HiKey (with
CRC and Crypto). Both run Linaro:
apm-mustang: $ cat /proc/cpuinfo
Features : fp asimd evtstrm
And:
hikey: $ cat /proc/cpuinfo
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
According to the GCC folks, we can get better code generation with
-mfpu=neon-fp-armv8
(http://gcc.gnu.org/ml/gcc-help/2016-05/msg00058.html and
https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html). However, it
results in:
$ g++ -DDEBUG -g3 -O0 -mfpu=neon-fp-armv8 -fPIC -pipe -c cryptlib.cpp
g++: error: unrecognized command line option ‘-mfpu=neon-fp-armv8’
GNUmakefile:753: recipe for target 'cryptlib.o' failed
It looks like -mfpu=neon-fp-armv8 is a GCC 4.9 feature
(http://gcc.gnu.org/gcc-4.9/changes.html), and Linaro supplies GCC
4.9.2:
$ g++ --version
g++ (Debian/Linaro 4.9.2-10) 4.9.2
Copyright (C) 2014 Free Software Foundation, Inc.
I'm wonder why the option is not being consumed by GCC. Are there any
ideas what I should be doing differently?
Thanks in advance.
Jeff
* On holiday [6/20]
# Progress #
* TCWG-655, Workaround ARM linux kernel ptrace bug. [2/20]
After the discussion, patch is posted. Pedro is on holiday, so the
patch is pending there for review.
* TCWG-518, ARM range stepping patches. [3/20]
The last "to-be-approved" patch is posted. Pending for review.
* TCWG-333, Thumb mode function pointer assignment in GDB. [2/20]
Working on a patch to handle both ARM/thumb and PPC64.
* TCWG-179, TLS variables can't be resolved in aarch64 GDB. [4/20]
GCC doesn't produce DW_AT_location
for TLS variable, because target hook TARGET_ASM_OUTPUT_DWARF_DTPREL
isn't defined for AArch64. Thanks to Jiong and Szabolcs's help, pick
up knowledge on TLS descriptor and TLS modes quickly. Still need to
figure out how to describe the location of TLS variable in debug info
if they are unknown in compilation/link time.
* Fix gdb.gdb/*.exp and gdb.mi/mi-reverse.exp test fails. [1/20]
* Upstreams patch review. [1/20]
* LAS16, sort out the invitation letter for US visa. [1/20]
# Plan #
* TCWG-333, TCWG-518, TCWG-655 and TCWG-179
* US visa application.
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.07 snapshot of Linaro GCC 6 source packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn238201 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.1+svn238201
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Hi Linaro Members,
while I am cross compiling the wpa supplicant with toolchain gcc-linaro-4.9-2015.05-x86_64_arm-linux-gnueabihf for hostapd and nl80211 mode enabled in menuconfig I am getting linker message ld:cannot find -lnl -3 (libnl) .I tried to locate the libnl libraries but they are not built in.could you please let me know how to enabled libnl in the toolchain.
Thanks
Best Regards --
Best Regards,
Rohit Kamat
CallSend SMSCall from mobileAdd to SkypeYou'll need Skype CreditFree via Skype
== Progress ==
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
- Committed all 3 patches upstream
* ARM: Different ABI functions based on optimization level [TCWG-669]
- Patch in upstream review, had to rework it a bit
* PR26038 - inline assembly assertion building ARM linux kernel [TCWG-590]
- Patch in upstream review
* Refactor SelectionDAGBuilder::visitInlineAsm [TCWG-643]
- In progress (trying to break it up into a few helper functions)
* Misc
- TCWG Sprint prep (slides etc)
== Plan ==
* TCWG Sprint
* Commit TCWG-669 and address any review comments on TCWG-590
== Progress ==
TCWG-653 ARM/Thumb interworking veneers
Committed upstream after several review rounds and at least one set of
build bot failures in systems/compilers we don't have set up.
TCWG-612 ARM TLS support in LLD
Have an implementation and most of the tests. Should be ok to upstream
next week.
Found that llvm-mc doesn't implement .word sym(tlsldo). Have a simple
fix that I'll need to upstream before I can test local-dynamic.
== Plan ==
11 - 15th July TCWG Sprint
== Absences ==
25th July - 20th August Sabbatical
The Linaro Binary Toolchain
============================
The Linaro GCC 5.3-2016.05-rc2 Release-Candidate is now available.
Notice: All Linaro GCC 5 series toolchain users should migrate to the
latest version of the Linaro GCC 5 toolchain in order to mitigate
potential security exposure to CVE-2015-7547. See the NEWS section
below for details.
Download release-candidate packages from:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.05-rc2/http://snapshots.linaro.org/components/toolchain/binaries/5.3-2016.05-rc2/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 5.3-2016.05-rc2
Linaro glibc 2.21 (linaro/2.21)
Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch)
Linaro binutils 2.25 (linaro_binutils-2_25-branch)
FSF GDB 7.10 (gdb-7.10-branch)
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search
NEWS for Linaro GCC 5.3-2016.05-rc2
====================================
* Increment binutils release date to 2016_02 to reflect the most recent
commit:
commit ef90a4718f535cbe6345b4e7168baea7b1972abf
Author: Matthew Wahab <matthew.wahab(a)arm.com>
Date: Tue Jan 12 16:35:30 2016 +0000
[ARM] Support ARMv8.2 RAS extension.
* Baremetal sysroot names now contain 'newlib' rather than 'glibc'.
* Manifests now contain relative paths rather than absolute paths.
* Now generating proper manifest files.
* Fixed pi requeue support in glibc 2.21 while allowing the existing
2.21 minimum kernel default setting. This was checked into the
linaro/2.21/master branch.
commit a68cafa11c500d8a49a3014c43c5152859d037ae
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
commit 6e5cb616b5b442ce8b2664ad673c0acf42a490ac
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
commit 9ac61c0047295696cbcdbc26bdc174c7bd25a3c8
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Backported support into GCC for Cortex-A32, Cortex-A35, and Cortex-R8.
* Applied fix for CVE-2015-7547 - A stack-based buffer overflow in
glibc's getaddrinfo() was corrected in glibc 2.23 and backported into
glibc 2.21.
https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html
* ARMv8.1 Instruction Support - ARMv8.1 instructions support was checked
into GCC and binutils. It has been backported into Linaro GCC 5.3
and Linaro binutils 2.25.
* Backported -Bsymbolic-functions into Linaro binutils 2.25.
* Performance related backports from Linaro GCC 5.2-2015.11, Linaro GCC
5.2-2015.12, and Linaro GCC 5.3-2016.01-1, Linaro GCC 5.3-2016.02,
Linaro GCC 5.3-2016.03, and Linaro GCC 5.3-2016.04 have been included.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.03http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.04
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Linaro Toolchain Engineering Manager
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
Hi Everyone,
I have a test script from help that repeatedly builds and runs a
library under different configurations. The script includes multiple
Asan tests.
The Asan tests are producing some findings under ARM32 as shown below.
Other platforms do not include Asan findings. In addition, Valgrind
does nt produce any findings.
The test program is always built with at least -g2, and sometimes
built with -g3. However, I am not seeing the symbolication. According
to the GCC folks, asan_symbolize is not required for GCC because it
uses libbacktrace. Also see
http://bugzilla.redhat.com/show_bug.cgi?id=1250844.
Why am I lacking symbolization, and how do I achieve it?
**********
AddressSanitizer: stack-buffer-overflow on address 0xbec57b18 at pc
0x38c651 bp 0xbec579e0 sp 0xbec579e4
AddressSanitizer: stack-buffer-overflow on address 0xbedbae9c at pc
0x6553f bp 0xbedbae68 sp 0xbedbae6c
AddressSanitizer: stack-buffer-overflow on address 0xbea67b18 at pc
0x38cbc5 bp 0xbea679e0 sp 0xbea679e4
AddressSanitizer: stack-buffer-overflow on address 0xbef0fe9c at pc
0x66117 bp 0xbef0fe68 sp 0xbef0fe6c
**********
$ uname -a
Linux cubietruck 3.4.39 #35 SMP PREEMPT Tue Sep 15 17:17:33 CST 2015
armv7l armv7l armv7l GNU/Linux
$ g++ --version
g++ (Ubuntu/Linaro 4.8.2-19ubuntu1) 4.8.2
Copyright (C) 2013 Free Software Foundation, Inc.
# Progress #
* TCWG-655, Workaround ARM linux kernel ptrace bug on setting VFP
registers. [2/10]
Think about different approaches to workaround the kernel bug, but
can't work unfortunately. Propose an approach that workaround it in
gdb testing by setting affinity if the kernel is known broken.
People agree on this.
* TCWG-333, Thumb mode function pointer assignment in GDB. [3/10]
It is broken when you assign a function to a function pointer in
thumb mode in GDB. My original attempt is to skip the test, because
it is difficult to do what MIPS does nowadays. After some
discussions, I realize it is a GDB bug, and we should fix it.
Fortunately it is broken on ppc64 as well because of function
descriptor :)
* TCWG-518, ARM range stepping patches. [2/10]
V3 are reviewed, but I misunderstood one comments to V2. I'll update
patches, retest and post them.
* ARM linux kernel raises SIGILL for unknown syscall number, while GDB
expects kernel returns -ENOSYS. [2/10]
The behaviour is different from other arch. The patch in GDB side is
committed, but still need to kernel people why ARM kernel behaves
this way.
* Misc [1/10]
# Plan #
* All above,
* Off on Thur and Fri.
--
Yao
o One day off (2/10)
== Progress ==
o Extended Validation (3/10)
- Benchmarking job babysitting.
- Looked at Dejagnu issue (pid killing, resurrected an old patch)
o Upstream GCC (3/10)
- __sync bultin fix for ARMv8.1:
Careful read of the doc shows that there is no issue with the
current implementation (no need to add an extra DMB, acq/rel
semantic is sufficient in this case)
- AArch64 and ARM backend cleanup w/r to reload remaining hooks
Analysis and validation on-going
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on-going tasks
== This Week ==
* LTO (6/10)
a) TCWG-548 (2/10)
- Tweaked algorithm, which shows some improvements in reducing external
references
b) TCWG-666 (4/10)
- Had a look at bitwise-ccp
- WIP prototype patch
* Benchmarking (1/10)
- Got results for linaro-gcc-6 for coremark-pro for arm-linux-gnueabihf
* Sick Leave (2/10)
* Misc (1/10)
- Pinged for reviewing patches for TCWG-665 and TCWG-72
- Meetings
== Next Week ==
- Address upstream reviews for TCWG-665
- TCWG-666: Continue with prototype patch.
- TCWG-548: Submit upstream for feedback.
- Benchmarking: Get results for coremark-pro for aarch64-linux-gnu.
== Progress ==
TCWG-653 ARM/Thumb interworking veneers
Have completed an implementation, now in upstream review. Had initial
set of comments and posted an update. Likely to take several
iterations before commit
TCWG-612 ARM TLS support in LLD
Made a start. Looks to be more straightforward the interworking
thunks, should just be grunt-work to get done.
Updated lld slides on llvm sprint presentation.
== Plan ==
TCWG-653 and TCWG-612.
== Progress ==
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [4/10]
- Committed another patch upstream, 3 more in review
* ARM: Different ABI functions based on optimization level [TCWG-669] [3/10]
- Make sure we're ABI-compliant at -O0
- Patch in upstream review, need to fix a few things
* List of active environments with llvm-env [TCWG-640] [1/10]
- Committed internally
* Refactor SelectionDAGBuilder::visitInlineAsm [TCWG-643] [1/10]
- In progress (trying to break it up into a few helper functions)
* PR26038 - inline assembly assertion building ARM linux kernel
[TCWG-590] [1/10]
- Started investigating
== Plan ==
* Address any review comments for TCWG-623 and TCWG-669
* Submit patches for TCWG-643 and TCWG-590
Hi Andrew,
On 27 June 2016 at 19:32, Pinski, Andrew <Andrew.Pinski(a)cavium.com> wrote:
>> No gain expected in implementing an Ifunc'ed version of the library.
>
> How did you prove that? What hardware did you run this on to prove it?
> Also have you thought at least doing an ifunc version for 128bit atomics?
up to 64bits, the calls to the libatomic routines are inlined and
armv8.1 CAS and load-operate version are used when the application is
build for armv8.1 architecture. For 128bits, a call to the lib is
made which uses the same LL/SC implementation with or without LSE
support, as CAS and load-operate instruction don't support this data
size.
I don't have armv8.1 hardware and made the analysis on the generated
assembler. Do you have use case on your side where an ifunc version
can be useful ? I'm not aware of an algorithm which can replace
effectively LL/SC implementation with shorter CAS, do you have any
pointers ? Maybe CASP can be used in some cases, I'll investigate it.
Thanks
Yvan
> Thanks,
> Andrew
>
> -----Original Message-----
> From: linaro-toolchain [mailto:linaro-toolchain-bounces@lists.linaro.org] On Behalf Of Yvan Roux
> Sent: Monday, June 27, 2016 1:40 AM
> To: Linaro Toolchain Mailman List <linaro-toolchain(a)lists.linaro.org>
> Subject: [ACTIVITY] Week 25
>
> == Progress ==
> o Extended Validation (1/10)
> - Benchmarking job babysitting.
>
> o Upstream GCC (4/10)
> - ARMv8.1 libatomic: Analysis completed.
> No gain expected in implementing an Ifunc'ed version of the library.
> - Working on __sync buitlins potential fix.
>
> o Misc (5/10)
> * Various meetings and discussions.
> * Internal appraisal
>
> == Plan ==
> o Continue on-going tasks (__sync, benchmarking) _______________________________________________
> linaro-toolchain mailing list
> linaro-toolchain(a)lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/linaro-toolchain
== Progress ==
o Extended Validation (1/10)
- Benchmarking job babysitting.
o Upstream GCC (4/10)
- ARMv8.1 libatomic: Analysis completed.
No gain expected in implementing an Ifunc'ed version of the library.
- Working on __sync buitlins potential fix.
o Misc (5/10)
* Various meetings and discussions.
* Internal appraisal
== Plan ==
o Continue on-going tasks (__sync, benchmarking)
# Progress #
* TCWG-333, ISA bit treatment in ARM thumb mode.
Got some comments from Maciej (MIPS) and need to address them.
* TCWG-518, ARM range stepping patches. [2/10]
Combine the path of "proceed" and "resume" so that we only change one
place instead of two to support range stepping. Patches are being
tested.
* TCWG-655, Workaround ARM linux kernel ptrace bug... [2/10]
by pining both program and debugger on the same core in the affected
test cases.
* Off on Wed to Fri. [6/10]
# Plan #
* Continue things above,
--
Yao
== This Week ==
* LTO (8/10)
a) TCWG-558 (2/10)
- found a way to detect if stmt is inside a loop
- addressed issue with -ffat-lto-objects
- patch posted upstream, waiting for review.
b) ipa-vrp (3/10)
- Prototype patch for propagating value ranges
inter-procedurally (accidental overlap with Kugan's patches)
- Experimented and reviewed Kugan's patch.
c) TCWG-548 (2/10)
- Wrote a pass to gather stats on external references.
- Measurements with SPEC2000 with and without prototype patch
d) Had a look at pointer alignment propagation within ipa-cp pass (1/10)
* Benchmarking (1/10)
- Obtained results for linaro-gcc-5, fsf-gcc-6 for coremark-pro for
arm-linux-gnueabihf target.
- Submitted job 112 for bkk16-buildfarm-benchmark, status shows SUCCESS, but it
appears no tcwg-benchmark job references build #112.
* Misc (1/10)
- Meetings
== Next Week ==
- Continue with TCWG-548 and ipa-vrp
- Ping patches in upstream reviews
== Progress ==
* Out of office on Monday and Tuesday [4/10]
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [4/10]
- First patch committed upstream (6 features / properties)
- Another patch in upstream review (5 features / properties)
- Working on another series of patches
* Use member initializers in ARMSubtarget [TCWG-659] [1/10]
- Trivial refactoring suggested during code review for TCWG-623
- Committed upstream
* Unbreak the selfhost bots [TCWG-661] [1/10]
- Currently bisecting the issue affecting
clang-cmake-thumbv7-full-sh (in progress)
- Tried bisecting one of the issues affecting
clang-cmake-armv7-selfhost and clang-cmake-armv7-selfhost-neon, but
the test board died in the process; Renato is trying to reproduce on
one of his boards
* Remove exit-on-error flag from CodeGen tests [TCWG-604]
- Finally committed upstream
== Plan ==
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
* Unbreak the selfhost bots [TCWG-661]
== Progress ==
* TCWG-653 Add interworking thunks to LLD
Investigated and reported upstream bug in existing implementation.
This has been fixed by reverting the change that introduced it. Got
some feedback about whether I would need to strictly follow existing
Thunk implementation.
Implemented an alternative thunk mechanism that should generalise to
supporting range extension and interworking thunks. It is passing the
existing lld regression tests.
== Plans ==
Finish off support for and add tests for ARM/Thumb interwork.
Tidy up and submit upstream.
== Progress ==
* Validation
- experimenting backport-multijob
- noticed dejagnu problems when trying to kill processes that timed out
- abe and jenkins configs patches / reviews
* Backports/snapshots
- restarted a few validations, to try to recover from disk full issues
* GCC
- neon-testgen.ml removal patch sent upstream
- PR 67591 (ARM v8 Thumb IT blocks deprecated)
- followup on vect.exp's check_vect() support for old arm cores.
- neon-fp16 tests consistency patch posted
- a couple of regressions flagged on trunk
* cortex-strings
- updated aarch64/strlen
* Support
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation:
- patch reviews
- look at xenial, docker builders
* Backports
- restart the ones that failed due to disk space issues
* GCC
- monitor trunk regressions
- fix "check_vect" guard in gcc.dg/vect tests
- pr 67591
- advsimd tests
== Progress ==
o Extended Validation (1/10)
- Benchmarking job babysitting.
o Linaro GCC (5/10)
- Merged FSF GCtC 6 branch
- Reviewed backports (very tedious because of infra issues)
- Released June snapshots (5.4 and 6.1)
o Upstream GCC (2/10)
- ARMv8.1 libatomic: Reading and code analysis.
o Misc (2/10)
* Various meetings and discussions.
== Plan ==
o Continue on-going tasks (libatomic, benchamrking)
# Progress #
* TCWG-333, ISA bit treatment in ARM thumb mode. [2/10]
Post a patch to skip the test for thumb mode. Finish the prototype
which shows many issues that I can't overcome. Convince myself that
we should skip the test rather than support that in GDB.
* TCWG-518, ARM range stepping patches. [3/10].
11 of 12 patches are approved, and some of them are already
committed. Need to address one comment that merge to execution paths
into one, which requires some big changes in GDBserver for linux.
* TCWG-651, Support 'catch syscall' in remote for aarch64 and arm.[3/10]
My patches are posted upstream.
* TCWG-556, aarch64 gdb buildbot. [1/10]
They are online.
http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-m64/http://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-native-gdbserver-m64
* TCWG-654, Build both cross/native arm/aarch64 gcc 5.4.1 to replace
the gcc in my gdb tests. Ongoing. [1/10]
# Plan #
* Follow up all of them above,
* Holiday from Wed - Fri.
--
Yao
== Progress ==
1 day public holidays
IPA VRP
- Implemented a version of early VRP.
- Verified with simple test cases.
- Some test cases are failing in regression testing, looking into it.
- Some design decisions need to be firmed up with the upstream
discussions.
== Plan ==
- Follow upon remaining upstream patches
- IPA VRP
== Progress ==
* Out of office on Monday [2/10]
* Remove exit-on-error flag from CodeGen tests [TCWG-604] [1/10]
- This is a follow-up of TCWG-592: when changing the diag handler,
some of the tests started to fail, so we had to add an exit-on-error
flag to preserve the old behaviour until we can fix the tests.
- Patch fixing one of the AMDGPU tests (PR27761) - in upstream review
- Patch fixing the ARM test (PR27765) - committed upstream
- Submitted a patch removing the flag from llc - accepted upstream,
pending on approval of AMDGPU patch
* Use git worktree in llvm helper scripts [TCWG-587] [2/10]
- Merged. Working on some follow-up stories
- Change interface to llvm-build [TCWG-629] - Modify llvm-build to
accept the targets defined by CMake
- Fix a bug in llvm-env [TCWG-644] - Initially went unnoticed due to
zsh vs bash differences
- Allow cloning from read-only repo [TCWG-652] - This is so non-TCWG
people can use our helper scripts
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623] [5/10]
- Submitted a patch extracting 6 new subtarget features
- Investigating more features that could be extracted
== Plan ==
* OOO on Monday and Tuesday
* ARM: Do not test for CPUs, use SubtargetFeatures [TCWG-623]
== Progress ==
* Validation
- disk full on builders: analysis simply shows that we need more disk :)
- updated "buildapp" job to support building the Linux kernel. We
need more dev packages installed in the *build* schroots for it to
work though.
* Backports/snapshots
- fsf-6 branch merge review
* GCC
- small cleanup in neon* effective-target tests done
- re-testing neon-testgen.ml removal patch
- PR 67591 (ARM v8 Thumb IT blocks deprecated)
- followup on vect.exp's check_vect() support for old arm cores.
* Support
* Misc (conf-calls, meetings, emails, ...)
== Next ==
* Validation:
- patch reviews
* Backports
- restart the ones that failed due do disk space issues
* GCC
- monitor trunk regressions
- fix "check_vect" guard in gcc.dg/vect tests
- hopefully test-neongen.ml removal
- pr 67591
- advsimd tests
== Progress ==
TCWG-611 Initial Thumbv7a support for LLD committed upstream.
Interworking is supported via BLX only. This is enough to run hello
world on a modern arm-linux-gnueabihf target.
TCWG-653 Interworking veneer support for LLD
The existing support for veneers (thunks in LLD terminology) is Mips
specific for non-pi to pi calls. Unless there is something I'm missing
it looks broken in the general case as well.
I have an implementation of minimal veneers that I'm not particular
happy with, but can experiment with to see what the implementation
options are. I am likely to need to go via and RFC first.
Holiday on Friday.
== Next Week ==
Continue working on TCWG-653.
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.06 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.1+svn237469 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.1+svn237469
* Backport of [Bugfix] [AArch32] PR target/69857 Remove bogus early
return false; in gen_operands_ldrd_strd
* Backport of [AArch32] Add mode to probe_stack set operands
* Backport of [AArch32] arm/ieee754-df.S: Fix typos in comments
* Backport of [AArch32] Do not set ARM_ARCH_ISA_THUMB for armv5
* Backport of [AArch32] Error out for incompatible ARM multilibs
* Backport of [AArch32] Fix costing of sign-extending load in rtx costs
* Backport of [AArch32] Tie operand 1 to operand 0 in AESMC pattern
when fusing AES/AESMC
* Backport of [AArch32] Use proper output modifier for DImode register
in store exclusive patterns
* Backport of [AArch64] 1/4 Add the missing support of vfms_n_f32,
vfmsq_n_f32, vfmsq_n_f64
* Backport of [AArch64] 2/4 Extend vector mutiply by element to all
supported modes
* Backport of [AArch64] 3/4 Reimplement multiply by element to get rid
of inline assembly
* Backport of [AArch64] 4/4 Reimplement vmvn* intrinscis, remove inline assembly
* Backport of [AArch64] Adjust SIMD integer preference
* Backport of [AArch64] Delete ASM_OUTPUT_DEF and fallback to default
.set directive
* Backport of [AArch64] Don't define a macro when a variable will do
* Backport of [AArch64] Fix shift attributes
* Backport of [AArch64] Improve aarch64_case_values_threshold setting
* Backport of [AArch64] print_operand should not fallthrough from
register operand into generic operand
* Backport of [AArch64] Remove aarch64_simd_attr_length_move
* Backport of [AArch64] Set TARGET_OMIT_STRUCT_RETURN_REG to true
* Backport of [AArch64] Simplify ashl<mode>3 expander for SHORT modes
* Backport of [AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
* Backport of [AArch64] Tie operand 1 to operand 0 in AESMC pattern
when AES/AESMC fusion is enabled
* Backport of [AArch64] Update documentation of AArch64 options for GCC6
* Backport of [AArch64] Wrap SHIFT_COUNT_TRUNCATED in brackets
* Backport of [Testsuite] [AArch32] 01/11 Fix typo in vreinterpret.c
test comment
* Backport of [Testsuite] [AArch32] 02/11 Remove useless #ifdefs from
these tests: vmul, vshl and vtst
* Backport of [Testsuite] [AArch32] 03/11 AdvSIMD tests: be more verbose
* Backport of [Testsuite] [AArch32] 04/11 Add forgotten vsliq_n_u64
vsliq_n_s64 tests
* Backport of [Testsuite] [AArch32] 05/11 Add missing
vreinterpretq_p{8,16} tests
* Backport of [Testsuite] [AArch32] 06/11 Add missing vtst_p16 and
vtstq_p16, and vtst_p{8,16} and vtstq_p{8,16} tests
* Backport of [Testsuite] [AArch32] 07/11 Add vget_lane fp16 tests
* Backport of [Testsuite] [AArch32] 08/11 Add missing vstX_lane fp16 tests
* Backport of [Testsuite] [AArch32] 09/11 Add missing vrnd{,a,m,n,p,x} tests
* Backport of [Testsuite] [AArch32] 10/11 Add missing tests for
intrinsics operating on poly64 and poly128 types
* Backport of [Testsuite] [AArch32] 11/11 Add missing tests for
vreinterpret, operating of fp16 type
* Backport of [Testsuite] [AArch64] Fix vmul_elem_1.c on big-endian
* Backport of [Testsuite] [AArch64] Guard float64_t with __aarch64__
* Backport of [Testsuite] [AArch64] Skip cpu-diagnostics tests when
overriding -mcpu
* Backport of [Testsuite] gcc-dg: handle all return values when
shouldfail is set
* Backport of [Testsuite] PR70227, skip g++.dg/lto/pr69589_0.C on
targets without -rdynamic support
* Backport of [Testsuite] PR tree-optimization/57206
* Backport of [Testsuite] Skip tail call tests on Thumb-1 targets
* Backport of [Misc] Increase default value of lto-min-partition to 10000
* Backport of [Misc] introduce --param max-lto-partition for having an
upper bound on partition size
* Backport of [Cleanup] [AArch32] Fix typos in *thumb1_mulsi3 comment
* Backport of [Cleanup] [AArch32] Remove unused TARGET_ARM_V*M macros
* Backport of [Cleanup] [AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes
* Backport of [Cleanup] [AArch64] Remove an unused reload hook
* Backport of [Cleanup] Convert conditional compilation on
WORD_REGISTER_OPERATIONS
* Backport of [Cleanup] Remove spurious debug code
* Backport of [Cleanup] Move wrong ChangeLog entry from toplevel to
gcc ChangeLog
* Backport of [Doc] Fix minor doc bugs, signalling typo, major version
changes rare
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn237113 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.08
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2016.06/
Interesting changes in this GCC source package snapshot include:
Updates to GCC 5.6+svn237113
* Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/69245: Set
TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is
the default node to recalculate optab availability
* Backport of [Bugfix] [AArch64] [Linaro #2185] PR target/70002: Make
aarch64_set_current_function play nice with pragma resetting
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[1]. Source package snapshots are defined when the compiler is only
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Hi,
I've stumbled across an assembler error message that I don't understand.
bl1/aarch64/bl1_exceptions.S: Assembler messages:
bl1/aarch64/bl1_exceptions.S:53: Error: non-constant expression in
".if" statement
It occurs when building ARM Trusted Firmware with aarch64-linux-gnu-gcc
that ships with Ubuntu 16.04. It does _not_ occur with an older Linaro
toolchain. More details in [1].
The .align directives in the vector_base and vector_entry macros _do_
make a difference. Are they the cause of the problem? Would you
recommend writing the code differently? Or is it a compiler bug?
[1] https://github.com/ARM-software/tf-issues/issues/401
Thanks,
--
Jerome
