== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (6/10)
- Tested and posted SImode and DImode patch upstream
- Feedback recommended supporting thumb2 in addition to arm architectures
- Patch to support thumb2 fails on all thumb architectures;
investigating failures
* Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in
thumb2 mode (2/10)
- Created new bug, developed and successfully tested patch
- Fix posted upstream
* Bugzilla 70014 - [ARM] Predicate does not match constraint
(*subsi3_carryin_const) (1/10)
- Created new bug and patch
* Misc (1/10)
== Next week ==
* Bugzilla 69663 - Cleanup by merging patterns using mode iterators,
submit upstream
* Bugzilla 70008 - Respond to upstream comments as appropriate
* Bugzilla 70014 - Post patch and respond to upstream comments
* Travel to Linaro Connect beginning March 3rd
== This Week ==
* LTO (6/10)
- TCWG 528:
a) reduced test-case for the case when decl node gets visited multiple times
b) updated patch not to walk artificial record decls (typeinfo
objects) as per Richard's suggestion.
submitted upstream, waiting for review.
- benchmarking: Aarch64 SPEC2006-int benchmarks complete
- looked at pr57703
- Slides
* setting up perf on chromebook (2/10)
- perf doc
- got perf running on chromebook by manually building it and set of
(clumsy) workarounds.
- perf annotate shows no output and perf stat shows "not supported" for almost
all entires except "page faults"
- will give a try to dual boot chrubuntu on chromebook
* half-day sick leave (1/10)
- doctor's appointment for eye inflammation
* Misc (1/10)
- Meetings
== Next Week ==
- LTO
- tcwg-310
- look at jenkins tutorial in collaborate wiki
== Progress ==
* Support (4/10)
- Updating patch D17141 for Darwin, resubmitting, discussions.
- Understanding PR21778, may need changes to SLP
- Benchmarking some scheduler choices for A17
* Release (1/10)
- 3.8.0 RC3 validation
* Background (5/10)
- Code review, meetings, discussions, general support, etc.
- Sifting through CVs, interviews, etc.
# Progress #
* Support range stepping on arm-linux. TCWG-518. [5/10]
Post patch series about "the thread is stepping over breakpoint but
it spawns child thread". The fix is OK but the test case changes are
being reviewed.
The more I test my range stepping patches, the more existing bugs I
find. Looking at the bug "software single step the instruction
branch to self."
* AArch64 linux syscall for record/replay. TCWG-532. [1/10]
Patch is out for review.
* Fix some ARM reverse debugging bugs. TCWG-183. [1/10]
Patch is pushed in. The original implementation wasn't carefully
reviewed, so I am sure there are bugs somewhere else.
* Patch review on arm tracepoint support. [1/10]
One patch is approved but I insist that another patch should be done
in generic part instead of ARM specific part, but the author wants do
it in ARM specific part because he things it is simpler.
* Misc [2/10]
** Go through the Linux kernel awareness GDB patches quickly, the first
reaction is "split your patch, please".
** Go to London to collect my passport.
# Plan #
* Support range stepping on arm-linux. TCWG-518.
* TCWG-167, TCWG-532.
* Prepare for the Linaro Connect travel.
--
Yao
Hi All,
Does linaro distributes arm-gcc as a pre-built static tool chain
distribution? If yes, where can i download them from. Please point me some
location from where i can download.
--
Thanks & Regards,
M.Srikanth Kumar.
Bug with compiler flag handling - (no ticket) [2/10]
* Coremark-Pro was ignoring compiler flags
* Fixed that, made flag handling consistent across all benchmarks
Release benchmarking via Jenkins - TCWG-348 [1/10]
* Seems to work with test workload
Port to microinstance - TCG-432 [3/10]
* Looked at some inconsistent results
* Worried that one of the Junos may be sick, but unproven for now
Backport benchmarking via Jenkins - TCWG-352 [1/10]
* Finished 'general benchmarking' job
* Switched backport job to build/test cross-compilers
* Recent backport results bundles are corrupted, unable to work out why
Document benchmarking infrastructure - TCWG-496 [1/10]
* Documented Jenkins interface
Misc [2/10]
=Plan=
If updated builder becomes available, convert uinstance job to use it
Continue assessing target stability/looking at inconsistent results
Rework LAVA scripts to permit multiple targets per builder
Hi all,
I download the pre-built toolchain for one of our armv6 board.
https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-…
After plug it into Yocto as an external toolchain, it failed to install it
correctly.
../meta-linaro/meta-linaro-toolchain/recipes-devtools/external-linaro-toolchain/
external-linaro-toolchain.bb, do_install
| DEBUG: Executing shell function do_install
| cp: cannot stat
`/opt/gcc-linaro-arm-none-eabi-4.8-2014.04_linux/arm-none-eabi/libc/lib/*':
No such file or directory
Any suggestion?
Thanks,
Joel
== This Week ==
* LTO (5/10)
- TCWG-528:
a) addressed Richard's comments.
b) investigating timeout with my patch for g++.dg/torture/pr31863.C
c) using hash_map to prevent decl from getting visited more than
once prevents the issue
d) patch: http://people.linaro.org/~prathamesh.kulkarni/increase-struct-align.diff
- Slides: mostly prepared, few tidbits (and demos) remaining
- Benchmarking: couple more failures due to my silly mistakes, now in progress.
* TCWG-310 (1/10)
- started to look at loop peeling with perf
* Public Holiday (2/10)
- Shiv Jayanti
* Misc (2/10)
- Meetings
- Committed r233426
- Looked at PR69766 caused due to r232622
== Next Week ==
- LTO: TCWG-528, benchmarking, slides
- TCWG-310
# Progress #
* Support range stepping on arm-linux. TCWG-518. [4/10]
My patches causes some regressions but my patches just expose the
existing problem in GDBserver. Fix them and post patches upstream.
* Linaro connect. [2/10]
Go to London for visa application.
* GDB 7.11 release. No issues from my side. The tentative date of
release is Feb 26th.
* Fix GDB reverse debugging tests failures.
** Add more test cases, TCWG-183/TCWG-174. [2/10]
** Fix syscall handling in reverse debugging on ARM and AArch64.
TCWG-532/TCWG-167. [2/10]
# Plan #
* Support range stepping on arm-linux. Continue.
* Fix GDB reverse debugging tests failures. Continue.
* Review upstream patches.
* Go to London to collect my passport.
--
Yao
== Progress ==
* Validation
- AArch64 bare metal validation fixed. Patches waiting approval
- noticed a few failures caused by timeouts and failure to download
testcases. Maybe we are causing too much load on the builders/testers
* Connect preparation
- thoughts on extended validation
* GCC
- upstream monitoring, reported a couple a of regressions
- a few backports
- target attributes backport. Still having problems with our branch
* Misc (conf calls, meetings, emails, ....)
== Next ==
Holidays most of next week
Hi Toolchain Group,
I am trying to study the effect of loop buffer size on loop unrolling & the
way gcc (aarch64) handles this.
To my understanding, Loop Buffer is like i-cache which contains pre-decoded
instruction that can be re-used if branch instruction loopbacks to an
instruction
which is still present in the buffer. For example, in Intel’s Nehalem loop
buffer size is 28 u-ops. In LLVM compiler, it seems LoopMicroOpBufferSize
is for the same purpose.
However, I could not find any parameter/variable inside config/aarch64
representing loop buffer size. I am using Linaro gcc 5.2.1
[Question]
1. Is there any example inside aarch64 (or in general) which uses the loop
buffer size in loop unrolling decision? If yes, could you please mention
the relevant files or code section?
2. Otherwise any guidance/input on adding this support in aarch64 backend
assuming architecture has the loop buffer support.
[My Experiments/Code Browsing]
I have collected following information from code browsing. Please correct
if I missed or misunderstood something.
TARGET_LOOP_UNROLL_ADJUST - This target hook return the number of times a
loop can be unrolled.
This can be used to handle the architecture constraint such number of
memory references inside a loop e.g. ix86_loop_unroll_adjust() &
s390_loop_unroll_adjust().
On the same note, can this be used to handle loop buffer size too?
Without above hook, in loop-unroll.c parameters like
PARAM_MAX_UNROLLED_INSNS (default 200), PARAM_MAX_AVERAGE_UNROLLED_INSNS
(default 80) decides the unrolling factor. e.g. nunroll = PARAM_VALUE
(PARAM_MAX_UNROLLED_INSNS) / loop->ninsns;
In config/aarch64.c, I found align_loops variable in
aarch64_override_options_after_change() function.
I guess this an alignment done before starting the loop header in the
executable. This should not play any role in loop unrolling. Right?
So any guidance on how we can instruct aarch64 backend to utilize loop
buffer size in deciding the loop unrolling factor?
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
== Progress ==
LLDB development
-- Handling aggregate types return values on arm-linux-gnueabihf ABI.
Patch review and committed upstream. [TCWG-228] [1/10]
-- Debugging of stepping issues on chromebook (arm hard float ABI)
[TCWG-230] [2/10]
-- Progress on vector return values and aggregate types return values
with vector elements. [TCWG-531] [2/10]
-- Started work on complex return values and aggregate types return
values with vector elements. [TCWG-531] [2/10]
-- Started writing test cases handling complex and vector return
values and aggregate types return values with vector and complex
elements. [TCWG-531] [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Finish work on complex return values and aggregate types return
values with vector elements. [TCWG-531]
-- Finish work on vector return values and aggregate types return
values with vector elements. [TCWG-531]
-- Finish work on test cases handling complex and vector return
values. [TCWG-531]
Port to microinstance - TCWG-432 [2/10]
* Better reporting/error trapping in dispatch scripts
* Some back and forth with Lab about builder implementation
* Started assessing target stability
* Fixed a few bugs in reporting/bundle generation
Document benchmarking infrastructure - TCWG-496 [2/10]
* All done apart from Jenkins interface
* Need to finish Jenkins interface first...
Generate graphs for benchmarking - TCWG-268 [1/10]
* Generate a bunch of filters and charts to track Coremark-Pro
* Wrote up what I learned about LAVA's reporting interface
EEMBC benchmarks - (no ticket) [2/10]
* Checked over what we had, decided it was probably complete
* Imported to our repos
* Wrote up what I know about this
* Moved Coremark-Pro into its own repo
** Broke some code that had worked by coincidence
** Fixed it
Misc
* Usual meetings/mail/etc
* Some fun with what turned out to be a known bug in the
linaro-media-create now used in main LAVA instance
* Educated guess as to why Jenkins-triggered jobs produced no bundle
** Raised a ticket
** Think I know how to fix on my side
=Plan=
If updated builder becomes available, convert uinstance jobs to use it
Test release benchmark job
Finish backport benchmarking
Document Jenkins interface
Assess target stability
More image reports in microinstance
== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10)
- Successfully tested SImode add, sub, and neg overflow patterns
- Developed DImode addv and subv patterns
- Debugging failures in DImode overflow patterns
* TCWG 833 - [ARM] Exploit Wide Add operations when appropriate (2/10)
- Made changes corresponding to upstream review
- Rebased to latest trunk
- Resolved issues with new test cases
- Fixed formatting and style issues
- Resubmitted upstream for final review
- previous review gave conditional support for GCC 7
- Successfully retested
- One remaining expected failure on targets with wide add support
(including aarch64)
- Plan to file a upstream bugzilla
* Misc (1/10)
* Vacation (4/10)
== Next week ==
* Bugzilla 69663 - Debug and resolve DImode pattern failures
* Bugzilla 69008 - Restart investigation
== Progress ==
BUGS (8/10)
- PR69708:
* Posted a patch to fix.
- PR69589:
* Posted a patch to fix.
- PR66726:
* Omitted the patch bu that triggered a bootstrap failure for ppc64.
Reverted the patch and looking into it.
- Misc (2/10)
* gcc/bug list
* Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
== This Week ==
* LTO/IPA (8/10)
- TCWG-528: patch cross-tested on arm*-*-* and aarch64*-*-*
- Submitted patch upstream to add entry for aarch64 to target-supports.exp
- Experimenting with Kugan's ipa-vrp prototype
- Had a look at ipa-comdat
- Connect slides
* benchmarking (1/10)
- issues with deployment (TICKET-259)
- Using Bernie's workaround for the above issue
* Misc (1/10)
- Meetings
== Next Week ==
- LTO/IPA: tcwg-528, benchmarking, look at ipa-comdat enhancements.
- Investigate tcwg-310 with perf
- Finish connect slides
== Progress ==
* Conference (2/10)
- More EuroLLVM paper reviews, discussions
* Support (5/10)
- Looking at PR16275 (review D17141)
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- Buildbots broken, bisects, debugging
- Defining and posting Job ad (wanna work with us?)
# Progress #
* Support range stepping on arm-linux. TCWG-518. [4/10]
Preparatory patches are pushed in. Patches are being tested.
* Linaro connect. [3/10]
** Slides are done.
** Collect documents for visa application.
* GDB 7.11 release. TCWG-509. [1/10]
Release branch is created. Discuss on issue related to big endian,
but ARM is the only user of that code.
* Patch review, especially arm tracepoint support. [2/10].
# Plan #
* TCWG-518, upstream patches if tests are OK.
* TCWG-172, continue look at test parity between arm and x86_64.
* Go to London on Wed for visa application.
--
Yao
Hi Linaro Toolchain Group,
I have a question on the ldr instruction selection in the aarch64 backend.
Could someone help me in this regards, please?
I am trying to allow only type A instructions while disabling the type B.
Type A example: ldr x4, [x20,x1] ---> allow
Type B example: ldr x1, [x9,x3,lsl #3] ---> disable
Experiment/My Understanding -
aarch64_classify_address() returns true if rtx X is a valid address. If
allow_reg_index_p=true then it calls aarch64_classify_index().
aarch64_classify_index() identify the address mode of second operand (op1)
and accordingly calculate the shift.
If shift=0 then type A is generated otherwise Type B will be generated.
Thus if (shift != 0) then I am returning 'false' from
aarch64_classify_index().
-------------------------patch---------
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3586,6 +3586,9 @@ aarch64_classify_index (struct aarch64_address_info
*info, rtx x,
if (GET_CODE (index) == SUBREG)
index = SUBREG_REG (index);
+ if (shift != 0)
+ return false;
if ((shift == 0 ||
(shift > 0 && shift <= 3
&& (1 << shift) == GET_MODE_SIZE (mode)))
---------------------------------------
Result -
Before change
ldr x0, [x13,x0,lsl #3]
After Change
lsl x1, x1, #3
ldr x0, [x15,x1]
Question -
How the returning 'false' from aarch64_classify_index() is resulting in the
selection of type A versus type B?
I could not find the function which is taking the decision based on return
from aarch64_classify_address().
Could someone please explain this process or point me to the relevant files
or code?
Please correct me if my understanding is wrong.
Thanks in advance for your time and patience.
--
with regards,
Virendra Kumar Pathak
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.02 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn233233 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.05
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn233233
* Backport of [Bugfix] [AArch32] PR target/69135: Mark ARMv8 vcvt
instructions as unconditional
* Backport of [Bugfix] [AArch32] PR target/69187 PR target/65624
* Backport of [Bugfix] [AArch32] PR target/69403: Bug in
thumb2_ior_scc_strict_it pattern
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796: Add
patterns for QImode and HImode comparison with zero
* Backport of [Bugfix] [AArch64] PR target/69176
* Backport of [Bugfix] PR target/69175
* Backport of [Bugfix] PR tree-optimization/67781
* Backport of [AArch32] Remove neon_reinterpret, use casts
* Backport of [AArch32] [RTEMS] Add Cortex-M7 multilib for FPU support
* Backport of [AArch64] Avoid emitting zero immediate as zero register
* Backport of [AArch64] Fix jit crash on aarch64
* Backport of [AArch64] Fix -mcpu/arch=native support for LSE
* Backport of [AArch64] Handle compare of zero_extract form of
TST-immediate in rtx costs
* Backport of [AArch64] Handle CSEL of zero_extended operands in rtx costs
* Backport of [AArch64] Properly reject invalid attribute strings
* Backport of [AArch64] Remove TODO (redundant type conversions) in arm_neon.h
* Backport of [Testsuite] [AArch32] Fix
gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0
* Backport of [Testsuite] [AArch32] Fix g++.dg/pr67989.C test failure
when running with -march or -mcpu
* Backport of [Doc] Remove outdated text from lto.texi
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Automated release benchmark Jenkins job - TCWG-348 [2/10]
* Drafted a job, it succeeds in dispatching to the uinstance
* Needs testing
Port to microinstance - TCWG-432 [5/10]
* Almost entirely fixing up the CPU2006 -> LAVA reporting
* Should now be able to report CPU2000 results as well
Misc [3/10]
* Mail/meetings/etc
* Connect slides
=Plan=
If builder is available, convert uinstance jobs to use it
Test release benchmark job
Produce image reports in microinstance
Attempt to finish backport benchmarking
Actually finish documentation
== Progress ==
LLDB development
-- Committed patch fixing return value handling on arm-linux-gnueabihf
[TCWG-228]
-- Finished work on handling aggregate types return values on
arm-linux-gnueabihf ABI. [TCWG-228] [5/10]
-- Submitted single and double precision handlers for upstream review.
[TCWG-228]
-- Started work on vector return values and aggregate types return
values with vector elements. [TCWG-228] [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
Public Holiday [2/10]
-- Friday 5th February 2016
== Plan ==
LLDB development
-- Update and commit aggregate type return values on
arm-linux-gnueabihf ABI patch.
-- Investigate issues while stepping over library functions on
arm-linux-gnueabihf
-- Further work on vector return values on arm-linux-gnueabihf ABI
== Progress ==
o Connect slides (2/10)
* Undefined behavior (slides and review)
o GCC dev. (5/10)
* Remote testing sanitizing: found a solution in dejaGNU and GCC
implementation and test ongoing
* Analysed and closed PR69590
o Misc (3/10)
* Various meetings
* internal discussions
== Plan ==
o Continue on GCC testsuite
o FSF branch merge and 2016.02 snapshot
== This Week ==
* TCWG-319 (1/10)
- Updated patch and re-posted, queued for stage-1
- Regression with armeb for -fvect-cost-model=cheap
* TCWG-528 (1/10)
- speculatively increase alignment for global structs with arrays.
* Backports (3/10)
- committed backport: 232688
- r232631 (partially?) reverts 232330
- modified script to follow git log <file>
* benchmarking (2/10)
- 464.h264ref triggered ICE for -O3 -mfloat-abi=hard -mfpu=neon,
reduced it (PR69282)
- Benchmarking tcwg-310 on SPEC2006 - +0.10%
- Benchmarking INT SPEC2k6 for aarch64 without LTO complete.
* Slides (2/10)
- Read doc and created outline for most of slides,
- expect to be mostly complete by next week
* Misc (1/10)
- Meetings
== Next Week ==
- LTO benchmarking and slides
- TCWG-528
== Progress ==
- LTO and TCWG480 (5/10)
* Started testing with the prototype patch
* Still trying to figure out what is the best way to set_range_info
based on IPA
* i.e., how to find the SSA_NAME initialized with PARM_DECL
- Misc (5/10)
* gcc/bug list
* Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
== This week ==
* Backports (1/10)
- 232493 - Committed to Linaro branch
- 232727 - Committed to Linaro branch
- 232414 - Committed to Linaro branch
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (5/10)
- Implemented SImode add, sub, and neg overflow patterns
- add overflow patterns pass testing
- debugging failures in subv overflow patterns
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Investigating Dead Store Elimination pass to determine if code can
be improved
* Misc (1/10)
== Next week ==
* Personal days on February 8th and 9th
* Resolve bugzilla 69663 subv issues and work on DImode patterns
* Bugzilla 69008 - continue investigation
* Investigate test case failure on backport 232600
* Off from Mon. to Wed. [6/10]
# Progress #
* TCWG-518. Support range stepping on arm-linux. Ongoing. [2/10]
First do software single step in GDBserver side.
* TCWG-509. GDB 7.11 release. [1/10]
PR 19474, review Keith's patch. The patch is OK to mainline, but we
don't want to take risk shipping this patch to 7.11 release.
* Misc, register to Linaro Connect BKK16, and get clarifications on my
visa to Thailand. [1/10]
* Monitor the discussions on kenernel awareness upstreams, and comment
on the display of CPSR register.
# Plan #
* Finish Linaro Connect slides.
* TCWG-509. Anything needed for GDB 7.11 release.
* TCWG-518.
--
Yao
== Progress ==
* Validation
- disabled Auto Backport Engine until the patch selection
is improved to avoid saturating the builders with undesirable
builds.
- AArch64 bare metal validation (bug #2011). Submitted a patch
for dejagnu aarch64-fv8.exp, and one for our builders schroots.
Will need another patch, in ABE.
- timeout issues: no progress
* Misc (conf calls, meetings, emails, ....)
- internal discussions
== Next ==
* Validation
- debug timeout issues
- cleanup
== Progress ==
LLDB development
-- Submitted patch fixing return value handling on arm-linux-gnueabihf
[TCWG-228] [5/10]
-- float and double types handled in above patch did some more
investigation for handling structs [TCWG-228] [2/10]
-- Collecting LLDB status data, ran testsuite on different hardware
and minor investigation of fails and xfails [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Update float/double return value patch after review and commit upstream
-- Submit a fix for handling structs as return types on arm-linux-gnueabihf
Public Holiday
-- Friday 5th February 2016
== Progress ==
- Public Holiday (2/10)
- LTO and TCWG480 (4/10)
* Started with a prototype for VRP
* Experimenting with simple test cases
- Misc (4/10)
* gcc/bug list
* LTO and Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
Hi,
My ARM target runs glibc 2.13 and I am having a hard time finding a
linaro toolchain for it. It seems like all the ones I have found ship with
glibc 2.15 (even old ones).
Where can I find the binaries for a linux toolchain that targets armhf
with glibc 2.13?
Thanks in advance
Port to microinstance - TCWG-432 [4/10]
* Went a few more rounds with the race condition, finally nailed it
* Tidied up transfer of Coremark results to LAVA
* Added metadata to LAVA results
* Sketched some charts using LAVA reporting
* Improved runtime benchmark logging
Benchmarking infrastructure documentation - TCWG-496 [2/10]
* Most everything drafted, some docs finished
Controlled image builds - TCWG-360 [2/10]
* Reached a better understanding of what a hwpack is
* Generated a few images, none of them booted
Misc [2/10]
=Plan=
Benchmarking-102 slides for Connect
Finish documentation
Backport benchmarking
If builder shows up in microinstance, evaluate stability of its Junos
o Teaching activity (3/10)
== Progress ==
o Infra/Validation (1/10)
* A couple of patches for release script.
o GCC dev. (2/10)
* Remote testing sanitizing: still digging.
o Misc (4/10)
* Various meetings (usual ones and internal ones)
* Backports reviews
== Plan ==
o Continue on GCC testsuite and opened cards.
Port to microinstance - TCWG-432 [2/10]
* More fallout from attempts to fix race condition
* Began cleaning job submission YAML
Controlled image builds - TCWG-360 [1/10]
* (Re)learned how to generate images from hwpack + filesystem
Struck down by flu [7/10]
== This week ==
* Backports (3/10)
- 232493 - Unrelated aarch64 failure and non-thumb asan test on
aarch32 big endian
- 232600 - All tests pass
- 232727 - unrelated non-thumb test failure
asan/deep-thread-stack-1.c asan/deep-thread-stack-1.c)
* Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard
names (3/10)
- Development halted due to submission of related patch by Richard
Henderson:
- https://gcc.gnu.org/ml/gcc-patches/2016-01/txt0WQOxpo0_5.txt
- Began implementation of aarch32 related patch
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Additional code is being generated in default abi case with
structure alignment equal to 8
- Investigating Dead Store Elimination pass to determine if code can
be improved
* Misc (1/10)
== Next week ==
* Create new bugzilla for aarch32 to implement overflow standard names
and continue implementation
* Bugzilla 69008 - continue investigation
* Work on backports as necessary
== This Week ==
* PR43721 (1/10)
- Submitted upstream.
- GIMPLE parts approved by Richard, wants someone else to approve
rtl-expansion bits.
* benchmarking (1/10)
- benchmarking tcwg-310 on cortex-a53, cortex-a57, r1-a12, cortex-a17
- submitted job for INT benchmarks for SPEC2006 for aarch64
* backports (2/10)
- r232688 automated backport build failed for aarch64-linux-gnu on
tcwg-backport-gerrit:
Unrecognized macro 'GERRIT_PATCHSET_REVISION' in '#664-
${GERRIT_PATCHSET_REVISION,length=8}'
Build successful on tcwg-backport-maxim
- r232737, r232631 have at least 4 dependencies.
- wrote bare bones script to find dependencies for revision
* ccp (2/10)
- enhancement to hoist stmt thru phi with all constant args
- patch: http://people.linaro.org/~prathamesh.kulkarni/ccp-mov.diff
- rejected by Richard, since PRE handles this case when it's
trivially profitable and phiprop does similar transform. In general,
it's not profitable to have this transform included.
* Public Holiday (2/10)
* Misc (2/10)
- Meetings
- Slides: short & long term activities
== Next Week ==
- PR43721: look at using define_expand instead of hook, add test-cases
and few nits
- tcwg-319 - analyse with perf
- LTO INT benchmarking for arm, aarch64 and x86
- LTO Slides
# Progress #
In general, GDB mainline is in a good state. All known bugs are fixed,
but still have some patches pending for review. The release can be
created after these pending patches are in.
* Fix fail in gdb.base/interrupt-noterm.exp. TCWG-517. Done. [2/10]
* Fix fail in gdb.fortran/vla-value.exp. TCWG-521. Done. [1/10]
* PR 19474. [3/10]
Tried different approaches, but still cause regression.
Fortunately get the right maintainer involved. Will discuss with
him on this bug next week.
* Range stepping doesn't work on arm-linux, which slows down stepping
over a line of source. TCWG-518. [2/10]
* Prepare slides for Linaro Connect. [2/10]
# Plan #
* Off on Mon. to Wed.
* Linaro connect slides.
* Thailand visa.
* Other issues on GDB 7.11 release, if any.
--
Yao
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2 Release Archives.
http://releases.linaro.org/components/toolchain/binaries/5.2-2015.11-2/http://releases.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2/
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will shortly
spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes
stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* GCC 5.2 2015.11-2
The Linaro GCC 5.2 2015.11-2 binary toolchain release respin is built from
the Linaro GCC-5.2-2015.11-2 release source archive. The Linaro
GCC-5.2-2015.11-2 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-2-rc1 release-candidate.
* GCC 5.2 2015.11-2-rc1
The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
Linaro bug 1995 identified a problem where the installed sysroot was not in
the place that the compiler expected the sysroot to be located by default.
This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain
release-candidate.
* GCC 5.2 2015.11-1
The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the
Linaro GCC-5.2-2015.11-1 release source archive. The Linaro
GCC-5.2-2015.11-1 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-1-rc1 release-candidate.
* GCC 5.2 2015.11-1-rc1
The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
The arm-eabi-none multi-libs are now available in the toolchain sysroot as
a fix for Linaro bug 1920 and Linaro bug 1922 .
Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 .
Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain
(arm-linux-gnueabihf triple).
* GCC 5.2 2015.11
The Linaro GCC 5.2 2015.11 binary toolchain release is built from the
Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11
release source archive is derived from the same sources as the Linaro
GCC-5.2-2015.10 snapshot source archive.
* GCC 5.2 2015.11-rc1
The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built
from the Linaro GCC-5.2-2015.11 release-candidate source archive. The
Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from
the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive.
--
Ryan S. Arnold
Linaro Toolchain Working Group - Engineering Manager
www.linaro.org
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2-rc1
Release-Candidate Archives.
http://snapshots.linaro.org/components/toolchain/binaries/5.2-2015.11-2-rc1/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2-r…
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will shortly
spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes
stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at http://
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* GCC 5.2 2015.11-2-rc1
The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
Linaro bug 1995 identified a problem where the installed sysroot was not in
the place that the compiler expected the sysroot to be located by default.
This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain
release-candidate.
* GCC 5.2 2015.11-1
The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the
Linaro GCC-5.2-2015.11-1 release source archive. The Linaro
GCC-5.2-2015.11-1 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-1-rc1 release-candidate.
* GCC 5.2 2015.11-1-rc1
The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
The arm-eabi-none multi-libs are now available in the toolchain sysroot as
a fix for Linaro bug 1920 and Linaro bug 1922 .
Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 .
Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain
(arm-linux-gnueabihf triple).
* GCC 5.2 2015.11
The Linaro GCC 5.2 2015.11 binary toolchain release is built from the
Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11
release source archive is derived from the same sources as the Linaro
GCC-5.2-2015.10 snapshot source archive.
* GCC 5.2 2015.11-rc1
The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built
from the Linaro GCC-5.2-2015.11 release-candidate source archive. The
Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from
the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive.
--
Ryan S. Arnold
Linaro Toolchain Working Group - Engineering Manager
www.linaro.org
Hi!
When using the linaro-4.9-2015.05 toolchain on the Linux master and on Linux stable releases
I am seeing a build issue below when using the allyesconfig. This does not seem to occur on the 5.2 tool chain.
We cannot move to 5.2 tool chain for our releases as they are based on 4.9.
LD init/built-in.o
arch/arm/kernel/built-in.o:(.text.fixup+0x1d4): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
arch/arm/kernel/built-in.o:(.text.fixup+0x1e0): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
arch/arm/kernel/built-in.o:(.text.fixup+0x1ec): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
drivers/built-in.o: In function `combiner_handle_cascade_irq':
:(.text+0x834): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0x868): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_irq_set_type':
:(.text+0xad0): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xb10): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_raise_softirq':
:(.text+0xc8c): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock_irqsave' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xdc8): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock_irqrestore' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_irq_set_affinity':
:(.text+0xefc): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xf78): additional relocation overflows omitted from the output
make: *** [vmlinux] Error 1
Please advise to how to resolve this issue within the 4.9 Linaro tool chain
Dan
--
------------------
Dan Murphy
== Progress ==
* Support (5/10)
- Bug triage: reviewing the 300+ bugs on ARM
- remaining 220 bugs are all still pertinent
* Release (2/10)
- Woes due to GCC ABI change may delay 3.8.0 release
- Tested on both ARM and AArch64 with old environment, all green.
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- EuroLLVM, FOSDEM preparations, ARM sync
o Teaching activity (2/10)
== Progress ==
o Linaro GCC (2/10)
* Delivered 2016.01-1 Snapshot respin with fix for Linaro PR #2001
* Gave some support on backports
o Infra/Validation (1/10)
* Compared ABE master results.
o GCC dev. (2/10)
* Identified the way testcases are uploaded on the remote target in
cross validation as the root cause of validation instabilities. Digging
into GCC .exp files and DejaGNU to fix it cleanly.
o Misc (3/10)
* Various meetings
* Start a backport/validation document
== Plan ==
o Continue backports/validation document
o Continue on the ongoing cards opened
== Progress ==
LLDB development
-- Debugging of return value related issue coming up on chromebook ARM
[TCWG-228] [2/10]
-- Setup of Arm testing on AArch64 using chroot on highkey [TCWG-231] [1/10]
-- Investigation of failures when setting watchpoint on vector
variables [TCWG-231] [4/10]
Miscellaneous [3/10]
-- Meetings, emails, discussions etc.
-- Travel for Thailand visa application
== Plan ==
LLDB development
-- Try a fix of return value related issue coming up on chromebook ARM
-- Submit fix for failures when setting watchpoint on vector variables
-- Mark triaged failures with xfail decorators and bug numbers.
== Progress ==
LLDB development
-- Triage testsuite failures on AArch64 highkey [TCWG-231] [5/10]
-- Triage testsuite failures on chromebook (armel) [TCWG-228] [3/10]
Miscellaneous [2/10]
-- Meetings, emails, discussions etc.
-- Documents preparation for Thailand visa
== Plan ==
LLDB development
-- Create chroots for armhf and armel testing on AArch64 highkey board
-- Investigate ABI related issues when returning values on armel and armhf
-- Further bug triage and mark triaged failures with xfail decorators
and bug numbers.
Miscellaneous
-- Travel for Thailand visa application submission.
