- linaro-toolchain - lists.linaro.org

by Bernie Ogden

Port to microinstance - TCWG-432 [17/10] * Investigating difference between LAVA and 'desktop Juno' runtimes ** Some of this was down to piles of /dev/console output - redirecting to file improved SPEC build time by 75%! ** Some cases make sense, others remain unexplained ** Might just go away if we update the Juno image * Wrote up how to do benchmarking for minimal-trust cases ** Needs both lab and development work * Merged another large tranche of changes back to benchmarking branch ** Microinstance more or less functional, main instance benchmarking seems unbroken ** But some more tweaks to make as Lab work happens * Prepared backport benchmarking for merge Misc [3/10] =Plan= * Submit backport benchmarking for review * Tweak uinstance in reaction to lab work * Implement the non-lab side of minimal-trust benchmarking * Return to looking at Juno image generation * Look some more at LAVA/desktop runtime differences * Implement small improvements, if time

10 years, 1 month

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[Weekly] 07-11 March 2016

by Michael Collison

== This week == * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10) - Resolved thumb2 failures - Negdi2 was not generating instruction to set condition codes * Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in thumb2 mode (1/10) - Created new patch using new predicate that matches arm and thumb2 constraints - Received approval to GCC 7 stage 1 * Bugzilla 70014 - [ARM] Predicate does not match constraint (*subsi3_carryin_const) (1/10) - Fix checked into trunk * Linaro Connect meetings (5/10) == Next week == * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names - Create compile only test cases and re-run validation testing - Post new patch upstream

10 years, 1 month

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Updating LLVM on Debian/Ubuntu

by Renato Golin

Hey, Regarding the GCC ABI 5 issue, I was wondering what's the policy behind updating packages on stable updates for both Debian and Ubuntu. Our time frame is a bit constrained, and we definitely will have to take some hard decisions in the next six months, so I'd like to understand everything that is at stake before I have my own opinion. LLVM has a 6 month major cycle, releasing around February / August. Major releases are allowed to break the ABI. Major breakages need one release warning period. Ubuntu has a 6 month release cycle, around April / October. IIUC, major releases are allowed to have new versions of packages, but updates for the next few years have to keep within the same major release. Debian has a -1 years release cycle (heh), and has the same major / minor policy, which makes it a lot harder to update major versions. However, I believe unstable is still not closed, nor will be in August this year, so updating to LLVM 3.9 will not be a problem, but it will mean users will have to wait a bit more to get a working LLVM. The time frame is then: 3.8.0 released March (without the fix) Ubuntu X released April 3.9.0 releases August (hopefully with a fix) Ubuntu X+1 released October Debian freezes ?? LLVM 3.8.1 ?? If we don't back-port GCC ABI 5 into 3.8.1, Ubuntu users will not have the fix ever, unless you *can* update to 3.9.0 in August. Ubuntu X+1 will be fine using 3.9, as will Debian after August, unless you guys freeze before that. I believe both Debian and Ubuntu have a trunk-based LLVM package for experimental use only, and it would be bad, but not completely broken, to recommend users to use that meanwhile. If Debian freezes *before* 3.9.0 is out, or if Ubuntu can't update to 3.9.0 on April's release, then we'll have a strong reason to back-port the change to 3.8.x. If not, even though it will be uncomfortable for users until August, the argument is not that strong and will be hard to get it through. Any comments? Ideas? Does any of that make sense? cheers, --renato

10 years, 1 month

2
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Some questions about the gcc __sync intrinsics

by Edward Nevill

Hi, I have been comparing the stock gcc 5.2 and the Linaro 5.2 (Linaro GCC 5.2-2015.11-1) and have noticed a difference with the __sync intrinsics. Here is the simple test case --- cut here --- int add_int(int add_value, int *dest) { return __sync_add_and_fetch(dest, add_value); } --- cut here --- Compiling with the stock gcc 5.2 (-S -O3) I get --------- add_int: .L2: ldaxr w2, [x1] add w2, w2, w0 stlxr w3, w2, [x1] cbnz w3, .L2 mov w0, w2 ret --------- Wheras with Linaro gcc 5.2 I get --------- add_int: .L2: ldxr w2, [x1] add w2, w2, w0 stlxr w3, w2, [x1] cbnz w3, .L2 dmb ish mov w0, w2 ret --------- Why the extra (unnecessary?) memory barrier? Also, is it worthwhile putting a prfm before the ldaxr. EG add_int: prfm pst1strm, [x1] .L2: ldaxr w2, [x1] See the following thread http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/355996.html All the best, Ed

10 years, 1 month

3
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FreeBSD + LLD Update

by Renato Golin

FYI, http://lists.llvm.org/pipermail/llvm-dev/2016-March/096449.html cheers, --renato

10 years, 1 month

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[ACTIVITY] Week 09

by Yvan Roux

== Progress == o GCC dev. (7/10) * Remote validation sanitizing: - fixed last issues in dejagnu patch and submitted it uptsream - 2 more cleanup/fix dejagnu patches submitted and merged upstream - proposed a fix/workaround for the output pattern issues (>400 failures removed with this patch) o Misc (3/10) * Various meetings * internal discussions == Plan == o Try to follow connect remotely o Extended validation work

10 years, 2 months

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[ACTIVITY] 29 February-4 March 2016

by Christophe Lyon

== Progress == * GCC bugs: - #2073 tried to reproduce it with a manually-built toolchain. No luck * GCC validation: - added support to choose simulated cpu (different from --with-cpu) * GCC: - completing Neon intrinsics tests, to prepare cleanup * Validation: - small improvements * Misc (conf calls, meetings, emails, ...) == Next == Remote Connect

10 years, 2 months

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[ACTIVITY]

by Renato Golin

== Progress == * Support (5/10) - Working on PR17193 - Continue review on D17141 * Background (5/10) - Code review, meetings, discussions, general support, etc. - Connect preparations - GCC ABI 5 discussions - Assessing Swift calling convention impact ARM back-end - Interviews

10 years, 2 months

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[ACTIVITY] 29 Feb -- 04 Mar

by Yao Qi

# Progress # * TCWG-545, Handle "branch-to-self" instruction in single stepping. [5/10] Patches are posted upstream for review. * TCWG-532, one patch is committed and one patch is posted for review. [2/10] * Tweak ARM process record. [2/10] Two patches are pushed in. Many test fails are fixed. * FSF patches review. [1/10]. # Plan # * Linaro Connect. -- Yao

10 years, 2 months

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gcc 5.2 code quality

by Edward Nevill

Hi, I have just switched to gcc 5.2 from 4.9.2 and the code quality does seem to have improved significantly. For example, it now seems much better at using ldp/stp and it seems to has stopped gratuitous use of the SIMD registers. However, I still have a few whinges:-) See attached copy.c / copy.s (This is a performance critical function from OpenJDK) pd_disjoint_words: cmp x2, 8 <<< (1) sub sp, sp, #64 <<< (2) bhi .L2 cmp w2, 8 <<< (1) bls .L15 .L2: add sp, sp, 64 <<< (2) (1) If count as a 64 bit unsigned is <= 8 then it is probably still <= 8 as a 32 bit unsigned. (2) Nowhere in the function does it store anything on the stack, so why drop and restore the stack every time. Also, minor quibble in the disass, why does sub use #64 whereas add uses just '64' (appreciate this is probably binutils, not gcc). .L15: adrp x3, .L4 add x3, x3, :lo12:.L4 ldrb w2, [x3,w2,uxtw] <<< (3) adr x3, .Lrtx4 add x2, x3, w2, sxtb #2 br x2 (3) Why use a byte table, this is not some sort of embedded system. Use a word table and this becomes. .L15: adrp x3, .L4 add x3, x3, :lo12:.L4 ldr x2, [x3, x2, lsl #3] br x2 An aligned word load takes exactly the same time as a byte load and we save the faffing about calculating the address. .L10: ldp x6, x7, [x0] ldp x4, x5, [x0, 16] ldp x2, x3, [x0, 32] <<< (4) stp x2, x3, [x1, 32] <<< (4) stp x6, x7, [x1] stp x4, x5, [x1, 16] (4) Seems to be something wrong with the load scheduler here? Why not move the stp x2, x3 to the end. It does this repeatedly. Unfortunately as this function is performance critical it means I will probably end up doing it in inline assembler which is time consuming, error prone and non portable. * Whinge mode off Ed

10 years, 2 months

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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.3-2016.02-rc1

by Ryan Arnold

The Linaro Binary Toolchain ==================================== Release-Candidate Linaro GCC 5.3-2016.02-rc1 is now available. Notice: All Linaro GCC 5 series toolchain users should migrate to the latest version of the Linaro GCC 5 toolchain in order to mitigate potential security exposure to CVE-2015-7545. See the NEWS section below for details. Download release-candidate packages from: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02-rc1/ http://snapshots.linaro.org/components/toolchain/binaries/5.3-2016.02-rc1/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 5.3-2016.02-rc1 FSF glibc 2.21 (release/2.21) Linaro newlib 2.1.0-2014.09 (linaro_newlib-branch) Linaro binutils 2.25 (linaro_binutils-2_25-branch) FSF GDB 7.10 (gdb-7.10-branch) Linaro toolchain package git branches are hosted at: http://git.linaro.org/?a=project_list&s=toolchain%2F&btnS=Search NEWS for Linaro GCC 5.3-2016.02-rc1 ==================================== * Applied fix for CVE-2015-7545 - A stack-based buffer overflow in glibc's getaddrinfo() was corrected in glibc 2.23 and backported into glibc 2.21. https://sourceware.org/ml/libc-alpha/2016-02/msg00416.html * ARMv8.1 Instruction Support - ARMv8.1 instructions support was checked into GCC and binutils. It has been backported into Linaro GCC 5.3 and Linaro binutils 2.25. * Backported -Bsymbolic-functions into Linaro binutils 2.25. * Performance related backports from Linaro GCC 5.2-2015.11, Linaro GCC 5.2-2015.12, and Linaro GCC 5.3-2016.01-1 have been included. See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

10 years, 2 months

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[ACTIVITY] 22nd - 26th February

by kugan

== Progress == - BUGS (6/10) * Posted patches for the bugs https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01974.html https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01927.html https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01905.html * Addressed review comments - Connect presentation (2/10) - Misc (2/10) * gcc/bug list * Meetings == Plan == * LTO * bugs

10 years, 2 months

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[ACTIVITY] Week 08

by Yvan Roux

== Progress == o GCC dev. (7/10) * Remote validation sanitizing: - Implemented and tested a pure dejagnu fix (the actual implementation works fine for GCC but might be an issue in a different context, a cleaner fix almost done) - Found a latent issue in GCC profiling test harness * ARM and AArch64 backends LRA cleanup: - Looked at the remaining artifacts, will prepare a patch for GCC 7 o Misc (3/10) * Various meetings * internal discussions == Plan == o Finalize and submit dejagnu fix

10 years, 2 months

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[ACTIVITY] 22nd - 26th February

by Bernie Ogden

Port to microinstance - TCWG-432 [7/10] * Merged last few months of development back to benchmarking branch * Restored support for multiple targets per builder * Updated builder landed, altered jobs to work with it ** Removed assumption that host filesystem is non-persistent ** Stacked up test runs for the weekend Transfer secret management to LAVA [1/10] * LAVA jobs now use a within-LAVA key to access sources Misc [2/10] * Unsuccessful fiddling with heat-monitoring tools on Juno * Usual background of mail and meetings =Plan= * Fallout from weekend test runs ** Some failure is going on, need to investigate * Update docs and Jenkins configs w.r.t. last week's activity * Further investigation on a couple of LAVA issues that are causing me pain ** Un-deserializable bundles ** Inaccessible image reports * Continue assessing target stability/looking at inconsistent results

10 years, 2 months

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[Weekly] 22-26 February 2016

by Michael Collison

== This week == * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (6/10) - Tested and posted SImode and DImode patch upstream - Feedback recommended supporting thumb2 in addition to arm architectures - Patch to support thumb2 fails on all thumb architectures; investigating failures * Bugzilla 70008 - [ARM] Reverse subtract with carry can be generated in thumb2 mode (2/10) - Created new bug, developed and successfully tested patch - Fix posted upstream * Bugzilla 70014 - [ARM] Predicate does not match constraint (*subsi3_carryin_const) (1/10) - Created new bug and patch * Misc (1/10) == Next week == * Bugzilla 69663 - Cleanup by merging patterns using mode iterators, submit upstream * Bugzilla 70008 - Respond to upstream comments as appropriate * Bugzilla 70014 - Post patch and respond to upstream comments * Travel to Linaro Connect beginning March 3rd

10 years, 2 months

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[ACTIVITY] 22-26 Feb 2016

by Prathamesh Kulkarni

== This Week == * LTO (6/10) - TCWG 528: a) reduced test-case for the case when decl node gets visited multiple times b) updated patch not to walk artificial record decls (typeinfo objects) as per Richard's suggestion. submitted upstream, waiting for review. - benchmarking: Aarch64 SPEC2006-int benchmarks complete - looked at pr57703 - Slides * setting up perf on chromebook (2/10) - perf doc - got perf running on chromebook by manually building it and set of (clumsy) workarounds. - perf annotate shows no output and perf stat shows "not supported" for almost all entires except "page faults" - will give a try to dual boot chrubuntu on chromebook * half-day sick leave (1/10) - doctor's appointment for eye inflammation * Misc (1/10) - Meetings == Next Week == - LTO - tcwg-310 - look at jenkins tutorial in collaborate wiki

10 years, 2 months

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[ACTIVITY]

by Renato Golin

== Progress == * Support (4/10) - Updating patch D17141 for Darwin, resubmitting, discussions. - Understanding PR21778, may need changes to SLP - Benchmarking some scheduler choices for A17 * Release (1/10) - 3.8.0 RC3 validation * Background (5/10) - Code review, meetings, discussions, general support, etc. - Sifting through CVs, interviews, etc.

10 years, 2 months

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[ACTIVITY] 22-26 Feb 2016

by Yao Qi

# Progress # * Support range stepping on arm-linux. TCWG-518. [5/10] Post patch series about "the thread is stepping over breakpoint but it spawns child thread". The fix is OK but the test case changes are being reviewed. The more I test my range stepping patches, the more existing bugs I find. Looking at the bug "software single step the instruction branch to self." * AArch64 linux syscall for record/replay. TCWG-532. [1/10] Patch is out for review. * Fix some ARM reverse debugging bugs. TCWG-183. [1/10] Patch is pushed in. The original implementation wasn't carefully reviewed, so I am sure there are bugs somewhere else. * Patch review on arm tracepoint support. [1/10] One patch is approved but I insist that another patch should be done in generic part instead of ARM specific part, but the author wants do it in ARM specific part because he things it is simpler. * Misc [2/10] ** Go through the Linux kernel awareness GDB patches quickly, the first reaction is "split your patch, please". ** Go to London to collect my passport. # Plan # * Support range stepping on arm-linux. TCWG-518. * TCWG-167, TCWG-532. * Prepare for the Linaro Connect travel. -- Yao

10 years, 2 months

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[ACTIVITY] 22-26 February 2016

by Christophe Lyon

Short week, off Mon-Wed == Progress == * Validation - testing timeout increase * Connect preparation - discussions on extended validation * GCC - looking at bug #2073 (GCC crash under Windows) - target attributes backport * Misc (conf-calls, meetings, emails, ....) == Next == * Connect preparation * GCC bugs

10 years, 2 months

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Static arm-gcc

by $rik＠nth

Hi All, Does linaro distributes arm-gcc as a pre-built static tool chain distribution? If yes, where can i download them from. Please point me some location from where i can download. -- Thanks & Regards, M.Srikanth Kumar.

10 years, 2 months

2
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[ACTIVITY] 15th - 19th Februrary

by Bernie Ogden

Bug with compiler flag handling - (no ticket) [2/10] * Coremark-Pro was ignoring compiler flags * Fixed that, made flag handling consistent across all benchmarks Release benchmarking via Jenkins - TCWG-348 [1/10] * Seems to work with test workload Port to microinstance - TCG-432 [3/10] * Looked at some inconsistent results * Worried that one of the Junos may be sick, but unproven for now Backport benchmarking via Jenkins - TCWG-352 [1/10] * Finished 'general benchmarking' job * Switched backport job to build/test cross-compilers * Recent backport results bundles are corrupted, unable to work out why Document benchmarking infrastructure - TCWG-496 [1/10] * Documented Jenkins interface Misc [2/10] =Plan= If updated builder becomes available, convert uinstance job to use it Continue assessing target stability/looking at inconsistent results Rework LAVA scripts to permit multiple targets per builder

10 years, 2 months

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[Weekly] 15-19 February 2016

by Michael Collison

== This week == * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (4/10) - Successfully tested SImode add, sub, and neg overflow patterns - Resolved DImode addv and subv code generation issues. - Minor cleanup work remains before posting upstream * Bugzilla 69008 - gcc emits unneeded memory access when passing trivial structs by value (ARM) (3/10) - Restarted by investigating dead store elimination pass * Misc (1/10) * Expedited passport (2/10) == Next week == * Bugzilla 69663 - Cleanup by merging patterns using mode iterators, submit upstream * Bugzilla 69008 - Continue investigation

10 years, 2 months

1
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[fido][meta-linaro-toolchain] arm-none-eabi-4.8-2014.04

by Xi Zhou Zhou

Hi all, I download the pre-built toolchain for one of our armv6 board. https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-… After plug it into Yocto as an external toolchain, it failed to install it correctly. ../meta-linaro/meta-linaro-toolchain/recipes-devtools/external-linaro-toolchain/ external-linaro-toolchain.bb, do_install | DEBUG: Executing shell function do_install | cp: cannot stat `/opt/gcc-linaro-arm-none-eabi-4.8-2014.04_linux/arm-none-eabi/libc/lib/*': No such file or directory Any suggestion? Thanks, Joel

10 years, 2 months

2
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[ACTIVITY] 15-19 Feb 2016

by Prathamesh Kulkarni

== This Week == * LTO (5/10) - TCWG-528: a) addressed Richard's comments. b) investigating timeout with my patch for g++.dg/torture/pr31863.C c) using hash_map to prevent decl from getting visited more than once prevents the issue d) patch: http://people.linaro.org/~prathamesh.kulkarni/increase-struct-align.diff - Slides: mostly prepared, few tidbits (and demos) remaining - Benchmarking: couple more failures due to my silly mistakes, now in progress. * TCWG-310 (1/10) - started to look at loop peeling with perf * Public Holiday (2/10) - Shiv Jayanti * Misc (2/10) - Meetings - Committed r233426 - Looked at PR69766 caused due to r232622 == Next Week == - LTO: TCWG-528, benchmarking, slides - TCWG-310

10 years, 2 months

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[ACTIVITY] 15 - 19 February 2016

by Yao Qi

# Progress # * Support range stepping on arm-linux. TCWG-518. [4/10] My patches causes some regressions but my patches just expose the existing problem in GDBserver. Fix them and post patches upstream. * Linaro connect. [2/10] Go to London for visa application. * GDB 7.11 release. No issues from my side. The tentative date of release is Feb 26th. * Fix GDB reverse debugging tests failures. ** Add more test cases, TCWG-183/TCWG-174. [2/10] ** Fix syscall handling in reverse debugging on ARM and AArch64. TCWG-532/TCWG-167. [2/10] # Plan # * Support range stepping on arm-linux. Continue. * Fix GDB reverse debugging tests failures. Continue. * Review upstream patches. * Go to London to collect my passport. -- Yao

10 years, 2 months

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[ACTIVITY] 15-19 February 2016

by Christophe Lyon

== Progress == * Validation - AArch64 bare metal validation fixed. Patches waiting approval - noticed a few failures caused by timeouts and failure to download testcases. Maybe we are causing too much load on the builders/testers * Connect preparation - thoughts on extended validation * GCC - upstream monitoring, reported a couple a of regressions - a few backports - target attributes backport. Still having problems with our branch * Misc (conf calls, meetings, emails, ....) == Next == Holidays most of next week

10 years, 2 months

1
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setting loop buffer size in the gcc (aarch64)

by Virendra Kumar Pathak

Hi Toolchain Group, I am trying to study the effect of loop buffer size on loop unrolling & the way gcc (aarch64) handles this. To my understanding, Loop Buffer is like i-cache which contains pre-decoded instruction that can be re-used if branch instruction loopbacks to an instruction which is still present in the buffer. For example, in Intel’s Nehalem loop buffer size is 28 u-ops. In LLVM compiler, it seems LoopMicroOpBufferSize is for the same purpose. However, I could not find any parameter/variable inside config/aarch64 representing loop buffer size. I am using Linaro gcc 5.2.1 [Question] 1. Is there any example inside aarch64 (or in general) which uses the loop buffer size in loop unrolling decision? If yes, could you please mention the relevant files or code section? 2. Otherwise any guidance/input on adding this support in aarch64 backend assuming architecture has the loop buffer support. [My Experiments/Code Browsing] I have collected following information from code browsing. Please correct if I missed or misunderstood something. TARGET_LOOP_UNROLL_ADJUST - This target hook return the number of times a loop can be unrolled. This can be used to handle the architecture constraint such number of memory references inside a loop e.g. ix86_loop_unroll_adjust() & s390_loop_unroll_adjust(). On the same note, can this be used to handle loop buffer size too? Without above hook, in loop-unroll.c parameters like PARAM_MAX_UNROLLED_INSNS (default 200), PARAM_MAX_AVERAGE_UNROLLED_INSNS (default 80) decides the unrolling factor. e.g. nunroll = PARAM_VALUE (PARAM_MAX_UNROLLED_INSNS) / loop->ninsns; In config/aarch64.c, I found align_loops variable in aarch64_override_options_after_change() function. I guess this an alignment done before starting the loop header in the executable. This should not play any role in loop unrolling. Right? So any guidance on how we can instruct aarch64 backend to utilize loop buffer size in deciding the loop unrolling factor? Thanks in advance for your time. -- with regards, Virendra Kumar Pathak

10 years, 2 months

3
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[ACTIVITY] 8 - 12 February 2016

by Omair Javaid

== Progress == LLDB development -- Handling aggregate types return values on arm-linux-gnueabihf ABI. Patch review and committed upstream. [TCWG-228] [1/10] -- Debugging of stepping issues on chromebook (arm hard float ABI) [TCWG-230] [2/10] -- Progress on vector return values and aggregate types return values with vector elements. [TCWG-531] [2/10] -- Started work on complex return values and aggregate types return values with vector elements. [TCWG-531] [2/10] -- Started writing test cases handling complex and vector return values and aggregate types return values with vector and complex elements. [TCWG-531] [2/10] Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB development -- Finish work on complex return values and aggregate types return values with vector elements. [TCWG-531] -- Finish work on vector return values and aggregate types return values with vector elements. [TCWG-531] -- Finish work on test cases handling complex and vector return values. [TCWG-531]

10 years, 2 months

1
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[ACTIVITY] 8th - 12th February

by Bernie Ogden

Port to microinstance - TCWG-432 [2/10] * Better reporting/error trapping in dispatch scripts * Some back and forth with Lab about builder implementation * Started assessing target stability * Fixed a few bugs in reporting/bundle generation Document benchmarking infrastructure - TCWG-496 [2/10] * All done apart from Jenkins interface * Need to finish Jenkins interface first... Generate graphs for benchmarking - TCWG-268 [1/10] * Generate a bunch of filters and charts to track Coremark-Pro * Wrote up what I learned about LAVA's reporting interface EEMBC benchmarks - (no ticket) [2/10] * Checked over what we had, decided it was probably complete * Imported to our repos * Wrote up what I know about this * Moved Coremark-Pro into its own repo ** Broke some code that had worked by coincidence ** Fixed it Misc * Usual meetings/mail/etc * Some fun with what turned out to be a known bug in the linaro-media-create now used in main LAVA instance * Educated guess as to why Jenkins-triggered jobs produced no bundle ** Raised a ticket ** Think I know how to fix on my side =Plan= If updated builder becomes available, convert uinstance jobs to use it Test release benchmark job Finish backport benchmarking Document Jenkins interface Assess target stability More image reports in microinstance

10 years, 2 months

1
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[Weekly] 08-12 February 2016

by Michael Collison

== This week == * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10) - Successfully tested SImode add, sub, and neg overflow patterns - Developed DImode addv and subv patterns - Debugging failures in DImode overflow patterns * TCWG 833 - [ARM] Exploit Wide Add operations when appropriate (2/10) - Made changes corresponding to upstream review - Rebased to latest trunk - Resolved issues with new test cases - Fixed formatting and style issues - Resubmitted upstream for final review - previous review gave conditional support for GCC 7 - Successfully retested - One remaining expected failure on targets with wide add support (including aarch64) - Plan to file a upstream bugzilla * Misc (1/10) * Vacation (4/10) == Next week == * Bugzilla 69663 - Debug and resolve DImode pattern failures * Bugzilla 69008 - Restart investigation

10 years, 2 months

1
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[ACTIVITY] 08 - 12 February

by Kugan

== Progress == BUGS (8/10) - PR69708: * Posted a patch to fix. - PR69589: * Posted a patch to fix. - PR66726: * Omitted the patch bu that triggered a bootstrap failure for ppc64. Reverted the patch and looking into it. - Misc (2/10) * gcc/bug list * Undefined behaviors slides for connect * Meetings == Plan == * LTO * bugs

10 years, 2 months

1
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[ACTIVITY] 8 - 12 Feb 2016

by Prathamesh Kulkarni

== This Week == * LTO/IPA (8/10) - TCWG-528: patch cross-tested on arm*-*-* and aarch64*-*-* - Submitted patch upstream to add entry for aarch64 to target-supports.exp - Experimenting with Kugan's ipa-vrp prototype - Had a look at ipa-comdat - Connect slides * benchmarking (1/10) - issues with deployment (TICKET-259) - Using Bernie's workaround for the above issue * Misc (1/10) - Meetings == Next Week == - LTO/IPA: tcwg-528, benchmarking, look at ipa-comdat enhancements. - Investigate tcwg-310 with perf - Finish connect slides

10 years, 2 months

1
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[ACTIVITY]

by Renato Golin

== Progress == * Conference (2/10) - More EuroLLVM paper reviews, discussions * Support (5/10) - Looking at PR16275 (review D17141) * Background (3/10) - Code review, meetings, discussions, general support, etc. - Buildbots broken, bisects, debugging - Defining and posting Job ad (wanna work with us?)

10 years, 2 months

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[ACTIVITY] 08 - 12 February

by Yao Qi

# Progress # * Support range stepping on arm-linux. TCWG-518. [4/10] Preparatory patches are pushed in. Patches are being tested. * Linaro connect. [3/10] ** Slides are done. ** Collect documents for visa application. * GDB 7.11 release. TCWG-509. [1/10] Release branch is created. Discuss on issue related to big endian, but ARM is the only user of that code. * Patch review, especially arm tracepoint support. [2/10]. # Plan # * TCWG-518, upstream patches if tests are OK. * TCWG-172, continue look at test parity between arm and x86_64. * Go to London on Wed for visa application. -- Yao

10 years, 2 months

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ldr instruction selection in the aarch64 backend

by Virendra Kumar Pathak

Hi Linaro Toolchain Group, I have a question on the ldr instruction selection in the aarch64 backend. Could someone help me in this regards, please? I am trying to allow only type A instructions while disabling the type B. Type A example: ldr x4, [x20,x1] ---> allow Type B example: ldr x1, [x9,x3,lsl #3] ---> disable Experiment/My Understanding - aarch64_classify_address() returns true if rtx X is a valid address. If allow_reg_index_p=true then it calls aarch64_classify_index(). aarch64_classify_index() identify the address mode of second operand (op1) and accordingly calculate the shift. If shift=0 then type A is generated otherwise Type B will be generated. Thus if (shift != 0) then I am returning 'false' from aarch64_classify_index(). -------------------------patch--------- --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3586,6 +3586,9 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x, if (GET_CODE (index) == SUBREG) index = SUBREG_REG (index); + if (shift != 0) + return false; if ((shift == 0 || (shift > 0 && shift <= 3 && (1 << shift) == GET_MODE_SIZE (mode))) --------------------------------------- Result - Before change ldr x0, [x13,x0,lsl #3] After Change lsl x1, x1, #3 ldr x0, [x15,x1] Question - How the returning 'false' from aarch64_classify_index() is resulting in the selection of type A versus type B? I could not find the function which is taking the decision based on return from aarch64_classify_address(). Could someone please explain this process or point me to the relevant files or code? Please correct me if my understanding is wrong. Thanks in advance for your time and patience. -- with regards, Virendra Kumar Pathak

10 years, 2 months

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[ANNOUNCE] Linaro GCC 5 2016.02 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2016.02 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.3+svn233233 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2016.05 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.3+svn233233 * Backport of [Bugfix] [AArch32] PR target/69135: Mark ARMv8 vcvt instructions as unconditional * Backport of [Bugfix] [AArch32] PR target/69187 PR target/65624 * Backport of [Bugfix] [AArch32] PR target/69403: Bug in thumb2_ior_scc_strict_it pattern * Backport of [Bugfix] [AArch64] PR rtl-optimization/68796: Add patterns for QImode and HImode comparison with zero * Backport of [Bugfix] [AArch64] PR target/69176 * Backport of [Bugfix] PR target/69175 * Backport of [Bugfix] PR tree-optimization/67781 * Backport of [AArch32] Remove neon_reinterpret, use casts * Backport of [AArch32] [RTEMS] Add Cortex-M7 multilib for FPU support * Backport of [AArch64] Avoid emitting zero immediate as zero register * Backport of [AArch64] Fix jit crash on aarch64 * Backport of [AArch64] Fix -mcpu/arch=native support for LSE * Backport of [AArch64] Handle compare of zero_extract form of TST-immediate in rtx costs * Backport of [AArch64] Handle CSEL of zero_extended operands in rtx costs * Backport of [AArch64] Properly reject invalid attribute strings * Backport of [AArch64] Remove TODO (redundant type conversions) in arm_neon.h * Backport of [Testsuite] [AArch32] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0 * Backport of [Testsuite] [AArch32] Fix g++.dg/pr67989.C test failure when running with -march or -mcpu * Backport of [Doc] Remove outdated text from lto.texi Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 2 months

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[ACTIVITY] 1st - 5th February

by Bernie Ogden

Automated release benchmark Jenkins job - TCWG-348 [2/10] * Drafted a job, it succeeds in dispatching to the uinstance * Needs testing Port to microinstance - TCWG-432 [5/10] * Almost entirely fixing up the CPU2006 -> LAVA reporting * Should now be able to report CPU2000 results as well Misc [3/10] * Mail/meetings/etc * Connect slides =Plan= If builder is available, convert uinstance jobs to use it Test release benchmark job Produce image reports in microinstance Attempt to finish backport benchmarking Actually finish documentation

10 years, 2 months

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[ACTIVITY] 1 - 5 February 2016

by Omair Javaid

== Progress == LLDB development -- Committed patch fixing return value handling on arm-linux-gnueabihf [TCWG-228] -- Finished work on handling aggregate types return values on arm-linux-gnueabihf ABI. [TCWG-228] [5/10] -- Submitted single and double precision handlers for upstream review. [TCWG-228] -- Started work on vector return values and aggregate types return values with vector elements. [TCWG-228] [2/10] Miscellaneous [1/10] -- Meetings, emails, discussions etc. Public Holiday [2/10] -- Friday 5th February 2016 == Plan == LLDB development -- Update and commit aggregate type return values on arm-linux-gnueabihf ABI patch. -- Investigate issues while stepping over library functions on arm-linux-gnueabihf -- Further work on vector return values on arm-linux-gnueabihf ABI

10 years, 2 months

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[ACTIVITY] Week 05

by Yvan Roux

== Progress == o Connect slides (2/10) * Undefined behavior (slides and review) o GCC dev. (5/10) * Remote testing sanitizing: found a solution in dejaGNU and GCC implementation and test ongoing * Analysed and closed PR69590 o Misc (3/10) * Various meetings * internal discussions == Plan == o Continue on GCC testsuite o FSF branch merge and 2016.02 snapshot

10 years, 2 months

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[ACTIVITY] 1 - 5 Feb 2016

by Prathamesh Kulkarni

== This Week == * TCWG-319 (1/10) - Updated patch and re-posted, queued for stage-1 - Regression with armeb for -fvect-cost-model=cheap * TCWG-528 (1/10) - speculatively increase alignment for global structs with arrays. * Backports (3/10) - committed backport: 232688 - r232631 (partially?) reverts 232330 - modified script to follow git log <file> * benchmarking (2/10) - 464.h264ref triggered ICE for -O3 -mfloat-abi=hard -mfpu=neon, reduced it (PR69282) - Benchmarking tcwg-310 on SPEC2006 - +0.10% - Benchmarking INT SPEC2k6 for aarch64 without LTO complete. * Slides (2/10) - Read doc and created outline for most of slides, - expect to be mostly complete by next week * Misc (1/10) - Meetings == Next Week == - LTO benchmarking and slides - TCWG-528

10 years, 2 months

1
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[ACTIVITY] 01 - 05 Feb 2016

by Kugan

== Progress == - LTO and TCWG480 (5/10) * Started testing with the prototype patch * Still trying to figure out what is the best way to set_range_info based on IPA * i.e., how to find the SSA_NAME initialized with PARM_DECL - Misc (5/10) * gcc/bug list * Undefined behaviors slides for connect * Meetings == Plan == * LTO * bugs

10 years, 2 months

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[Weekly] 01-05 February 2016

by Michael Collison

== This week == * Backports (1/10) - 232493 - Committed to Linaro branch - 232727 - Committed to Linaro branch - 232414 - Committed to Linaro branch * Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (5/10) - Implemented SImode add, sub, and neg overflow patterns - add overflow patterns pass testing - debugging failures in subv overflow patterns * Bugzilla 69008 - gcc emits unneeded memory access when passing trivial structs by value (ARM) (3/10) - Investigating Dead Store Elimination pass to determine if code can be improved * Misc (1/10) == Next week == * Personal days on February 8th and 9th * Resolve bugzilla 69663 subv issues and work on DImode patterns * Bugzilla 69008 - continue investigation * Investigate test case failure on backport 232600

10 years, 2 months

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[ACTIVITY]

by Renato Golin

== Progress == * Conferences (4/10) - Fosdem organisation, travel, video cutting (all lost) - EuroLLVM paper review, schedule, meetings * Buildbots (2/10) - Bisecting test-suite regression - Infrastructure clean up - Reverting broken patches * Support (1/10) - Looking at some bugs, fixed PR26450 * Background (3/10) - Code review, meetings, discussions, general support, etc. - Jira farming, planing, resourcing

10 years, 3 months

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[ACTIVITY] 01-05 Feb 2016

by Yao Qi

* Off from Mon. to Wed. [6/10] # Progress # * TCWG-518. Support range stepping on arm-linux. Ongoing. [2/10] First do software single step in GDBserver side. * TCWG-509. GDB 7.11 release. [1/10] PR 19474, review Keith's patch. The patch is OK to mainline, but we don't want to take risk shipping this patch to 7.11 release. * Misc, register to Linaro Connect BKK16, and get clarifications on my visa to Thailand. [1/10] * Monitor the discussions on kenernel awareness upstreams, and comment on the display of CPSR register. # Plan # * Finish Linaro Connect slides. * TCWG-509. Anything needed for GDB 7.11 release. * TCWG-518. -- Yao

10 years, 3 months

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[ACTIVITY] 1-5 February 2016

by Christophe Lyon

== Progress == * Validation - disabled Auto Backport Engine until the patch selection is improved to avoid saturating the builders with undesirable builds. - AArch64 bare metal validation (bug #2011). Submitted a patch for dejagnu aarch64-fv8.exp, and one for our builders schroots. Will need another patch, in ABE. - timeout issues: no progress * Misc (conf calls, meetings, emails, ....) - internal discussions == Next == * Validation - debug timeout issues - cleanup

10 years, 3 months

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[ACTIVITY] 25 - 29 January 2016

by Omair Javaid

== Progress == LLDB development -- Submitted patch fixing return value handling on arm-linux-gnueabihf [TCWG-228] [5/10] -- float and double types handled in above patch did some more investigation for handling structs [TCWG-228] [2/10] -- Collecting LLDB status data, ran testsuite on different hardware and minor investigation of fails and xfails [2/10] Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == LLDB development -- Update float/double return value patch after review and commit upstream -- Submit a fix for handling structs as return types on arm-linux-gnueabihf Public Holiday -- Friday 5th February 2016

10 years, 3 months

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[ACTIVITY] 25-29 January 2016

by Kugan

== Progress == - Public Holiday (2/10) - LTO and TCWG480 (4/10) * Started with a prototype for VRP * Experimenting with simple test cases - Misc (4/10) * gcc/bug list * LTO and Undefined behaviors slides for connect * Meetings == Plan == * LTO * bugs

10 years, 3 months

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armhf toolchain with glibc 2.13

by Aaron R

Hi, My ARM target runs glibc 2.13 and I am having a hard time finding a linaro toolchain for it. It seems like all the ones I have found ship with glibc 2.15 (even old ones). Where can I find the binaries for a linux toolchain that targets armhf with glibc 2.13? Thanks in advance

10 years, 3 months

2
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[ACTIVITY] 25th - 29th January

by Bernie Ogden

Port to microinstance - TCWG-432 [4/10] * Went a few more rounds with the race condition, finally nailed it * Tidied up transfer of Coremark results to LAVA * Added metadata to LAVA results * Sketched some charts using LAVA reporting * Improved runtime benchmark logging Benchmarking infrastructure documentation - TCWG-496 [2/10] * Most everything drafted, some docs finished Controlled image builds - TCWG-360 [2/10] * Reached a better understanding of what a hwpack is * Generated a few images, none of them booted Misc [2/10] =Plan= Benchmarking-102 slides for Connect Finish documentation Backport benchmarking If builder shows up in microinstance, evaluate stability of its Junos

10 years, 3 months

1
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[ACTIVITY] Week 04

by Yvan Roux

o Teaching activity (3/10) == Progress == o Infra/Validation (1/10) * A couple of patches for release script. o GCC dev. (2/10) * Remote testing sanitizing: still digging. o Misc (4/10) * Various meetings (usual ones and internal ones) * Backports reviews == Plan == o Continue on GCC testsuite and opened cards.

10 years, 3 months

1
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