# Progress #
* Holiday on Monday [2/10]
* TCWG-857, [4/10]. All the multi-arch work are done
(I hope) but patches can't be sent out until kernel patches
are pushed in upstream.
** Collect some arguments from kernel folks to defend my change
"32-bit CPSR to 64-bit PSTATE". Patch is posted out.
** Finish the patch to convert siginfo_t between 32-bit debuggee
and 64-bit debugger. Done. Will post it next week.
** Get right TLS base in multi-arch debugging. Patch is done.
* Happen to see we can improve GDB performance in some case by
avoid sending some packets. Patch is done, but need to collect
some performance data. [2/10]
* Misc [1/10]
** Close some tickets, TCWG-567, TCWG-876, as they are done.
* TCWG-757 [1/10], many patches review.
# Plan #
* Continue to upstream multi-arch patches.
* Upgrade my juno board kernel to git master to test kernel patches
for multi-arch debugging work properly.
* Collect some GDB performance data for my patch.
--
Yao
Hi-
It seems that there is some discrepancy between Linaro GCC 4.8 2015.06 and Linaro GCC 4.8 2014.11 with regards to precompiled headers.
It appears that 2015.06 doesn't even attempt to open the precompiled headers according to strace. I have been looking on gcc mailing list but have not been able to find any fixes related to precompiled headers.
Does anyone have any pointers as to what should I be looking at to get to the bottom of this issue?
This simple program compiles without any problems on 2014.11, but fails on 2015.06 because 2015.06 doesn't even attempt to read tst.h.gch created by "make header"
dragans@tst:~$ cat Makefile
PROJ=tst
CC=arm-linux-gcc
LD=arm-linux-ld
all: header $(PROJ)
header: $(PROJ)._
cp $(PROJ)._ $(PROJ).h
$(CC) -x c-header -c $(PROJ).h
$(PROJ):
$(RM) $(PROJ).h
$(CC) $(PROJ).c -o $(PROJ)
clean:
$(RM) $(PROJ).h.gch $(PROJ).h $(PROJ)
dragans@tst:~$ cat tst._
#include <stdio.h>
dragans@tst:~$ cat tst.c
#include "tst.h"
int main(int argc, char**argv)
{
char *s = "Test";
printf("%s\n", s);
return 0;
}
== Progress ==
LLDB development
-- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [7/10]
-- Improve error handling of AArch64 watchpoint code. Submitted,
got reviewed and committed http://reviews.llvm.org/D12328
-- Looked into ways to improve watchpoint installation lag.
-- Looked into issues pertaining to un-alligned watchpoints installation.
-- Committed upstream arm hardware breakpoint and watchpoint support
[TCWG-770] [TCWG-794] [1/10]
-- Ran lldb testsuite in various combinations to figure out Arm and
AArch64 status [1/10]
-- Testing on chromebook with precise chroot works.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Try to find ways to debug lldb-server platform forked gdbserver instance.
-- Test, debug and fix testsuite failures on Arm and AArch64.
== Progress ==
LLDB development
-- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [2/10]
-- Looked into watchpoint tests which are still failing after
committing watchpoint support and bug fixes.
-- Modifications to arm hardware breakpoint and watchpoint support
[TCWG-770] [TCWG-794] [7/10]
-- Resubmitted the pending patch http://reviews.llvm.org/D9703
-- Testing on chromebook with precise chroot works.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
-- Looking into slow data transfer issues on chromebook and highkey board
== Plan ==
LLDB development
-- Get patches reviewed and committ them.
-- Continue looking into tests which are still failing on Arm and AArch64
-- Run test comparison between linux x86, android arm and linux arm
o 3 days off (6/10)
== Progress ==
o Linaro GCC validation (3/10)
* Reviewed, validated and committed on-going backports
* backported more revisions
o Misc (1/10)
* Various meetings
== Plan ==
o Continue backports/validation
== Progress ==
* Annual Leave (2/10)
* Widening pass (TCWG-547) - 6/10
- Fixed all execution test failure.
- bootstrap failure due to “Drop copy-rename” is still not resolved.
Found a workaround.
- Sorted debug_stmt handling
* TACT 1/10
- Started looking to cross execution set-up
* Misc - 1/10
- gcc-patches, gcc-bugs list
== Plan ==
* Continue with widening pass
== This Week ==
* TCWG-777 (3/10)
- Fixed ICE with the patch - toolchain builds with the patch.
- Sent patch to tcwg list for review
- Investigating why combine fails to combine
arm_andsi3_insn/arm_cmpsi_insn into zeroextractsi_compare0_scratch
when the pass uses ud-chains to find def but works
when def is found using ad-hoc way.
* TCWG-871 (4/10)
- Getting familiar with firefox build system
- LTO build lto/non-lto on x86 and arm (doc)
- Figuring out how to resolve "plugin needed to handle lto object" error.
tried the following:
binutils configured with: --enable-plugin, --enable-lto
gcc configured with: --enable-lto --with-ld-plugin=<just built ld>
Doesn't appear to work.
* TCWG-835 (1/10)
- Build failure with spec (PR67399)
* Misc (2/10)
- Meetings
- Looked at rtl dataflow (df.h and df*.c) and ree.c
== Next Week ==
Continue with TCWG-777, TCWG-835, TCWG-871
== This week ==
* TCWG-832 -Exploit vector multiply by scalar instructions when multiple
scalars are used as
coefficients in a loop (2/10)
- Initial investigation.
* TCWG-833 - Exploit Wide Add operations when appropriate (4/10)
- Ramana is reviewing Aarch32 patch
- Recoded Aarch64 support to use vect_select
- Debugging Aarch64 lto, tree-dump regression suite failures
* TCWG-834 - Use non-unit stride loads by preference when applicable (1/10)
- TCWG 834 is Bugzilla 67323 upstream; Richard Biener took ownership
as a vectorizer failure
- My plan was to write a test case that failed until fixed, but
Richard indicated this is not
standard practice
- Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10)
- Separated patch from Bugzilla 67321 patch and sent upstream
- Pinged upstream for comments
- Bugzilla 67320 - Incorrect standard names for wide addition (1/10)
- committed upstream in trunk
* Misc (1/10)
- Conference calls
== Next week ==
- Resolve Aarch64 TCWG-833 patch, validate and upstream
- Additional investigation into TCWG-832
# Progress #
* TCWG-857 [3/10]
With one kernel fix, HW breakpoint works for unaligned address
(2-byte aligned).
Debug linux kernel with KGDB. KGDB exposes an existing GDB bug, I
fixed it, but need some time thinking about how to submit it upstream.
* TCWG-567, arm watchpoint fixes [4/10]. All fails are fixed, but need
another round of test to confirm. ARM HW watchpoint doesn't work on
4.0.0 kernel, but I don't investigate on it.
* TCWG-757 [2/10], some patches review.
* Misc, meeting, [1/10]
# Plan #
* TCWG-857.
* Upstream the leftover of aarch64 multi-arch patches.
--
Yao
== Progress ==
o Linaro GCC validation (9/10)
* Analysed x86_64 fstack-protector and sse2 issue
* This is due to "ulimit -v" usage which brakes asan testing
and gcc testsuite caching mechanism.
* Validation is now stable on Hetzner/Austin hardware
* Documented summer validation issues
* Validate and committed on-going backports
o Upstream GCC (0/10)
* Armeb OOM fix committed into gcc-5
o Misc (1/10)
* Various meetings
== Plan ==
o 3 days off
o Continue backports/validation
== Progress ==
* Widening pass (TCWG-547) - 8/10
- Fixed all but one execution test failure.
- aarch64 and x86 are clean
- arm has one but this looks like a latent issue (in expand); looking
into it
- Latest trunk with aarch64 miscompiles stage2 fwprop (-fno-forwprop
works).
This happens with the commit 94f92c36a83d66a893c3bc6f00a038ba3dbe2a6f
[PR64164] Drop copyrename, use coalescible partition as base when
optimizing
- Tried forcing the same promote_mode for x86_64 and can reproduce it
with x86_64 also.
- Looking into it to see if this is an error with the commit
* Misc - 2/10
- gcc-patches, gcc-bugs list
== Plan ==
- Continue with widening pass
Upcoming Absences
* Away from this Wednesday until next Tuesday, inclusive
Benchmark infrastructure - TCWG-360 [1/10]
* Finished filling out cards/bugs for benchmarking work
* Which makes the rest of this report more fine-grained
Multinode wrapper - TCWG-888 [2/10]
* Completed oversubscription workaround
* Herded most tests through
* Uncovered one significant bug, seems fixed
Centralized source/results storage - TCWG-722 [1/10]
* Wrote draft of source/results handling rules
* Confirmed that old repos are subsets of new repos
Noise control experiments - TCWG-897 [2/10]
* Learned more about firmware, openembedded
* Juno running a minimal filesystem, needs some tidying up
Misc [4/10]
* Including a further 1/10 of ARM management
=Plan=
* Herd remaining multinode tests through
** Depends on LAVA lab coming back from power cut
** And queues being short enough
* Progress (finish?) Juno bring-up
* Share source/results rules draft
== This week ==
* TCWG-833 - Exploit Wide Add operations when appropriate (8/10)
- Reworked patch to use vect_select instead of unspec as requested
by Ramana
- Bugzilla 57195 (mode iterator bug) blocked compiling new pattern
- Created patch which successfully bootstrapped
- Created Bugzilla 67320 - Incorrect standard names for wide
addition (documentation bug)
- Successfully regression tested Aarch32 changes
- Send Aarch32 patch upstream for review
- Reworking patch for Aarch64 to use vect_select as well
- Created Bugzilla 67321 - [ARM] Exploit wide adds when appropriate
- Created Bugzilla 67322 - [Aarch64] Exploit wide adds when appropriate
* TCWG-834 - Use non-unit stride loads by preference when applicable (1/10)
- Created Bugzilla 67323 to track until fixed in GCC 6 by Richard Biener
- Began writing test case that fails
* Misc (1/10)
- Conference calls
== Next week ==
- Respond to Aarch32 TCWG-833 upstream requests and hopefully check-in patch
- Complete Aarch64 TCWG-833 patch, validate and upstream
- Finish testcase for TCWG-834 and submit upstream
== Progress ==
* Maintenance (CARD-1833 2/10)
- Fixing libc++abi build on AArch64
- Trying to remove a hack in ARMTargetInfo about default CPUs
- Bisecting PR24292
- Working with ARM to fix it, backport
* Buildbots (CARD-1823 8/10)
- Working with Adhemerval on VMA 42bits sanitizer
- Setting up a libc++ "full" build on the second stage, since
gcc can't build it yet. 171 tests fail.
- Ubuntu Vivid (39-bits VA / 4k pages) with Uboot is
the winner of stability, speed and easiness.
- Power outage meant I had to unbreak *a lot* of broken stuff
* Background (2/10)
- Code review, meetings, discussions, etc.
- Some Android/TSAN/AArch64 shenanigans
== Plan ==
Holidays all week
== Issues ==
Yes, it does add up to 12/10, since I had to work most of Saturday and
some of Sunday to fix the mess that the power cuts made on our lab.
If we had generators, that wouldn't have happened.
== This Week ==
* TCWG-835 (2/10)
- Testing on SPEC CPU2006
- Found ICE while testing on spec unrelated to my patch, created
reduced test-case.
* TCWG-777 (2/10)
- Working on RTL pass - enhanced it so it only replicates insn when required.
- Prototype patch works for the test-case but ICE's during toolchain build.
- Trunk generates expected output for -O2, git-bisect shows from r226516
* TCWG-871 (1/10)
- Built for x86_64 non LTO
- Trying to cross compile for ARM
* Sick Leave (2/10)
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue with TCWG-777, TCWG-835, TCWG-871
# Progress #
* TCWG-806, aarch64 remote debugging multi-arch
support. Patches are pushed in. Done. [2/10]
* TCWG-857, HW breakpoint/watchpoint in multi-arch. [3/10]
Both GDB and linux
kernel needs some fixes. Fix one bug in GDB. Read ARMv8 manual about
byte address select for thumb code (2-byte aligned instruction) and
the implementation in kernel.
* TCWG-757 some patches review, [1/10]
* Misc [4/10]
** ARM new starter training on Wed. afternoon and Thu.
** Read early-debug https://gcc.gnu.org/wiki/early-debug
# Plan #
* TCWG-857.
* Update the state of some old linaro tickets on GDB.
--
Yao
Hi,
I compiled the Linaro cross tool chain for arm v7 SOC and using the buildroot to create the images. When I use the downloaded precompiled tool chain from linaro releases, I am not facing any issues. But with compiled tool chain, multiple packages are failing with similar to below mentioned error. I tried building cross tool chain on both redhat and Ubuntu machines. When I see the difference of gcc -v, the cross compile is with "--host=x86_64-build_unknown-linux-gnu" and the pre compiled is with "--host=i686-build_pc-linux-gnu". I tried with "crosstool-ng-linaro-1.13.1-4.9-2014.08.tar.bz2" and "crosstool-ng-linaro-1.13.1-4.9-2014.09.tar.bz2".
configure:25287: checking for MD5 in -lcrypto
configure:25312: /projects/broadcom-linux/dhananjay/nas/iproc/buildroot/output/host/usr/bin/arm-linux-gnueabihf-gcc -std=gnu99 -o conftest -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -pipe -Os -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 conftest.c -lcrypto >&5
/projects/broadcom-linux/dhananjay/toolchain/tool9/toolchain/lib/ct-ng-linaro-1.13.1-4.9-2014.08/install/lib/gcc/arm-linux-gnueabihf/4.9.2/../../../../arm-linux-gnueabihf/bin/ld: warning: libdl.so.2, needed by /projects/broadcom-linux/dhananjay/nas/iproc/buildroot/output/host/usr/arm-buildroot-linux-gnueabihf/sysroot/usr/lib/libcrypto.so, not found (try using -rpath or -rpath-link)
-bash-4.1$ uname -a
Linux lab-rtp-gw-05 2.6.32-358.23.2.el6.x86_64 #1 SMP Sat Sep 14 05:32:37 EDT 2013 x86_64 x86_64 x86_64 GNU/Linux
Can somebody help me here.
Thanks
Dhananjay
Hi Linaro Toolchain Group,
I am trying to compiling cross aarch64-linux-gnu toolchain using local
directory (tar file) for gcc.
I am using file:/// as mentioned in the https://wiki.linaro.org/ABE.
../abe/abe.sh --target aarch64-linux-gnu --build all --release
20150819 --tarbin
gcc=file:///home/vpathak/arm/toolchain/build/snapshots/gcc-2015.11-5.tar.bz2
But I get following error:
ERROR (#146): get_URL (not supported for .tar.* files.)
ERROR (#533): get_source
(file:///home/vpathak/arm/toolchain/build/snapshots/gcc-2015.11-5.tar.bz2
not a valid sources.conf identifier.)
TRACE(#190): checkout ()
ERROR (#193): checkout (No URL given!)
ERROR (#161): checkout_all (Failed checkout out of gcc.)
Am I missing something ? How can we use a local directory (e.g. gcc
source code) for building toolchain using abe ?
Please help.
Thanks.
--
with regards,
Virendra Kumar Pathak
== Progress ==
LLDB development
-- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [7/10]
-- Submitted following fixes and got them reviewed
-- http://reviews.llvm.org/D11899
-- http://reviews.llvm.org/D11902
-- http://reviews.llvm.org/D11987
Miscellaneous [3/10]
-- Meetings, emails, discussions etc.
-- 14th August Public Holiday
== Plan ==
LLDB development
-- Further progress on fixing test failues on hikey AArch64.
-- Testsuite status compilation for armel and armhf
== Progress ==
* Short week due to GNU Cauldron Travel
* Widening pass (TCWG-547) - 3/10
- Looked at the false positive warning for uninitialized variable
- Have a reduced test-case and looking at ways to fix this
- Split the patch for easy review
- Fixed test-cases and going through all the test-case failures
* Misc - 2/10
- gcc-patches, gcc-bugs list
- Looked at gcc vectorization
== Plan ==
- Widening pass
== Progress ==
o Linaro GCC validation (4/10)
* Validation issues investigation
* Austin's APM board seems more reliable
* New validation instability on x86_64 discovered:
- Analysis on-going but it is related to fstack-protector
* Waiting for VPN access
o Upstream GCC (4/10)
* Reworked OOM issue on armeb-linux-gnu target fix
* Patch committed on trunk
* Backport on gcc-5 validated and about to be committed
o Misc (2/10)
* Various meetings
* Team member support
== Plan ==
o Continue on validation
o Redo FSF branch merge after big-endian fix committed.
Benchmark infrastructure - TCWG-360 [6/10]
* Fixed remaining known critical issues in multinode
** Testing stymied by LAVA oversubscription
** Attempted to implement some workarounds for oversubscription
* Some discussion/investigation on generating filesystems for benchmarking
* Started brain-dumping state of infrastructure into cards.linaro.org
Bringing up Juno for noise control experiments [1/10]
* Some struggles with firmware/bootloader configuration
Misc [3/10]
Featuring some ARM management duties
= Plan =
* Get benchmarking tests through, if LAVA permits
* Fix any critical issues discovered
* Finish brain-dump into cards.l.o
* Bring up Juno for noise control experiments
* Some more ARM management
== This week ==
* TCWG-140 - Transform end of loop conditions to min_expr (4/10)
- Wrote initial test case as requested by maintainers
- Need to determine how to not run test case on targets with no
MIN_EXPR/MAX_EXPR
* TCWG-833 - Exploit Wide Add operations when appropriate (4/10)
- Fixed internal error by using unspec for vector sign/zero-extend
- Fixed multiple issues with test cases
- Investigating why gcc.dg/vect/slp-reduc-3.c with lto is regressing
for aarch32 and aarc64
- Investigating two additional regression failures on aarch64
* TCWG-834 - Use non-unit stride loads by preference when applicable (1/10)
- Spoke with Richard Biener at GNU cauldron.
- He indicated this was a problem with a interaction problem with
vectorizer not attempting multiple strategies
- He indicated that he planned to fix this for GCC 6 and not to
attempt a fix
- My plan is to write a test case that fails until the issue is
addressed in GCC 6
* Misc (1/10)
- Conference calls
== Next week ==
- Resolve testsuite regressions for TCWG-833
- Create bugzilla reports for TCWG-833 and TCWG-834
- Write testcase for TCWG-834 and submit upstream
- Investigate TCWG-832 as time permits
== This Week ==
* TCWG-777 (4/10)
- Working on RTL pass, prototype patch works for the test-case.
- updating the trunk to r226907 , it appears combine can fold
arm_andsi3_insn/arm_cmpsi_insn
into zeroextractsi_compare0_scratch at -O2 while not at -O1.
.* TCWG-835 (2/10)
- Testing patch with Spec 2006
- Found ICE unrelated to my patch
* Misc (4/10)
- Travel to home from GNU Tools Cauldron 2015, Prague.
== Next Week ==
- Continue working on TCWG-777
- Continue testing TCWG-835 patch with SPEC 2006
== Progress ==
* Buildbots (CARD-1823 6/10)
- Setting up new APMs
- Running around for a decent UEFI, Kernel, Distro
- Testing different builds, configurations
- Managed to get one APM doing the test-suite *only*! sigh...
- http://buildmaster.tcwglab.linaro.org/builders/clang-cmake-aarch64-lnt
* Background (4/10)
- Code review, meetings, discussions, etc.
- Doing more reviews than usual due to buildbot work being erradic
- Laptop is playing stupid again
== Plan ==
* Moar bots
* Moar code review
* Maybe some vodka, to wash it all up
== Progress ==
LLDB development
-- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [9/10]
-- Debugging of watchpoint test failures and problems with multiple
watchpoints.
-- Clean-up of AArch64 watchpoint code and fixing watchpoint cache bugs.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Submit and get review on bug fixes for lldb on hikey AArch64 code changes.
-- Investigate further lldb test failues on hikey AArch64.
Miscellaneous
-- Friday 14th August, Independence day public holiday in Pakistan.
== Progress ==
o Linaro GCC validation (4/10)
* Look at the various validation issues we have
* Dug into the logs, restarted jobs, asked to restart
builders/testers. etc ...
o Upstream GCC (5/10)
* Investigate OOM issue on armeb-linux-gnu target
* Found the issue and raised an upstream bugzilla:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67127
* Submitted a fix for it
o Misc (1/10)
* Various meetings
== Plan ==
o Continue validation babysitting
== Progress ==
LLDB development
-- Setup lldb test debug environment for testing failing tests on
chromebook. [1/10]
-- Debug various lldb hang scnarios on chromebook for armhf support
[TCWG-855] [4/10]
-- Figure out alternate fix for http://reviews.llvm.org/D11129.
[TCWG-855] [3/10]
Miscellaneous [2/10]
-- Fix chromebook malfunction due to battery issues
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Debug lldb test cases on armhf to figure out problems in
individual test-cases
-- Create an updated lldb development project plan on JIRA.
-- Update collaborate with steps on LLDB development process.
== Progress ==
* Widening pass (TCWG-547) - 8/10
- Handled review comments.
- Improved CONVERT_EXPR handling.
- Re based and retested - found some failures.
- This was due to VRP reusing the range info computed in VRP1 after
type promotion is applied. Invalidating the range info when type is
promoted.
- ARM with type promotion now improves (-O2) about ~2.8% with one tiny
benchmark (where it used to regress).
- Still some test cases failures (not execution failures but scanning
certain patterns in the dump/asm).
* Misc - 2/10
- Connect slides.
- gcc-patches, gcc-bgs list
- Meetings
== Plan ==
- Widening pass
== This week ==
* TCWG-146 - Detect smin/umin idiom (1/10)
- Incorporated final feedback and submitted code in SVN
* TCWG-140 - Transform end of loop conditions to min_expr (1/10)
- Misc. discussion upstream about concerning where optimization
should be performed
- Upstream maintainers asked me to create gimple ir test case
* TCWG-833 - Exploit Wide Add operations when appropriate (1/10)
- Unable to validate yet
* TCWG-834 - Use non-unit stride loads by preference when applicable (5/10)
- Further Aarch32 investigation to determine where decision to forgo
vld3 decision is being made
* Linaro connect preparation (1/10)
* Misc (1/10)
- Conference calls
== Next week ==
- Validate patches for TCWG-833 and submit upstream
- Further TCWG-834 investigation
- GNU Cauldron conference and travel
== This Week ==
* TCWG-835 (4/10)
- Validated and submitted patch upstream for review.
- Made changes to patches according to upstream reviews.
- Microbenchmarks: http://pastebin.com/tDnHZuG5
* TCWG-777 (5/10)
- Investigating different ICE's caused by my gimple remove-temps pass
- Looked at expansion of GIMPLE_COND
- Trying to write rtl version of remove-temps pass
* Misc (1/10)
- Conference calls
== Next Week ==
- Continue with TCWG-777
- GNU Tools Cauldron 2015
== Progress ==
* Performance (CARD-1832 1/10)
- Checking differences of PostRAListSched on OOO ARM cores
- Not many changes, ignoring for now
* Maintenance (CARD-1833 4/10)
- Building libc++/abi/unwind in LLVM/Clang tree
- Getting -Wa,-mfpu patches in, last important Clang driver ARM bug
- Some patches to get libunwind and libc++ to compile in-tree on ARM
- Fixed native sub-features detection (http://llvm.org/PR12794)
* Background (5/10)
- Code review, meetings, discussions, etc.
- Long discussions about TargetTuple/TargetParser/Triple
- Lots of patch reviews this week (I mean, *A LOT*)
- Moving some machines around, checking for Chromebook batteries
- Setting up cross-builder using multiarch / QEMU
- Some future planning
== Plan ==
* Look for some more performance issues in 3.7
* Try to hook up the cross-builder
* Investigate libc++ check-all failures
Benchmark infrastructure - TCWG-360 [8/10]
* Testing found many problems in multinode
* Iterating to solutions
Misc [2/10]
=Plan=
Holiday next week.
Then back to fixing multinode, incorporating into jenkins, noise
control experiments
Hi Linaro Toolchain Group,
I am building a native toolchain for aarch64 with below configurations:
--build=x86_64-unknown-linux-gnu --host=aarch64-linux-gnu
--target=aarch64-linux-gnu.
In copy_gcc_libs_to_sysroot() - which copy libgcc.a to sysroot, current
implementation try to find the absolute path of libgcc.a as below :
libgcc="`${local_builds}/destdir/${host}/bin/${target}-gcc
-print-file-name=${libgcc}`
But above line will not execute (i.e. gcc -print-file-name) on x86_64 as
the toolchain is native toolchain for aarch64-linux-gnu. Thus a infinite
loop will be created in copy command i.e. copying directory x in x.
however, when I hard coded the libgcc.a path in my machine (as below),
everything went fine.
libgcc="/home/vpathak/arm/toolchain/build_abe_new/builds/destdir/aarch64-linux-gnu/lib/gcc/aarch64-linux-gnu/5.1.1/libgcc.a"
I think this is a bug in ABE build infrastructure.
Thanks.
--
with regards,
Virendra Kumar Pathak
* TCWG-806, aarch64 remote debugging multi-arch support. [4/10]
Patches are done. Need to test them and polish them.
Fix various multi-arch issues when --wrapper is used in GDBserver.
Patches are pushed in to mainline.
Could you describe this activity in more detail?
Is the goal here to support mixed aarch32/aarch64 in the same GDB binary
and detect the change at runtime?
Thanks.
-Duane
== Progress ==
* Factor conversion out of COND_EXPR - TCWG-849 (5/10)
- Iterated through the review and more testing
* Looked at widening pass and the test-case from Wilco (1/10)
* Misc (2/10)
- Connect slides.
- gcc-patches, gcc-bugs list
- Meetings
* Sick (2/10)
== Plan ==
- GCC Bugs
- Widening pass
- Linaro bug 1318
== This week ==
* TCWG-146 - Detect smin/umin idiom (1/10)
- Made change recommended upstream and resubmitted
* TCWG-140 - Transform end of loop conditions to min_expr (1/10)
- Validated and submitted upstream
* TCWG-833 - Exploit Wide Add operations when appropriate (5/10)
- Added early clobber and forced operand 0 and operand 2 to match
- Finished Aarch32 by using mode iterators
- Developed patch for Aarch64
- Wide add instructions are now emitted for both Aarch32 and Aarch64
* TCWG-834 - Use non-unit stride loads by preference when applicable (2/10)
- Further Aarch32 investigation
* Misc (1/10)
- Conference calls
== Next week ==
- Validate patches for TCWG-833 and submit upstream
- Further TCWG-834 investigation
- Linaro connect presentation preparation
* TCWG-835 (6/10)
- Looked at newton raphson method
- Need to write new md pattern that matches sdiv_optab for modes == v2sf, v4sf
- First attempt for patch: http://pastebin.com/NKy8WdWC
* TCWG-830 (2/10)
- Ran Charles's benchmarks on ARM and AArch64.
- Investigating testsuite fallout for ARM patch.
- Still blocked by permissions to do benchmarking
* Misc (2/10)
- Conference Calls
- US visa collection
== Next Week ==
- Continue with TCWG-830, TCWG-835, TCWG-777
Hi Linaro Toolchain Group,
I am trying to learn the 'decoding decision tree' for aarch64 in binutils
by trying to add a new assembly instruction 'addvp'.
For example: addvp x0, x0, 9
For this, I added a entry in struct aarch64_opcode aarch64_opcode_table[]
(file opcodes/aarch64-tbl.h) as below:
{"addvp", 0x01000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP,
AIMM), QL_R2NIL, F_SF},
ARM manual say, bit 27 & bit 28 are unallocated. Thus for addvp, I am
giving opcode 01000000 (with bit 27 & 28 as 0).
With this, generating object file from assembly file is successful (test.s
--> test.o); but while disassembling using objdump, it say undefined
instruction.
>From objdump log:
81002400 .inst 0x81002400 ; undefined
(but instruction was generated correct i.e. 81002400 !!!).
I know since addvp is a hack instruction, it won't execute on cpu. But
still disassembly should succeed.
1. Please help me in knowing what I am doing wrong here ? What else I
should do to add a new instruction in binutils ?
2. I also saw some printf in opcodes/aarch64-gen.c which I guess create
decoding tree (initialize_decoder_tree()). How to print them ? I made debug
=1 but still print is not coming.
3. There are some auto-generated files
like aarch64-asm-2.c, aarch64-dis-2.c. How to re-generate them ?
Thanks.
--
with regards,
Virendra Kumar Pathak
== Progress ==
* Maintenance (CARD-1833 5/10)
- Building libc++/abi/unwind in LLVM/Clang tree
- Fixing some build errors (D11486)
- Addressing comments to submissions from last week
- Committing approved ones
- Re-working the others
* Releases (CARD-1431 1/10)
- Building 3.7.0-RC1 on ARM and AArch64, uploading
* Benchmarks (CARD-716 2/10)
- Running LNT, SPEC and EEMBC on ARM and AArch64 for 3.7.0
* Background (2/10)
- Code review, meetings, discussions, etc.
- Upgraded APM to Debian, kernel 3.16
- Perf still segfaults. :(
== Plan ==
* Finish open reviews
* Continue getting libc++ to build and pass the tests in tree
* Look at some of the performance regressions in 3.7