- linaro-toolchain - lists.linaro.org

[ACTIVITY] 9-13 November 2015

by Christophe Lyon

1 day off (Wednesday) (2/10) == Progress == * Validation - Jenkins jobs maintenance & cleanup - comparison of build times between old & new lab - dedicated slave for results comparison works well * GCC - trunk monitoring, reported a few new failures. - high rate of commits before e/o stage1 means lots of patches to check - infrastructure problems in the ST compute farm mean a few false errors needed analysis - looked at bug #1869, (problem with binary toolsets on RHEL6). Made some progress == Next == * Validation: - continue preparation of switch, as dev-01 is now back - improve reporting * GCC: - check Neon tests cleanup - bug #1869 - look at how to send valuable reports to gcc-regression

10 years, 5 months

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[ACTIVITY] 9th -- 13th November

by Yao Qi

* Off on Wed afternoon [1/10]. # Progress # * Fails in gdb.threads/multiple-step-overs.exp, (TCWG-332) [1/10] Patch V2 is posted, pending for review. * TCWG-422, patch is committed. Done. [2/10]. * TCWG-423, patches are ready, being regression tested. [2/10] * TCWG-433, build GDB with -fsanitize=address, and exposes many memory issues. Some of them are fixed. [2/10]. * Upstream patch review, [1/10] * Misc, meeting, [1/10] # Plan # * TCWG-423, Post patches upstream. * Understand ST's jtag probe and help them to make use of multi-arch with GDB. * TCWG-433, Continue fixing memory issues exposed by -fsanitize=address. -- Yao

10 years, 5 months

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Re: [U-Boot] aarch64-linux-gnu-objdump gives all zeros in init_sequence_f[]

by Shawn Guo

Hi Albert, On Thu, Nov 12, 2015 at 08:20:18AM +0100, Albert ARIBAUD wrote: > Can you provide the target name and commit ID that you are building, > s well as the version of the toolchain that you are building with? > Without being able to reproduce your issue, it's kind of hard to > diagnose it. With the explanation from Ard, I understand the thing now. But thanks for the reply anyway. Shawn

10 years, 5 months

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aarch64-linux-gnu-objdump gives all zeros in init_sequence_f[]

by Shawn Guo

Hi, I need some help to understand aarch64-linux-gnu-objdump output in .data section as below. It's part of the dump of u-boot image with command 'aarch64-linux-gnu-objdump -D -z u-boot'. Disassembly of section .data: 0000000035039898 <reserved_list>: <snip> 0000000035039948 <init_sequence_f>: 35039948: 00000000 .word 0x00000000 3503994c: 00000000 .word 0x00000000 35039950: 00000000 .word 0x00000000 35039954: 00000000 .word 0x00000000 35039958: 00000000 .word 0x00000000 3503995c: 00000000 .word 0x00000000 35039960: 00000000 .word 0x00000000 35039964: 00000000 .word 0x00000000 35039968: 00000000 .word 0x00000000 3503996c: 00000000 .word 0x00000000 35039970: 00000000 .word 0x00000000 35039974: 00000000 .word 0x00000000 35039978: 00000000 .word 0x00000000 3503997c: 00000000 .word 0x00000000 35039980: 00000000 .word 0x00000000 35039984: 00000000 .word 0x00000000 35039988: 00000000 .word 0x00000000 3503998c: 00000000 .word 0x00000000 35039990: 00000000 .word 0x00000000 35039994: 00000000 .word 0x00000000 35039998: 00000000 .word 0x00000000 3503999c: 00000000 .word 0x00000000 350399a0: 00000000 .word 0x00000000 350399a4: 00000000 .word 0x00000000 350399a8: 00000000 .word 0x00000000 350399ac: 00000000 .word 0x00000000 350399b0: 00000000 .word 0x00000000 350399b4: 00000000 .word 0x00000000 350399b8: 00000000 .word 0x00000000 350399bc: 00000000 .word 0x00000000 350399c0: 00000000 .word 0x00000000 350399c4: 00000000 .word 0x00000000 350399c8: 00000000 .word 0x00000000 350399cc: 00000000 .word 0x00000000 350399d0: 00000000 .word 0x00000000 350399d4: 00000000 .word 0x00000000 350399d8: 00000000 .word 0x00000000 350399dc: 00000000 .word 0x00000000 350399e0: 00000000 .word 0x00000000 350399e4: 00000000 .word 0x00000000 350399e8: 00000000 .word 0x00000000 350399ec: 00000000 .word 0x00000000 350399f0: 00000000 .word 0x00000000 350399f4: 00000000 .word 0x00000000 350399f8: 00000000 .word 0x00000000 350399fc: 00000000 .word 0x00000000 35039a00: 00000000 .word 0x00000000 35039a04: 00000000 .word 0x00000000 35039a08: 00000000 .word 0x00000000 35039a0c: 00000000 .word 0x00000000 35039a10: 00000000 .word 0x00000000 35039a14: 00000000 .word 0x00000000 35039a18: 00000000 .word 0x00000000 35039a1c: 00000000 .word 0x00000000 35039a20: 00000000 .word 0x00000000 35039a24: 00000000 .word 0x00000000 35039a28: 00000000 .word 0x00000000 35039a2c: 00000000 .word 0x00000000 35039a30: 00000000 .word 0x00000000 35039a34: 00000000 .word 0x00000000 35039a38: 00000000 .word 0x00000000 35039a3c: 00000000 .word 0x00000000 35039a40: 00000000 .word 0x00000000 35039a44: 00000000 .word 0x00000000 35039a48: 00000000 .word 0x00000000 35039a4c: 00000000 .word 0x00000000 The init_sequence_f[] is an array defined in U-Boot v2015.04 source common/board_f.c, which holds a bunch of pointers to critical initialization functions that have to be called during boot. Obviously, the array cannot be all zeros like what objdump tells. And I confirmed that by printing the pointers at run-time as below. init_sequence_f[0]: 0000000035004280 init_sequence_f[1]: 00000000350042a8 init_sequence_f[2]: 0000000035004380 init_sequence_f[3]: 00000000350042a0 init_sequence_f[4]: 00000000350044b8 init_sequence_f[5]: 0000000035004388 init_sequence_f[6]: 0000000035029538 init_sequence_f[7]: 000000003500675c init_sequence_f[8]: 000000003500447c init_sequence_f[9]: 000000003501d864 init_sequence_f[10]: 0000000035013778 init_sequence_f[11]: 0000000035004398 init_sequence_f[12]: 0000000035028ab8 init_sequence_f[13]: 0000000035004278 init_sequence_f[14]: 0000000035004270 init_sequence_f[15]: 000000003500445c init_sequence_f[16]: 0000000035001f20 init_sequence_f[17]: 0000000035004574 init_sequence_f[18]: 00000000350042b0 init_sequence_f[19]: 00000000350042c4 init_sequence_f[20]: 00000000350042cc init_sequence_f[21]: 00000000350042f8 init_sequence_f[22]: 00000000350044d4 init_sequence_f[23]: 000000003500430c init_sequence_f[24]: 0000000035004314 init_sequence_f[25]: 0000000035004330 init_sequence_f[26]: 0000000035004390 init_sequence_f[27]: 00000000350045bc init_sequence_f[28]: 0000000035004550 init_sequence_f[29]: 0000000035004518 init_sequence_f[30]: 0000000035004378 init_sequence_f[31]: 0000000035004428 init_sequence_f[32]: 00000000350043f0 Dumping an u-boot image built for 32-bit platform with arm-linux-gnueabi-objdump gives correct pointer values for the same array. 17853c7c <init_sequence_f>: 17853c7c: 17805600 strne r5, [r0, r0, lsl #12] 17853c80: 17805620 strne r5, [r0, r0, lsr #12] 17853c84: 1780574c strne r5, [r0, ip, asr #14] 17853c88: 178007ec strne r0, [r0, ip, ror #15] 17853c8c: 1780583c ; <UNDEFINED> instruction: 0x1780583c 17853c90: 17805834 ; <UNDEFINED> instruction: 0x17805834 17853c94: 1780315c ; <UNDEFINED> instruction: 0x1780315c 17853c98: 178015f4 ; <UNDEFINED> instruction: 0x178015f4 17853c9c: 17800890 ; <UNDEFINED> instruction: 0x17800890 17853ca0: 17801c0c strne r1, [r0, ip, lsl #24] 17853ca4: 178078f8 ; <UNDEFINED> instruction: 0x178078f8 17853ca8: 17805808 strne r5, [r0, r8, lsl #16] 17853cac: 17829564 strne r9, [r2, r4, ror #10] 17853cb0: 17816104 strne r6, [r1, r4, lsl #2] 17853cb4: 1783dea4 strne sp, [r3, r4, lsr #29] 17853cb8: 178055f8 ; <UNDEFINED> instruction: 0x178055f8 17853cbc: 17801a54 ; <UNDEFINED> instruction: 0x17801a54 17853cc0: 17805b4c strne r5, [r0, ip, asr #22] 17853cc4: 178057e0 strne r5, [r0, r0, ror #15] 17853cc8: 178057c8 strne r5, [r0, r8, asr #15] 17853ccc: 17802e20 strne r2, [r0, r0, lsr #28] 17853cd0: 17805910 usada8ne r0, r0, r9, r5 17853cd4: 17805628 strne r5, [r0, r8, lsr #12] 17853cd8: 17805640 strne r5, [r0, r0, asr #12] 17853cdc: 17805678 ; <UNDEFINED> instruction: 0x17805678 17853ce0: 17805680 strne r5, [r0, r0, lsl #13] 17853ce4: 178056b0 ; <UNDEFINED> instruction: 0x178056b0 17853ce8: 17805850 ; <UNDEFINED> instruction: 0x17805850 17853cec: 178056c8 strne r5, [r0, r8, asr #13] 17853cf0: 178056dc ; <UNDEFINED> instruction: 0x178056dc 17853cf4: 178056f8 ; <UNDEFINED> instruction: 0x178056f8 17853cf8: 17805768 strne r5, [r0, r8, ror #14] 17853cfc: 17805950 ; <UNDEFINED> instruction: 0x17805950 17853d00: 178058ec strne r5, [r0, ip, ror #17] 17853d04: 17805894 ; <UNDEFINED> instruction: 0x17805894 17853d08: 17805744 strne r5, [r0, r4, asr #14] 17853d0c: 17805798 ; <UNDEFINED> instruction: 0x17805798 17853d10: 17805770 ; <UNDEFINED> instruction: 0x17805770 17853d14: 00000000 andeq r0, r0, r0 Here are my questions: - Is this only because that ARM 64-bit toolchain doesn't show the real value of the pointers, or there are some linking or run-time magics to get these pointers correct when the binary is actually running? - Is this different behavior between ARM 32-bit and 64-bit toolchain expected? Or did I miss anything on 64-bit toolchain usage? Any hints or comments are much appreciated. Thanks, Shawn

10 years, 5 months

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Re: [lng-odp] Runtime inlining

by Mike Holmes

On 11 November 2015 at 00:45, Savolainen, Petri (Nokia - FI/Espoo) < petri.savolainen(a)nokia.com> wrote: > > > > -----Original Message----- > > From: lng-odp [mailto:lng-odp-bounces@lists.linaro.org] On Behalf Of > > EXT Nicolas Morey-Chaisemartin > > Sent: Tuesday, November 10, 2015 5:13 PM > > To: Zoltan Kiss; linaro-toolchain(a)lists.linaro.org > > Cc: lng-odp > > Subject: Re: [lng-odp] Runtime inlining > > > > As I said in the call last week, the problem is wider than that. > > > > ODP specifies a lot of types but not their sizes, a lot of > > enums/defines (things like ODP_PKTIO_INVALID) but not their value > > either. > > For our port a lot of those values were changed for > > performance/implementation reason. So I'm not even compatible between > > one version of our ODP port and another one. > > > > The only way I can see to solve this is for ODP to fix the size of all > > these types. > > Default/Invalid values are not that easy, as a pointer would have a > > completely different behaviour from structs/bitfields > > > > Nicolas > > > > Type sizes do not need to be fixed in general, but only when an > application is build for binary compatibility (the use case we are talking > here). Binary compatibility and thus the fixed type sizes are defined per > ISA. > > We can e.g. define a configure target (for our reference implementation == > linux-generic) "--binary-compatible=armv8.x" or > "--binary-compatible=x86_64". When you build your application with that > option, "platform dependent" types and constants would be fixed to > pre-defined values specified in (new) ODP API arch files. > > So instead of building against > odp/platform/linux-generic/include/odp/plat/queue_types.h ... > > typedef ODP_HANDLE_T(odp_queue_t); > #define ODP_QUEUE_INVALID _odp_cast_scalar(odp_queue_t, 0) > #define ODP_QUEUE_NAME_LEN 32 > > > ... you'd build against odp/arch/armv8.x/include/odp/queue_types.h ... > With the introduction of odp/arch at the top level I think we should also move platform/linux-generic/arch to the same location > typedef uintptr_t odp_queue_t; > #define ODP_QUEUE_INVALID ((uintptr_t)0) > #define ODP_QUEUE_NAME_LEN 64 > > > ... or odp/arch/x86_64/include/odp/queue_types.h > > typedef uint64_t odp_queue_t; > #define ODP_QUEUE_INVALID ((uint64_t)0xffffffffffffffff) > #define ODP_QUEUE_NAME_LEN 32 > > > For highest performance on a fixed target platform, you'd still build > against the platform directly > > odp/platform/<soc_vendor_xyz>/include/odp/plat/queue_types.h > > typedef xyz_queue_desc_t * odp_queue_t; > #define ODP_QUEUE_INVALID ((xyz_queue_desc_t *)0xdeadbeef) > #define ODP_QUEUE_NAME_LEN 20 > > > -Petri > > > > > _______________________________________________ > lng-odp mailing list > lng-odp(a)lists.linaro.org > https://lists.linaro.org/mailman/listinfo/lng-odp > -- Mike Holmes Technical Manager - Linaro Networking Group Linaro.org <http://www.linaro.org/> *│ *Open source software for ARM SoCs

10 years, 5 months

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[ACTIVITY] 2nd - 6th November

by Bernie Ogden

Holiday [2/10] Juno crash analysis [2/10] * Spent some time fiddling with kexec on AArch64 * Worked in one very specific case * Another patch series is (apparently) coming, will look out for it and try again SPEC-on-Android [2/10] * Supporting Qian on getting this working * Wrote a readme for the repository, fixed a Makefile bug that Qian's cross-compiler happened to tickle Jenkins benchmarking job - TCWG-348 [1/10] * Tested, tidied up pbl hacks to generate JSON * Tested my pbl with Jenkins prototype jobs * A few minor bug fixes/enhancements for pbl LAVA jobs for uinstance - TCWG-432 [1/10] * Reworked jobs to support uinstance, maintaining backward compatibility as far as possible * Started adding support to submit results to bundle stream Misc [2/10] * Debian FS ready to submit * Usual meetings/mail/etc background =Plan= Look at doing pbl hacks properly in Fathi's in-development refactored p-b-l Pull together Jenkins/LAVA/pbl, ready to test when uinstance is available Write up noise control report (If time, if patches land) have another go at crashdump

10 years, 5 months

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[ACTIVITY] Week 44

by Yvan Roux

== Progress == o Linaro GCC (4/10) * Delivered GCC 4.9 2015.10 snapshot * More backports forGCC 5 2015.11 * Many instabilities on Hetzner this week o Upstream work (2/10) * Sanitizing gfortran testsuite o Release tools (2/10) * Added RCs and binaries support to our snapshot.linaro.org publishing job o Misc (2/10) * Various meetings * Some support == Plan == o Track missing backports dependencies o Continue ongoing tasks.

10 years, 5 months

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[Weekly] 02-06 November 2015

by Michael Collison

== This week == * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Determined that vectorizer is failing for all targets that have widening adds with V8HI to V4SI support (aarch64, ia64, powerPC). - Modified test cases to indicate expected failure with wide add V8HI to V4SI support - Patch sent upstream for approval * Bugzilla 68223 - arm_[su]min_cmp pattern fails - Resolved by reverting patch for tcwg-146 as pattern fail in some corner cases. (3/10) - Reverted patch checked in upstream * Misc (1/10) - Conference calls * Illness, November 2nd (2/10) == Next week == - TCWG-317 - Resolve lto big endian failures

10 years, 5 months

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[ACTIVITY] 2-6 November 2015

by Kugan

== Progress == - Leave (2/10) - Widening pass (TCWG-547) - 5/10 * Made the latest changes requested in the review * Fixed bootstrap and bootstrap mis-compare for ppc64-linux-gnu * Making uninitialized variable as anonymous ssa (as asked in review) results in few ICEs. * Posted updated patch for feedback - Misc (3/10) * started looking into LTO status * Looked at LuaJIT for arm * gcc/bug list == Plan == * continue with widening pass based on feedback * Look at implementing LuaJIT for aarch64 * LTO

10 years, 5 months

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[ACTIVITY] 2 - 6 November 2015

by Prathamesh Kulkarni

== This week == * TCWG-72 (6/10) - 5 iterations since the original patch. Changes include: a) Integration into widening_mul patch b) Rewriting the divmod transform so DIVMOD() is placed before the topmost div/mod stmt c) Removed check for widening mode and optab handler check in expand_DIVMOD d) Fixed ICE when constant is one of the operands to div/mod stmt. e) Fixed mis-compilation with a test-case when operands matched but in opposite order. f) Formatting nits and fixed test-cases. - Richard suggested no need to check for post-domination conditions. - Not sure on what condition to gate the transform. Checking for availability of divmod/div/mod is not sufficient because arm defines optab handler for mod which only matches r0 % n where n is constant and power of 2 for other cases it's expanded via divmod libcall thru expand_divmod. We would rather need to check if the template for mod/div gets matched than just to check if optab handler exists. AFAIK this cannot be done during tree-ssa passes. I can think of two approaches: a) Do the transform to DIVMOD representation unconditionally in widening_mul pass. And then in expand_DIVMOD check if the template for mod can be matched. If it does match then undo the transform from DIVMOD to original representation and expand. I am not sure how feasible it is to undo the transform at expansion time, and start expanding the modified cfg. b) Define a new target hook combine_divmod. Default implementation could check for optab handler for div/mod/divmod. and I could override it for arm-backend to additionally check if the second operand is a constant and power of 2 and fail for this case (since we want this to be expanded from modsi3 pattern). Not sure if this is a good idea, I am replicating the information from the modsi3 pattern. If the pattern changes, the hook would also need to be changed. * Convert ASM_FORMAT_PRIVATE_NAME to hook (2/10) * TCWG-319 (1/10) - Bencharmking for patch in progress * Misc (1/10) - Meetings - Sync with Kugan == Next Week == - Continue with TCWG-72 - Complete the patch with build, test and config-builds for ASM_FROMAT_PRIVATE_NAME and submit upstream - Continue benchmarking TCWG-319, TCWG-310

10 years, 5 months

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[ACTIVITY]

by Renato Golin

== Progress == * Buildbots (5/10) - Some broken bots, bisecting, etc - Helping a MIPS patch pass on ARM bot * Maintenance (2/10) - SciMark2 seems not to be unstable or slow any more in ARM64 - Some more investigations on Loop Load Elimination - Profiling bigfib on APM and HiKey * Background (3/10) - Code review, meetings, discussions, general support, etc. - Some FOSDEM fiddling - Some power issues

10 years, 6 months

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[ACTIVITY] 2-6 November 2015

by Christophe Lyon

== Progress == * Validation - moved list of unstable tests to a separate repo, to make maintenance easier (TCWG-425) - Jenkins jobs maintenance & cleanup - a few ABE reporting patches - comparison of results between old & new lab * GCC - trunk monitoring, reported a few new failures. - Send patch to fix vqtb[lx][34] intrinsics on aarch64_be * Binutils - Added a Jenkins job to build+check binutils on a variety of configurations: https://ci.linaro.org/view/tcwg-ci/job/tcwg-binutils/ - sent a small patch to fix a bug in the recent STM32L4XX erratum patch == Next == * Validation: - work on the switch to the new lab, once dev-01 is back online - more tuning to avoid deadlocks - re-measure build time on dev-01, to better tune other build jobs

10 years, 6 months

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[ACTIVITY] 2nd - 6th Nov

by Yao Qi

* Two half day off. [2/10] # Progress # * TCWG-332, fails in gdb.threads/multiple-step-overs.exp. [1/10] Testing the simpler approach suggested during the review. * TCWG-387, done. [1/10] GDB patches are pushed in. * TCWG-422, GNU vector extension support in ARM GDB. [2/10] Patches are done, and being tested. * TCWG-423, GNU vector extension support in AArch64 GDB. [2/10] Writing patches. Find more issues for AArch64 that GDB doesn't fully understand the AArch64 calling convention. Need more work here. * Review ARM GDBserver software single step patch. [1/10] * Misc, meeting, email, [1/10] # Plan # * Off on Wed afternoon. * TCWG-422, post patches * TCWG-423, continue. -- Yao

10 years, 6 months

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[ANNOUNCE] Linaro Binary Toolchain Release-Candidate GCC 5.2 2015.11-rc1

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-rc1 Release-Candidate Archives. http://snapshots.linaro.org/components/toolchain/binaries/5.2-2015.11-rc1/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-rc1/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. Please evaluate this release-candidate for correctness. Linaro will shortly spin the Linaro GCC 5.2-2015.11 release if this release-candidate passes stakeholder validation. For bugs related to this release-candidate please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * GCC 5.2 2015.11-rc1 The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built from the Linaro GCC-5.2-2015.11 release-candidate source archive. The Linaro GCC-5.2-2015.11 release source archive is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive. -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

10 years, 6 months

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GCC performance questions

by Gunnar von Boehn

Dear List, I'm new to this list and have some questions. Looking at the created code of GCC on ARMv8, we noticed some areas where there is room for performance improvements. I assume that these items might already be noticed by you guys. For example: 1) We noticed that when writing typical DGEMM like code, GCC includes unnecessary DUP instruction 2) GCC seems unwilling to use LDP loads 3) For optimal FPU performance on some A57 its needed to interleave instruction working on ODD and EVEN registers GCC seem not properly support this. Here sometimes 100% performance increase could be reached by different instruction interleaving. 4) Some work loops highly benefit of interleaving of FPU instructinons and loads. GCC seems to likes to re-arrange the code so that most or all loads are put on top of the loop. This can reduce the performance of a well written workloop significantly. I have no patches to fix this. But I can produce C- code and ASM output which will show these performance issues. Please tell me what the next recommended step will be now. Are all these items known already, or shall I provide code examples to further explain them? Kind regards Gunnar von Boehn

10 years, 6 months

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[ACTIVITY] 26-30 October 2015

by Christophe Lyon

== Progress == * Validation - comparing results and build times between the 2 labs - tuning jobs scheduling to avoid deadlocks * GCC trunk monitoring - lots of validation results to check after 1 week of holidays :-) - a few regressions/new failures/wrong tests reported * Backports - a few reviews == Next == * Infrastructure/Validation * GCC dev: try to fix vqtbl intrinsics for aarch64_be before e/o stage1

10 years, 6 months

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[ANNOUNCE] Linaro GCC 4.9 2015.10 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.10 snapshot of the Linaro GCC 4.9 source package. This snapshot[1] is based on FSF GCC 4.9.4-pre+svn229467 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 4.9.4-pre+svn229467 * Backport of [Bugfix] PR tree-optimization/65735 * Backport of [Bugfix] PR tree-optimization/65177 * Backport of [Bugfix] PR tree-optimization/65048 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 6 months

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[ACTIVITY]

by Renato Golin

== Progress == * Infrastructure (4/10) - Installing Ubuntu on APM (perf works!) - Setting up a HiKey for in-order perf - Helping Milosz with crashing HiKeys * Maintenance (4/10) - Helping ARM with test-suite patches (D14061) - Investigating read-after-read dependency (D13259) * Background (2/10) - Code review, meetings, discussions, general support, etc.

10 years, 6 months

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[ACTIVITY] Week 43

by Yvan Roux

== Progress == o Linaro GCC (9/10) * Backports and reviews for our GCC 5 2015.11 snapshot * FSF branch merge and needed backports for our GCC 4.9 2015.10 snapshot o Misc (1/10) * Various meetings == Plan == o Complete 4.9 snapshot

10 years, 6 months

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[ACTIVITY] 26th - 30th October

by Bernie Ogden

Noise control experiments - TCWG-358 [3/10] * Some analysis of data to date Debian filesystem - TCWG-360 [3/10] * Got stuck on LAVA interactions * Now booting-to-LAVA-usability, needs some cleanup and testing with real benchmark runs Benchmarking-via-Jenkins - TCWG-348 [1/10] * Picked back up on understanding that LAVA uinstance is a-coming * Hacked pbl.py (post-build-lava) to generate suitable JSON ** As a bonus, this can work as a CLI job-submission tool =Plan= Holiday Friday (pending approval) Set up crashdumping on my Juno, try to learn why it crashes Finish Debian filesystem Get Jenkins generating and submitting jobs suitable for uinstance Write up noise control report (probably will get bumped to next week)

10 years, 6 months

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[Weekly] 26-30 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (3/10) - Could not reproduce test failure in qemu - Waiting on feedback from Maxim who is running patch on Linaro validation * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Debugging tree vectorizer to determine why loops with no wide add operations are no longer being vectorized * TCWG 146 - Debugging regression on arm big endian with Linaro 5 branch (2/10) * Misc (1/10) - Conference calls == Next week == - TCWG-317 - Resolve lto big endian failures - TCWG-369 - Identify why loops are not being vectorized - TCWG-146 - Resolve big endian failures

10 years, 6 months

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[ACTIVITY] 26-30 October 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 / PR43721 (8/10) - Completed writing expand_DIVMOD() and submitted patch upstream - Reworked patch according to Richard Biener's comments. (http://people.linaro.org/~prathamesh.kulkarni/pr43721-patch-v2.diff) - Wrote test-cases. * TCWG-319 (1/10) - Benchmark run without patch complete for "int" benchmarks on a53, a57 - Benchmark run with patch in progress for "int" benchmarks on a53, a57 * Misc (1/10) - Meetings == Next Week == - Continue with TCWG-72, TCWG-310li, TCWG-319 benchmarking

10 years, 6 months

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[ACTIVITY] 26-30 October 2015

by Yao Qi

# Progress # * TCWG-332, [1/10], patch is posted for review. * TCWG-187, [1/10], looks like a kernel (~3.4) bug on setting VFP registers through ptrace. Fails go away after I upgrade the kernel. * TCWG-387, [2/10], binutils patch is committed, while GDB patches are being reviewed. * TCWG-422, [3/10], Read AAPCS and gcc source code to understand the calling convention. On going. * FSF patch review, [2/10] ** Review patch set "all-stop on top of non-stop for remote". ** Review ARM fast tracepoint patches. ** Reopen PR 15564, as the fail isn't fixed. * Misc, meeting, [1/10] # Plan # * TCWG-422 * Support ST on using AArch64 multi-arch GDB if needed. * Review ARM GDBserver software single step patch. -- Yao

10 years, 6 months

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[Weekly] 19-23 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (5/10) - Continued to debug big endian/lto failure of four torture tests - Differences in lto vs. non-lto executables showed no significant differences * TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (4/10) - Resolved three of six test suite failures * Misc (1/10) - Conference calls == Next week == - TCWG-317 - Resolve lto big endian failures by debugging test cases with qemu - TCWG-369 - Resolve remaining test suite failures -- Michael Collison Linaro Toolchain Working Group michael.collison(a)linaro.org

10 years, 6 months

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linux ipv4 forward performance issue

by Liu Ting

Hello all, When upgrading meta-linaro/meta-linaro-toolchain from daisy to fido, we faced drastic performance downgrade (-34.06%) on linux ipv4 forwarding. The board is ls1021atwr (ARM Cortex-A7 MPCore compliant with ARMv7-A architecture). We did some investigation, and suspected that it is caused by the toolchain upgrade. Did someone meet similar issue? The detailed toolchain info: https://git.linaro.org/openembedded/meta-linaro.git/shortlog/refs/heads/fido gcc-linaro-4.9.3-2015.03, glibc-linaro-2.20-2014.11, binutils-linaro-2.25-2015.01 https://git.linaro.org/openembedded/meta-linaro.git/shortlog/refs/heads/dai… gcc-linaro-4.8.3-2014.04, eglibc-linaro-2.19-r2014.04, binutils-linaro-2.24-r2014.03 thanks. -Ting

10 years, 6 months

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[ACTIVITY] Week 41 - 42

by Yvan Roux

o Week 42 off (10/10) == Progress == o Linaro GCC (9/10) * Completed backports and reviews * Delivered GCC 5 2015.10 snapshot * Completed TCWG 389 (deploy snapshot job) o Misc (1/10) * Various meetings == Plan == o Back to work

10 years, 6 months

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[ACTIVITY] 19th - 23rd October

by Bernie Ogden

Mustang benchmarking bringup - (no ticket) [2/10] Controlled Debian build - TCWG-360 [1/10] * Constructed filesystem, works OK as chroot * Next step is to boot it Investigate Workload Automation framework - TCWG-361 [1/10] * Seems to basically work * SPEC support dubious Misc * LAVA uinstance background (TCWG-396, < 1/10) * Noise control experiments (TCWG-358, < 1/10) * ARM management duties [2/10]

10 years, 6 months

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[ACTIVITY] 19 - 23 October 2015

by Prathamesh Kulkarni

== This Week == * TCWG-72 (4/10) - wrote new pass to generate "divmod" internal fn. - investigating segfault during expansion of divmod. * TCWG-319 (2/10) - Benchmarking setup - Running INT benchmarks for a53, a57. * TCWG-310 (1/10) - Looked at how peeling occurs - Email discussions * Public Holiday (2/10) * Misc (1/10) - Meetings == Next week == - Submit patch for TCWG-72 upstream - TCWG-319 benchmarking - Convert ASM_FORMAT_PRIVATE_NAME macro to hook. - Continue with TCWG-310

10 years, 6 months

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[ACTIVITY]

by Renato Golin

== Progress == * Maintenance (5/10) - Investigating some LivermoreLoops that don't vectorise - Reducing cases to single specific causes * Background (5/10) - Code review, meetings, discussions, general support, etc. - More code of conduct stuff, license change to Apache 2 - Following up on sanitizers VMA discussion

10 years, 6 months

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[ACTIVITY] 19 - 23 October 2015

by Yao Qi

* Two days (Tue and Thu) off. [4/10] # Progress # * TCWG-180, patch is committed by Andrew Stubs. [1/10] I review and approve it. * Review patch set "all-stop on top of non-stop for remote". [3/10] Test them on aarch64 and arm. Triage and fix one regression. Review is still on going. * Review patch set "ARM gdbserver software breakpoint". [2/10] Review and approve them. They are preparatory to ARM tracepoint. # Plan # * Patch review. * TCWG-387, Move GDB using libopcodes to decode instructions. -- Yao

10 years, 6 months

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[ANNOUNCE] Linaro Binary Toolchain Release GCC 5.1 2015.08

by Ryan Arnold

The Linaro Toolchain Working Group is pleased to announce the availability of the Linaro Stable Binary Toolchain GCC 5.1-2015.08 Archives. http://releases.linaro.org/components/toolchain/binaries/5.1-2015.08/ These archives provide cross-toolchain executables (compiler, debugger, linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain binaries execute on a Linux or MS Windows (under mingw32) host operating-system. For bugs related to this release please email linaro-toolchain(a)lists.linaro.org or file a bug at https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain NEWS * 2015.08 * The Linaro GCC 5.1 2015.08 binary toolchain release is based on the Linaro GCC-5.1-2015.08 source archive release <http://releases.linaro.org/components/toolchain/gcc-linaro/5.1-2015.08/>. The major changes contained in 2015.08 over 2015.05 are described in the sections below on 2015.08-rc1 and 2015.08-rc2 . * 2015.08-rc2 * The Linaro 2015.08-rc2 release-candidate binary toolchain is based on the Linaro GCC-5.1-2015.08-rc1 release-candidate source archive. The only changes between 2015.08-rc1 and 2015.08-rc2 were the following changes in how the binary toolchains were built. The compiler itself was not changed. * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchains are now correctly configured. This was broken in 2015.08-rc1. The cross-compiler targetting armv8l-linux-gnueabihf is now correctly configured with --with-arch=armv8-a --with-fpu=neon-fp-armv8 --with-float=hard --disable-multilib --enable-multiarch. * Glibc’s slibdir and libdir were once again modified to address Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. The following are now the correct locations: libdir=lib/ (linker-scripts and static archives) slibdir=usr/lib/ (shared objects) rtlddir=lib/ (dynamic linker) * 2015.08-rc1 * x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchain now provided. Delivering on REQ-477 – Enable x86_64 to Aarch32 (32-bit ARMv8-A) cross binary toolchain product release and CARD-1637 – Enable Aarch32 (32-bit ARMv8-A) cross binary toolchain product releases , armv8l-linux-gnueabihf targetted toolchains are now available as part of this release-candidate. * Python support in GDB for both Linux and Mingw32 (32-bit windows). Delivered as requested in the linaro-toolchain mailing list post title – windows binary builds with gdb-python enabled?. * Added missing expat support to GDB. This addresses the following linaro-toolchain mailing list post – "Missing expat support in GDB 7.8 multi-lib enablement for arm bare-metal targets." * A fix for multilib enablement in baremetal toolchains (as described in ABE Review 6862). * Library Paths are now congruent with older Linaro Toolchain path layouts. This addresses Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to /libc/usr/lib/ which breaks things. libdir=lib/ (shared objects) slibdir=usr/lib/ (static libraries) rtlddir=lib/ (dynamic linker) -- Ryan S. Arnold Linaro Toolchain Working Group - Engineering Manager www.linaro.org

10 years, 6 months

1
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Question about the Linaro toolchain version

by Luo Zhenhua

Hi, The default gcc version of Yocto 2.0(Jethro) is 5.2.0, the gcc version in meta-linaro is gcc-4.9.4, may I know if gcc-linaro-4.9.4 will be used for Yocto 2.0 release? when will the linaro gcc be upgraded to gcc-5.x? BTW, can someone please help point out where the Linaro toolchain roadmap can be got? Best Regards, Zhenhua

10 years, 6 months

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[ACTIVITY] 12 - 16 October 2015

by Omair Javaid

== Progress == LLDB development -- Verify LLDB watchpoints on Android Arm and AArch64 targets. [TCWG-405] [4/10] - Ran LLDB testsuite on Nexus5, Nexus 7, Nexus S and Nexus 9 devices. - Started into failing watchpoint tests on all devices. -- Investigate and fix LLDB watchpoints tests that are failing on Android Nexus 9 AArch64 target. [TCWG-405] [5/10] - Debugging of ptrace watchpoint installation code. - Prepared a fix and tested on Nexus 9. Miscellaneous [1/10] -- Meetings, emails, discussions etc. == Plan == Further progress on investigating LLDB watchpoint issues on Android Nexus devices. Local testbots setup using new Android Nexus and Arm linux devices.

10 years, 6 months

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[ACTIVITY]

by Renato Golin

== Progress == * Libraries (3/10) - Back investigating libc++ issues in AArch64 buildbot - http://buildmaster.tcwglab.linaro.org/builders/clang-cmake-aarch64-prototype - Trying to solve the rt/unw/c++ library entanglement in the driver * Buildbots (1/10) - Trying to perf an application on APM, but it crashed while - Rebooted it for now, but on the list to migrate to a newer kernel * Background (6/10) - Code review, meetings, discussions, general support, etc. - Laptop playing stupid again, lost a day trying to fix things - New LLVM "code of conduct" sparked a huge discussion

10 years, 6 months

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[ACTIVITY] 12th - 16th October

by Bernie Ogden

Investigate effectiveness of noise-control measures - TCWG-358 [4/10] * Recovered from a couple more crashes, existing logging sheds no light * Explored the existing data a bit, need more to draw any conclusions Controlled image builds - TCWG-360 [2/10] * Looked into controlled, repeatable debian builds, B&B-style * Got the general shape of it, checking my understanding with Fathi LAVA microinstance - TCWG-396 [1/10] * Sent doc for review, revised it a bit Misc [3/10] * Exported benchmark/results handling rules to a place other Linaro-ans can read them * Updated example LAVA jobs to use tcwg tag (for load balancing purposes) * Meetings, mail, etc =Plan= Generate more noise data, watching out for crashes Produce a candidate Debian image, document how I did it If time, learn about Workload Automation

10 years, 6 months

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[Weekly] 12 - 16 October 2015

by Michael Collison

== This week == * TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (6/10) - Debugging failures on -flto/big endian combination - Wrote code for big endian lane support; failures still exist - Debugging lto to see if optimization is causing failures * TCWG-77 - Transform end of loop conditions to min_expr (1/10) - patch approved, checked in upstream * Misc (1/10) - Conference calls * US Holiday, Monday October 12th (2/10) == Next week == - TCWG-317 - Debug to determine if lto is causing failures

10 years, 6 months

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[ACTIVITY] 12th - 16th October

by Kugan

== Progress == - Run spec2006 with DS5/Streamline Performance Analyzer (3/10) - Setup DS5 - Setting up client for chromebook which requires kernel rebuild - Widening pass (TCWG-547) - 5/10 * iterated based on review comments * re-wrote GIMPLE_DEBUG handling - Misc (2/10) * gcc/bug list == Plan == * perf with spec2000 * continue with widening pass based on feedback

10 years, 6 months

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[ACTIVITY] 12th - 16th October

by Yao Qi

# Progress # * TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [1/10] Patches are committed. * TCWG-335, HW breakpoint on 2-byte aligned address, [3/10] patch is tested against most recent kernel. Everything works. Patch is committed. * TCWG-166, Review ARM software breakpoint in GDBserver patches. [1/10] Almost done. * Review various upstream patches. [2/10]. * Misc, [3/10] ** Meeting, ** Write up some slides about recent GDB development, and present them in ARM. # Plan # * TCWG-387, Move GDB using libopcodes to decode instructions. * More upstream patches review. * Two days off on Tue and Thu. Maybe off on Friday too. -- Yao

10 years, 6 months

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[ANNOUNCE] Linaro GCC 5 2015.10 snapshot

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.10 snapshot of the Linaro GCC 5 source package. This monthly snapshot[1] is based on FSF GCC 5.2+svn228499 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.10/ Interesting changes in this GCC source package snapshot include: * Updates to GCC 5.2+svn228499 * Backport of [Bugfix] [AArch32] Fix PR target/29693 * Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target * Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target * Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check * Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane bounds in expand * Backport of [Bugfix] [AArch32] PR 66541, 52144 Fix ARM/thumb pragma target * Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404 * Backport of [Bugfix] [AArch32] PR target/52144 attribute target (thumb,arm) [2.2/6] * Backport of [Bugfix] [AArch32] PR target/52144 target attributes Clean up arm_option_params_internals macro settings for attribute/pragma targets * Backport of [Bugfix] [AArch32] PR target/65768 * Backport of [Bugfix] [AArch64] PR63870 Neon error messages for vldN_lane/vstN_lane * Backport of [Bugfix] Fix PR66168 * Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765 * Backport of [Bugfix] PR c/49551 * Backport of [Bugfix] PR middle-end/64130 * Backport of [Bugfix] PR middle-end/66726 * Backport of [Bugfix] PR target/65768 Check cost of constants before propagating * Backport of [Bugfix] PR tree-optimization/67043 * Backport of [AArch32] 1-ARM/Thumb target attributes * Backport of [AArch32] 2-ARM/Thumb target attributes * Backport of [AArch32] 3-ARM/Thumb target attributes * Backport of [AArch32] Add ARM/thumb attribute target * Backport of [AArch32] Add ARM/thumb pragma target * Backport of [AArch32] Add TARGET_OPTION_PRINT * Backport of [AArch32] attribute target (thumb,arm) [2.1/6] * Backport of [AArch32] Correct spelling of references to ARMv6KZ * Backport of [AArch32] Fix ChangeLog * Backport of [AArch32] fix date * Backport of [AArch32] Fix static interworking call * Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM * Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT * Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when -mrestrict-it is in place * Backport of [AArch32] Use dmb ish instead of dmb sy for ARM * Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap instructions when available * Backport of [AArch64] [1/4] Define candidates for instruction fusion in a .def file * Backport of [AArch64] 1/5 Use atomic instructions for swap and fetch-update operations * Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap instructions when available * Backport of [AArch64] [2/4] Control the FMA steering pass in tuning structures rather than as core property * Backport of [AArch64] 2/5 Make BIC, other logical instructions, available * Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap instructions when available * Backport of [AArch64] [3/4] De-const-ify struct tune_params * Backport of [AArch64] 3/5 Add atomic load-operate instructions * Backport of [AArch64] [4/4] Add -moverride tuning command, and wire it up for control of fusion and fma-steering * Backport of [AArch64] 4/5 Use atomic load-operate instructions for fetch-update patterns * Backport of [AArch64] 5/5 Use atomic load-operate instructions for update-fetch patterns * Backport of [AArch64] Add ACLE predefined marcos: __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR * Backport of [AArch64] Add support for ARMv8.1 command line options * Backport of [AArch64] Always register fma_steering pass but gate it on the target option instead * Backport of [AArch64] [armv8.1] Expand +rdma documentation, small changes to march and mcpu text * Backport of [AArch64] --with-arch in config.gcc support "." * Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter * Backport of [AArch64] Fix another ICE with -mgeneral-regs-only * Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp * Backport of [AArch64] fix regrename pass to ensure renamings produce valid insns * Backport of [AArch64] Fix type of *<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3 pattern * Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [AArch64] Improve spill code - swap order in shl pattern * Backport of [AArch64] Improve spill code - swap order in shr patterns * Backport of [AArch64] movi type attribute confusion * Backport of [AArch64] Removed unused SLOWMUL target flags * Backport of [AArch64] typo fix in attribute for vst2_lane * Backport of [AArch64] Use conditional negate for abs * Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests * Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when Thumb mode is not supported * Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c * Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c * Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c * Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should not add -mfloat-abi=soft * Backport of [Testsuite] [AArch32] target attribute cleanup directives * Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn * Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32x4_t case * Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected values * Backport of [Testsuite] Don't specify "dg-do run" explicitly for vect test cases * Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove movw and movt * Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the testsuite is explicitly passing -mfloat-abi=hard * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] New AdvSIMD test * Backport of [Testsuite] Skip tests for inappropriate multilibs * Backport of [Misc] [1] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] Set REG_EQUAL * Backport of [Misc] [2] Allow REG_EQUAL for ZERO_EXTRACT * Backport of [Misc] Fix ChangeLog * Backport of [Misc] fix segfault in verify_flow_info() with -dx option * Backport of [Misc] fix typo * Backport of [Misc] Fix typo: Rename insn_reservation cortex_53_advsimd to cortex_a53_advsimd * Backport of [Misc] Fuseable is not a word -> s/fuseable/fusible/g * Backport of [Misc] [ifcvt Fix typo in comment * Backport of [Misc] [match-and-simplify] fix incorrect code-gen in 'for' pattern * Backport of [Misc] [match-and-simplify] reject expanding operator-list to implicit 'for' * Backport of [Misc] [match-and-simplify] report error for invalid operator-lists * Backport of [Misc] [simplify-rtx][2/2] Simplify - (y ? -x : x) -> (!y ? -x : x) * Backport of [Misc] The comparison in a compare exchange should not take place in VOIDmode * Backport of [Misc] Use cinc mnemonic for *csinc2<mode>_insn * Backport of [Misc] warn for empty struct -Wc++-compat * Backport of [Misc] [Driver] Wrong C++ paths when configuring with "--with-sysroot=/" * Backport of [Misc] [combine][1/2] Try to simplify before substituting * Backport of [Doc] [AArch64] Clarify feature modifiers {no,}{fp,simd,crypto} * Backport of [Doc] [AArch64] Fix position of -moverride documentation * Backport of [Doc] move (Variable Attributes, Type Attributes) up Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1]. Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2]. Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years, 6 months

1
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[ACTIVITY] Week 40 #2

by Yvan Roux

== Progress == o Linaro GCC (9/10) * Backports and Reviews - FSF branch merge - AArch64 armv8-1 support backported - Attribute target almost done * Long discussion on infra and stability o Misc (1/10) * Various meetings == Plan == o Complete backports o 2015.10 Snapshot

10 years, 6 months

1
0
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[ACTIVITY] 4th - 9th October

by Bernie Ogden

LAVA uinstance for benchmarking - TCWG-396 [3/10] * Long meeting with Renato + LAVA/lab people * Much thinking about the security side * Wrote up rough draft of what I understand the design to be Investigate effectiveness of noise control measures - TCWG-358 [3/10] * Set up new host node * Dealt with one host node crash, one target crash ** Noticed that target was writing logs to tmpfs, changed that so I can investigate next crash * Both sides stayed up through the weekend, hurrah * Some work on data-massaging scripts Misc [4/10] Heavier than usual week mail-wise, plus performance review prep =Plan= Clean up uinstance design, circulate to make sure we're all on same page Look at data from experiments so far Investigate B&B's Debian-building tools

10 years, 6 months

1
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[ACTIVITY] 5 - 9 October 2015

by Kugan

== Progress == - 1 day off public holiday (2/10) - Upstream patch follow-ups (2/10) * https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html Trying to reproduce 1.cc failure found with Christophe's testing * https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html Committed it and verified this will not happen with linaro-5 branch - Widening pass (TCWG-547) - 4/10 * iterated based on review comments - Misc (2/10) * gcc/bug list * setup vpn to lab == Plan == * perf with spec2000 * continue with widening pass based on feedback

10 years, 6 months

1
0
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[ACTIVITY]

by Renato Golin

== Progress == * Maintenance (1/10) - Removed redundant DefaultCPU in ARMTargetInfo * Buildbots (4/10) - Looong discussions upstream about stability of buildbots - Trial with IFC6410 marginally successfull, still not good enough, aborting - Moved benchmark buildbot to silent (avoid unnecessary spam) - Writing up some docs on current infra and plan * Infrastructure (3/10) - Long internal discussions about stability of TCWG validation - Agreeing on a LAVA micro-instance in TCWG for benchmarks * Background (2/10) - Code review, meetings, discussions, general support, etc. - Checking status of OpenMP on AArch64 (~10 failures out of ~240 tests) == Plan == More stuff...

10 years, 6 months

1
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[ACTIVITY] 5-9 October 2015

by Christophe Lyon

== Progress == * Infrastructure/validation (3/10) - prototyping a new Jenkins to job properly allocate testers. This raises more questions.... * Backports (1/10) - a few reviews * GCC (3/10) - sent updated patch for vtbX34 AdvSIMD intrinsics - discussed a few regressions * Misc (conf calls, meetings, emails, ...) (3/10) == Next == * Backports reviews * Infrastructure * GCC devs

10 years, 6 months

1
0
0 0

[ACTIVITY] 5th October -- 9th October

by Yao Qi

# Progress # * TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [4/10] After testing, patches are posted upstream. * In order to review one c++ debugging patch, learn some C++ abi, vtable and VTT, etc. Understand gcc dump by -fdump-class-hierarchy. [3/10] * Fix GDB cxx build breakage caused by my patch. [1/10] * Ask the effect of -fstack-check=specific to AArch64 prologue. GDB needs update. [1/10] * Misc, email, meeting. [1/10]. # Plan # * TCWG-162, commit patches if no objections. * TCWG-387, use libopcodes to decode instructions in GDB. -- Yao

10 years, 6 months

1
0
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ILP32 is a parity feature to x86_64 (x32)

by Pinski, Andrew

10 years, 7 months

2
1
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Fw: [Bug target/67877] New: Split stack needs to be support for AARCH64

by Pinski, Andrew

FYI. This is a parity feature with both PowerPC64 and x86_64. Needed to support GCCgo. Note full gold support is needed too. ---------- Forwarded message ---------- From: pinskia at gcc dot gnu.org <gcc-bugzilla(a)gcc.gnu.org> Date: Tue, Oct 6, 2015 at 3:30 PM Subject: [Bug target/67877] New: Split stack needs to be support for AARCH64 To: gcc-bugs(a)gcc.gnu.org https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67877 Bug ID: 67877 Summary: Split stack needs to be support for AARCH64 Product: gcc Version: 6.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: pinskia at gcc dot gnu.org Target Milestone: --- Target: aarch64-linux-gnu* To support gccgo better split stack should be implemented.

10 years, 7 months

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[ACTIVITY] 28th August - 2nd October

by Bernie Ogden

Connect recovery - [2/10] Investigate effectiveness of noise-control measures - TCWG-358 [3/10] * Host node crashed, tried to recover it, failed, started building a new one Jenkins automation - TCWG-348 [3/10] * Everything in place up to first interaction with LAVA kvm * Considered LAVA team's micro-instance proposal Misc [2/10] =Plan= Discuss micro-instance proposal Work on whatever comes out of discussion Finish building new host node, get experiments running again

10 years, 7 months

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[ACTIVITY] 14th - 18th September

by Bernie Ogden

Investigate effectiveness of noise-control measures - TCWG-358 [6/10] * Finished setup, started running experiments * Initial data pretty noisy, more runs needed * Kicked off more runs for week of Connect Ensure that all critical data is logged - TCWG-349 [1/10] * Logged a few more variables, tested, merged * Put down until we have a controlled image build Misc - [3/10]

10 years, 7 months

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[ACTIVITY] Week 40

by Yvan Roux

* 2 post-connect days off (4/10) == Progress == o Linaro GCC (3/10) * Backporting armv8-1 support * Dealing with conflicts o Misc (3/10) * Various meetings * Internal report on Connect == Plan == o Backports o Releases process tasks

10 years, 7 months

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