The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2015.10 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.2+svn228499 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.2+svn228499
* Backport of [Bugfix] [AArch32] Fix PR target/29693
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check
* Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane
bounds in expand
* Backport of [Bugfix] [AArch32] PR 66541, 52144 Fix ARM/thumb pragma target
* Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404
* Backport of [Bugfix] [AArch32] PR target/52144 attribute target
(thumb,arm) [2.2/6]
* Backport of [Bugfix] [AArch32] PR target/52144 target attributes
Clean up arm_option_params_internals macro settings for
attribute/pragma targets
* Backport of [Bugfix] [AArch32] PR target/65768
* Backport of [Bugfix] [AArch64] PR63870 Neon error messages for
vldN_lane/vstN_lane
* Backport of [Bugfix] Fix PR66168
* Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765
* Backport of [Bugfix] PR c/49551
* Backport of [Bugfix] PR middle-end/64130
* Backport of [Bugfix] PR middle-end/66726
* Backport of [Bugfix] PR target/65768 Check cost of constants before
propagating
* Backport of [Bugfix] PR tree-optimization/67043
* Backport of [AArch32] 1-ARM/Thumb target attributes
* Backport of [AArch32] 2-ARM/Thumb target attributes
* Backport of [AArch32] 3-ARM/Thumb target attributes
* Backport of [AArch32] Add ARM/thumb attribute target
* Backport of [AArch32] Add ARM/thumb pragma target
* Backport of [AArch32] Add TARGET_OPTION_PRINT
* Backport of [AArch32] attribute target (thumb,arm) [2.1/6]
* Backport of [AArch32] Correct spelling of references to ARMv6KZ
* Backport of [AArch32] Fix ChangeLog
* Backport of [AArch32] fix date
* Backport of [AArch32] Fix static interworking call
* Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM
* Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT
* Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when
-mrestrict-it is in place
* Backport of [AArch32] Use dmb ish instead of dmb sy for ARM
* Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap
instructions when available
* Backport of [AArch64] [1/4] Define candidates for instruction fusion
in a .def file
* Backport of [AArch64] 1/5 Use atomic instructions for swap and
fetch-update operations
* Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [2/4] Control the FMA steering pass in tuning
structures rather than as core property
* Backport of [AArch64] 2/5 Make BIC, other logical instructions, available
* Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [3/4] De-const-ify struct tune_params
* Backport of [AArch64] 3/5 Add atomic load-operate instructions
* Backport of [AArch64] [4/4] Add -moverride tuning command, and wire
it up for control of fusion and fma-steering
* Backport of [AArch64] 4/5 Use atomic load-operate instructions for
fetch-update patterns
* Backport of [AArch64] 5/5 Use atomic load-operate instructions for
update-fetch patterns
* Backport of [AArch64] Add ACLE predefined marcos:
__ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR
* Backport of [AArch64] Add support for ARMv8.1 command line options
* Backport of [AArch64] Always register fma_steering pass but gate it
on the target option instead
* Backport of [AArch64] [armv8.1] Expand +rdma documentation, small
changes to march and mcpu text
* Backport of [AArch64] --with-arch in config.gcc support "."
* Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter
* Backport of [AArch64] Fix another ICE with -mgeneral-regs-only
* Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp
* Backport of [AArch64] fix regrename pass to ensure renamings produce
valid insns
* Backport of [AArch64] Fix type of
*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3 pattern
* Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch64] Improve spill code - swap order in shl pattern
* Backport of [AArch64] Improve spill code - swap order in shr patterns
* Backport of [AArch64] movi type attribute confusion
* Backport of [AArch64] Removed unused SLOWMUL target flags
* Backport of [AArch64] typo fix in attribute for vst2_lane
* Backport of [AArch64] Use conditional negate for abs
* Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests
* Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when
Thumb mode is not supported
* Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c
* Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should
not add -mfloat-abi=soft
* Backport of [Testsuite] [AArch32] target attribute cleanup directives
* Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn
* Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32x4_t case
* Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove
useless expected values
* Backport of [Testsuite] Don't specify "dg-do run" explicitly for
vect test cases
* Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove
movw and movt
* Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the
testsuite is explicitly passing -mfloat-abi=hard
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] Skip tests for inappropriate multilibs
* Backport of [Misc] [1] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Set REG_EQUAL
* Backport of [Misc] [2] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Fix ChangeLog
* Backport of [Misc] fix segfault in verify_flow_info() with -dx option
* Backport of [Misc] fix typo
* Backport of [Misc] Fix typo: Rename insn_reservation
cortex_53_advsimd to cortex_a53_advsimd
* Backport of [Misc] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [Misc] [ifcvt Fix typo in comment
* Backport of [Misc] [match-and-simplify] fix incorrect code-gen in
'for' pattern
* Backport of [Misc] [match-and-simplify] reject expanding
operator-list to implicit 'for'
* Backport of [Misc] [match-and-simplify] report error for invalid
operator-lists
* Backport of [Misc] [simplify-rtx][2/2] Simplify - (y ? -x : x) ->
(!y ? -x : x)
* Backport of [Misc] The comparison in a compare exchange should not
take place in VOIDmode
* Backport of [Misc] Use cinc mnemonic for *csinc2<mode>_insn
* Backport of [Misc] warn for empty struct -Wc++-compat
* Backport of [Misc] [Driver] Wrong C++ paths when configuring with
"--with-sysroot=/"
* Backport of [Misc] [combine][1/2] Try to simplify before substituting
* Backport of [Doc] [AArch64] Clarify feature modifiers {no,}{fp,simd,crypto}
* Backport of [Doc] [AArch64] Fix position of -moverride documentation
* Backport of [Doc] move (Variable Attributes, Type Attributes) up
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
== Progress ==
o Linaro GCC (9/10)
* Backports and Reviews
- FSF branch merge
- AArch64 armv8-1 support backported
- Attribute target almost done
* Long discussion on infra and stability
o Misc (1/10)
* Various meetings
== Plan ==
o Complete backports
o 2015.10 Snapshot
LAVA uinstance for benchmarking - TCWG-396 [3/10]
* Long meeting with Renato + LAVA/lab people
* Much thinking about the security side
* Wrote up rough draft of what I understand the design to be
Investigate effectiveness of noise control measures - TCWG-358 [3/10]
* Set up new host node
* Dealt with one host node crash, one target crash
** Noticed that target was writing logs to tmpfs, changed that so I
can investigate next crash
* Both sides stayed up through the weekend, hurrah
* Some work on data-massaging scripts
Misc [4/10]
Heavier than usual week mail-wise, plus performance review prep
=Plan=
Clean up uinstance design, circulate to make sure we're all on same page
Look at data from experiments so far
Investigate B&B's Debian-building tools
== Progress ==
- 1 day off public holiday (2/10)
- Upstream patch follow-ups (2/10)
* https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html
Trying to reproduce 1.cc failure found with Christophe's testing
* https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html
Committed it and verified this will not happen with linaro-5 branch
- Widening pass (TCWG-547) - 4/10
* iterated based on review comments
- Misc (2/10)
* gcc/bug list
* setup vpn to lab
== Plan ==
* perf with spec2000
* continue with widening pass based on feedback
== Progress ==
* Maintenance (1/10)
- Removed redundant DefaultCPU in ARMTargetInfo
* Buildbots (4/10)
- Looong discussions upstream about stability of buildbots
- Trial with IFC6410 marginally successfull, still not good enough, aborting
- Moved benchmark buildbot to silent (avoid unnecessary spam)
- Writing up some docs on current infra and plan
* Infrastructure (3/10)
- Long internal discussions about stability of TCWG validation
- Agreeing on a LAVA micro-instance in TCWG for benchmarks
* Background (2/10)
- Code review, meetings, discussions, general support, etc.
- Checking status of OpenMP on AArch64 (~10 failures out of ~240 tests)
== Plan ==
More stuff...
# Progress #
* TCWG-162, Aarch64 non-stop debugging (or displaced stepping). [4/10]
After testing, patches are posted upstream.
* In order to review one c++ debugging patch, learn some C++ abi,
vtable and VTT, etc. Understand gcc dump by -fdump-class-hierarchy.
[3/10]
* Fix GDB cxx build breakage caused by my patch. [1/10]
* Ask the effect of -fstack-check=specific to AArch64 prologue. GDB
needs update. [1/10]
* Misc, email, meeting. [1/10].
# Plan #
* TCWG-162, commit patches if no objections.
* TCWG-387, use libopcodes to decode instructions in GDB.
--
Yao
FYI. This is a parity feature with both PowerPC64 and x86_64. Needed to support GCCgo. Note full gold support is needed too.
---------- Forwarded message ----------
From: pinskia at gcc dot gnu.org <gcc-bugzilla(a)gcc.gnu.org>
Date: Tue, Oct 6, 2015 at 3:30 PM
Subject: [Bug target/67877] New: Split stack needs to be support for AARCH64
To: gcc-bugs(a)gcc.gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67877
Bug ID: 67877
Summary: Split stack needs to be support for AARCH64
Product: gcc
Version: 6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: pinskia at gcc dot gnu.org
Target Milestone: ---
Target: aarch64-linux-gnu*
To support gccgo better split stack should be implemented.
Connect recovery - [2/10]
Investigate effectiveness of noise-control measures - TCWG-358 [3/10]
* Host node crashed, tried to recover it, failed, started building a new one
Jenkins automation - TCWG-348 [3/10]
* Everything in place up to first interaction with LAVA kvm
* Considered LAVA team's micro-instance proposal
Misc [2/10]
=Plan=
Discuss micro-instance proposal
Work on whatever comes out of discussion
Finish building new host node, get experiments running again
Investigate effectiveness of noise-control measures - TCWG-358 [6/10]
* Finished setup, started running experiments
* Initial data pretty noisy, more runs needed
* Kicked off more runs for week of Connect
Ensure that all critical data is logged - TCWG-349 [1/10]
* Logged a few more variables, tested, merged
* Put down until we have a controlled image build
Misc - [3/10]
* 2 post-connect days off (4/10)
== Progress ==
o Linaro GCC (3/10)
* Backporting armv8-1 support
* Dealing with conflicts
o Misc (3/10)
* Various meetings
* Internal report on Connect
== Plan ==
o Backports
o Releases process tasks
== This week ==
* TCWG-317 - Exploit wide add operations when appropriate for Aarch32 (4/10)
- Patch sent upstream for review
- Fixed some failing tree-ssa testcases by modifying
'check_effective_target_vect_widen_sum_hi_to_si_pattern' to indicate
Aarch32 supports vector widening add
- Fixed length attributes on patterns in neon.md
- Added test cases to ChangeLog
- Debugging failures on -flto and arm big endian
* TCWG-369 - Exploit wide add operations when appropriate for Aarch64 (3/10)
- Fixed some failing tree-ssa testcases by modifying
'check_effective_target_vect_widen_sum_hi_to_si_pattern' to indicate
Aarch64 supports vector widening add
- Debugging tree-ssa test suite failures
* Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10)
- Patch checked in upstream on trunk
* TCWG-77 - Transform end of loop conditions to min_expr (2/10)
- Submitted upstream waiting for final approval
- Merged multiple patterns into one pattern in match.md
- Rewrote test case to work on all targets
* Misc (1/10)
- Conference calls
== Next week ==
- Holiday/vacation
== Progress ==
- 1 day off recovering from travel and 1 public holiday (4/10)
- https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02196.html (1/10)
* Approved patch
* re-based and retesting before committing
- https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html (1/10)
* Found a latent issue while testing patches
* posted a patch for review
- Widening pass (TCWG-547) - 4/10
* Working on review comments
== Plan ==
* Monday public holiday
* Post the revised patch for widening pass
* commit approved patches
== Progress ==
* Monday off (2/10)
* Buildbot (6/10)
- Investigating sanitizer crash in Thumb2+NEON
- Testing IFC6410 with Linaro 15.09
- CPUs good, 1.7GHz on all cores, stable, cool
- Not enough space on local (fast) flash
- USB stick stable, but slow (3h vs 2h on Chrome 2)
- USB disk unstable and slow (power management, etc)
- SATA broken, and slow
* Infrastructure (1/10)
- Discussing LAVA instance in TCWG lab, benchmarks
- Playing with D02: corrupted system, but the machine is *fast*
* Background (1/10)
- Code review, meetings, discussions, general support, etc.
== Plan ==
* More infrastructure meetings
* More buildbot work
* Whatever...
# Progress #
* TCWG-373, Aarch64 non-stop debugging (or displaced stepping). [2/10]
Patches V1 are ready for upstream submission, but find opcodes has
already interfaces to decode instructions, so decide to use opcodes
for aarch64 GDB first.
* TCWG-387, one patch exposing one opcode interface is pushed in. [4/10]
Switch software single step code for aarch64 to using opcodes
interface. Patch is pushed in.
Rewriting prologue analyser to use opcode interface too.
* TCWG-159, Kernel awareness in GDB. [1/10]
Resume the work as Peter Griffin has cycles to do so. We are happy
with the plan so far.
* Review arm software breakpoint in GDBserver patches. [1/10]
* Misc, [2/10]
# Plan #
* TCWG-387, TCWG-373
--
Yao
== Progress ==
2 days off (4/10)
* Infrastructure/validation: (3/10)
further checking of cross-testing results stability on aarch64-linux
- found a workaround for a timestamp problem (_Pragma3 testcase)
- looked at c11-atomic-exec-5 whose execution time ranges between 1s
and 1h :-)
- forcing make check to -j8 seems to work well, will work on a nicer
improvement
* reported and briefly looked at failure in a new libstdc++ test
(directory_iterator) on armv5t
* Misc (conf calls, meetings, emails, ....) (2/10)
* Internal (1/10)
- GNU linker patch review
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain Release-Candidate GCC 5.1-2015.08-rc2
Archives.
http://snapshots.linaro.org/components/toolchain/binaries/5.1-2015.08-rc2/
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will
shortly spin the Linaro GCC 5.1-2015.08 release if this release-candidate
passes stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at http://
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* 2015.08-rc2
* The Linaro 2015.08-rc2 release-candidate binary toolchain is based on
the Linaro GCC-5.1-2015.08-rc1 release-candidate source archive. The only
changes between 2015.08-rc1 and 2015.08-rc2 were the following changes in
how the binary toolchains were built. The compiler itself was not changed.
* x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchains are
now correctly configured. This was broken in 2015.08-rc1. The
cross-compiler targetting armv8l-linux-gnueabihf is now correctly
configured with --with-arch=armv8-a --with-fpu=neon-fp-armv8
--with-float=hard --disable-multilib --enable-multiarch.
* Glibc’s slibdir and libdir were once again modified to address Linaro
Bugzilla 1717 – Linaro-4.9-2015.05 moved system libs from /libc/lib/ to
/libc/usr/lib/ which breaks things. The following are now the correct
locations:
libdir=lib/ (linker-scripts and static archives)
slibdir=usr/lib/ (shared objects)
rtlddir=lib/ (dynamic linker)
* 2015.08-rc1
* x86_64 hosted, armv8l-linux-gnueabihf targetted cross toolchain now
provided.
Delivering on REQ-477 – Enable x86_64 to Aarch32 (32-bit ARMv8-A)
cross binary toolchain product release and CARD-1637 – Enable Aarch32
(32-bit ARMv8-A) cross binary toolchain product releases ,
armv8l-linux-gnueabihf targetted toolchains are now available as part of
this release-candidate.
* Python support in GDB for both Linux and Mingw32 (32-bit windows).
Delivered as requested in the linaro-toolchain mailing list post
title – windows binary builds with gdb-python enabled?.
* Added missing expat support to GDB.
This addresses the following linaro-toolchain mailing list post –
"Missing expat support in GDB 7.8 multi-lib enablement for arm bare-metal
targets."
* A fix for multilib enablement in baremetal toolchains (as described
in ABE Review 6862).
* Library Paths are now congruent with older Linaro Toolchain path
layouts. This addresses Linaro Bugzilla 1717 – Linaro-4.9-2015.05 moved
system libs from /libc/lib/ to /libc/usr/lib/ which breaks things.
libdir=lib/ (shared objects)
slibdir=usr/lib/ (static libraries)
rtlddir=lib/ (dynamic linker)
# Progress #
* TCWG-189, Aarch64 fast tracepoint. [2/10]
Done. Patches are committed.
* TCWG-373, Support displaced stepping on aarch64-linux. [4/10]
GDB works basically, still need to refactor and polish the code.
* TCWG-374, Test displaced stepping on aarch64-linux. [1/10]
Add new tests.
* TCWG-166, gdbserver support for tracepoints on ARM. [3/10].
Review patches, play with patches, and investigate on some issues.
Ongoing.
# Plan #
* TCWG-373, TCWG-374, and TCWG-166.
--
Yao
# Progress #
* TCWG-188, aarch64 GDB multi-arch support. [2/10]
All patches went upstream except that one is blocked by kernel patch.
The work is done!
* TCWG-189, aarch64 fast tracepoint support. [2/10]
Update them and post V2 out. Pending for review.
* TCWG-373, Aarch64 non-stop debugging (or displaced stepping). [2/10]
Think about it, and break it into pieces. Refactor fast tracepoint
code so that some can be reused for displaced stepping.
* TCWG-375, Don't skip gdb.asm/asm-source.exp on aarch64. [1/10]
Patch is pushed in.
* TCWG-166, Review arm tracepoint patches from Ericsson upstream. [1/10]
May have something wrong for permanent breakpoint on thumb code.
Need to figure out a case to trigger that.
* Misc, meeting and training. [2/10]
# Plan #
* TCWG-189, TCWG-373, TCWG-166.
--
Yao
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2015.09 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.2+svn227732 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.2+svn227732
* Backport of [Bugfix] [AArch32] PR target/26702
* Backport of [Bugfix] [AArch32] PR target/26702
* Backport of [Bugfix] [AArch32] PR rtl-optimization/34503
* Backport of [Bugfix] [AArch32] PR target/64208 iwmmxt pattern
* Backport of [Bugfix] [AArch32] PR target/65924
* Backport of [Bugfix] [AArch64] PR 65770 vstN_lane on bigendian
* Backport of [Bugfix] [AArch64] PR 65375 Fix RTX cost for vector SET
* Backport of [Bugfix] [AArch64] PR target/65491: Classify V1TF
vectors as AAPCS64 short vectors rather than composite types
* Backport of [Bugfix] [AArch64] PR target/66049
* Backport of [Bugfix] [AArch64] PR 63949
* Backport of [Bugfix] PR rtl-optimization/64616 Move insns without
introducing new temporaries in loop2_invariant
* Backport of [Bugfix] PR rtl-optimization/66076
* Backport of [Bugfix] PR tree-optimization/65447
* Backport of [AArch32] Add cpu_defines.h for ARM
* Backport of [AArch32] Additional bics patterns
* Backport of [AArch32] Add support for CFI directives in fp emulation
routines for ARM
* Backport of [AArch32] Add support for crtfastmath
* Backport of [AArch32] Apply arm.h change for previous commit
* Backport of [AArch32] (*arm_subsi3_insn): Fixed redundant alternatives
* Backport of [AArch32] Fix up bootstrap and fix typo in related changelog entry
* Backport of [AArch32] Handle UNSPEC_VOLATILE in rtx costs and don't
recurse inside the unspec
* Backport of [AArch32] insns attributes and alternative cleanups
* Backport of [AArch32] Make tune params tables more self-documenting
* Backport of [AArch32] Remove vec_shr and vec_shr optabs
* Backport of [AArch32] Use uppercase for code iterator names
* Backport of [AArch64] Add alternative 'extr' pattern, calculate rtx
cost properly
* Backport of [AArch64] Add branch-cost to cpu tuning information
* Backport of [AArch64] Add __extension__ and __always_inline__ to
crypto intrinsics
* Backport of [AArch64] Add vcond(u?)didi pattern
* Backport of [AArch64] Fix aarch64_rtx_costs of PLUS/MINUS
* Backport of [AArch64] Fix Cortex-A53 shift costs
* Backport of [AArch64] Fix geniterators.sh to use standard BRE syntax in sed
* Backport of [AArch64] Fix up new line in previous commit
* Backport of [AArch64] Handle FLOAT and UNSIGNED_FLOAT in rtx costs
* Backport of [AArch64] Idiomatic 64x1 comparisons in arm_neon.h
* Backport of [AArch64] Implement -m{cpu,tune,arch}=native using only
/proc/cpuinfo
* Backport of [AArch64] In aarch64_class_max_nregs use UNITS_PER_VREG
and UNITS_PER_WORD
* Backport of [AArch64] Make aarch64_min_divisions_for_recip_mul configurable
* Backport of [AArch64] Properly cost FABD pattern
* Backport of [AArch64] Properly cost MNEG/[SU]MNEGL patterns
* Backport of [AArch64] Properly handle mvn-register and add EON+shift
pattern and cost appropriately
* Backport of [AArch64] Properly handle SHIFT ops and EXTEND in
aarch64_rtx_mult_cost
* Backport of [AArch64] Remember to cost operand 0 in FP compare-with-0.0 case
* Backport of [AArch64] Use extend_arith rtx cost appropriately
* Backport of [AArch64] Use mov for add with large immediate
* Backport of [AArch64] Fix a couple of bugs regarding loop invariant
motion discovered by spec2k6 on aarch64
* Backport of [Musl libc] Add musl support to GCC
* Backport of [Musl libc] libitm fixes for musl support
* Backport of [Musl libc] musl libc config
* Backport of [Musl libc] mips musl support
* Backport of [Musl libc] unwind fix for musl
* Backport of [Musl libc] libstdc++, libgfortran gthr workaround for musl
* Backport of [Musl libc] fixincludes update for musl support
* Backport of [Musl libc] [AArch32] [4/13] arm musl support
* Backport of [Musl libc] [AArch64] [3/13] aarch64 musl support
* Backport of [Testsuite] [AArch32] advsimd-intrinsics.exp:
dg-do-what=compile if HW does not have Neon
* Backport of [Testsuite] [AArch32] Fix test for pr64616
* Backport of [Testsuite] [AArch32] Require Thumb2 effective target
* Backport of [Testsuite] [AArch32] Fix r222371 (PR target/26702)
* Backport of [Testsuite] Cleanup advsimd-intrinsics.exp, removing
unnecessary loop
* Backport of [Testsuite] don't clobber dg-do-what-default in
advsimd-intrinsics.exp
* Backport of [Testsuite] don't try to execute simd.exp tests on
targets without NEON
* Backport of [Testsuite] move check-gcc parallelize value into C front end
* Backport of [Testsuite] new vqmovn test
* Backport of [Testsuite] new vqmovun test
* Backport of [Testsuite] new vqrdmulh_lane test
* Backport of [Testsuite] new vqrdmulh_n test
* Backport of [Testsuite] new vqrdmulh test
* Backport of [Testsuite] new vqrshl test
* Backport of [Testsuite] new vqrshn_n test
* Backport of [Testsuite] new vqrshun_n test
* Backport of [Testsuite] new vqshl_n test
* Backport of [Testsuite] new vqshl test
* Backport of [Testsuite] new vqshlu_n test
* Backport of [Testsuite] new vqshrn_n test
* Backport of [Testsuite] new vqshrun_n test
* Backport of [Testsuite] Reinstate torture-init and torture-finalize
in advsimd-intrinsics.exp
* Backport of [Misc] Try REG_EQUAL for nonzero_bits
* Backport of [Misc] Don't reset ssa_name infor in struct iv
* Backport of [Misc] make clean' fix
* Backport of [Misc] Make vector_compare_rtx cope with VOID mode constants
* Backport of [Misc] set_nonzero_bits_and_sign_copies/combine.c
* Backport of [Misc] Expand pow (x, CONST) using square roots when possible
* Backport of [Doc] [AArch32] (ARM Options, mtune): add missing entries
* Backport of [Doc] Add missing jit and lto info.....
* Backport of [Doc] Declaring Attributes of Functions/split by target
* Backport of [Doc] reorganize (Type Attributes) and (Variable Attributes)
* Backport of [Doc] Update __atomic builtins documentation
* Backport of [Doc] Update definition location of attribute_spec in
documentation
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing
list":http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC
product:http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro
support":mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Ensure all critical (benchmarking) data is logged - TCWG-349 [1/10]
* Added logging of several factors
* Documented what we do and don't log
Noise control experiments on Juno - TCWG-349 [4/10]
* Rediscovered that my Juno is an r0, not an r1
* Rebuilt target image in a carefully scripted way
* Fiddled about with differences between local and LAVA targets
* Ran a couple of trials to test infrastructure
Connect preparation - [2/10]
* General sorting out of tickets et al
* Final pass through benchmarking presentation
Misc - [3/10]
=Plan=
Merge 'logging' branch
Final pass through logging documentation
Run some noise experiments on Juno
If time, work on Jenkins benchmarking jobs
== Progress ==
LLDB development
-- Progress to add support for un-alinged watchpoints on AArch64
[TCWG-367] [5/10]
-- Truncating watched bits wasnt accepted as a solution, will look
into issues during connect.
-- Trying to figure out a way to use multiple watchpoint slots for a
single watchpoint.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
-- Travel preparations
Holiday 10 - 11 September 2015 - Travelling to US
== Plan ==
Holiday 14 - 18 September 2015
Connect 21 - 25 September 2015
Holiday 28 September - 5th October 2015
Hi,
I've tried probably a dozen different ABE build command lines with various combinations of cpu/arch/tune on the latest tree and on the 2014.09 release and am unable to build for the armv6/1136J-S.
Before bothering the list, I scoured the gzipped archive back through 2013, and there is little mention of any problems OR successes with armv6. I am wondering if armv6 is supported, and if so, what is the secret sauce ABE command line to build successfully for the 1136J-S.
Some of the builds I tried were missing tarball components, others fail later on such as the one below that gets through building gcc and bombs building the eabi.
--------------------
'abe.sh -target arm-linux-gnueabi -build all -set cpu=arm1136j-s' produces the following, see further below for the gcc version data:
arm-linux-gnueabi-gcc ../sysdeps/arm/aeabi_memclr.c -c -std=gnu99
-fgnu89-inline -O2 -Wall -Werror -Winline -Wno-error=undef -Wundef
-Wwrite-strings -fmerge-all-constants -frounding-math -g
-Wstrict-prototypes -I../include
-I/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu
-I/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master
-I../sysdeps/unix/sysv/linux/arm -I../sysdeps/arm/nptl
-I../sysdeps/unix/sysv/linux/include -I../sysdeps/unix/sysv/linux
-I../sysdeps/nptl -I../sysdeps/pthread -I../sysdeps/gnu
-I../sysdeps/unix/inet -I../sysdeps/unix/sysv -I../sysdeps/unix/arm
-I../sysdeps/unix -I../sysdeps/posix -I../sysdeps/arm/armv6
-I../sysdeps/arm/include -I../sysdeps/arm -I../sysdeps/wordsize-32
-I../sysdeps/ieee754/flt-32 -I../sysdeps/ieee754/dbl-64
-I../sysdeps/ieee754 -I../sysdeps/generic -I.. -I../libio -I. -nostdinc
-isystem
/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu/lib/gcc/arm-linux-gnueabi/5.1.1/include
-isystem
/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu/lib/gcc/arm-linux-gnueabi/5.1.1/include-fixed
-isystem /home/billd/_build/sysroots/arm-linux-gnueabi/usr/include
-D_LIBC_REENTRANT -include
/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/libc-modules.h
-DMODULE_NAME=libc -include ../include/libc-symbols.h -o
/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/aeabi_memclr.o
-MD -MP -MF
/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/aeabi_memclr.o.dt
-MT
/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/aeabi_memclr.o
/tmp/ccTT8UgL.s: Assembler messages:
/tmp/ccTT8UgL.s:492: Error: lo register required -- `add
pc,r3,#(0xffff0fc0-0xffff0fff)'
/tmp/ccTT8UgL.s:490: Error: invalid immediate: -61441 is out of range
make[2]: ***
[/home/billd/_build/builds/x86_64-unknown-linux-gnu/arm-linux-gnueabi/glibc.git~release-2.21-master/csu/libc-start.o]
Error 1
--- here is the gcc -v output for the build above. ----
./arm-linux-gnueabi-gcc -v
Using built-in specs.
COLLECT_GCC=./arm-linux-gnueabi-gcc
COLLECT_LTO_WRAPPER=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu/libexec/gcc/arm-linux-gnueabi/5.1.1/lto-wrapper
Target: arm-linux-gnueabi
Configured with:
'/home/billd/_build/snapshots/gcc.git~linaro-gcc-5-branch/configure'
SHELL=/bin/bash --with-bugurl=https://bugs.linaro.org
--with-mpc=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu
--with-mpfr=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu
--with-gmp=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu
--with-gnu-as --with-gnu-ld --disable-libstdcxx-pch --disable-libmudflap
--with-cpu=arm1136j-s --with-cloog=no --with-ppl=no --with-isl=no
--disable-nls --enable-c99 --with-fpu=vfpv3-d16 --with-float=softfp
--with-mode=thumb --disable-multilib --enable-multiarch --disable-libssp
--disable-libquadmath --disable-threads --without-headers --with-newlib
--disable-libmudflap --disable-bootstrap --disable-decimal-float
--disable-libgomp --disable-libatomic --disable-libsanitizer
--disable-plugins --disable-libitm MAKEINFO=echo --enable-languages=c
--with-sysroot=/home/billd/_build/builds/sysroot-arm-linux-gnueabi
--disable-shared --with-glibc-version=2.18
--build=x86_64-unknown-linux-gnu --host=x86_64-unknown-linux-gnu
--target=arm-linux-gnueabi
--prefix=/home/billd/_build/builds/destdir/x86_64-unknown-linux-gnu
Thread model: single
gcc version 5.1.1 20150608 (Linaro GCC 5.1-2015.06-1~dev)
== Progress ==
o Linaro GCC validation (8/10)
* Finished on-going backports validation
* Still dealing with jenkins/infra instability
* Prepared branch merge
* Continue on my new reviewing/validation tool
o Misc (2/10)
* Various meetings
* AArch64 libunwind patch review
== Plan ==
o Finish branch merge
o GCC snapshot
o Travel to SFO'15
== This week ==
* TCWG-316 -Exploit vector multiply by scalar instructions when multiple
scalars are used as
coefficients in a loop (5/10)
- Wrote patterns to allow combine pass to mergenon-standard multiply
by lane patterns.
* Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10)
- Updated patch based on upstream comments and re-sent upstream
* TCWG-77 - Transform end of loop conditions to min_expr (1/10)
- Writing dejagnu test case.
- Writing function to check for min expr support on target
* Misc (1/10)
- Conference calls
* Holiday (2/10)
== Next week ==
- Complete TCWG-77 and send upstream
- Continued investigation into TCWG-316
== This week ==
* TCWG-80 (1/10)
- PRE and dead-store elimination ipa pass (WIP upstream) already
handles optimization
* TCWG-120 (2/10)
- Investigating 3 possible approaches:
a) fold arm_andsi3_insn/arm_cmpsi_insn to
zeroextractsi_compare0_scratch/andsi3_compare0_scratch
b) Undo cse in test conditions, and modify arm_rtx_costs to fold
arm_andsi3_insn/arm_cmpsi_insn to
zeroextractsi_compare0_scratch/andsi3_compare0_scratch
c) Expand directly to zeroextractsi_compare0_scratch/andsi3_compare0_scratch
- Not sure whether the generated assembly is better (in terms of
speed) than with trunk.
asm diff at -O1: http://pastebin.com/yXBHHkhM
* TCWG-72 (2/10)
- Rebased Kugan's patch
* TCWG-299 (3/10)
- Simple workaround for PR65837 - configure gcc with --with-fpu=neon
- Firefox trunk doesn't build with gcc for arm, using apt-get source firefox
- LTO build fails with out-of-memory on my laptop in qemu-arm chroot
* TCWG-319 (1/10)
- Benchmarking setup with Bernie on Juno for running SPEC.
- SPEC Runs without error on Juno-{a53,a57} and APM
* Misc (1/10)
- Meetings
== Next Week ==
- Continue with TCWG-120, TCWG-72, TCWG-319
Hi!
The pre-built version of the stable version of Linaro Toolchain (Linaro
GDB 2015.02-3) for Windows is shipped with GDB 7.8-2014.09-1-git. GDB
was built with the following options:
(gdb) show configuration
This GDB was configured as follows:
configure --host=i686-w64-mingw32 --target=arm-linux-gnueabihf
--with-auto-load-dir=$debugdir:$datadir/auto-load
--with-auto-load-safe-path=$debugdir:$datadir/auto-load
--without-expat
--with-gdb-datadir=/home/buildslave/workspace/BinaryRelease/label/hetzner/target/arm-linux-gnueabihf/_build/builds/destdir/i686-w64-mingw32/share/gdb
(relocatable)
--with-jit-reader-dir=/home/buildslave/workspace/BinaryRelease/label/hetzner/target/arm-linux-gnueabihf/_build/builds/destdir/i686-w64-mingw32/lib/gdb
(relocatable)
--without-libunwind-ia64
--without-lzma
--without-guile
--with-separate-debug-dir=/home/buildslave/workspace/BinaryRelease/label/hetzner/target/arm-linux-gnueabihf/_build/builds/destdir/i686-w64-mingw32/lib/debug
(relocatable)
--without-zlib
--without-babeltrace
As you can see in the output GDB was built without expat support. This
is a major problem for widely used micro controllers like ARM Cortex A8
(e.g. used in Beaglebone Black), because the technical description of
this microcontroller is loaded out of xml files (arm-with-neon.xml part
of GDB). It's also possible to do that manually with "set tdesc filename
<xml-file>, before connecting to the target.
Without having the expat option enabled the g package, which is sent
from gdbserver during establishing a connection to gdb, can't be parsed
correctly. The result is in the first step a warning because of the
missing xml support and later on a error regarding the unexpected
content of the g package:
warning: Can not parse XML target description; XML support was disabled
at compile time
Remote 'g' packet reply is too long:
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0fcffbe00000000407afdb6300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Old GDB versions of Linaro Toolchain like 7.6.1-2013.10 doesn't have
that problem because they were compiled with enabled expat support.
In my opinion there can be two root causes regarding that missing expat
support:
a) Expat support was explicitly disabled with --without-expat option
during the built of GDB.
b) On the build machine there wasn't a expat library available when gdb
was built.
Best regards,
Andreas Schmidl
== Progress ==
* Libraries (1/10)
- Working on getting the libc++ tests green
* Maintenance (6/10)
- Working with Vinicius on the gnueabi memcpy issue
- More TargetTuple/TargetParser discussions
- More sanitizers discussions, patch reviews
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- Connect stuff
== Plan ==
* Look a bit more on the library issues, try to upstream the bot changes
* Check instability in SciMark2
* Change HD from a D01
* Continue discussion about the sanitizer's multiple VMA problem
* Prepare for Connect, travel arrangements, etc.
# Progress #
* TCWG-857, [7/10]
One patch is upstreamed. The rest of them are in the queue.
Upgrade juno board linux kernel to 4.2.0-rc4+ to test some
multi-arch kernel patches. It isn't easy to run that new kernel
on juno board, takes much time on this.
* Misc [3/10]. Meetings, online trainings, etc.
# Plan #
* Continue to upstream multi-arch patches.
* Some upstream patch reviews on tracepoint.
--
Yao
Hello guys,
I am newbie here and need your kindly help:)
When trying to use gcc-linaro-4.9 to build u-boot for ls1021atwr (ARM Cortex-A7 MPCore compliant with ARMv7-A architecture), we face issue. U-boot hangs at PCI-E.
After tracing the code, the issue is located at the line "*val = readl(addr);".
u-boot/drivers/pci/pcie_layerscape.c: ls_pcie_read_config():
if (PCI_BUS(d) == hose->first_busno) {
...
} else {
...
if (PCI_BUS(d) == hose->first_busno + 1) { #PCI_BUS(d) 1, hose->first_busno 0
ls_pcie_cfg0_set_busdev(pcie, busdev);
addr = pcie->va_cfg0 + (where & ~0x3); #pcie->va_cfg0 0x24000000, where 0xc
} else {
....
}
}
*val = readl(addr);
The gcc source we used is gcc-linaro-4.9-2015.02.tar.xz<https://releases.linaro.org/15.02/components/toolchain/gcc-linaro/4.9/gcc-l…> (link<https://releases.linaro.org/15.02/components/toolchain/gcc-linaro/4.9/>) which is based on FSF GCC 4.9.3-pre+svn220525.
Meanwhile, gcc-linaro-4.9-2015.01.tar.xz<https://releases.linaro.org/15.02/components/toolchain/gcc-linaro/4.9/gcc-l…> does not have this issue.
After Bisecting, we tracked down a gcc commit:
https://git.linaro.org/toolchain/gcc.git/commitdiff/e4f9e85e8152379aef37377…
2015-01-23 Jakub Jelinek <jakub(a)redhat.com>
PR rtl-optimization/63637
PR rtl-optimization/60663
* cse.c (merge_equiv_classes): Set new_elt->cost to MAX_COST
if elt->cost is MAX_COST for ASM_OPERANDS.
(find_sets_in_insn): Fix up comment typo.
(cse_insn): Don't set src_volatile for all non-volatile
ASM_OPERANDS in PARALLELs, but just those with multiple outputs
or with "memory" clobber. Set elt->cost to MAX_COST
for ASM_OPERANDS in PARALLEL. Set src_elt->cost to MAX_COST
if new_src is ASM_OPERANDS and elt->cost is MAX_COST.
* gcc.dg/pr63637-1.c: New test.
* gcc.dg/pr63637-2.c: New test.
* gcc.dg/pr63637-3.c: New test.
* gcc.dg/pr63637-4.c: New test.
* gcc.dg/pr63637-5.c: New test.
* gcc.dg/pr63637-6.c: New test.
* gcc.target/i386/pr63637-1.c: New test.
* gcc.target/i386/pr63637-2.c: New test.
* gcc.target/i386/pr63637-3.c: New test.
* gcc.target/i386/pr63637-4.c: New test.
* gcc.target/i386/pr63637-5.c: New test.
* gcc.target/i386/pr63637-6.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@220323 138bc75d<https://git.linaro.org/toolchain/gcc.git/object/138bc75d>-0d04-0410-961f-82ee72b054a4<https://git.linaro.org/toolchain/gcc.git/object/82ee72b054a4>
Before this commit, u-boot can boot up.
So any hint/suggestion? if more details needed, please feel free to tell us.
Thank you in advance.
-Ting
== Progress ==
LLDB development
-- Testing and bug fixing lldb on hikey AArch64 [TCWG-231] [4/10]
-- Looking into multi-threaded watchpoint test failures on
AArch64 highkey board.
-- Fixed watchpoint installation lag and unexpected behaviour.
Submitted http://reviews.llvm.org/D12522
-- Start work to add support for un-alinged watchpoints on AArch64
[TCWG-367] [3/10]
Miscellaneous [3/10]
-- Meetings, emails, discussions etc.
-- Laptop LCD screen malfunctioned, found a temporary replacement.
== Plan ==
LLDB development
-- Progress towards un-allinged watchpoint support on AArch64 LLDB
-- Fix broken parts of LLDB testsuite on AArch64.
== Progress ==
o Linaro GCC validation (8/10)
* Reviewed, validated and committed more backports
* New stability issues after executor number increased
* Started to script branch merge
* Developed a new tool to avoid wasting time in gerrit/jenkins/logs
navigation
o Upstream GCC (1/10)
* Looked at and updated some bugzillas
o Misc (1/10)
* Various meetings
== Plan ==
o Continue backports/validation/branch merge
== Progress ==
* Widening pass (TCWG-547) – 6/10
- Looked at “Error: unaligned opcodes detected in executable segment”
* Spent lot of time trying to understand the root cause.
* Got some suggestions from Jim and looking into it.
- Posted some of the important patches for review.
* https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00399.html
* https://bugs.linaro.org/show_bug.cgi?id=1318 (2/10)
- Tried reproducing with the source provided without success.
- Could build and reproduce with emacs-24.4 release.
- Trunk GCC version 6.0.0 20150902 works.
- GCC version 4.9.3 20150209 (Linaro GCC 4.9-2015.02) fails.
* Misc - 2/10
- gcc-patches, gcc-bugs list
== Plan ==
* Continue with widening pass
* Fix Bug1318
Holiday [4/10]
Multinode wrapper - TCWG-350 [2/10]
* Merged to benchmarking branch, roughly documented
* Tested & added job definition templates
Setting up VPN [2/10]
* Much struggling with mutt, pgp, VM vs real system, Mac vs Linux
* Still not working, but wrote up what I've learned on the Collaborate page
Misc [2/10]
* ARM admin, meetings, mail, etc etc
=Plan=
Last pass through benchmarking presentation
Finish multinode/updating benchmarking docs
Back to Juno noise control experiments
Back to Jenkins - get it to drive multinode
(Reporting with new Jira numbers)
Holiday [6/10]
Investigate effectiveness of noise control - TCWG-358 [2/10]
* Learned to build OE filesystems
* Got Juno running with more or less provenance-tracked firmware,
kernel, filesystem
Misc - [2/10]
* Pushed through some updates to benchmark sources
* Struggled with Collaborate permissions to share source/results handling rules
* Remaining multinode tests passed
== This week ==
* TCWG-832 -Exploit vector multiply by scalar instructions when multiple
scalars are used as
coefficients in a loop (4/10)
- Continued investigation.
* TCWG-833 - Exploit Wide Add operations when appropriate (4/10)
- Reworked Aarch64 patch to avoid redundant moves
- Sent patch upstream for review
- Debugging Aarch64 tree-dump regression suite failures
- Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10)
- Separated patch from Bugzilla 67321 patch and sent upstream
- Pinged upstream for comments
* Misc (1/10)
- Conference calls
== Next week ==
- USA Labor day holiday, September 7th
- Additional investigation into TCWG-832
== This Week ==
* TCWG-120 (8/10)
- Resolved df issue in my patch, sent to tcwg list for review,
- VRP makes the issue latent at -O2. Reproducible with -fno-tree-vrp
- Taking another approach to run a "specialized" combine pass before
combine pass that
folds arm_andsi3_insn/arm_cmpsi_insn to zeroextracsi_compare0_scratch
or andsi3_compare0_scratch without relying on combine.
Patch: http://pastebin.com/gLVg7pbN
Asm diff at -O1: http://pastebin.com/yXBHHkhM
Asm diff at -O2 -fno-tree-vrp: http://pastebin.com/EKj6hXkt
* Misc (2/10)
- Meetings
- Had a look at vect test-cases failing due to LTO
== Issues ==
- No access to Juno
- Can't login to IRC via ZNC (can connect directly).
== Next Week ==
- Continue with TCWG-120
- Start looking at TCWG-80
== Progress ==
* Holidays (4/10)
* Buildbots (2/10)
- Several breakages, Clang alignment issue sill breaking
self-hosted bots...
* Maintenance (2/10)
- Backtracks on the TargetParser, code heavily modified,
discussions ensued.
- Helping Vinicius with __aeabi_memcpy in the kernel
* Releases (0/10)
- Release 3.7.0 final validated / uploaded
- Waiting for final switch
* Background (2/10)
- Code review, meetings, discussions, etc.
- Backlog of emails, reviews
== Plan ==
Look at libc++ / RT / unwind again see if I can reduce the errors in
both AArch64 and ARM to zero.
== Issues ==
The power cuts and the effect it had on my buildbots made me spend 3
days of my holidays to fix. Other buildbot breakages made me spend
another 2, and I couldn't wait until I was back, or it would have
wasted an entire week (as it has happened before).
In a nutshell, I can't have holidays. Yay!
# Progress #
* Holiday on Monday [2/10]
* TCWG-857, [4/10]. All the multi-arch work are done
(I hope) but patches can't be sent out until kernel patches
are pushed in upstream.
** Collect some arguments from kernel folks to defend my change
"32-bit CPSR to 64-bit PSTATE". Patch is posted out.
** Finish the patch to convert siginfo_t between 32-bit debuggee
and 64-bit debugger. Done. Will post it next week.
** Get right TLS base in multi-arch debugging. Patch is done.
* Happen to see we can improve GDB performance in some case by
avoid sending some packets. Patch is done, but need to collect
some performance data. [2/10]
* Misc [1/10]
** Close some tickets, TCWG-567, TCWG-876, as they are done.
* TCWG-757 [1/10], many patches review.
# Plan #
* Continue to upstream multi-arch patches.
* Upgrade my juno board kernel to git master to test kernel patches
for multi-arch debugging work properly.
* Collect some GDB performance data for my patch.
--
Yao
Hi-
It seems that there is some discrepancy between Linaro GCC 4.8 2015.06 and Linaro GCC 4.8 2014.11 with regards to precompiled headers.
It appears that 2015.06 doesn't even attempt to open the precompiled headers according to strace. I have been looking on gcc mailing list but have not been able to find any fixes related to precompiled headers.
Does anyone have any pointers as to what should I be looking at to get to the bottom of this issue?
This simple program compiles without any problems on 2014.11, but fails on 2015.06 because 2015.06 doesn't even attempt to read tst.h.gch created by "make header"
dragans@tst:~$ cat Makefile
PROJ=tst
CC=arm-linux-gcc
LD=arm-linux-ld
all: header $(PROJ)
header: $(PROJ)._
cp $(PROJ)._ $(PROJ).h
$(CC) -x c-header -c $(PROJ).h
$(PROJ):
$(RM) $(PROJ).h
$(CC) $(PROJ).c -o $(PROJ)
clean:
$(RM) $(PROJ).h.gch $(PROJ).h $(PROJ)
dragans@tst:~$ cat tst._
#include <stdio.h>
dragans@tst:~$ cat tst.c
#include "tst.h"
int main(int argc, char**argv)
{
char *s = "Test";
printf("%s\n", s);
return 0;
}
== Progress ==
LLDB development
-- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [7/10]
-- Improve error handling of AArch64 watchpoint code. Submitted,
got reviewed and committed http://reviews.llvm.org/D12328
-- Looked into ways to improve watchpoint installation lag.
-- Looked into issues pertaining to un-alligned watchpoints installation.
-- Committed upstream arm hardware breakpoint and watchpoint support
[TCWG-770] [TCWG-794] [1/10]
-- Ran lldb testsuite in various combinations to figure out Arm and
AArch64 status [1/10]
-- Testing on chromebook with precise chroot works.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Try to find ways to debug lldb-server platform forked gdbserver instance.
-- Test, debug and fix testsuite failures on Arm and AArch64.
== Progress ==
LLDB development
-- Testing and bug fixing lldb on hikey AArch64 [TCWG-886] [2/10]
-- Looked into watchpoint tests which are still failing after
committing watchpoint support and bug fixes.
-- Modifications to arm hardware breakpoint and watchpoint support
[TCWG-770] [TCWG-794] [7/10]
-- Resubmitted the pending patch http://reviews.llvm.org/D9703
-- Testing on chromebook with precise chroot works.
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
-- Looking into slow data transfer issues on chromebook and highkey board
== Plan ==
LLDB development
-- Get patches reviewed and committ them.
-- Continue looking into tests which are still failing on Arm and AArch64
-- Run test comparison between linux x86, android arm and linux arm
o 3 days off (6/10)
== Progress ==
o Linaro GCC validation (3/10)
* Reviewed, validated and committed on-going backports
* backported more revisions
o Misc (1/10)
* Various meetings
== Plan ==
o Continue backports/validation
== Progress ==
* Annual Leave (2/10)
* Widening pass (TCWG-547) - 6/10
- Fixed all execution test failure.
- bootstrap failure due to “Drop copy-rename” is still not resolved.
Found a workaround.
- Sorted debug_stmt handling
* TACT 1/10
- Started looking to cross execution set-up
* Misc - 1/10
- gcc-patches, gcc-bugs list
== Plan ==
* Continue with widening pass
== This Week ==
* TCWG-777 (3/10)
- Fixed ICE with the patch - toolchain builds with the patch.
- Sent patch to tcwg list for review
- Investigating why combine fails to combine
arm_andsi3_insn/arm_cmpsi_insn into zeroextractsi_compare0_scratch
when the pass uses ud-chains to find def but works
when def is found using ad-hoc way.
* TCWG-871 (4/10)
- Getting familiar with firefox build system
- LTO build lto/non-lto on x86 and arm (doc)
- Figuring out how to resolve "plugin needed to handle lto object" error.
tried the following:
binutils configured with: --enable-plugin, --enable-lto
gcc configured with: --enable-lto --with-ld-plugin=<just built ld>
Doesn't appear to work.
* TCWG-835 (1/10)
- Build failure with spec (PR67399)
* Misc (2/10)
- Meetings
- Looked at rtl dataflow (df.h and df*.c) and ree.c
== Next Week ==
Continue with TCWG-777, TCWG-835, TCWG-871
== This week ==
* TCWG-832 -Exploit vector multiply by scalar instructions when multiple
scalars are used as
coefficients in a loop (2/10)
- Initial investigation.
* TCWG-833 - Exploit Wide Add operations when appropriate (4/10)
- Ramana is reviewing Aarch32 patch
- Recoded Aarch64 support to use vect_select
- Debugging Aarch64 lto, tree-dump regression suite failures
* TCWG-834 - Use non-unit stride loads by preference when applicable (1/10)
- TCWG 834 is Bugzilla 67323 upstream; Richard Biener took ownership
as a vectorizer failure
- My plan was to write a test case that failed until fixed, but
Richard indicated this is not
standard practice
- Bugzilla 57195 (mode iterator bug) blocked compiling new pattern (1/10)
- Separated patch from Bugzilla 67321 patch and sent upstream
- Pinged upstream for comments
- Bugzilla 67320 - Incorrect standard names for wide addition (1/10)
- committed upstream in trunk
* Misc (1/10)
- Conference calls
== Next week ==
- Resolve Aarch64 TCWG-833 patch, validate and upstream
- Additional investigation into TCWG-832