== Progress ==
Benchmarking 2015.02 [2/10]
. it turns out to be difficult to build previous releases with abe.sh
(bz#776, bz#1307)
. submitted patch to gerrit to improve abe.sh error handling
. benchmarks started on Jenkins
Backports [4/10]
. investigating incorrect merge discovered in review
. resolved... then found more conflicts with other backports
. need to redo backports
bug #1254 [1/10]
. reduced
. started investigating
misc [1/10]
. mailing lists
. meetings
== Plan ==
redo backports of 217440, 217885
start backports of 218021, 218534
bug#1254
vectorization investigation
look at benchmarking results from Jenkins
# Progress #
* aarch64 gdb , TCWG-652, [6/10]
** TCWG-662: Fixed and committed (by Pedro).
** TCWG-660: Rebuild toolchain with ABE.
** TCWG-663: Root cause of fails are known, that test case sets HW
breakpoint on arbitrary address while aarch64 HW breakpoint requires
4-byte align. ARM has the similar HW breakpoint feature, need to
to check on arm target too.
* fsf gdb patch review [2/10]
** Review and approve one patch from IBM which fixes TCWG-669 too.
** Discuss on re-org for syscall catchpoint for different target/arch.
* misc [2/10]
** Meeting.
** Move to the new house.
# Issues #
* Need an ARM board with HW breakpoint support in kernel. I tried
32-bit system on my juno board via schroot, but
PTRACE_SETHBPREGS doesn't work properly.
# Plan #
* TCWG-660: Teach ABE to import systemtap and build glibc with
--enable-systemtap.
* TCWG-663: See how the tests behave on ARM if ARM board is available.
* Other cards under TCWG-652.
--
Yao
== Progress ==
* Validation: (2/10)
- reached a state where Jenkins "green" actually means no regression found
- submitted patches for review
- confirmed that ABE master branch produces results similar to merge branch
- stopped checking the accuracy of report.sh since a few bugzilla
had been submitted, using ST script instead
* Backports (3/10)
- reviews are getting difficult, with lots of conflicts as the 4.9
branch has diverged from trunk quite a lot
* Sanitizers (1/10)
- trying to build LLVM+run the ASAN tests on AArch32
- tried to reconfigure my Hikey 96board with a 42 VA bits enabled
kernel, but it didn't boot: I still don't have access to such a
platform
* GCC FSF trunk/4.9 monitoring
- stopped tracking random "Interrupted system call"
- builds and validations now run faster, but with more frequent such errors
* Misc (4/10)
- meetings, conf-calls, emails, ...
- Release/maintenance branches policy, respin criteria, validation matrix
== Next ==
* Backports: reviews, and improve review-tool
* Sanitizers
Hi,
I have being trying to persuade gcc to generate the ldp instruction without success. I have tried many combinations, below is an example.
--- cut here ---
#define LDP(x,y,p) { \
struct vec { long x, y; } data; \
data = *(struct vec *)p; p += 2; \
x = data.x; y = data.y; \
}
long testp(long *p) {
long x, y;
LDP(x, y, p);
return x+y;
}
--- cut here ---
$ gcc --version
gcc (GCC) 4.9.1
Copyright (C) 2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ gcc -S -O3 ldp.c
$ cat ldp.s
.cpu generic+fp+simd
.file "ldp.c"
.text
.align 2
.global testp
.type testp, %function
testp:
ldr x1, [x0,8] ;; why not ldp?????
ldr x0, [x0]
add x0, x1, x0
ret
.size testp, .-testp
.ident "GCC: (GNU) 4.9.1"
What can I do do make it generate ldp?
Ed.
== Progress ==
Bug triage [2/10]
Bug 1199 analysis [4/10]
reproduced, studied IRA dumps for a while, will have to report this upstream
Backports + BackFLiP enhancement [3/10]
Misc [1/10]
meetings, git training presentation, mailing lists
== Plans ==
benchmark 2015.02 release
more bugs
== Progress ==
LLDB development
-- Some code sniffing and created JIRA cards with some task estimation [2/10]
-- Trying AArch64 cross build and update howto [1/10]
-- Trying Arm cross build and update howto [2/10]
GDB patch updates and test cases for ARM record-replay instruction
recording [4/10]
Miscellaneous [1/10]
-- 96board with custom kernel no success with getting ethernet
working on it yet
== Plan ==
Wind up all pending gdb patches
== Issue ==
* none
== Progress ==
* Release and Backports (6/10)
- Supported backporting activity
- Added new feature to Backflip
- Discussed redefinition of release/maintenance policy
* Misc (4/10)
- Various meetings
- Catch up with mails
- Updated GCC release process in collaborate
- HiKey
== Plan ==
* Release and backport support
== This week ==
Short week - 3 days. Took Sat, Sun off due to health issues, severe
ear infection -:(
* Modularization project
a) TCWG-637: Applied TLC to parser in include-remove tool
b) TCWG-621: Began refactoring rtl.h
c) TCWG-628.
* TCWG-619:
- Started going through LTO documentation.
* Bugs
1178: Found a possible fix, prevents the ICE for the test-case.
== Next week ==
* TCWG-619
* Submit fix to 1178 upstream
* TCWG-628
== This week ==
* GCC Modularization project
- TCWG-621: Refactoring rtl.h almost completed.
- TCWG-639: Working on rewriting the tool in python.
- TCWG-637: Working on basing the tool on rtags instead of ctags.
- TCWG-629: Continue target-hook conversion.
* Backports:
- Submitted following backports for review:
r215612, r215722, r219656, r219657, r219659, r219661
== Issues ==
- Building chromium dependencies.
- Cannot log in to NX session on tcwg-env-05.
== Next Week ==
- Chromium LTO build (TCWG-619)
- Validate and commit backports.
== Progress ==
* compiler-pass to widen computation (TCWG-547) - (7/10)
- ran into -std=gnu90 issue in compiling spec2k/2006 with the trunk
using the new infrastructure
- ran benchmarking but the results are not much different
- tried with -save-temps but the intermediates are gone. Not sure if
infrastructure cleans it
- setting up spec2k in nx aarch64 chroot for easy comparison of
intermediate values (asm and tree dumps)
- also plan to try benchmarking with widening pass enabled only for
unsigned type where BIT_AND_EXPR (zero_extend) is optimized well as
compared to new middle-end ZEXT_EXPR (which is not handled well yet) to
see if the difference is there.
* Improve register allocation for AArch64 (TCWG-620) - (1/10)
- Looked at the relevant patches and code
* https://bugs.linaro.org/show_bug.cgi?id=1291 (1/10)
* Misc (1/10)
== Plan ==
* TCWG-620 and TCWG-547
* https://bugs.linaro.org/show_bug.cgi?id=1291
* TSAN support for Aarch64 (5/10)
TCWG-642
Discussed on making -pie for -fsanitize=thread as default in GCC.
Learnt that LLVM sanitizers now support both -pie and non -pie mode.
Discussed the same issue with sanitizer's group. They asked me to
do -pie for aarch64 as first version. Pushed GCC changes to
linaro git.
TCWG-654
Discussed with Renato, moved to LLVM tree and woking on that.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64946.
TCWG-634
Ran ASAN tests which 32 bit allocator code now as default on amd-01.
/home/venkataramanan.kumar/LLVM/TSAN_port/Source/projects/compiler-
rt/lib/sanitizer_common/sanitizer_allocator.h:841
((res)) < ((kNumPossibleRegions)) (4193146, 524288)
I got similar error in TSAN and it went off when I switched to 64
bit allocator.
* Bug 869 - Wrote a pattern in match.pd to remove type promotion in
ABS_EXPR . Richard Beiner suggested to add ABSU_EXPR to take care of
signed overflows (3/10)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64946
* Emails, meetings. (2/10)
* Linaro 1-1 with christophe, maxim and Ryan.
* AMD meetings/event, 1-1 with AMD manager, status meeting.
* GCC mailing list.
== Plan ==
* TSAN/ASAN support look if 64 allocator is needed or not .
* LLVM build with local patches.
* Bug869.
* Misc and Meetings (AMD, LInaro)
== Progress ==
* Releases (CARD-1431 2/10)
- Spinning RC4, final, all green
* Buildbots (CARD-1823 1/10)
- Adding new quick Thumb2 non-NEON bot
- Adding new full self-hosting Thumb2 bot
* Libraries (CARD-1831 1/10)
- Trying to build a soft-float compiler-rt test-suite
* Sanitizers for AArch32/64 (CARD-1753 4/10)
- Investigating/fixing broken sanitizer bots (4 failures)
- Investigating other sanitizer failures on Junos
- More planning on TSAN, ASAN
* Background (2/10)
- Code review, meetings, discussions, etc.
- Reviewing the remaining EuroLLVM papers
- More LLDB planning
== Plan ==
* LLDB meeting with Google
* EuroLLVM final paper review meeting
* Continue building test-suite with Compiler-RT, libc++
* Continue help on ASAN/TSAN
* Try our first sprint planning...
# Progress #
* aarch64 gdb, TCWG-652, [5/10]
** TCWG-653: triage fails in aarch64-linux gdb testing, both native and
remote. Nearly done.
** TCWG-670: Clean up GDB testsuite for syscall catchpoint first.
Ongoing.
** TCWG-672: GDB can't unwind from glibc with the expected function name
if glibc is stripped. Nearly done.
** Committed two patches upstream fixing two fails on aarch64-linux
target.
** Clean up arm and aarch64 bug reports on sourceware.org bugzilla.
* fsf gdb patch review [4/10]
** Reviewed Omair's two process record GDB patches.
** Reviewed one patch may cause fails on remote testing.
* misc [1/10]
** 1x1 with Ryan.
** With Bernard's help, set up ssh access to linaro servers.
# Plan #
* All cards under TCWG-652.
* Move out of temporary apartment to a rented one on Friday.
--
Yao
Go away where ? ABE just uses whatever triplet you give it. I commonly use just arm-linux-gnueabi for example. If you don't specify 'none', it shouldn't appear anywhere. If it does, let me know and I'll fix it.
- rob -
-------- Original message --------
From: Christopher Covington <cov(a)codeaurora.org>
Date: 02/26/2015 2:52 AM (GMT+07:00)
To: linaro-toolchain(a)lists.linaro.org
Subject: Debian Multiarch Tuple Style Naming With ABE
Hi,
I recently built with ABE for the first time. It's pretty slick.
Is there a way to make the vendor string (the "none" in
"arm-none-linux-gnueabihf-*") go away? It breaks my scripts without appearing
to add value.
Thanks,
Chris
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
linaro-toolchain mailing list
linaro-toolchain(a)lists.linaro.org
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Holiday Friday [2/10]
catomics - TCWG-436 [2/10]
* Fixed broken benchmark-against-sysroot code in scripts
* Built a lot of sysroots
Juno cache effects - LDTS-1238 [4/10]
* Quite a bit of reading and learning some more perf and other tools
* Formed a few hypothesis, started testing
* Looking promising, but I find these things often go wrong, so we'll see
Misc [2/10]
* Featuring first successful Jenkins run of all of SPEC2006
=Plan=
Make sure I've really fixed the last sysroot bug, actually run
benchmarks on catomics
Attempt to close out the cache effects issue
Carry on with Jenkins
Hi,
I recently built with ABE for the first time. It's pretty slick.
Is there a way to make the vendor string (the "none" in
"arm-none-linux-gnueabihf-*") go away? It breaks my scripts without appearing
to add value.
Thanks,
Chris
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi,
I am trying to port the Boost.Context library (from www.boost.org) to aarch64 gcc and have come across a gnarly problem.
Boost.Context essentially does co-routine style context switching. It has a structure f_context which it uses to save and restore contexts. The structure f_context contains both integer (x0..xN) and floating point VFP (d8..d15) context.
The function jump_context switches contexts
typedef struct f_context *f_context_t
extern void jump_context(fcontext_t *old, f_context_t new, bool save_fp);
So this jumps to a new context returning the old context in *old. If save_fp is set the floating point context must be saved because the application uses floating point. Otherwise the save and restore of the floating point context may be ignored.
So, essentially, to save the old context it does
jump_fcontext:
# prepare stack for GP + FPU
sub sp, sp, #0xb0
# test if fpu env should be preserved
cmp w3, #0
b.eq 1f
# save d8 - d15
stp d8, d9, [sp, #0x00]
stp d10, d11, [sp, #0x10]
stp d12, d13, [sp, #0x20]
stp d14, d15, [sp, #0x30]
1:
# save x19-x30
stp x19, x20, [sp, #0x40]
stp x21, x22, [sp, #0x50]
stp x23, x24, [sp, #0x60]
stp x25, x26, [sp, #0x70]
stp x27, x28, [sp, #0x80]
stp x29, x30, [sp, #0x90]
However, there is a problem with this because gcc may store integer value in floating point registers around a function call.
So, I have no way of knowing whether it is actually necessary to save/restore floating point context.
Even worse applications using Boost.Context may be completely borken if they assume it is safe to call jump_context with save_fp == 0.
Any suggestions?
Ed.
== This week ==
* Released Linaro 4.8 and 4.9 February 2015 release (2/10)
* Vector Extensions Project (7/10)
- Design work on C++ classes
- Reviewed Boost.simd as alternative implementation
- Review of libvpx benchmark
* Misc. (1/10)
- Conference calls
- ARM required online training
== Next week ==
- ARM CodeGen conference in Cambridge
--
Michael Collison
Linaro Toolchain Working Group
michael.collison(a)linaro.org
== Progress ==
LLDB development
-- LLDB Call graph analysis for understanding some development nits [1/10]
-- Trying out LLDB server arm and aarch64 cross compilation. [2/10]
-- List down arm-lldb task list with some debugging [2/10]
Miscellaneous [1/10]
-- 96board setup
Holiday [4/10]
-- Monday 16th and Tuesday 17th Feb 2015
== Plan ==
Convert LLDB Arm task list to JIRA cards
Try to fix LLDB server arm and aarch64 cross build issues.
Some GDB patch updates
Connect detox [2/10]
ABE benchmarking automation - TCWG-360 [5/10]
* Backport benchmarking
** Harder than expected, have to build the backport into a binary,
then benchmark that binary, passing information between jobs.
** AFAIK I'm blazing the Jenkins-chainging trail for us.
* Release benchmarking
** New LAVA release broke my image (but quickly fixed by the LAVA folks)
** Now seems to be running into issues with Jenkins/builders/an
anonymous job-slayer
* Misc fixes and improvements
** Main highlight being support for building with separated-out sysroot
Misc - [3/10]
=Plan=
Kick off catomics benchmark runs
(Attempt to) close out cache effects on Juno issue
Carry on with Jenkins
=Issues=
* Some of the Jenkins builders seem unreliable
* My lightly hacked version of the BinaryRelease job is unreliable
** Is the BinaryRelease job itself is reliable
* TSAN support for Aarch64 (5/10)
Fixed some kernel size issues in my local working tree. (TCWG-581) .
GCC does not default to -fPIE or -pie. Ran into address layout
issues when I used -fsanitize=thread. Some test cases passed with the
mapping I used for 42 bit VA when -pie and -fPIE are added.
* Bug 869 - Looking at match.pd to remove type promotion in ABS_EXPR (1/10)
* Emails, meetings. (2/10)
* Linaro 1-1 with maxim and Ryan.
* AMD meetings/event, 1-1 with AMD manager, status meeting.
* GCC mailing list.
Leave on 20-Feb-2015 (2/10)
== Plan ==
* TSAN support for Aarch64 work fixing GCC -fsanitize=thread option.
* Break tasks under TCWG-581.
* LLVM build with local patches.
* Bug869.
* Misc and Meetings (AMD, LInaro)
== Progress ==
* compiler-pass to widen computation (TCWG-547) - (5/10)
- Analysed core-mark code size regression
- fixed constant handling
- Added VRP support for ZEXT_EXPR
* Improve register allocation for AArch64 (TCWG-620) - (1/10)
- Looked at the relevant patches
* Misc (4/10)
- Setting up ABE benchmarking scripts
- Ran into some LAVA related issues for ABE benchmarking
- Recovering from connect
- Started with 69 board setup
== Plan ==
* TCWG-620 and TCWG-547
* ABE benchmarking
== Progress ==
* GCC trunk/4.9 monitoring
* Neon intrinsics tests
- committed the last patch of the 2nd series.
- about another 1/3 of the tests remain to be converted: will wait
for GCC stage1
* AArch64 sanitizers (2/10)
- Renato committed my patches to enable ASAN in LLVM/AArch64
- the official aarch64 buildbot (Juno) had problems after these, so
the asan tests are disabled again until the problem is understood.
Probable board configuration problem, since the tests passed on our
Juno.
- preparing a patch to solve the long standing issue with dependency
on aarch64 kernel version (kernel_old_[ug]id)
* Backports (4/10)
- reviews
- respawned validations under MergeFarm
* ABE:
- improving reporting
* Misc (4/10)
- meetings, conf-calls, emails, ....
== Next ==
Connect, then holidays
== Progress ==
* Rebooting brain after Connect (2/10)
* Friday off (2/10)
* Release 3.6 (CARD-1431 1/10)
- Spinning RC3, RC4
- Long discussions about Phoronix benchmark regressions
* Buildbots (CARD-1823 2/10)
- Buildbot cleanup and reshape
- Adding two new internal buildbots
- Investigating AArch64 broken bot
* Background (3/10)
- Code review, meetings, discussions, etc.
- Sprint planning
- Catching up on emails
- Servers purchase
- EuroLLVM paper reviews
== Plan ==
* Install new servers when they come
* Add the two new bots upstream
* Plan LLDB with Omair, contact Google
* Plan TSAN with Venkat
* Help Christophe investigate ASAN on AArch64
Holiday [3/10]
ABE benchmarking automation - TCWG-360 [3/10]
* Initial Jenkins implementation
Investigating cache effects on Juno - LDTS-1238 [2/10]
* One effect due to write streaming, others still to look at
Misc [2/10]
* Unpacking, some background catomics
Connect [10/10]
=Plan=
Carry on with Jenkins implementation
Run some benchmarks on catomics
Juno cache effects
Write up/think about where to go with libm exercising
ABE benchmarking automation - TCWG-360 [8/10]
* Pursued sneaky bugs through twisty mazes of bash
* Learned that ControlMaster does not play nice with my scripts
* Learned more about IPC pitfalls
* Cleaned up build behaviour of scripts somewhat
* Implemented support for benchmarking against sysroot (needed by Will
and by me)
* Generally tried to help Charles
* A bit of Jenkins testing
Misc [2/10]
* Featuring part 1 of an office move
=Plan=
Holiday Wednesday, 1/2 of Thursday
Part 2 of office move
Support benchmark users
Look more at cache effects on Juno
Get Jenkins working
Benchmark catomic patches (as much as I can without putting even more
pressure on the Junos)
Write up/think about where to go with libm exercising
Final preparation for Connect
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.02
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2015.02 is the eleventh Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.3-pre+svn220525 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include
* Backport of [AArch32] PR63676, exit tree fold when node be TREE_CLOBBER_P
* Backport of [AArch32] M0/M1 small multiply
* Backport of [AArch64] Fix unsafe access to deallocated stack
* Backport of Int div by constant compilation enhancement
* Backport of [AArch32] Fix PR target/64460: Set 'shift' attr properly on some patterns
* Backport of [AArch32] Fix typo in *<arith_shift_insn>_shiftsi
* Backport of [AArch64] Let LR register allocable
* Backport of Improve warning message for bitfields
* Backport of [AArch32] PR rtl-optimization/64011
* Backport of Fix checking on MAX_PENDING_LIST_LENGTH
* Backport of Remove VEC_LSHIFT_EXPR and vec_shl_optab
* Backport of [AArch64] Use new reduc_[us](min|max)_scal optabs, inc. for builtins
* Backport of [AArch64] Use new reduc_plus_scal optabs, inc. for __builtins
* Backport of Add new optabs for reducing vectors to scalars
* Backport of [Vectorizer] Make REDUC_xxx_EXPR tree codes produce a scalar result
* Backport of [AArch32] new cortex-m7 tune option
* Backport of [AArch32] cortex-m7 scheduling
* Backport of Improve Neon intrinsics testing
* Backport of [AArch32] [testsuite] gnu11 cleanup for aapcs testcases
Linaro GCC 4.8 2015.02 is the sixteenth release in the 4.8 series and is in
maintenance. Based off the latest GCC 4.8.4+svn220525 release, it includes
performance improvements and bug fixes.
The Linaro GCC 4.8 maintenance branch will be retired when Linaro GCC 5.1 is delivered.
Linaro GCC 4.9 will become the new maintenance release. Interesting changes in this GCC source
package release include:
* Updates to GCC 4.8.4+svn220525
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
--
Michael Collison
Linaro Toolchain Working Group
michael.collison(a)linaro.org
== This week ==
* Linaro 4.8 and 4.9 Releases (9/10)
- Validated backports, followed release process and staged tarballs
for release
* Misc (1/10)
- Conference calls
== Next week ==
- Backports
- Work on bug fixes
* TSAN support for Aarch64 (3/10)
Working on memory map layout for TSAN in Aarch64 (TCWG-581) .
Experimenting switching on 64 bit allocator as default.
* Bug 869 - Analyzing tree dumps on how VECT_CONVERT_EXPR works (2/10)
* Emails, meetings. (3/10)
* Linaro remote hack sessions.
* internal AMD meetings/event, 1-1 with AMD manager, .
* GCC mailing list.
Leave on 10-Feb-2015 (2/10)
== Plan ==
* TSAN support for Aarch64 work on memory layout.
* Bug869
* Review/Watch connect slides.
== This week ==
* Created dummy release in preparation for February Linaro release (2/10)
* Backports (2/10)
- Backported 216220 and 217229
- Additional merge issues indicates another backport is required.
- I will abandon the backports for this release.
* Bug fixing (5/10)
- Bug 535 - Could not reproduce after triage.
- Bug 539 - Additional triage.
* Misc (1/10)
- Conference calls
== Next week ==
- Commit validated backports and create release
== Progress ==
* AArch64 ILP32 toolchain (5/10)
- Got SPEC2k results for LP64 and ILP32
* Committed patch for AArch64 -Bsymbolic ld issue (1/10)
* Other stuff (2/10)
- Working on handing over various projects
- Email, meetings, etc.
* Friday travelling to Connect (2/10)
== Issues ==
* Juno boards have been busy
== Plan ==
* Connect
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Automation Framework (CARD-1378 1/10)
- Restarting build-02
- Trying new way to setup juno-01, failed
- Moving gateway-config to new private git server
* Release 3.6 (CARD-1431 4/10)
- Found NEON regression, reverting patches
- Setting up more new NEON buildbots
* Libraries (CARD-1831 1/10)
- Opening discussion on libunwinder move, getting consensus
* Background (2/10)
- Code review, meetings, discussions, etc.
- FOSDEM 2015 (http://llvm.org/devmtg/2015-02/)
* Flying to Connect (2/10)
== Issues ==
After working on Sunday and all nights since, I'll be off tomorrow and
will get ready to Connect on Friday. Email/HO/IRC as usual.
== Plan ==
Connect
* TSAN support for Aarch64 (5/10)
Working on memory map layout for TSAN in Aarch64 (TCWG-581) .
* Emails, meetings. (3/10)
* 1-1 with maxim, linaro status call.
* internal AMD meetings, 1-1 with AMD manager.
* GCC mailing list.
Leave on 26-Jan-2014 (India Holiday) (2/10)
Planned Leave on 04-Feb-2014
== Plan ==
* TSAN support for Aarch64 work on memory layout.
== This week ==
* Backports (10/10)
- 216734 - Temporarily remove aarch64_gimple_fold_builtin code for
reduction operations
- 216736 - [Vectorizer] Make REDUC_xxx_EXPR tree codes produce a
scalar result
- 216737 - Add new optabs for reducing vectors to scalars
- 216738 - Use new reduc_plus_scal optabs, inc. for __builtins
- 216741 - Use new reduc_[us](min|max)_scal optabs, inc. for builtins
- 216742 - Restore gimple_folding of reduction intrinsics
- 216779 - Remove VEC_LSHIFT_EXPR and vec_shl_optab
- 217331 - Fix checking on MAX_PENDING_LIST_LENGTH
- 217430 - Fix typo in *<arith_shift_insn>_shiftsi
- 217431 - Let LR register allocable
- 217533 - Pair load store instructions using a generic scheduling
fusion pass
- 219717 - PR rtl-optimization/64011
- 219718 - Improve warning message
== Next week ==
- Prepare for release by creating "dummy" release
- Work on bug fixes
Hi,
We've noticed that in the 14.11 toolchain binary release that the .asc files
contain md5sums instead of PGP signatures. Would it be possible to either
switch these files to contain signatures or change the filename to indicate
that they contain md5sums?
I also noticed that an md5sum is missing:
http://releases.linaro.org/14.11/components/toolchain/binaries/armeb-linux-…
Finally, there appears to be some inconsistent usage of tuples in the download
directories. Would it be possible to use the same tuple for a particular
toolchain everywhere that tuple is used? For example, for the arm-none-eabi
toolchain, the directory is "arm-none-eabi", but the compiler tarball has only
"arm-eabi".
Thanks,
Chris
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
== Progress ==
* Automation Framework (CARD-1378 1/10)
- Setting up new box
* Release 3.6 (CARD-1431 5/10)
- Looking for the patch that introduced a major NEON regression since December
* Background (4/10)
- Code review, meetings, discussions, etc.
- More Jira farming...
- Some EuroLLVM paper reviews
- LLVM/Android planning
== Plan ==
* Keep trying to find the bug in release 3.6
* Try to have some time to fix the NEON unwinder issue
* Preparing for Connect
== Issues ==
I cocked up the LLVM 3.6 ARM release last December when I
inadvertently ignored a bug report about clang not self-hosting on
NEON machines. To make matters worse, I was the one that decided to
move *all* our buildbots to non-NEON machines, expecting that the
test-suite on a Chromebook would catch all NEON problems.
There are limits to human intelligence, not human stupidity.
== Progress ==
* LLD (1/10, TCWG-561, TCWG-563, TCWG-570)
- Updated and added more cards, adding more detail and loose priorities
- Rebased, fixed up and resubmitted relocation test patch
* AArch64 ILP32 toolchain (4/10)
- Attempted various SPEC2k runs and fixed issues found
* Submitted patch for AArch64 -Bsymbolic ld issue (1/10)
* Connect slides (2/10)
* Other stuff (1/10)
- Email, meetings, etc.
* Tuesday looking after sick child
== Issues ==
* Juno access has been patchy
== Plan ==
* Get SPEC2k running ok on Juno and with ILP32
* Push remaining LLD patches
--
Will Newton
Toolchain Working Group, Linaro
Hello,
I have a question about the status of overo support in qemu-linaro vs upstream qemu; from a quick look on the Git commits for qemu-linaro, most things seemed to have been ported back upstream into qemu as of v2.0.0, although there does appear to be some recent new commits. However, I'm looking for overo board support, and although I see that OMAP3 chip support has been merged upstream, there aren't any board configuration files for overo. What would be the easiest way to get working qemu overo board support?
Additionally, I don't see any recent binary packages available for qemu-linaro. The qemu-linaro packages on the Ubuntu PPA haven't been built for almost a year now, and the releases.linaro.org page doesn't seem to have recent qemu-linaro builds either.
Thanks,
Dominic
