The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.12
release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.12 is the ninth Linaro GCC source package release. It is
based on FSF GCC 4.9.3-pre+svn218412 and includes performance improvements and
bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly enginering[2] releases.
Interesting changes in this GCC source package release include
* Updates to GCC 4.9.3-pre+svn218412
* Backport of [AArch64] arm_neon.h - add vpaddd_f64, vpaddd_s64,
vpaddd_u64 intrinsics
* Backport of [AArch64] Move some code around in aarch64_expand_mov_immediate
* Backport of [AArch64] Improve codegen of vector compares inc. tst instruction
* Backport of [AArch64] Remove vector compare/tst __builtins
* Backport of [AArch64] Add execution tests of vget_low and vget_high
* Backport of [AArch64] Replace temporary inline assembler for vget_high
* Backport of [AArch64] PR 61749: Do not ICE in lane intrinsics when
passed non-constant lane number
* Backport of [AArch32] Disable xordi3-opt.c/iordi3-opt.c on thumb1 target
* Backport of [AArch64] Fix scan-assembler test false alarm on aarch64-linux-gnu
* Backport of [AArch64] Add test of vld[234]q? intrinsic
* Backport of [AArch64] Extend test of vld1+vst1 intrinsics to cover
more variants
* Backport of [AArch64] Add a test of vldN_dup intrinsics
* Backport of [AArch64] Add a test of the vldN_lane intrinsic
* Backport of [AArch64] Add a test of the vst[234](q?) intrinics
* Backport of [AArch64] Add execution test of vset(q?)_lane intrinsics.
* Backport of [AArch64] Add cost handling of CALLER_SAVE_REGS and POINTER_REGS
* Backport of [AArch64] Fix cost for Q register moves
* Backport of [AArch64] Add regmove_costs for Cortex-A57 and A53
* Backport of [AArch64] Add aarch64 to list of targets that support gold
* Backport of [testsuite] whole_vector_shift
* Backport of [testsuite] vect-reduc-or
* Backport of [testsuite] Fix race in libstdc++ testsuite
* Backport of [testsuite] update testcases for GNU11
* Backport of [testsuite] fix gcc-dg-prune glitch when filtering
"relocation truncation" error
* Backport of [testsuite] Update testcases for GNU11
* Backport of [testsuite] fix wrap_compile_flags
* Backport of Increase PARAM_MAX_COMPLETELY_PEELED_INSNS when branch is costly
* Backport of Add -mthunderx option
* Backport of Accept cortex-m7/fpv5-sp-16/fpv5-d16
* Backport of Remove unused variable and marco
* Backport of Target Legitimize Address
* Backport of Hookize and remove *_BY_PIECES_P
* Backport of Remove no-longer-needed fp-bit target macros.
* Backport of Fix CLZ_DEFINED_VALUE_AT_ZERO for vector modes
* Backport of ifcvt: Allow CC mode if HAVE_cbranchcc4
* Backport of Fix predicate and constraint mismatch in logical atomic operations
* Backport of Migrate to new reduc_plus_scal_optab
* Backport of Migrate to new reduc_[us](min|max)_scal_optab
* Backport of Change CORE_REGS in GENERAL_REGS
* Backport of Fix IRA ICE tmpdir-gcc-.dg-struct-layout-1/t028
* Backport of Fix IRA ICE tmpdir-gcc-.dg-struct-layout-1/t028 -addon
* Backport of PR target/63937 fix 216996
* Backport of PR rtl-optimization/63210 IRA
* Backport of PR 63173 fix vldX_dup
* Backport of PR 63442 libgcc_cmp_return_mode not always return word_mode
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
Folks,
Me and Nick have been back and forth with the IFC6410, using Linaro's
utopic Ubuntu + 3.17 kernel, and I can now declare it stable enough to
run toolchain tests, maybe not yet builds.
The reason is that the kernel, although stable, is only just because
it throttles speed to a minimum. So, the core runs at 920MHz and the
memory bus is at its minimum frequency. Nick gathers we could speed it
up by a factor of 30% and 40% respectively while remaining on the
safety zone.
However, that would still be not enough. Currently, the boards build
LLVM in 7hs, when a Panda does it in 5h, a Chromebook does in 3.5hs
and a Chrome2 in 2hs. Improving it by 85% would get us just under 4hs,
which is still worse than a Chromebook. If we increase the CPU clock
to 1.5GHz per core, we may get it fast enough (but still slower than
the Chrome2), to be useful.
Their form-factor are better for rack-usage (remote serial, remote
reboot, small footprint), so even being slower than Chrome 2s, they'll
be faster than Chrome 1s and much more rack-friendly. That, of course,
assuming they remain stable at 1.5GHz. Heating will be an issue, but
we now have a decent server room and we can buy rack-mounted fans for
them, if we need it.
In a nutshell, I won't give up on them just yet, but I won't speed up
replacing the other boards with them either. We may have to wait a few
more releases to be sure, but I'm not expecting anything going in
production before February.
cheers,
--renato
PS: Nick, if you want to increase the clock speeds now just to see
what happens, I'm game.
Hi,
The latest toolchain on the following page appears to be broken.
http://www.linaro.org/projects/armv8/
Looking around one comes across the following path.
http://releases.linaro.org/latest/components/toolchain/.binaries
However the tarballs there yield: "You do not have permission to access this
file."
Thanks,
Chris
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
== Progress ==
QEMU kernel debugging setup [5/10] [TCWG-568]
-- Setup arm Linux kernel debugging to debug watchpoints
GDB with cygwin build/testing process [2/10]
-- Figured out GDB build and test procedure on cygwin.
Miscellaneous [3/10]
-- Meetings, Emails etc
-- Hong Kong visa application: re-submission of application.
== Plan ==
QEMU kernel debugging setup [TCWG-568]
-- Try to figure out kernel debugging help for ptrace debug
GDB with cygwin build/testing process
-- Document cygwin gdb work flow
-- Buid arm-remote gdb on cygwin
-- Identify gdb-remote issues on a cygwin host if any
== This week ==
* GCC modularization project
- Fixed df.h flattening patch to build on all targets in config-list.mk
- Flattening expr.h patch in progress.
== Next week ==
- complete expr.h patch
- Submit df.h flattening patch to gcc-patches for review
- Test cfgloop.h flattening patch on all targets with ISL enabledin
config-list.mk and submit to gcc-patches for review.
Holiday [6/10]
Misc [3/10]
* Mail backlog
* Moved all current AArch64 work off 'my' Juno, as ARM needed it back
* A little bit of a look at another possible memcpy performance issue
libm exercising - TCWG-558 [1/10]
* Reduced 'needless calls to pow' to a simple test case
** Found that this is actually an all-targets thing (at least AArch32,
AArch64, x86)
* Looked through benchfft output
** Looks like only one implementation calls libm much
** This is probably just bad code, but could do with a comparison run
on non-AArch64 to be sure
=Plan=
Switch to TCWG Junos
Think about where to go next with libm exercising
Complete 'same network' workaround, test benchmark repeatability
Port benchmarking scripts to ABE repo
Get storage/automation started, if Rob has time
=Absences=
On holiday Monday 22nd Dec to Friday 2nd Jan
== Progress ==
Bug#403/#418/PR63870 [7/10]
. Prepared patches for vldN_lane/vstN_lane
. reviewed related patches on list
. code changes are ready, but reveal errors in the testsuite
Misc [3/10]
. mailing llists
. meetings
. some help with lab config with Renato
= Progress ==
* TSAN support for Aarch64 (6/10)
* Emails, linaro/AMD status meetings. (4/10)
1-1 with maxim, Christophe.
== Plan ==
* TSAN support for Aarch64.
* Fix Linaro Bug 863
== This week ==
* GCC Modularization Project (9/10)
- Flattening header files
- tree-core.h, and tree.h, c-common.h
- Completed
- Bootstrap successful on x86
- Testing in progress on all platforms listed in config-list.mk
- Reviewed and tested patches from Prathamesh
* Misc (1/10)
- Conference calls
== Next week ==
- Submit tree.h and related patches for review
Hi all,
I've asked ITS to install a git post-commit hook to send an email
after commits in the toolchain git repos.
It turns out that they prefer to send such email to mailing-lists, to
avoid having to maintain the list of recipients themselves, which of
course really makes sense.
So far, we already have a cbuild2 mailing-list for commits, which Rob
asked to now point to abe instead of cbuild2 repo.
I was thinking about asking a single new mailing-list (eg
tcwg-commits) and send commit emails to that list for all ours repos,
instead of having a list per repo to which interested team members
would have to subscribe.
We currently have the following git repos:
abe
backflip
backport-tools
binutils-gdb
binutils
cbuild2
cortex-malloc
cortex-strings
cross-build-tools
dejagnu
dmucs
eglibc
fakebench
gcc-new
gcc
gdb
glibc
lavabench
newlib
release-notes
spec2xxx-utils
tcwg-sysadmin
Any objection to having such a list?
(I do not plan to force subscription of any of you :-)
Christophe.
== Progress ==
* Automation Framework (CARD-1378 5/8)
- Re-adding Junos and D01s to the rack
- Planning access from remote servers
- Following up new rack setup
- Moving lab bridge to a VM
- Re-checking all boards for stability
- Working on the dragon boards to get them stable
* Background (3/8)
- Code review, meetings, discussions, etc.
- Trying to get the LLVM Perf system back online
- Multiple bot breakages
- Reviewing patches for 3.5.1 release
- Jira farming
* 1 day off
== Plan ==
* Continue working on the dragon boards
* Try to get an internal ARM64 buildbot
* Hopefully finish off the lab move
== Progress ==
* GCC trunk/4.9 monitoring (2/10)
- still tracking cause of random "interrupted system call" errors
- checked possible regressions
* AArch64 sanitizers (1/10)
- managed to build on board, didn't try to run the tests yet
* Neon intrinsics tests (2/10)
- fixed a couple of bugs in the already upstreamed tests
- continued conversion to GCC testsuite
- support to external user (LLVM based compiler)
* 4.9-2014.12 release (1/10)
- backports+branch reviews
* Misc (4/10)
- meetings, conf-calls, emails....
== Next ==
* GCC trunk/4.9 monitoring
* AArch64 sanitizers
* Neon intrinsics tests
* cbuild2/abe: look at backport and tcwgweb
Holidays: Dec 22nd - Jan 2nd
Apology for sending this out late.
== Progress ==
Debugging ARM gdb watchpoint failures [4/10] [TCWG-567]
-- Prepared a testsuite patch for unsupported tests on ARM
-- Investigation of other failures due to watchpoints installation
rejected through ptrace interface.
QEMU kernel debugging setup [4/10] [TCWG-568]
-- Setup arm Linux kernel debugging to debug watchpoints
Studying arm debug unit architecture versions for possible upgrade to
watchpoint/hwbreak implementation. [1/5] [TCWG-569]
Miscellaneous [1/10]
-- Meetings, Emails etc
-- Follow up on Hong Kong Visa
== Plan ==
Figure out unexplained arm gdb watchpoint rejection from ptrace interface.
More work to figure out a way to debug arm Linux kernel using QEMU
Some further study on arm debug unit architecture versions.
== Progress ==
Holiday [1/10]
Investigated bug #928 [4/10]
. turns out to be invalid implementation of memset in old linux kernels
. raises a question - do we want to provide support for users of old
Linux kernels on new compilers? We could spend a long time rehashing
work the kernel community has already done.
bugs #403/418 [3/10]
. working on fixing error reporting for Aarch64 vldN_lane/vstN_lane
. trickier than expected, but have found a plan to implement this week
Misc [2/10]
== Plan ==
submit patch for #403/418 vldN_lane and work on more intrinsics
== Issues ==
* Validation unusable all week, seems to be operational now.
== Progress ==
* GCC 4.9 2014.12 (5/10)
- Struggle with backports validation,
- everything is in the pipe now ... wait and see
* Misc: (5/10)
- Scripted the GCC revisions management, now able
to track ARM related trunk contribution and fill the backport
spreadsheet, and will be able to generate the release notes.
- Various meetings.
== Plan ==
* Backports
* Branch merge
* Libunwind (AArch64_be review)
Back from Vacation 24, 26, 27 and 28 November. (8/10)
= Progress ==
* TSAN support for Aarch64 (1/10)
* Emails, linaro and AMD status meetings. (1/10)
1-1 with maxim
== Plan ==
* TSAN support for Aarch64.
* Fix Linaro Bug 863
* catchup emails and other discussions
== This week ==
* GCC Modularization Project
- created initial patch for flattening cfgloop.h.
- created initial patch for flattening df.h.
== Next Week ==
- Finalizing patches for cfgloop.h and df.h.
- Continue working on flattening header files.
== Progress ==
* Zero/sign extension elimination with widening types (1/10)
- Addressing comments from the review
* BUG #398 #412 (5/10)
- built kernel revision with provided config and toolchain binary
release to reproduce gcc segafult. Couldn’t reproduce it. Since there
is no more details to reproduce, closed it as cant reproduce.
- Spec2k gcc optimization issue was reproduced and reduced test-case
was created.
- dumps shows that this issue could be related to splitting constants
for early during expand might be the root cause.
* Holiday (4/10)
== Plan ==
* Continue with Zero/sign extension.
* BUG #412
== Planned Leave ==
* 11/12/2014 to 24/12/2014 - 10 days
== Progress ==
* 2 days sick
* Lab move (2/6)
* Buildbots (TCWG-76 2/6)
- Created a buildmaster at Linaro to help local development
- Put a dragonboard as a slave, which lasted 2 days up
* Background (2/6)
- Code review, meetings, discussions, etc.
== Plan ==
* I have no idea
== Progress ==
* Building an ILP32 toolchain for AArch64 (3/10, TCWG-559)
- More work on tidying patches
- Trying to get a test environment for ILP32
* LLD for ARM and AArch64 (5/10)
- Submit more reloc cleanups for LLVM
- Patch review
- Reading code
* glibc patch review (1/10, CARD-341)
* Email, meetings, etc. (1/10)
== Issues ==
* OE on Junos no good for building toolchains
* Ubuntu on Junos still seems vaporware
* Running out of disk space on development machine (bought an external HD)
== Plan ==
* More work on LLD
* Try QEMU for ILP32 work
--
Will Newton
Toolchain Working Group, Linaro
ABE benchmarking - TCWG-360 [4/10]
* Implemented most of a solution to the 'must be in same network' restriction
libm exercising - TCWG-558 [4/10]
* lulesh generates needless calls to pow on AArch64 (as opposed to
'pow is slow')
** Working on a reduced test case
* Ran a chunk of benchfft, left a process searching the perf reports
for libm calls
* More chroot/glibc fiddling
* Decided Graph500 was unlikely to be interesting
Misc - [2/10]
=Plan=
On holiday Monday - Wednesday
More lulesh, benchfft results
Think about where to go next with libm exercising
Complete 'same network' workaround, test benchmark repeatability
Port benchmarking scripts to ABE repo
Get storage/automation started, if Rob has time
Hi All,
Currently linaro toolchain for arm-linux-gnueabihf built with crosstool-ng scripts uses prebuilt sysroot.
I am trying to build eglibc on my own without using prebuilt sysroot. I am not able to exactly create same layout in the library layout.
Linaro build layout looks:
gcc-linaro-arm-linux-gnueabihf-4.8-2014.01_linux\arm-linux-gnueabihf\libc\usr\lib --> arm-linux-gnueabi arm-linux-gnueabihf
one for soft float and other for hard float fp. Can anybody please tell how we tell build system to create directories like above while building eglibc?
I used following commands to build eglibc:
../src_eglibc/configure --disable-profile --without-gd --without-cvs --prefix=/usr libc_cv_forced_unwind=yes libc_cv_c_cleanup=yes --with-headers=<some_dir>/arm-linux-gnueabihf/libc/usr/include --host=arm-linux-gnueabihf
Make all
make install install_root= <some_dir>/arm-linux-gnueabihf/libc/
Thank you very much for your help.
//Mallikarjuna
Forwarding this message to the linaro toolchain list instead. I am not the person who should be supporting the Linaro ODP project with GCC questiosn; the toolchain team inside Linaro should be instead.
Thanks,
Andrew Pinski
________________________________________
From: Ola Liljedahl <ola.liljedahl(a)linaro.org>
Sent: Monday, November 24, 2014 2:31 PM
To: lng-odp(a)lists.linaro.org; Pinski, Andrew
Subject: strange behavior in GCC for use of uninitialized variables
Consider the following code fragment (from real life):
#include <stdint.h>
typedef volatile uint32_t odp_atomic_u32_t;
static inline uint32_t odp_atomic_fetch_inc_u32(odp_atomic_u32_t *ptr)
{
return __sync_fetch_and_add(ptr, 1);
}
static inline void odp_spin(void)
{
#ifdef __SSE2__
__asm__ __volatile__ ("pause");
#else
__asm__ __volatile__ ("rep; nop");
#endif
}
typedef struct {
int count;
odp_atomic_u32_t bar;
} odp_barrier_t;
void odp_barrier_wait(odp_barrier_t *barrier)
{
uint32_t count;
int wasless;
// wasless = barrier->bar < barrier->count; <<<lost on git add -p
__atomic_thread_fence(__ATOMIC_SEQ_CST);
count = odp_atomic_fetch_inc_u32(&barrier->bar);
if (count == 2*barrier->count-1) {
barrier->bar = 0;
} else {
while ((barrier->bar < barrier->count) == wasless)
odp_spin();
}
__atomic_thread_fence(__ATOMIC_SEQ_CST);
}
While fixing and cleaning up this code, the indicated line that
initializes 'wasless' was dropped (because it reappears in a later
patch in the patch set after the odp_atomic_fetch_inc call). To my
surprise, GCC did not complain when compiling this file (using -O2
-Wall). But it does complain when compiling with -O0 -Wall. With some
investigation, it seems like GCC understands that if a statement does
not have any side effects so it can optimize away everything,
including the usage of the uninitialized variable and thus also the
corresponding warning.
olli@macmini:~/hacking/gcc-wunit$ gcc -O2 -Wall -c odp_barrier.c
olli@macmini:~/hacking/gcc-wunit$ gcc -O0 -Wall -c odp_barrier.c
odp_barrier.c: In function ‘odp_barrier_wait’:
odp_barrier.c:42:9: warning: ‘wasless’ may be used uninitialized in
this function [-Wmaybe-uninitialized]
while ((barrier->bar < barrier->count) == wasless)
^
However the proper code seems to be generated in both cases (there is
a "pause" instruction inlined or a call to odp_spin). So odp_spin() is
not without side effects and is not optimized away. This contradicts
my hypothesis.
Consider this minimalistic example:
olli@macmini:~/hacking/gcc-wunit$ cat wunit.c
#include <stdlib.h>
void test(void)
{
int wasless;
int wasmore;
if (wasless) (void)0;
if (wasmore) abort();
}
olli@macmini:~/hacking/gcc-wunit$ gcc -O0 -Wall -c wunit.c
wunit.c: In function ‘test’:
wunit.c:9:5: warning: ‘wasmore’ is used uninitialized in this function
[-Wuninitialized]
if (wasmore) abort();
^
olli@macmini:~/hacking/gcc-wunit$ gcc -O2 -Wall -c wunit.c
wunit.c: In function ‘test’:
wunit.c:9:5: warning: ‘wasmore’ is used uninitialized in this function
[-Wuninitialized]
if (wasmore) abort();
^
Here GCC warns when used with both -O0 and -O2 but only for the usage
where there is a side effect. The use of 'wasless' that does not lead
to any side-effects is ignored (and possibly rightly so, I can imagine
this is undefined behavior, fortunately I did not attempt to run this
program or my computer could have melted).
It is a bit worrying to me that instances of use of initialized
variables is sometimes missed by GCC. Both because of lack of
diagnostics for what is most likely a bug but also because I don't
understand why GCC does this and the implications of that (at least it
is a known unknown now).
-- Ola
cbuild2/ABE benchmarking - TCWG-360 [1/10]
* Attempted to use LAVA for benchmarks
** Fell over on lack of TCWG machines in same network
libm exercising - TCWG-558 [6/10]
* Much fiddling with chroots
* Some fiddling with benchfft
* Little actual progress
Meetings/mail/etc - [3/10]
=Plan=
libm exercising
* Run benchfft in chroots
* Investigate Graph500
* Validate existing results with consistent methodology
** Hopefully this is reaching the point of handle-turning
ABE benchmarking
* Port 'cbuild2' benchmarking to ABE repository
* Test ABE benchmarking in TCWG lab (and LAVA?)
* Test repeatability (assuming the above go well)
* Get storage/automation started, if Rob has time
Holiday *next* week (Tuesday and Wednesday, perhaps Monday as well)
== Progress ==
* Building an ILP32 toolchain for AArch64 (4/10, TCWG-559)
- Applied a few simple ILP32 patches to glibc
- Rebasing and reworking existing ILP32 glibc patches
* LLD for ARM and AArch64 (5/10)
- Submit first set of reloc cleanups for LLVM
* Email, meetings, etc. (1/10)
== Issues ==
* None
== Plan ==
* Submit more ILP32 patches for glibc
* Further LLVM/LLD changes
--
Will Newton
Toolchain Working Group, Linaro
The Linaro Toolchain and Platform Working Groups are pleased to
announce the 2013.07 release of the Linaro Toolchain Binaries, a
pre-built version of Linaro GCC and Linaro GDB that runs on generic
Linux or Windows and targets the glibc Linaro Evaluation Build.
Uses include:
* Cross compiling ARM applications from your laptop
* Remote debugging
* Build the Linux kernel for your board
What's included:
* Linaro GCC 4.8 2013.07-1
* Linaro Newlib 2.0 2013.06
* Linaro Binutils 2.23 2013.06
* Linaro Eglibc 2.17-2013.07-2
* Linaro GDB 7.6 2013.05
* A statically linked gdbserver
* A system root
* Manuals under share/doc/
The system root contains the basic header files and libraries to link
your programs against.
Interesting changes include:
* The sysroot is based on Linaro versions of Eglibc. About details of
Linaro Eglibc, please refer
https://releases.linaro.org/13.07/components/toolchain/eglibc-linaro.
The Linux version is supported on Ubuntu 10.04.3 and 12.04, Debian
6.0.2, Fedora 16, openSUSE 12.1, Red Hat Enterprise Linux Workstation
5.7 and later, and should run on any Linux Standard Base 3.0
compatible distribution. Please see the README about running on x86_64
hosts.
The Windows version is supported on Windows XP Pro SP3, Windows Vista
Business SP2, and Windows 7 Pro SP1.
The binaries and build scripts are available from:
https://launchpad.net/linaro-toolchain-binaries/trunk/2013.07
Need help? Ask a question on https://ask.linaro.org/
Already on Launchpad? Submit a bug at
https://bugs.launchpad.net/linaro-toolchain-binaries
On IRC? See us on #linaro on Freenode.
Other ways that you can contact us or get involved are listed at
https://wiki.linaro.org/GettingInvolved.
Know issues:
* Some version information in README are incorrect.
* gdb can not backtrace into libc.
Notes:
* To use all of the features of Linaro eglibc, the sysroot in 32-bit
toolchain release is updated to Linaro eglibc, which is 2.17. If you
get runtime errors about libc version, please get the sysroot from the
release tarball
(gcc-linaro-arm-linux-gnueabihf-4.8-2013.07-1_linux/arm-linux-gnueabihf/libc/)
or download from launchpad
https://launchpad.net/linaro-toolchain-binaries/support/01/+download/linaro…
If you do not want to use Linaro sysroot, you'd add option to gcc to
find your sysroot:
--sysroot=<directory>
* To run 32-bit application built from arm-linux-gnueabihf toolchain
in aarch64 system, you'd copy sysroot and runtime from release package
to your root of aarch64 system. i,e.
scp -r gcc-linaro-arm-linux-gnueabihf-4.8-2013.07-1_linux/arm-linux-gnueabihf/libc/*
AARCH64-SYSTEM:/
scp -r gcc-linaro-arm-linux-gnueabihf-4.8-2013.07-1_runtime/* AARCH64-SYSTEM:/
== Issues ==
* none.
== Progress ==
* GCC 4.9 2014.12 (2/10)
- Back on Backports.
- Around 30 revisions backported are under review.
* AArch64 libunwind/ptrace (6/10)
- Remote unwinding is not working because of a wrong ptrace invocation.
- Implement registers access with PTRACE_GETREGSET
* Misc: (2/10)
- GCC git mirror migration.
- Various meetings.
== Plan ==
* Backports
* Libunwind
== This week ==
* GCC Modularization Project (7/10)
- Flattening header files
- Submitted gimple-streamer.h, tree-streamer.h, lto-streamer.h
patches to gcc-patches list
- tree-core.h
- Several rounds of changes based on review and bootstraps
- final fifty target bootstrap in progress
- df.h
- Initial round of changes
- cfgloop.h
- Initial patch created by Parthamesh
* Bug fixing (2/10)
- Investigation of bug 539 - .LTHUNK symbols are surviving
* Misc (1/10)
- Conference calls
- Worked with Prathamesh to bootstrap him on GCC modularization project
== Next week ==
- Submit tree-core.h patches
- Complete df.h pathces
- Review Prathamesh's patches to cfgloop.h
- Thanksgiving holiday, November 27-28
== Progress ==
* Zero/sign extension elimination with widening types (2/10)
- Addressing comments from the review
* Improve block memory operations by GCC (TCWG-142 - 3/10)
-Looked at ARM vs AArch64
* BUG #880 (3/10)
- Analysed tree dumps.
- Updated bug report with the findings.
* MISC (2/10)
- Looked at git and stg documents
== Plan ==
* Continue with Zero/sign extension.
== Planned Leave ==
* 27/11/2014 to 28/11/2014 - 2 days
* 11/12/2014 to 24/12/2014 - 10 days
== Progress ==
Environment setup, installations, board setup etc [4/10]
-- Prepared a local dev machine to work with in absence of lab.
-- Prepare panda board for gdb on android testing.
-- Figure out SSH failure issues with gdb testsuite runs.
-- Try out foundation model for android testing.
-- Getting to know CBuildv2 tried to set it up locally.
On travel to submit Hong Kong visa application [5/10]
Miscellaneous [1/10]
-- Meetings, Emails etc
== Plan ==
Try android boot with foundation model some more and hope that it works.
Resume AArch64 work with lab availability.
Review and update GDB related cards.
== Progress ==
bug #403/418 [5/10]
. submitted partial patch to list for core fix for Aarch64
. needs reworking of expansion for a bunch of builtins + corresponding patterns
. discussion/review of related upstream patches
bug #868 - brief investigation [1/10]
Misc [4/10]
== Plan ==
On holiday on Friday and following Monday morning
1 day off (2/10)
== Issues ==
* none.
== Progress ==
* GCC 4.9 and 4.8 2014.11 (6/10)
- Backported ILP32 related commits in 4.9
- Validate and committed Linaro release macros in Linaro branches.
- Released 4.9 and 4.8 2014.11
* Lab move (1/10)
- Tested new validation infrastructure.
* Misc: (1/10)
- Finished libunwind task
- Various meetings.
== Plan ==
* Back on backports
cbuild2 benchmarking - TCWG-360 [5/10]
* Fixed some bugs and did some general tidying up
* Pulled SPEC2000 into my framework
* Did some test runs on local machines, looks promising
libm exercising - TCWG-558 [3/10]
* Much fiddling with one benchmark (MCB)
* Experimented, thought about methodology
Meetings/mail/etc - [2/10]
=Plan=
cbuild2 benchmarking
* Tweak eembc - it worked before, but spec forced me to change the
scripts a little
* Test in LAVA/new TCWG infrastructure when available
* Test repeatability (depends on above)
* Possibly have another go at building tools on AArch64
libm exerising
* Work through the most interesting benchmarks with a fixed method
* Hopefully reach the end and do some analysis
= Progress ==
* TSAN support for Aarch64 (4/10)
* Fix Linaro Bug 863,869 - reproduced them. Working on fixing 863 (1/10)
* Misc [3/10]
Emails, linaro and AMD status meetings.
1-1 with inline mangers (Mev, Ryan).
1-1 with christophe.
* 11/11/2014 Leave (2/10)
The task on "Debug and understand the inline differences trunk vs linaro
compiler for core mark at -O3 with LTO + PGO" is on hold now.
== Plan ==
* TSAN support for Aarch64.
* Fix Linaro Bug 863
* AMD internal event on 17/11/2014.
== Progress ==
* Zero/sign extension elimination with widening types (5/10)
- Addressing comments from the review
* Improve block memory operations by GCC (TCWG-142 - 5/10)
- Looked at gcc/glibc implementations
- Experimented with x86_64 vs ARM and found different implementation
decisions
- Discussed work items
== Plan ==
* Continue with improve block memory operations by GCC.
* Continue with Zero/sign extension.
== Progress ==
* Building an ILP32 toolchain for AArch64 (5/10, TCWG-559)
* Investigate ARM port of lld (3/10)
* Email, meetings, etc. (2/10)
== Issues ==
* None
== Plan ==
* Further work on ILP32 toolchain
* LLD
--
Will Newton
Toolchain Working Group, Linaro
1 day off (2/10)
== Progress ==
* Linaro GCC 4.8
- updated branch merge, to include the latest errata-related backport
- added Michael's backport for bug #534.
* GCC trunk/4.9 cross-validation (2/10)
- updated vbic/vorn tests patch
- trying to track down cause of spurious 'interrupted system call'
errors in the ST Compute Farm
* AArch64 sanitizer (1/10)
- After discussing with Arnd, the kernel patch causing trouble to
libsanitizer should also be backported to stable kernel branches. This
makes a compiler test based on kernel version impracticable.
- Shared this feedback with sanitizer maintainers, got no feedback.
- libsanitizer maintainers have updated GCC's snapshot with a more
recent version:
- GCC trunk now requires updated kernel headers for aarch64
- reported regressions when the compiler generates Thumb code
(incomplete backtrace)
* Neon intrinsics tests (2/10)
- submitted a series of 9 new tests.
- looking at vldX bugs on aarch64_be, along with ARM's incomplete patches.
* cbuild2
- no progress
* Misc (3/10)
- calls, meetings, support
== Next ==
* AArch64 sanitizers
* Neon intrinsics
* cbuild2 (improve backport-test and tcwgweb)
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.11
stable release of both Linaro GCC 4.9 and Linaro GCC 4.8 source packages.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly engineering[2] releases.
Linaro GCC 4.9 2014.11 is the eighth Linaro GCC source package release and
second stable one in the 4.9 series. It is based on FSF GCC4.9.3-pre+svn216979
and includes performance improvements and bug fixes.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.3-pre+svn216979
* Backport of [AArch64] Fix ILP32 ld.so
* Add new Linaro release macros : __LINARO_RELEASE__ and __LINARO_SPIN__
Linaro GCC 4.8 2014.11 is the fifteenth release in the 4.8 series and second
one since entering maintenance. Based off the latest GCC 4.8.4-pre+svn217270
release, it includes performance improvements and bug fixes.
Interesting changes in this GCC source package release include:
* Linaro bugzilla PR fixed : #307, #534
* Updates to GCC 4.8.4-pre+svn217270
* Add new Linaro release macros : __LINARO_RELEASE__ and __LINARO_SPIN__
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
Hello,
We have implemented gdb server in one of our project and we are using Linaro aarch64-none-elf-gdb.exe as gdb client. Our gdb server will response to packet 'qXfer:features:read:target.xml:0,fff' with a xml file which only claims feature 'org.gnu.gdb.aarch64.core'. However, when I issue 'info reg' command with the gdb client, it actually sends out a packet '$p42#d6', which is trying to read fpsr if I understand correctly. Is this an expected behavior or not? I just want to figure out whether our gdb server send some bad info to the gdb client and made the client thinks FP registers are valid. I hope I made my question clear and I'm really appreciate if anybody can help us on this again.
Thanks,
Strong
Hi toolchain champions,
[please keep me in cc as I'm not subscribed to
linaro-toolchain(a)lists.linaro.org]
In OP-TEE we are going to activate a pager which is an integrated part of
the statically linked secure OS binary (compiled for ARMv7/Aarch32 now, but
at some point also Aarch64).
The pager in OP-TEE allows use of more memory than the amount of available
physical memory. This makes it possible to for instance have an OP-TEE
binary that requires more memory than the amount of available memory. What
the pager does is to map a physical page at the virtual address where the
memory is needed and populate it which what is expected on demand. The
pager also unmaps physical pages that hasn't been used in a while to be
able to recycle it.
The code used by the pager to map and populate a page must always be mapped
since we would otherwise get a deadlock. The problem is that the pager is
also part of OP-TEE so we need to partition the binary in a way that all
code needed to handle a page fault is in one area in the binary and always
mapped.
Annotating functions and such as it's done in the Linux kernel with __init
will not scale here since the pager will need routines from "third-party"
libraries. We can make small changes to the libraries but identifying and
annotating everything needed by the pager is too much. We would also run
into troubles with strings.
I have a couple ideas below that I need help exploring.
What if we do an incremental linking of the entire TEE Core with garbage
collect only keeping the entry functions of the pager? Then we would get an
object file with everything the pager depends on included but not much
more. It would be easy to put this single object file in a separate part of
the OP-TEE binary. The procedure would be something like:
Compile everything with -ffunction-sections -fdata-sections
ld -i --gc-sections -u pager_entry -o pager_code.o $(objs) $(link-ldadd)
$(libgcc)
ld $(link-ldflags) pager_code.o $(objs) $(link-ldadd) $(libgcc)
But the problem comes with linking in the rest of the code in the last
step, we would get lots of multiple defined symbols. We could create a
libtee_core.a file where we put all the $(objs) files and the linker would
only use the needed object files. But we would still have some multiple
defined symbols left since each .o file contains more than just one section.
Any ideas how to solve this?
We could perhaps split each .o file into several .o files each with only
one section. Would it work? Would it make the resulting binary larger or
inefficient?
Another option could be to mark all symbols in libtee_core.a and other
libaries as weak, but the problem here is that we already have some weak
functions in TEE Core so this would break that. Perhaps if it would be
possible to have different levels of weakness.
Any ideas are welcome, either along this path or different approaches.
Regards,
Jens
== Progress ==
AArch64 work on tracepoints and watchpoints failures [4/10]
-- Review of AArch64 debug hardware architecture
-- AArch64 debugging/testing stalled due to lab down time
-- Tried compiling and running custom AArch64 kernel with foundation model
Work on some arm specific fix of reverse-step and reverse-finish
commands. [TCWG-498] [1/10]
Miscellaneous [1/10]
-- Meetings, Emails etc
-- Prepared Hong Kong visa documents
-- Annual Review 2014
Public Holidays [4/10]
== Plan ==
Complete documents and travel to Islamabad for Hong Kong visa
Resume AArch64 work on tracepoints and watchpoints failures with lab
availability.
== Progress ==
* Pushed malloc microbenchmark to glibc (1/10, TCWG-160)
* Upstream work (4/10, CARD-341)
- glibc patch review (C11 atomics series)
- glibc patchwork cleanup
* Look into binutils input fuzzing fixes (1/10)
* Investigate ARM port of lld (2/10)
* Email, meetings, review, etc. (2/10)
== Issues ==
* Installed new cable modem. Seems to be working...
== Plan ==
* Plan toolchain ILP32 work
* lld investigation
--
Will Newton
Toolchain Working Group, Linaro