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cross compiling eglibc with Linaro toolchain

by shyamalan sivan

Hello experts, I don't know whether this is the place to ask this question.Please forgive if i am wrong. I am trying to cross-compile Eglibc,(which i thought is similar to the glibc) library with Linaro tool chain.My aim is to cross-compile the library and add it with the tool-chain( i assumed that Linaro doesn't ahve the eglibc libraries by itself). . I referred to the link http://www.eglibc.org/archives/patches/msg00078.html (README.cross-compiling of the libc) and did the following. I thought that binutils is not required as the tool chain itself contains the loader, assembler etc.(which are the most important in the binutils).So i skipped that step.(i am not sure whether this is right.please correct me if i am wrong). I did the below steps as in the above link. 1) Copied the Linux Kernel Headers 2) EGLIBC Headers and Preliminary Objects 2.1) configuring the Eglibc headers by the below steps. appan@oplt$ ~/cross_compile_eglibc/ppc/obj/eglibc-headers$ BUILD_CC=gcc CC=/home/appan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-gcc CXX=/home/appan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-cpp AR=/home/appan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-ar RANLIB=/home/appaan/cross_compile_eglibc/ppc/tools/bin/arm-linux-gnueabi-ranlib /home/appan/cross_compile_eglibc/src/libc/configure --prefix=/home/appan/CC_EGLIBC --with-headers=/home/appan/cross_compile_eglibc/ppc/sysroot/usr/include/ --build=i686-pc-linux-gnu --host=arm-unknown-linux-gnu --enable-add-ons --with-tls --with-__thread 2.2) compilation make install-headers install_root=$sysroot install-bootstrap-headers=yes But following is the error i get. > /home/appan/cross_compile_eglibc/ppc/obj/eglibc-headers/Versions.v.iT<http://versions.v.it/> In file included from <stdin>:1:0: ports/sysdeps/arm/nptl/tls.h:48:3: error: #*error "TLS support is required.* " make[1]: *** No rule to make target `headers_install'. Stop. make[1]: Leaving directory `/home/appan/cross_compile_eglibc/src/libc' make: *** [headers_install] Error 2 I tried googling, but i did not get the solution for this.. please provide me with some suggestions and that will be of great help to me... thanks and regards appan

13 years, 4 months

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Automatically save preprocessed source on ICE

by Asa Sandahl

Hi there! I need some help with how to handle this bug: https://bugs.launchpad.net/gcc-linaro/+bug/873977 It looks like an improvement suggestion more than a bug. Regards Åsa *Automatically save preprocessed source on ICE*In order to help with bug reporting, gcc could save the preprocessed source of the unit that caused the ICE, so one can just pick it up and attach it to bug reports instead of trying to reproduce it manually.

13 years, 4 months

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KVM and OpenStack integration

by Michael Hope

Hi Peter. I've had a poke about in qemu-linaro, OpenStack, and libvirt to get a feel for the KVM integration work. My scratch notes are here: https://wiki.linaro.org/MichaelHope/Sandbox/QEMUA15GuestNotes I'm feeling happy about the integration. The parts that I've seen have good separation, are architecture neutral, and have some ARM support. We can prototype using virtual x86 based masters and QEMU TCG based compute instances. I've seen a few bugs and assumptions: OpenStack defaults to virtio, boot=hda, and fixed kernel args; and libvirt can't parse the the qemu-linaro version string. There will be more. I'll feed this into the KVM 1.0 task list and share it. -- Michael

13 years, 4 months

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New conference call number

by Michael Hope

Hi there. Starting next week we'll switch to the Zip conference line. See: https://wiki.linaro.org/Resources/ZipConferenceLine under 1-719-457-1414 for a list of numbers. A selected few are: UK 0 808 101 1146 Germany 0 800 181 9019 Sweden 02 079 7556 Brazil, Sao Paulo Local +55 11 5582 6534 Australia 1 800 105 680 China +400 148 5400 NZ 0800 451 015 The code is 763 804 0680. I've updated the meeting calendar and will update the wiki page once Monday comes around. The moderator code is on the toolchain internal page. Amber, could you update the public event please? Ramana, could you update the performance call for two weeks time? Maybe move it to linaro-events so I can edit it. -- Michael

13 years, 4 months

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Cross-compiling Eglibc library with Linaro toolchain

by Amber Graner

Hi all, In my search for Linaro related news this morning, I saw a tweet from Linuxquestions.org referencing a cross-compiling questions. Here is the link to the post on Linuxquestions.org - http://www.linuxquestions.org/questions/linux-embedded-78/cross-compiling-e… Thanks, I'll answer from the Linaro Tweeter account that it's been past to the Linaro Developers. Cheers, Amber -- Amber Graner User Experience and Community Specialist Linaro.org <http://www.linaro.org/>* **│ *Open source software for ARM SoCs* *** Follow *Linaro: *Facebook <http://www.facebook.com/pages/Linaro> | Twitter<http://twitter.com/#%21/linaroorg> | Blog <http://www.linaro.org/linaro-blog/> *+1.828.582.9469* cell *+1.828.395.1049* office irc: akgraner amber.graner(a)linaro.org (email and Google chat)

13 years, 4 months

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Triage of #914703

by Asa Sandahl

Hi Michael, So, I gave my best shot at: https://bugs.launchpad.net/gcc-linaro/+bug/914703 Kind of similar to the one in your walk-through, but I couldn't actually reproduce on the version reported. Could you please check if this looks OK? Regards Åsa

13 years, 4 months

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Bug triage run-through

by Michael Hope

Hi Åsa. I've triaged a bug and written down my notes on the way. See: https://wiki.linaro.org/MichaelHope/Sandbox/TriageRunThrough This one turned out to be easy but at least you have the basics. Could you triage the bug for real and see what I've missed? I'm unsatisfied with the result on that bug. The fault is in the Ubuntu Natty compiler which we've long since fixed in Linaro GCC. It would be nice if we could point the bug reporter to an updated GCC. Ask Marcin and Matthias what they think. -- Michael

13 years, 4 months

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[ACTIVITY] Week 02

by Zhenqiang Chen

Summary: * Enhance crosstool-ng build process. Details: 1. crosstool-ng patches: * Reproduce the build process by following the README and enhance the document. * Update .config to strip all toolchain executables * Replace harded-coded VERSION by reading config file. * Remove host libiberty.a * Patch on how to strip debug sections is in discussion. 2. Update the crosstool-ng based embedded toolchain build scripts according to the review comments. And replace most of hard-coded config by reading them from .config. 3. Unexpected build fail for gcc 4.7/trunk from crosstool-ng due to unsupported ENDIAN_LDFLAG "-EL", which is used in "LDFLAGS_FOR_TARGET" to build libstdc++. (LDFLAGS_FOR_TARGET seams not used in gcc 4.6). Need more investigation. Plan: * Fix the binary build related bugs. * Ramp-up on gcc. Planned Absence: * Jan 21-29, 2012 Chinese Spring Festival Best regards! -Zhenqiang

13 years, 4 months

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uImage built with pre-built linaro toolchain failed to start

by Lv Terry-R65388

Hi, I use pre-built version of linaro toolchain (got from http://people.linaro.org/~michaelh/incoming/binaries/) to build a uImage. The build succeeded, but the uImage couldn't start. The console hangs at: Using FEC0 device TFTP from server 10.193.100.158; our IP address is 10.193.102.233 Filename 'uImage_linaro'. Load address: 0x70800000 Loading: ################################################################# ################################################################# ################################################################# ####################### done Bytes transferred = 3193292 (30b9cc hex) ## Booting kernel from Legacy Image at 70800000 ... Image Name: Linux-2.6.38-01026-gc9c8ead Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3193228 Bytes = 3 MB Load Address: 10008000 Entry Point: 10008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. Does anyone meet this before? How can I fix it? Thanks~~ Yours Terry

13 years, 4 months

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[ACTIVITY] w02

by Asa Sandahl

* Started with some day-to-day activities in the team. Looking after the proposals and the cbuild scheduler. Will start Created problem log for scheduler problems, there is a link to it from the jobs page. https://wiki.linaro.org/WorkingGroups/ToolChain/SchedulerProblems * Worked on producing graphs for benchmark results using matplotlib. Michael: Would it be ok to put my script in linaro-toolchain-benchmarks/scripts? * Kicked off some benchmarks with gcc-linaro-4.6-2012.01. To start with coremark, eembc, denbench, pybench and spec2000. We will see what's there after the weekend. Variants: os-neon, o2-neon, o3-neon-novect and o3-neon. /Regards Åsa

13 years, 4 months

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[ACTIVITY] Jan 09 - Jan 13

by Ulrich Weigand

== GDB == * Implemented, tested, and posted for discussion yet another version of remote support for "info proc" and core file generation, this time via accessing /proc files via generic file I/O primitives. == GCC == * Tested and merged Revital's fix for LP #879725. * Tested Richard's patch to help code generation for NEON strided loads by enabled forward-propagation of subreg expressions. This caused optimization failures on x86_64; investigated the root cause and engaged in discussion on mailing list on potential fixes. * Helped Ramana look into PR 43808 and PR 50313. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 4 months

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[ACTIVITY] 9th - 13th January

by Andrew Stubbs

Continued work on 64-bit shifts. I've tidied up most of the nastiness I had in my first attempt at this work, unified the logic into fewer places, and fixed the one logic error that I knew about. I had a mysterious reload bug that just wouldn't go away, but having stared at it for some time I've decided that what I was doing wasn't the best option in any case, and the new way seems to work. I still have the problem that register-allocation prefers to allocate the values in core-registers, even when it would seem to me to work better in NEON. This maybe because the shift amount must be negated in some cases, and there isn't a neon instruction for that. Continued trying to use LAVA to do builds. Unfortunately this seems to have hit against a lava-test bug. Filed as lp:915915.

13 years, 4 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, * built linaro binary toolchain using Michaels crosstool-ng environment: * disabled multiarch and pkg-config * uses eglibc 2.13 (due to RPC headers) * using Linux kernel version 2.6.32.48 (longterm) * debugged why /sbin/init fails when using the linaro binary toolchain: * the loader and libc of the binary toolchain is build for armv7 * the binaries (init, busybox, ...) are linked against this glibc and using the libdl-2.13.so of the binary toolchain * it causes the boot to fails due to illegal insn caused by the dl * built the minimal image for armv7-a: * use the vexpress_defconfig of linaro 3.1 tree linux-linaro-3.1.git (instead of the OE vesatilebp kernel) * boots fine using the vexpress-a9 QEMU system model * sato image (X and gtk+ apps) for armv7-a: * Tremor (vorbis): inline assembly only supports ARM mode quick workaround: undefine _ARM_ASSEM_ to fall back to C * pulseaudio/libatomics-ops: inline asm that only supports ARM mode quick workaround: use the latest version from upstream * gtk+_2.24.8 fails due to the libstdc++ libtool archive easy fix: delete the *la files (just like most of the distributors) the *la files prevent the the binary toolchain from being "relocatable" * sato image boots and shows the gui but the X resolution is higher and the X cursor behaves strange (probably not a miscompile but a difference of the linaro kernel) Regards, Ken

13 years, 4 months

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[ACTIVITY] report week 02

by Peter Maydell

RAG: Red: Amber: Green: good progress on A15 vexpress system model Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-02-20 || || ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| || (for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM) Historical Milestones: ||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 || ||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 || == cp15-rework == * estimate shifted back since it turns out we can do something useful in initial-a15-system-model without this as a prerequisite, so that's a better order to do things in == initial-a15-system-model == * I now have a working vexpress-a15 board model, and enough of the a15 private peripheral region and CPU definition that we can boot a kernel compiled for A15-without-LPAE * patchseries mostly looks ok to upstream but there are some loose ends to fix up involving SMP secondary boot CPU protocol and making sure the right one of the two graphics controllers gets to display things; also it depends on some patches in the Calxeda/Samsung patchseries == other == * patch review: Calxeda now basically ready to commit, another round with Samsung * made qemu-linaro 2012.01 release * usual round of meetings etc

13 years, 4 months

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[ACTIVITY] Week 2

by Ramana Radhakrishnan

==Progress=== * Backported one part of the partial-partial PRE patch . Still looking into it. * Investigate PR48308 - a bug where combine was generating incorrect transformations. * Reopened PR50313 - a bug which I originally thought was a dup of PR48308. * Looked at upstream bugzilla for sometime and triaged a few bugs. * Linaro patch review. === Plans === * Continue looking at partial-partial PRE and try and understand it further. * Look at PR50313 further * Upstream patch review. * Finish submitting PGO patch and ABI tests patch * Look at Andrew's patches for neon shifts - Absences. * Feb 6-10 : Linaro Connect Q1.12. * Feb 13- 18 : Holiday.

13 years, 4 months

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[ACTIVITY] Week 1

by Ramana Radhakrishnan

==Progress=== * Short week - 4 days only after the bank holiday monday. * Investigated PR48308 for a bit. * Caught up with emails after vacation. * Looked at fate an automatic tester for libav to validate my fixed to fp conversions . Need to finish that off. * 1 more bug with output_move_double ICE looked at briefly. Appears to be memory corruption but valgrinding didn't find the issue. Prioritizing PR48308 above this. === Plans === * Look at PR48308 a bit more seriously. * Finish my long standing patches. Absences. * Feb 6-10 : Linaro Connect Q1.12. * Feb 13- 18 : Holiday.

13 years, 4 months

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Microkernel based virtualisation

by Michael Hope

Amber noticed this on her Twitter feed: a L4 microkernel based para-virtualisation that runs on the A9: http://l4dev.org/ They're currently running the 11.12 LEB on a Versatile Express. The project overview: http://l4dev.org/codezero_overview talks about their 'hyperswitch' method to reduce the para-virtualisation overhead and reduce the number of changes to the Linux kernel. -- Michael

13 years, 4 months

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Release done, branch is open

by Michael Hope

The GCC release tested up just fine. The branch is now open for commits. The next release is Thursday the 9th of February. Note that this is in the middle of Connect. -- Michael

13 years, 4 months

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Linaro GCC 4.6 and 4.5 2012.01 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the 2012.01 release of Linaro GCC 4.6 and Linaro GCC 4.5. No changes were made in Linaro GDB this month and, as such, no release has been made. Linaro GCC 4.6 2012.01 is the eleventh release in the 4.6 series. Based off the latest GCC 4.6.2+svn182894 release, it contains a few bug fixes from over the Christmas break. Interesting changes include: * Updates to 4.6.2+svn182894 Fixes: * PR51301 ICE in vectorised widening multiplies * LP: #897583 Code generation bug with -O2 (-foptimize-sibling-calls) * LP: #736661 armel FTBFS due to compiler ICE Linaro GCC 4.5 2012.01 is the seventeenth release in the 4.5 series. Interesting changes include: * Updates to 4.5.3+svn182893 Fixes: * LP: #736661 armel FTBFS due to compiler ICE The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.6-2012.01 https://launchpad.net/gcc-linaro/+milestone/4.5-2012.01 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro More information on the features and issues are available from the release page: https://launchpad.net/gcc-linaro/4.6/4.6-2012.01 https://launchpad.net/gcc-linaro/4.5/4.5-2012.01 Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain Bugs: https://bugs.launchpad.net/gcc-linaro/ Questions? https://ask.linaro.org/ Interested in commercial support? inquire at support(a)linaro.org -- Michael

13 years, 4 months

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Linaro QEMU 2012.01 released

by Peter Maydell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2012.01. Linaro QEMU 2012.01 is the latest monthly release of qemu-linaro. Based off upstream (trunk) QEMU, it includes a number of ARM-focused bug fixes and enhancements. New in this month's release: - Several bug fixes which reinstate support for running on ARM hosts - Support for previously missing *xattr syscalls in usermode emulation - A (dummy) model of the L2x0/PL310 L2 cache contrnoller (thanks to Rob Herring and Mark Langsdorf of Calxeda) Known issues: - Graphics do not work for OMAP3 based models (beagle, overo) with 11.10 Linaro images. The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2012.01 More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

13 years, 4 months

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[PATCH 1/1] hw: Add IGEPv2 board support

by Javier Martinez Canillas

Add ISEE IGEPv2 board definition (an OMAP3730 based board). Signed-off-by: Javier Martinez Canillas <javier(a)dowhile0.org> --- Makefile.target | 2 +- hw/igep.c | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+), 1 deletions(-) create mode 100644 hw/igep.c diff --git a/Makefile.target b/Makefile.target index 409748f..2923dd7 100644 --- a/Makefile.target +++ b/Makefile.target @@ -349,7 +349,7 @@ obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o \ obj-arm-y += omap2.o omap_dss.o soc_dma.o omap_gptimer.o omap_synctimer.o \ omap_gpmc.o omap_sdrc.o omap_spi.o omap_tap.o omap_l4.o obj-arm-y += omap3.o omap_usb.o omap3_boot.o omap3_mmc.o dsi.o -obj-arm-y += twl4030.o beagle.o overo.o +obj-arm-y += twl4030.o beagle.o overo.o igep.o obj-arm-y += omap_sx1.o palm.o tsc210x.o obj-arm-y += nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o obj-arm-y += mst_fpga.o mainstone.o diff --git a/hw/igep.c b/hw/igep.c new file mode 100644 index 0000000..5254ddf --- /dev/null +++ b/hw/igep.c @@ -0,0 +1,123 @@ +/* + * ISEE IGEPv2 board emulation. + * + * Copyright (c) 2012 ISEE 2007, SL + * Written by Javier Martinez Canillas (based on Gumstix Overo emulation code) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu-common.h" +#include "sysemu.h" +#include "omap.h" +#include "arm-misc.h" +#include "boards.h" +#include "i2c.h" +#include "net.h" +#include "devices.h" +#include "flash.h" +#include "sysbus.h" +#include "blockdev.h" +#include "exec-memory.h" + +#define IGEP_NAND_CS 0 +#define IGEP_NET_CS 5 + +struct igep_s { + struct omap_mpu_state_s *cpu; + + DeviceState *nand; + void *twl4030; + DeviceState *eth; + DeviceState *ddc; +}; + +static void igep_init(ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, + const char *cpu_model) +{ + MemoryRegion *sysmem = get_system_memory(); + struct igep_s *s = (struct igep_s *) g_malloc0(sizeof(*s)); + DriveInfo *dmtd = drive_get(IF_MTD, 0, 0); + DriveInfo *dsd = drive_get(IF_SD, 0, 0); + + if (ram_size > 1024 * 1024 * 1024) { + fprintf(stderr, "igep: maximum permitted RAM size 1024MB\n"); + exit(1); + } + + if (!dmtd && !dsd) { + hw_error("%s: SD or NAND image required", __func__); + } + s->cpu = omap3_mpu_init(sysmem, omap3630, ram_size, + NULL, NULL, serial_hds[0], NULL); + + s->nand = qdev_create(NULL, "onenand"); + qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_STMICRO); + qdev_prop_set_uint16(s->nand, "device_id", 0x40); + qdev_prop_set_uint16(s->nand, "version_id", 0x121); + qdev_prop_set_int32(s->nand, "shift", 1); + if (dmtd && dmtd->bdrv) { + qdev_prop_set_drive_nofail(s->nand, "drive", dmtd->bdrv); + } + qdev_init_nofail(s->nand); + omap_gpmc_attach(s->cpu->gpmc, IGEP_NAND_CS, + sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0)); + + if (dsd) { + omap3_mmc_attach(s->cpu->omap3_mmc[0], dsd->bdrv, 0, 0); + } + + /* FAB revs >= 2516: 4030 interrupt is GPIO 0 (earlier ones were 112) */ + s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c, 0), + qdev_get_gpio_in(s->cpu->gpio, 0), + NULL, NULL); + + /* Wire up an I2C slave which returns EDID monitor information; + * newer Linux kernels won't turn on the display unless they + * detect a monitor over DDC. + */ + s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c, 2), "i2c-ddc", 0x50); + + omap_lcd_panel_attach(s->cpu->dss); + + /* Strictly this should be a LAN9221 */ + if (nd_table[0].vlan) { + /* The ethernet chip hangs off the GPMC */ + NICInfo *nd = &nd_table[0]; + qemu_check_nic_model(nd, "lan9118"); + s->eth = qdev_create(NULL, "lan9118"); + qdev_set_nic_properties(s->eth, nd); + qdev_init_nofail(s->eth); + omap_gpmc_attach(s->cpu->gpmc, IGEP_NET_CS, + sysbus_mmio_get_region(sysbus_from_qdev(s->eth), 0)); + sysbus_connect_irq(sysbus_from_qdev(s->eth), 0, + qdev_get_gpio_in(s->cpu->gpio, 176)); + } +} + +QEMUMachine igep_machine = { + .name = "igep", + .desc = "ISEE IGEPv2 board (OMAP3730)", + .init = igep_init, +}; + +static void igep_machine_init(void) +{ + qemu_register_machine(&igep_machine); +} + +machine_init(igep_machine_init); -- 1.7.4.1

13 years, 4 months

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First proposals

by Michael Hope

Hi Åsa. Well, the first proposals have arrived. I've cc'ed this to linaro-toolchain so we have a record. First, visit: http://ex.seabright.co.nz/helpers/proposals and see there are new merge requests from Ulrich with new results. Next, login: http://ex.seabright.co.nz/helpers/login Your login is your Launchpad OpenID login "https://launchpad.net/~asa-sandahl" After logging in, go back to the proposals page. See that the fwprop-subreg merge request has a i686 and x86_64 result. The i686 one is fine so click 'Record' and follow your nose. The x86_64 is interesting - the fault might be real. Click 'Record'. Note the subject line has 'regressed' in it. Ulrich will have to investigate. The lp-879725 results look fine so record both of those. Scanning down the page shows that everything else is recorded so you're done! The tool is a bit slow so don't be surprised if an operation takes ~10 s. The tool is backed by a cache so you won't see the results for ~2 hours. -- Michael

13 years, 4 months

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Next week

by Andrew Stubbs

Hi Michael, I can't remember if I told you before, but I shall be away at the CodeSourcery (Ok, Mentor Graphics's ESD TOOLS) annual meeting most of next week. I ought to be back at work on Friday. In the meantime I shall be reading email, but not spending much time on Linaro work. I can probably still get the GCC release process done, but if you'd prefer Ramana did it this month then that's fine with me. Andrew

13 years, 4 months

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Spinning the build

by Michael Hope

Hi Andrew. The current tip looks good. Could you please run the release process, spin the build, and fire it into the auto builders? Ta, -- Michael

13 years, 4 months

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Backporting A15 changes

by Michael Hope

Hi there. Linaro is about what's next and, as part of this, we should backport any reasonable Cortex-A15 changes to our 4.6 branch. Richard and Matthew, could you let us know directly when new patches from ARM land upstream? We're already doing this but I thought I'd say it out loud. -- Michael

13 years, 4 months

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Building Linaro GCC from source

by Javier Martinez Canillas

Hello, I'm trying to build the Linaro GCC from source on an x86_64 Fedora 16 box. I'm using as a guide a wiki entry I found in linaro.org site [1] that explains how to build a native version of the compiler. But instead of a native version I want to be able to cross-compile ARM binaries for my target machine. This is what I tried: [javier@munra src]$ wget -c http://launchpadlibrarian.net/86993387/gcc-linaro-4.6-2011.12.tar.bz2 [javier@munra src]$ tar xaf gcc-linaro-4.6-2011.12.tar.bz2 [javier@munra src]$ mkdir build && cd build [javier@munra build]$ ../gcc-linaro-4.6-2011.12/configure --target=arm-linux --disable-bootstrap --enable-languages=c --prefix=/home/javier/tools [javier@munra build]$ make -j4 && make install But got this error: make[2]: Leaving directory `/home/javier/src/build/gcc' Checking multilib configuration for libgcc... mkdir -p -- arm-linux/libgcc Configuring in arm-linux/libgcc configure: creating cache ./config.cache checking for --enable-version-specific-runtime-libs... no checking for a BSD-compatible install... /usr/bin/install -c checking for gawk... gawk checking build system type... x86_64-unknown-linux-gnu checking host system type... arm-unknown-linux-gnu checking for arm-linux-ar... arm-linux-ar checking for arm-linux-lipo... arm-linux-lipo checking for arm-linux-nm... /home/javier/src/build/./gcc/nm checking for arm-linux-ranlib... arm-linux-ranlib checking for arm-linux-strip... arm-linux-strip checking whether ln -s works... yes checking for arm-linux-gcc... /home/javier/src/build/./gcc/xgcc -B/home/javier/src/build/./gcc/ -B/home/javier/tools/arm-linux/bin/ -B/home/javier/tools/arm-linux/lib/ -isystem /home/javier/tools/arm-linux/include -isystem /home/javier/tools/arm-linux/sys-include checking for suffix of object files... configure: error: in `/home/javier/src/build/arm-linux/libgcc': configure: error: cannot compute suffix of object files: cannot compile See `config.log' for more details. make[1]: *** [configure-target-libgcc] Error 1 make[1]: Leaving directory `/home/javier/src/build' make: *** [all] Error 2 Before trying to compile I've installed the libgmp, libmpfr and arm cross tool-chain [2] Fedora packages so I guess all gcc dependencies are met (binutils, glibc, etc). Could someone be so kind to point me out what am I doing wrong? I'm sending as an attachment the config.log generated file. Please let me know if you need any more information about my setup and environment. [1]: https://wiki.linaro.org/WorkingGroups/ToolChain/Using/GCCNative [2]: http://fedoraproject.org/wiki/Architectures/ARM/CrossToolchain Thanks a lot and best regards, Javier

13 years, 5 months

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A high level try at KVM for ARM

by Michael Hope

I've taken a stab at the medium term requirements for KVM on ARM: https://wiki.linaro.org/WorkingGroups/ToolChain/Specs/KVMEpic I haven't looked outside Linaro so apologies if this overlaps with other people's plans. Peter, this is high level and hopefully matches what's in your head. I want to use this to do a project plan, see if it can be done in 6-9 calendar months, and see if we need more people. Are there any implementation details that we should call out, similar to calling out virtio and UEFI? Rusty, this should tell you more about where we're going. Mounir, you, Peter, and I should turn this into a basic project plan. -- Michael

13 years, 5 months

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agenda for tomorrow's performance call.

by Ramana Radhakrishnan

Hi, Does anyone have anything they'd like to bring up in tomorrow's performance call. ? I don't have any topics other than following on action items from last time's call - which was comparing movw/ movt with constant pools . https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings/2012-01-10 Please add to it as you deem fit. cheers Ramana

13 years, 5 months

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[ACTIVITY] 2nd - 6th January

by Andrew Stubbs

* Linaro Continued work on getting GCC to build on LAVA. I've ironed out a few more bugs from my test scripts, but it's slow going because a test runs takes a long time to run, and there are very few useful error messages when something goes wrong. Wrote, posted, and committed a patch to fix the "120" testsuite bug I encountered last month. Basically the GCC testsuite's "headmerge-1" testcase would have failed from now until September because a sloppy regex happening to match "120" in the toolchain version string's snapshot date. I've also backported it to upstream 4.6 and posted a merge request for Linaro 4.6. Continued running benchmarks for the generic tuning project. Continued looking at optimizing 64-bit shifts. No real progress this week though. * Other Monday: Public holiday. Tuesday: Vacation. Caught up on a mountain of email.

13 years, 5 months

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[ACTIVITY] Jan 04 - Jan 06

by Zhenqiang Chen

Summary: * Read armV7-A/R reference manual and analyze bugs. Details: * Read armV7-A/R reference manual and share the instruction set part with local team. * Analyze bugs: LP: #889985 "binaries: can't step out of helper functions" and LP: #889984 "binaries: should step across helper functions" Plan: * Ramp-up on gcc. Planed leave: * Jan 21 - 29: Chinese new year holiday. Best regards! -Zhenqiang

13 years, 5 months

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Jobs/tasks inside the group

by Michael Hope

Hi there. I want each administrative task inside our group to have an owner and a fill-in. I've started a list at: https://wiki.linaro.org/WorkingGroups/ToolChain/Jobs I took the chance to hand off some of my jobs as well so you might see your name somewhere new (but hopefully not surprising). I'll discuss this at tonight's meeting and in the 1-on-1s. Reply away if you'd like more detail or have a task to add. -- Michael

13 years, 5 months

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[ACTIVITY] report week 01

by Peter Maydell

[short week, three days] RAG: Red: Amber: Green: Current Milestones: || || Planned || Estimate || Actual || ||cp15-rework || 2012-01-06 || 2012-01-17 || || ||initial-a15-system-model || 2012-01-27 || 2012-01-27 || || ||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| || (for blueprint definitions: https://wiki.linaro.org/PeterMaydell/QemuKVM) Historical Milestones: ||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 || ||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 || == other == * catchup on email, etc * patch review: patches for Calxeda's Highbank SoC model * put together pull requests for target-arm and arm-devs patchqueues * rebased qemu-linaro, added patches for things we want to fix in 2011.01, rolled a tarball, tested it and sent to Michael H for testing

13 years, 5 months

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Operations on intrinsic types

by Michael Hope

Hi Ramana. You were right about being able to do operations on intrinsic types. Instead of doing the admittedly made up: int16x4_t foo2(int16x4_t a, int16x4_t b) { int16x4_t ca = vdup_n_s16(0.2126*256); int16x4_t cb = vdup_n_s16(0.7152*256); return vadd_s16(vmul_s16(ca, a), vmul_s16(cb, b)); } you can do: int16x4_t foo3(int16x4_t a, int16x4_t b) { int16x4_t ca = vdup_n_s16(0.2126*256); int16x4_t cb = vdup_n_s16(0.7152*256); return ca*a + cb*b; } which is more readable and, as an added bonus, generates the multiply-and-accumulate that I missed when using intrinsics. Nice. -- Michael

13 years, 5 months

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[ACTIVITY] Jan 02 - Jan 05

by Ulrich Weigand

== GDB == * Ongoing discussion on remote support for "info proc" and core file generation. * Fixed various GDB 7.4 regressions on multiple platforms. == GCC == * Patch review week. * Started looking into current status of performance patches. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 5 months

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Release notes for 2012.01

by Michael Hope

I liked Andrew's idea of sharing the release notes so I stole it for this month: https://wiki.linaro.org/MichaelHope/Sandbox/GCC2012.01ReleaseNotes Please add anything new and noteworthy that you've done to this draft. -- Michael

13 years, 5 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, * Android * migrated my linaro android build environment * did a small change to the debuggerd patch (thanks Sylvain) * OpenEmbedded * the linaro binary toolchain uses multiarch paths while OE doesn't -> setup a workaround to make it look like a classic one * however, I think what I really want is to build the libc instead of using the one provided by the binary external toolchain * The core-image-minimal still doesn't boot properly because 'init' doesn't come properly Regards Ken

13 years, 5 months

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Patch drop: fwprop.c patch for neon-strided-load-extract

by Richard Sandiford

The remaining change for neon-strided-load-extract is to allow fwprop.c to propagate: (set (reg X) (subreg (reg Y) N)) even if no further simplifications are possible. I posted the original patch for comments here: http://article.gmane.org/gmane.comp.gcc.patches/246180/ and fixed the problem that H.J. spotted. I wasn't entirely happy with the benchmark results though, so it never became an RFA. Richard gcc/ * fwprop.c (propagate_rtx): Also set PR_CAN_APPEAR for subregs. Index: gcc/fwprop.c =================================================================== --- gcc/fwprop.c 2011-09-15 14:36:23.206143787 +0100 +++ gcc/fwprop.c 2011-09-15 14:36:40.995131564 +0100 @@ -664,7 +664,12 @@ propagate_rtx (rtx x, enum machine_mode return NULL_RTX; flags = 0; - if (REG_P (new_rtx) || CONSTANT_P (new_rtx)) + if (REG_P (new_rtx) + || CONSTANT_P (new_rtx) + || (GET_CODE (new_rtx) == SUBREG + && REG_P (SUBREG_REG (new_rtx)) + && (GET_MODE_SIZE (mode) + <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (new_rtx)))))) flags |= PR_CAN_APPEAR; if (!for_each_rtx (&new_rtx, varying_mem_p, NULL)) flags |= PR_HANDLE_MEM;

13 years, 5 months

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[ACTIVITY] 2011-12-23 - and goodbye

by David Gilbert

== QEMU == * Wrote the context routines for Eglibc, including those that QEMU uses These pass all the context tests I could find, including QEMUs coroutine tests, and with them QEMU seems to boot OK. I've got a full eglibc test run going at the moment, but I don't think anything else uses them. I posted them with comments and a question to libc-ports; I'll try and chase follow ups. == String routines == * I posted the strchr and strlen routines to eglibc (libc-ports) * On strchr the question of whether it was worth using the longer version that's faster for longer strings (but slower for shorter strings) came up. I posted some stats, observations etc - and there is still a discussion on going about it. * For strlen, rth noted the same trick that I'd originally seen in newlib (and for which RichardS and Ramana had suggested) of a quicker end-of-string sequence using clz. I'd avoided this because I'd originally seen it in newlib and didn't want to copy it; but since 3 people have individually suggested it it would seem using. == Goodbye! == Thank you all for a fun & interesting year! I'm sure many of us will meet online again in the future. I'll try and follow my linaro.org address while it's still live to check for any replies to any patches/comments etc. Feel free to mail me at davidgil(a)uk.ibm.com (work) or dave(a)treblig.org (home); for Linaro people I've also added some more contact methods at: https://wiki.linaro.org/Internal/People/DaveGilbert/Contact Thanks again! Dave

13 years, 5 months

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Fwd: New question: problem in installing Linaro tools on Ask Linaro

by Andy Doan

anyone have a suggestion for this person? -------- Original Message -------- Subject: New question: problem in installing Linaro tools on Ask Linaro Date: Mon, 26 Dec 2011 21:31:57 -0800 (PST) From: Ask Linaro <dnsadmin(a)linaro.org> To: doanac <andy.doan(a)linaro.org> Ask Linaro - Q & A forum for Linaro developers <http://ask.linaro.org/> ------------------------------------------------------------------------ Hello doanac, chandrakala <http://ask.linaro.org/users/172/chandrakala> has just posted a new question on Ask Linaro, entitled problem in installing Linaro tools <http://ask.linaro.org/questions/456/problem-in-installing-linaro-tools> and tagged "/linaro <http://ask.linaro.org/tags/linaro/> installation <http://ask.linaro.org/tags/installation/>/". Here's what it says: Hi all, Iam new to linux and gnu tools. i have downloaded linaro gnu tools to install cortex-a8 on my ubuntu machine. iam able to successfully install gcc tools. But when i try to install arm tools it is throwing error. following are the commands used to install gnu tools and the error it is generated mckala@mckala:~/Desktop/gstreamer/gcc_objdir$ ../gcc-linaro-4.6-2011.12/gcc-linaro-4.6-2011.12/configure --target=arm-*-elf --disable-bootstrap --enable-languages=c,c++ --with-mode=thumb --with-arch=armv7-a --with-tune=cortex-a8 --with-fpu=neon --with-float=softfp --prefix=/home/mckala/Desktop/gstreamer/gcc_objdir --disable-werror --with-newlib mckala@mckala:~/Desktop/gstreamer/gcc_objdir$ make all-host mckala@mckala:~/Desktop/gstreamer/gcc_objdir$ make install-host with this gnu tools installation is completed and i did not get any error. when i used the following command to install cross compiler, it is giving error mckala@mckala:~/Desktop/gstreamer/gcc_objdir$ make The error is checking for suffix of object files... configure: error: in |/home/mckala/Desktop/gstreamer/gcc_objdir/arm-*-elf/libgcc': configure: error: cannot compute suffix of object files: cannot compile See|config.log' for more details. make[1]: *** [configure-target-libgcc] Error 1 config.log file is showing the following error. gcc_objdir/arm-/-elf/bin/ -B/home/mckala/Desktop/gstreamer/gcc_objdir/arm-/-elf/lib/ -isystem /home/mckala/Desktop/gstreamer/gcc_objdir/arm-/-elf/include -isystem /home/mckala/Desktop/gstreamer/gcc_objdir/arm-/-elf/sys-include -V >&5 xgcc: fatal error: no input files compilation terminated. Can any one please help on this. Thanks in advance. Don't forget to come over and cast your vote. Thanks, Ask Linaro P.S. You can always fine-tune which notifications you receive here <http://ask.linaro.org//users/16/doanac/subscriptions/>. ------------------------------------------------------------------------

13 years, 5 months

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Round-up and goodbye

by Richard Sandiford

I've posted all my WIP patches to this list over the last few days. Please treat them kindly. :-) I've also tried to update the relevant blueprints. I pinged the 4.5 and 4.6 backports for lp736661 on gcc-patches last week, then again this week, but there's obviously not likely to be much response at this time of year. I therefore went ahead with the Linaro merges of the branches rather than relying on them being committed to FSF branches in time for next month's Linaro release. I'll continue to ping though. If I've forgotten anything, or if you need more info, please don't hesitate to ask. I'll continue to monitor my Linaro email address as long as it remains active, although rdsandiford(a)googlemail.com is likely to be a better bet. With all that out of the way, I just wanted to say thank you to everyone for making this a really enjoyable project to work on. It feels like we managed to get through a fair number of new features, performance improvements and bug fixes this year. I hope Linaro will be around for a good few years yet and that it continues to go from strength to strength. Happy New Year, and all the best, Richard

13 years, 5 months

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Patch drop: sms-and-memory-dependencies

by Richard Sandiford

Here's the patch for sms-and-memory-dependencies. The idea is to bypass the sched-deps.c {output,read,anti,true}_dependence tests altogether -- which is easy to do thanks to the note_mem_dep hook -- and instead handle them in ddg.c. The ddg.c tests then use RTL loop iv analysis to try to get longer distances on the memory dependencies. (Note that other memory-related dependencies, such as those between volatile MEMs and other volatile instructions, are still handled by sched-deps.c.) Dependencies are now always created in pairs, so there's no need for get_sched_window to set an upper bound when processing incoming MEM_DEPs, or a lower bound when processing outgoing MEM_DEPs; we can rely on the partnering edge to do that instead. Richard gcc/ * Makefile.in (ddg.o): Depend on $(TREE_PASS_H). * ddg.h (REG_OR_MEM_DEP, REG_AND_MEM_DEP): Delete. (ddg_mem_ref): New structure. (ddg): Add loads and stores array. (create_ddg): Add a loop argument. (add_edges_to_ddg): Declare. (MAX_DDG_DISTANCE): New macro. * ddg.c: Include tree-pass.h. (mem_ref_p, mark_mem_use, mark_mem_use_1, mem_read_insn_p) (mark_mem_store, mem_write_insn_p, rtx_mem_access_p) (mem_access_insn_p): Delete. (create_mem_ref): New function. (graph_and_node): New structure. (record_loads, record_stores): New functions. (create_ddg_dep_from_intra_loop_link): Treat all dependencies as register dependencies. (walk_mems_2, walk_mems_1, insns_may_alias_p, add_intra_loop_mem_dep) (add_inter_loop_mem_dep): Delete. (build_intra_loop_deps): Ignore memory dependencies created by sched-deps.c. Don't handle memory dependencies here. (measure_mem_distance, add_memory_dep): New functions. (FOR_EACH_LATER_MEM_REF): New macro. (build_memory_deps): New function. (create_ddg): Take the loop as argument. Don't count loads and stores here. Call iv_analysis_loop_init. Pass all loads to record_loads and all stores to record_stores. Move edge creation to... (add_edges_to_ddg): ...this new function. Also call build_memory_deps. * modulo-sched.c (sat_mulpp, sat_addsp, sat_subsp): New functions. (schedule_reg_moves): Only handle register dependencies. (sms_schedule): Update call to create_ddg. Call iv_analysis_done after creating all ddgs. Only set issue_rate if there are ddgs. Only call setup_sched_infos and haifa_sched_init if there are ddgs. Call add_edges_to_ddg before processing each ddg. (get_sched_window): Use saturating arithmetic. Do not add an implicit upper bound for incoming MEM_DEPs, or an implicit lower bound for outgoing MEM_DEPs. Rework calculation of final window. (calculate_must_precede_follow, compute_split_row): Use saturating arithmetic. Index: gcc/Makefile.in =================================================================== --- gcc/Makefile.in 2011-12-30 13:13:45.077544981 +0000 +++ gcc/Makefile.in 2011-12-30 13:24:57.330195801 +0000 @@ -3316,7 +3316,7 @@ ddg.o : ddg.c $(DDG_H) $(CONFIG_H) $(SYS $(DIAGNOSTIC_CORE_H) $(RTL_H) $(TM_P_H) $(REGS_H) $(FUNCTION_H) \ $(FLAGS_H) insn-config.h $(INSN_ATTR_H) $(EXCEPT_H) $(RECOG_H) \ $(SCHED_INT_H) $(CFGLAYOUT_H) $(CFGLOOP_H) $(EXPR_H) $(BITMAP_H) \ - hard-reg-set.h sbitmap.h $(TM_H) + hard-reg-set.h sbitmap.h $(TM_H) $(TREE_PASS_H) modulo-sched.o : modulo-sched.c $(DDG_H) $(CONFIG_H) $(CONFIG_H) $(SYSTEM_H) \ coretypes.h $(TARGET_H) $(DIAGNOSTIC_CORE_H) $(RTL_H) $(TM_P_H) $(REGS_H) $(FUNCTION_H) \ $(FLAGS_H) insn-config.h $(INSN_ATTR_H) $(EXCEPT_H) $(RECOG_H) \ Index: gcc/ddg.h =================================================================== --- gcc/ddg.h 2011-12-30 13:13:45.077544981 +0000 +++ gcc/ddg.h 2011-12-30 13:24:57.324195831 +0000 @@ -35,8 +35,7 @@ typedef struct ddg_scc *ddg_scc_ptr; typedef struct ddg_all_sccs *ddg_all_sccs_ptr; typedef enum {TRUE_DEP, OUTPUT_DEP, ANTI_DEP} dep_type; -typedef enum {REG_OR_MEM_DEP, REG_DEP, MEM_DEP, REG_AND_MEM_DEP} - dep_data_type; +typedef enum {REG_DEP, MEM_DEP} dep_data_type; /* The following two macros enables direct access to the successors and predecessors bitmaps held in each ddg_node. Do not make changes to @@ -44,6 +43,28 @@ typedef enum {REG_OR_MEM_DEP, REG_DEP, M #define NODE_SUCCESSORS(x) ((x)->successors) #define NODE_PREDECESSORS(x) ((x)->predecessors) +/* A structure that represents a memory read or write in the DDG; + context decides which. */ +struct ddg_mem_ref { + /* The previous reference of the same type (read or write) in the DDG. */ + struct ddg_mem_ref *prev; + + /* The DDG node that contains the memory reference. */ + ddg_node_ptr node; + + /* The memory reference itself. */ + rtx mem; + + /* If the address is a known induction variable, its value in iteration + I is given by: + + BASE + OFFSET + I * STEP + + In other cases BASE is null. */ + rtx base; + HOST_WIDE_INT offset, step; +}; + /* A structure that represents a node in the DDG. */ struct ddg_node { @@ -117,6 +138,11 @@ struct ddg /* Number of instructions in the basic block. */ int num_nodes; + /* The loads and stores in the BB, from the end of the block to + the beginning. */ + struct ddg_mem_ref *loads; + struct ddg_mem_ref *stores; + /* Number of load/store instructions in the BB - statistics. */ int num_loads; int num_stores; @@ -167,7 +193,9 @@ struct ddg_all_sccs }; -ddg_ptr create_ddg (basic_block, int closing_branch_deps); +struct loop; +ddg_ptr create_ddg (struct loop *, basic_block, int closing_branch_deps); +void add_edges_to_ddg (ddg_ptr); void free_ddg (ddg_ptr); void print_ddg (FILE *, ddg_ptr); @@ -188,4 +216,7 @@ int longest_simple_path (ddg_ptr, int fr bool autoinc_var_is_used_p (rtx, rtx); +/* The maximum allowable distance on a DDG edge. */ +#define MAX_DDG_DISTANCE INT_MAX + #endif /* GCC_DDG_H */ Index: gcc/ddg.c =================================================================== --- gcc/ddg.c 2011-12-30 13:13:45.077544981 +0000 +++ gcc/ddg.c 2011-12-30 13:36:35.005498271 +0000 @@ -43,6 +43,7 @@ Software Foundation; either version 3, o #include "expr.h" #include "bitmap.h" #include "ddg.h" +#include "tree-pass.h" #ifdef INSN_SCHEDULING @@ -61,88 +62,102 @@ static ddg_edge_ptr create_ddg_edge (ddg dep_data_type, int, int); static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr); -/* Auxiliary variable for mem_read_insn_p/mem_write_insn_p. */ -static bool mem_ref_p; +/* Create a memory reference record for MEM, which occurs in NODE. + PREV is the previous reference of the same type. */ +static struct ddg_mem_ref * +create_mem_ref (struct ddg_mem_ref *prev, ddg_node_ptr node, rtx mem) +{ + struct ddg_mem_ref *entry; + enum machine_mode pmode; + struct rtx_iv iv; + rtx x; + + entry = XCNEW (struct ddg_mem_ref); + entry->prev = prev; + entry->node = node; + entry->mem = mem; + + pmode = targetm.addr_space.address_mode (MEM_ADDR_SPACE (mem)); + if (iv_analyze_expr (node->insn, XEXP (mem, 0), pmode, &iv) + && iv.extend == UNKNOWN + && CONST_INT_P (iv.step)) + { + x = iv.base; + if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) + { + entry->base = XEXP (x, 0); + entry->offset = INTVAL (XEXP (x, 1)); + } + else + { + entry->base = x; + entry->offset = 0; + } + entry->step = INTVAL (iv.step); + } -/* Auxiliary function for mem_read_insn_p. */ -static int -mark_mem_use (rtx *x, void *data ATTRIBUTE_UNUSED) -{ - if (MEM_P (*x)) - mem_ref_p = true; - return 0; + if (dump_file) + { + fprintf (dump_file, "Found memory reference in insn %d:\n", + INSN_UID (node->insn)); + print_rtl (dump_file, mem); + if (entry->base) + { + fprintf (dump_file, "\nwith base:"); + print_rtl (dump_file, entry->base); + fprintf (dump_file, "\noffset " HOST_WIDE_INT_PRINT_DEC + " and step " HOST_WIDE_INT_PRINT_DEC "\n\n", + entry->offset, entry->step); + } + else + fprintf (dump_file, "\nwhich isn't a recognized iv\n\n"); + } + return entry; } -/* Auxiliary function for mem_read_insn_p. */ -static void -mark_mem_use_1 (rtx *x, void *data) -{ - for_each_rtx (x, mark_mem_use, data); -} +/* A structure for pairing a node and the graph to which it belongs. */ +struct graph_and_node { + ddg_ptr g; + ddg_node_ptr node; +}; -/* Returns nonzero if INSN reads from memory. */ -static bool -mem_read_insn_p (rtx insn) +/* A for_each_rtx callback. Record all loads in an instruction. + DATA points to a graph_and_node. */ +static int +record_loads_1 (rtx *loc, void *data) { - mem_ref_p = false; - note_uses (&PATTERN (insn), mark_mem_use_1, NULL); - return mem_ref_p; -} + struct graph_and_node *gn; -static void -mark_mem_store (rtx loc, const_rtx setter ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED) -{ - if (MEM_P (loc)) - mem_ref_p = true; + if (MEM_P (*loc)) + { + gn = (struct graph_and_node *) data; + gn->g->loads = create_mem_ref (gn->g->loads, gn->node, *loc); + gn->g->num_loads++; + } + return 0; } -/* Returns nonzero if INSN writes to memory. */ -static bool -mem_write_insn_p (rtx insn) +/* A note_uses callback. Record all loads in an instruction. + DATA points to a graph_and_node. */ +static void +record_loads (rtx *loc, void *data) { - mem_ref_p = false; - note_stores (PATTERN (insn), mark_mem_store, NULL); - return mem_ref_p; + for_each_rtx (loc, record_loads_1, data); } -/* Returns nonzero if X has access to memory. */ -static bool -rtx_mem_access_p (rtx x) +/* A note_stores callback. Record all stores in an instruction. + DATA points to a graph_and_node. */ +static void +record_stores (rtx x, const_rtx setter ATTRIBUTE_UNUSED, void *data) { - int i, j; - const char *fmt; - enum rtx_code code; - - if (x == 0) - return false; + struct graph_and_node *gn; if (MEM_P (x)) - return true; - - code = GET_CODE (x); - fmt = GET_RTX_FORMAT (code); - for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) { - if (fmt[i] == 'e') - { - if (rtx_mem_access_p (XEXP (x, i))) - return true; - } - else if (fmt[i] == 'E') - for (j = 0; j < XVECLEN (x, i); j++) - { - if (rtx_mem_access_p (XVECEXP (x, i, j))) - return true; - } + gn = (struct graph_and_node *) data; + gn->g->stores = create_mem_ref (gn->g->stores, gn->node, x); + gn->g->num_stores++; } - return false; -} - -/* Returns nonzero if INSN reads to or writes from memory. */ -static bool -mem_access_insn_p (rtx insn) -{ - return rtx_mem_access_p (PATTERN (insn)); } /* Return true if DEF_INSN contains address being auto-inc or auto-dec @@ -175,9 +190,6 @@ create_ddg_dep_from_intra_loop_link (ddg ddg_edge_ptr e; int latency, distance = 0; dep_type t = TRUE_DEP; - dep_data_type dt = (mem_access_insn_p (src_node->insn) - && mem_access_insn_p (dest_node->insn) ? MEM_DEP - : REG_DEP); gcc_assert (src_node->cuid < dest_node->cuid); gcc_assert (link); @@ -201,7 +213,7 @@ create_ddg_dep_from_intra_loop_link (ddg TODO: support the removal of all anti-deps edges, i.e. including those whose register has multiple defs in the loop. */ if (flag_modulo_sched_allow_regmoves - && (t == ANTI_DEP && dt == REG_DEP) + && t == ANTI_DEP && !autoinc_var_is_used_p (dest_node->insn, src_node->insn)) { rtx set; @@ -224,7 +236,7 @@ create_ddg_dep_from_intra_loop_link (ddg } latency = dep_cost (link); - e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance); + e = create_ddg_edge (src_node, dest_node, t, REG_DEP, latency, distance); add_edge_to_ddg (g, e); } @@ -380,107 +392,6 @@ build_inter_loop_deps (ddg_ptr g) } } - -static int -walk_mems_2 (rtx *x, rtx mem) -{ - if (MEM_P (*x)) - { - if (may_alias_p (*x, mem)) - return 1; - - return -1; - } - return 0; -} - -static int -walk_mems_1 (rtx *x, rtx *pat) -{ - if (MEM_P (*x)) - { - /* Visit all MEMs in *PAT and check indepedence. */ - if (for_each_rtx (pat, (rtx_function) walk_mems_2, *x)) - /* Indicate that dependence was determined and stop traversal. */ - return 1; - - return -1; - } - return 0; -} - -/* Return 1 if two specified instructions have mem expr with conflict alias sets*/ -static int -insns_may_alias_p (rtx insn1, rtx insn2) -{ - /* For each pair of MEMs in INSN1 and INSN2 check their independence. */ - return for_each_rtx (&PATTERN (insn1), (rtx_function) walk_mems_1, - &PATTERN (insn2)); -} - -/* Given two nodes, analyze their RTL insns and add intra-loop mem deps - to ddg G. */ -static void -add_intra_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to) -{ - - if ((from->cuid == to->cuid) - || !insns_may_alias_p (from->insn, to->insn)) - /* Do not create edge if memory references have disjoint alias sets - or 'to' and 'from' are the same instruction. */ - return; - - if (mem_write_insn_p (from->insn)) - { - if (mem_read_insn_p (to->insn)) - create_ddg_dep_no_link (g, from, to, - DEBUG_INSN_P (to->insn) - ? ANTI_DEP : TRUE_DEP, MEM_DEP, 0); - else - create_ddg_dep_no_link (g, from, to, - DEBUG_INSN_P (to->insn) - ? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 0); - } - else if (!mem_read_insn_p (to->insn)) - create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 0); -} - -/* Given two nodes, analyze their RTL insns and add inter-loop mem deps - to ddg G. */ -static void -add_inter_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to) -{ - if (!insns_may_alias_p (from->insn, to->insn)) - /* Do not create edge if memory references have disjoint alias sets. */ - return; - - if (mem_write_insn_p (from->insn)) - { - if (mem_read_insn_p (to->insn)) - create_ddg_dep_no_link (g, from, to, - DEBUG_INSN_P (to->insn) - ? ANTI_DEP : TRUE_DEP, MEM_DEP, 1); - else if (from->cuid != to->cuid) - create_ddg_dep_no_link (g, from, to, - DEBUG_INSN_P (to->insn) - ? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 1); - } - else - { - if (mem_read_insn_p (to->insn)) - return; - else if (from->cuid != to->cuid) - { - create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 1); - if (DEBUG_INSN_P (from->insn) || DEBUG_INSN_P (to->insn)) - create_ddg_dep_no_link (g, to, from, ANTI_DEP, MEM_DEP, 1); - else - create_ddg_dep_no_link (g, to, from, TRUE_DEP, MEM_DEP, 1); - } - } - -} - /* Perform intra-block Data Dependency analysis and connect the nodes in the DDG. We assume the loop has a single basic block. */ static void @@ -493,6 +404,9 @@ build_intra_loop_deps (ddg_ptr g) /* Build the dependence information, using the sched_analyze function. */ init_deps_global (); + /* Ignore the usual dependencies between two MEM rtxes. We still rely + on sched_analyze to handle memory barriers and the like. */ + sched_deps_info->note_mem_dep = 0; init_deps (&tmp_deps, false); /* Do the intra-block data dependence analysis for the given block. */ @@ -519,37 +433,6 @@ build_intra_loop_deps (ddg_ptr g) create_ddg_dep_from_intra_loop_link (g, src_node, dest_node, dep); } - - /* If this insn modifies memory, add an edge to all insns that access - memory. */ - if (mem_access_insn_p (dest_node->insn)) - { - int j; - - for (j = 0; j <= i; j++) - { - ddg_node_ptr j_node = &g->nodes[j]; - if (DEBUG_INSN_P (j_node->insn)) - continue; - if (mem_access_insn_p (j_node->insn)) - { - /* Don't bother calculating inter-loop dep if an intra-loop dep - already exists. */ - if (! TEST_BIT (dest_node->successors, j)) - add_inter_loop_mem_dep (g, dest_node, j_node); - /* If -fmodulo-sched-allow-regmoves - is set certain anti-dep edges are not created. - It might be that these anti-dep edges are on the - path from one memory instruction to another such that - removing these edges could cause a violation of the - memory dependencies. Thus we add intra edges between - every two memory instructions in this case. */ - if (flag_modulo_sched_allow_regmoves - && !TEST_BIT (dest_node->predecessors, j)) - add_intra_loop_mem_dep (g, j_node, dest_node); - } - } - } } /* Free the INSN_LISTs. */ @@ -560,13 +443,187 @@ build_intra_loop_deps (ddg_ptr g) sched_free_deps (head, tail, false); } +/* Given a "source" memory reference from iteration 0 and a "target" + memory reference from iteration BASE_DISTANCE, return the first + N >= BASE_DISTANCE such that the source reference in iteration 0 + overlaps the target reference in iteration N. + + FROM_OFFSET is the offset of the source reference from an unspecified + base, while TO_OFFSET is the offset of the target reference from that + same base. FROM_SIZE and TO_SIZE are the sizes of the two references + in bytes. + + PMODE is the mode of both addresses, and STEP is the amount that + will be added to each address by one loop iteration. */ +static int +measure_mem_distance (enum machine_mode pmode, + unsigned HOST_WIDE_INT from_offset, + unsigned HOST_WIDE_INT from_size, + unsigned HOST_WIDE_INT to_offset, + unsigned HOST_WIDE_INT to_size, + unsigned HOST_WIDE_INT base_distance, + HOST_WIDE_INT step) +{ + unsigned HOST_WIDE_INT extra, from2to, to2from; + + from2to = (to_offset - from_offset) & GET_MODE_MASK (pmode); + to2from = (from_offset - to_offset) & GET_MODE_MASK (pmode); + if (from2to < from_size || to2from < to_size) + /* The source reference in iteration 0 overlaps the target reference + in iteration BASE_DISTANCE. The check is written this way to cope + with cases where offset + size overflows. */ + return base_distance; + + /* N > BASE_DISTANCE. To cope more easily with cases where the round-up + divisions: + + (to2from - (to_size - 1) + (step - 1)) / step + (from2to - (from_size - 1) + (step - 1)) / step + + would overflow, bump BASE_DISTANCE and subtract STEP from each + dividend to compensate. */ + base_distance++; + if (step > 0) + extra = (to2from - to_size) / (unsigned HOST_WIDE_INT) step; + else + extra = (from2to - from_size) / (unsigned HOST_WIDE_INT) -step; + if (extra > MAX_DDG_DISTANCE || base_distance + extra > MAX_DDG_DISTANCE) + return MAX_DDG_DISTANCE; + return base_distance + extra; +} + +/* If FROM and TO might alias, record memory dependencies: + + FROM--(FORWARD_TYPE)-->TO + and TO--(BACKWARD_TYPE)-->FROM + + FROM comes before TO in the original loop, and both belong to G. + FORWARD_DISTANCE is the minimum distance of the FROM--->TO dependence. */ +static void +add_memory_dep (ddg_ptr g, struct ddg_mem_ref *from, + struct ddg_mem_ref *to, dep_type forward_type, + dep_type backward_type, int forward_distance) +{ + HOST_WIDE_INT step; + unsigned HOST_WIDE_INT from_size, to_size, to_disp, abs_step, future_offset; + enum machine_mode pmode; + int backward_distance; + + gcc_checking_assert (from->node->cuid < to->node->cuid); + + if (!may_alias_p (from->mem, to->mem)) + return; + + /* In the worst case, the TO---->FROM edge has a distance of 1. */ + backward_distance = 1; + + /* See if we can get more accurate distances. Look for cases where + the addresses of FROM and TO are ivs with the same base and step. */ + if (from->base + && to->base + && from->step + && from->step == to->step + && !MEM_VOLATILE_P (from->mem) + && !MEM_VOLATILE_P (to->mem) + && MEM_SIZE_KNOWN_P (from->mem) + && MEM_SIZE_KNOWN_P (to->mem) + && MEM_ADDR_SPACE (from->mem) == MEM_ADDR_SPACE (to->mem) + && rtx_equal_p (from->base, to->base)) + { + step = to->step; + abs_step = (step < 0 ? -step : step); + from_size = MEM_SIZE (from->mem); + to_size = MEM_SIZE (to->mem); + + /* If the step is a power of two, or the negative of a power of two, + see whether we can prove that the references never overlap. */ + if (abs_step == (abs_step & -abs_step)) + { + to_disp = (to->offset - from->offset) % abs_step; + if (from_size <= to_disp && to_disp + to_size <= abs_step) + return; + } + + pmode = targetm.addr_space.address_mode (MEM_ADDR_SPACE (to->mem)); + future_offset = to->offset + forward_distance * step; + forward_distance = measure_mem_distance (pmode, + from->offset, from_size, + future_offset, to_size, + forward_distance, step); + future_offset = from->offset + backward_distance * step; + backward_distance = measure_mem_distance (pmode, + to->offset, to_size, + future_offset, from_size, + backward_distance, step); + } + + if (DEBUG_INSN_P (from->node->insn) || DEBUG_INSN_P (to->node->insn)) + { + forward_type = ANTI_DEP; + backward_type = ANTI_DEP; + } + create_ddg_dep_no_link (g, from->node, to->node, forward_type, MEM_DEP, + forward_distance); + create_ddg_dep_no_link (g, to->node, from->node, backward_type, MEM_DEP, + backward_distance); +} + +/* Make REF2 iterate over all entries in ddg_mem_ref list LIST + that come later than ddg_mem_ref REF1. */ +#define FOR_EACH_LATER_MEM_REF(REF2, REF1, LIST) \ + for (REF2 = (LIST); \ + REF2 && REF2->node->cuid > REF1->node->cuid; \ + REF2 = REF2->prev) + +/* Check for dependencies between pairs of memory rtxes. */ +static void +build_memory_deps (ddg_ptr g) +{ + struct ddg_mem_ref *ref1, *ref2; + int distance; + + for (ref1 = g->loads; ref1; ref1 = ref1->prev) + { + /* LOAD--->LOAD. */ + if (MEM_VOLATILE_P (ref1->mem)) + FOR_EACH_LATER_MEM_REF (ref2, ref1, g->loads) + if (MEM_VOLATILE_P (ref2->mem)) + add_memory_dep (g, ref1, ref2, ANTI_DEP, ANTI_DEP, 0); + + /* LOAD--->STORE. */ + FOR_EACH_LATER_MEM_REF (ref2, ref1, g->stores) + { + distance = anti_dependence (ref1->mem, ref2->mem) ? 0 : 1; + add_memory_dep (g, ref1, ref2, ANTI_DEP, TRUE_DEP, distance); + } + } + + for (ref1 = g->stores; ref1; ref1 = ref1->prev) + { + /* STORE--->LOAD. */ + FOR_EACH_LATER_MEM_REF (ref2, ref1, g->loads) + { + distance = true_dependence (ref1->mem, VOIDmode, + ref2->mem, rtx_varies_p) ? 0 : 1; + add_memory_dep (g, ref1, ref2, TRUE_DEP, ANTI_DEP, distance); + } + + /* STORE--->STORE. */ + FOR_EACH_LATER_MEM_REF (ref2, ref1, g->stores) + { + distance = output_dependence (ref1->mem, ref2->mem) ? 0 : 1; + add_memory_dep (g, ref1, ref2, OUTPUT_DEP, OUTPUT_DEP, distance); + } + } +} -/* Given a basic block, create its DDG and return a pointer to a variable - of ddg type that represents it. +/* Given a basic block, create the nodes of its DDG and return a pointer + to a variable of ddg type that represents it. Initialize the ddg structure fields to the appropriate values. */ ddg_ptr -create_ddg (basic_block bb, int closing_branch_deps) +create_ddg (struct loop *loop, basic_block bb, int closing_branch_deps) { + struct graph_and_node gn; ddg_ptr g; rtx insn, first_note; int i; @@ -586,13 +643,6 @@ create_ddg (basic_block bb, int closing_ if (DEBUG_INSN_P (insn)) g->num_debug++; - else - { - if (mem_read_insn_p (insn)) - g->num_loads++; - if (mem_write_insn_p (insn)) - g->num_stores++; - } num_nodes++; } @@ -603,6 +653,8 @@ create_ddg (basic_block bb, int closing_ return NULL; } + iv_analysis_loop_init (loop); + /* Allocate the nodes array, and initialize the nodes. */ g->num_nodes = num_nodes; g->nodes = (ddg_node_ptr) xcalloc (num_nodes, sizeof (struct ddg_node)); @@ -637,18 +689,31 @@ create_ddg (basic_block bb, int closing_ g->nodes[i].predecessors = sbitmap_alloc (num_nodes); sbitmap_zero (g->nodes[i].predecessors); g->nodes[i].first_note = (first_note ? first_note : insn); - g->nodes[i++].insn = insn; + g->nodes[i].insn = insn; first_note = NULL_RTX; + + gn.g = g; + gn.node = &g->nodes[i]; + note_uses (&PATTERN (insn), record_loads, &gn); + note_stores (PATTERN (insn), record_stores, &gn); + + i++; } /* We must have found a branch in DDG. */ gcc_assert (g->closing_branch); + return g; +} +/* Add the edges to a DDG that was previously created by create_ddg. + This function relies on scheduler dependencies. */ - /* Build the data dependency graph. */ +void +add_edges_to_ddg (ddg_ptr g) +{ build_intra_loop_deps (g); build_inter_loop_deps (g); - return g; + build_memory_deps (g); } /* Free all the memory allocated for the DDG. */ Index: gcc/modulo-sched.c =================================================================== --- gcc/modulo-sched.c 2011-12-30 13:13:45.077544981 +0000 +++ gcc/modulo-sched.c 2011-12-30 13:24:57.327195816 +0000 @@ -345,6 +345,38 @@ ps_num_consecutive_stages (partial_sched return ps_reg_move (ps, id)->num_consecutive_stages; } +/* Perform a saturating multiplication of nonnegative values A and B. */ + +static inline int +sat_mulpp (unsigned int a, unsigned int b) +{ + if ((unsigned int) INT_MAX / b <= a) + return INT_MAX; + else + return a * b; +} + +/* Perform a saturating addition of signed value A and nonnegative value B. */ + +static inline int +sat_addsp (int a, int b) +{ + if (INT_MAX - b <= a) + return INT_MAX; + return a + b; +} + +/* Perform a saturating subtraction of signed value A and nonnegative + value B. */ + +static inline int +sat_subsp (int a, int b) +{ + if (INT_MIN + b >= a) + return INT_MIN; + return a - b; +} + /* Given HEAD and TAIL which are the first and last insns in a loop; return the register which controls the loop. Return zero if it has more than one occurrence in the loop besides the control part or the @@ -709,7 +741,9 @@ schedule_reg_moves (partial_schedule_ptr ranges started at u (excluding self-loops). */ distances[0] = distances[1] = false; for (e = u->out; e; e = e->next_out) - if (e->type == TRUE_DEP && e->dest != e->src) + if (e->data_type == REG_DEP + && e->type == TRUE_DEP + && e->dest != e->src) { int nreg_moves4e = (SCHED_TIME (e->dest->cuid) - SCHED_TIME (e->src->cuid)) / ii; @@ -781,7 +815,9 @@ schedule_reg_moves (partial_schedule_ptr copy of this register, depending on the time the use is scheduled. Record which uses require which move results. */ for (e = u->out; e; e = e->next_out) - if (e->type == TRUE_DEP && e->dest != e->src) + if (e->data_type == REG_DEP + && e->type == TRUE_DEP + && e->dest != e->src) { int dest_copy = (SCHED_TIME (e->dest->cuid) - SCHED_TIME (e->src->cuid)) / ii; @@ -1355,6 +1391,7 @@ sms_schedule (void) basic_block condition_bb = NULL; edge latch_edge; gcov_type trip_count = 0; + int num_ddgs; loop_optimizer_init (LOOPS_HAVE_PREHEADERS | LOOPS_HAVE_RECORDED_EXITS); @@ -1364,34 +1401,19 @@ sms_schedule (void) return; /* There are no loops to schedule. */ } - /* Initialize issue_rate. */ - if (targetm.sched.issue_rate) - { - int temp = reload_completed; - - reload_completed = 1; - issue_rate = targetm.sched.issue_rate (); - reload_completed = temp; - } - else - issue_rate = 1; - - /* Initialize the scheduler. */ - setup_sched_infos (); - haifa_sched_init (); - /* Allocate memory to hold the DDG array one entry for each loop. We use loop->num as index into this array. */ g_arr = XCNEWVEC (ddg_ptr, number_of_loops ()); if (dump_file) - { - fprintf (dump_file, "\n\nSMS analysis phase\n"); - fprintf (dump_file, "===================\n\n"); - } + { + fprintf (dump_file, "\n\nSMS loop discovery phase\n"); + fprintf (dump_file, "========================\n\n"); + } /* Build DDGs for all the relevant loops and hold them in G_ARR indexed by the loop index. */ + num_ddgs = 0; FOR_EACH_LOOP (li, loop, 0) { rtx head, tail; @@ -1512,7 +1534,7 @@ sms_schedule (void) instructions. The branch is rotated to be in row ii-1 at the end of the scheduling procedure to make sure it's the last instruction in the iteration. */ - if (! (g = create_ddg (bb, 1))) + if (! (g = create_ddg (loop, bb, 1))) { if (dump_file) fprintf (dump_file, "SMS create_ddg failed\n"); @@ -1523,12 +1545,38 @@ sms_schedule (void) if (dump_file) fprintf (dump_file, "...OK\n"); + num_ddgs++; + } + iv_analysis_done (); + + if (num_ddgs == 0) + { + if (dump_file) + fprintf (dump_file, "No suitable loops\n"); + goto done; } + + /* Initialize issue_rate. */ + if (targetm.sched.issue_rate) + { + int temp = reload_completed; + + reload_completed = 1; + issue_rate = targetm.sched.issue_rate (); + reload_completed = temp; + } + else + issue_rate = 1; + + /* Initialize the scheduler. */ + setup_sched_infos (); + haifa_sched_init (); + if (dump_file) - { - fprintf (dump_file, "\nSMS transformation phase\n"); - fprintf (dump_file, "=========================\n\n"); - } + { + fprintf (dump_file, "\nSMS transformation phase\n"); + fprintf (dump_file, "=========================\n\n"); + } /* We don't want to perform SMS on new loops - created by versioning. */ FOR_EACH_LOOP (li, loop, 0) @@ -1542,6 +1590,8 @@ sms_schedule (void) if (! (g = g_arr[loop->num])) continue; + add_edges_to_ddg (g); + if (dump_file) { rtx insn = BB_END (loop->header); @@ -1754,10 +1804,12 @@ sms_schedule (void) free_ddg (g); } - free (g_arr); - /* Release scheduler data, needed until now because of DFA. */ haifa_sched_finish (); + + done: + free (g_arr); + loop_optimizer_finalize (); } @@ -1844,6 +1896,7 @@ #define DFA_HISTORY SMS_DFA_HISTORY /* A threshold for the number of repeated unsuccessful attempts to insert an empty row, before we flush the partial schedule and start over. */ #define MAX_SPLIT_NUM 10 + /* Given the partial schedule PS, this function calculates and returns the cycles in which we can schedule the node with the given index I. NOTE: Here we do the backtracking in SMS, in some special cases. We have @@ -1896,7 +1949,7 @@ get_sched_window (partial_schedule_ptr p fprintf (dump_file, "=========== =========== =========== ===========" " =====\n"); } - /* Calculate early_start and limit end. Both bounds are inclusive. */ + /* Calculate early_start and limit start. Both bounds are inclusive. */ if (psp_not_empty) for (e = u_node->in; e != 0; e = e->next_in) { @@ -1905,26 +1958,36 @@ get_sched_window (partial_schedule_ptr p if (TEST_BIT (sched_nodes, v)) { int p_st = SCHED_TIME (v); - int earliest = p_st + e->latency - (e->distance * ii); - int latest = (e->data_type == MEM_DEP ? p_st + ii - 1 : INT_MAX); + int earliest = sat_subsp (sat_addsp (p_st, e->latency), + sat_mulpp (e->distance, ii)); + if (e->data_type == MEM_DEP) + { + start = MAX (start, earliest); + if (dump_file) + fprintf (dump_file, "%11d %11s %11s %11s", + earliest, "", "", ""); + } + else + { + early_start = MAX (early_start, earliest); + if (dump_file) + fprintf (dump_file, "%11s %11d %11s %11s", + "", earliest, "", ""); + } if (dump_file) { - fprintf (dump_file, "%11s %11d %11s %11d %5d", - "", earliest, "", latest, p_st); + fprintf (dump_file, " %5d", p_st); print_ddg_edge (dump_file, e); fprintf (dump_file, "\n"); } - early_start = MAX (early_start, earliest); - end = MIN (end, latest); - if (e->type == TRUE_DEP && e->data_type == REG_DEP) count_preds++; } } - /* Calculate late_start and limit start. Both bounds are inclusive. */ + /* Calculate late_start and limit end. Both bounds are inclusive. */ if (pss_not_empty) for (e = u_node->out; e != 0; e = e->next_out) { @@ -1933,20 +1996,30 @@ get_sched_window (partial_schedule_ptr p if (TEST_BIT (sched_nodes, v)) { int s_st = SCHED_TIME (v); - int earliest = (e->data_type == MEM_DEP ? s_st - ii + 1 : INT_MIN); - int latest = s_st - e->latency + (e->distance * ii); + int latest = sat_addsp (sat_subsp (s_st, e->latency), + sat_mulpp (e->distance, ii)); + if (e->data_type == MEM_DEP) + { + end = MIN (end, latest); + if (dump_file) + fprintf (dump_file, "%11s %11s %11s %11d", + "", "", "", latest); + } + else + { + late_start = MIN (late_start, latest); + if (dump_file) + fprintf (dump_file, "%11s %11s %11d %11s", + "", "", latest, ""); + } if (dump_file) { - fprintf (dump_file, "%11d %11s %11d %11s %5d", - earliest, "", latest, "", s_st); + fprintf (dump_file, " %5d", s_st); print_ddg_edge (dump_file, e); fprintf (dump_file, "\n"); } - start = MAX (start, earliest); - late_start = MIN (late_start, latest); - if (e->type == TRUE_DEP && e->data_type == REG_DEP) count_succs++; } @@ -1963,14 +2036,22 @@ get_sched_window (partial_schedule_ptr p /* Get a target scheduling window no bigger than ii. */ if (early_start == INT_MIN && late_start == INT_MAX) - early_start = NODE_ASAP (u_node); - else if (early_start == INT_MIN) - early_start = late_start - (ii - 1); - late_start = MIN (late_start, early_start + (ii - 1)); - - /* Apply memory dependence limits. */ - start = MAX (start, early_start); - end = MIN (end, late_start); + { + /* The default window (as given in the paper) is based on + the node's ASAP value, but shift or shrink it as necessary + in order to honor memory dependencies. */ + early_start = MIN (NODE_ASAP (u_node), end - (ii - 1)); + start = MAX (early_start, start); + } + else + { + end = MIN (end, late_start); + if (early_start == INT_MIN) + start = MAX (start, end - (ii - 1)); + else + start = MAX (start, early_start); + } + end = MIN (end, start + (ii - 1)); if (dump_file && (psp_not_empty || pss_not_empty)) fprintf (dump_file, "%11s %11d %11d %11s %5s final window\n", @@ -2060,8 +2141,8 @@ calculate_must_precede_follow (ddg_node_ SCHED_TIME (e->src) - (e->distance * ii) == first_cycle_in_window */ for (e = u_node->in; e != 0; e = e->next_in) if (TEST_BIT (sched_nodes, e->src->cuid) - && ((SCHED_TIME (e->src->cuid) - (e->distance * ii)) == - first_cycle_in_window)) + && (sat_subsp (SCHED_TIME (e->src->cuid), sat_mulpp (e->distance, ii)) + == first_cycle_in_window)) { if (dump_file) fprintf (dump_file, "%d ", e->src->cuid); @@ -2371,7 +2452,8 @@ compute_split_row (sbitmap sched_nodes, int v = e->src->cuid; if (TEST_BIT (sched_nodes, v) - && (low == SCHED_TIME (v) + e->latency - (e->distance * ii))) + && low == sat_subsp (sat_addsp (SCHED_TIME (v), e->latency), + sat_mulpp (e->distance, ii))) if (SCHED_TIME (v) > lower) { crit_pred = v;

13 years, 5 months

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Update to lp:~rsandifo/+junk/loop-microbenchmarks

by Richard Sandiford

About three months ago, 4.7 stopped being able to optimise things like: int *__restrict x = ...; The (libav) loop microbenchmarks that I'd written used this construct a lot, as an easy way of automatically generating a whole function from a loop kernel. I spent a while testing 4.7 with the restrict patch reverted, while I caught up with my post-holiday email backlog and saw whether the effect on this code was deliberate. I eventually realised it was, so implemented a change that Ira had suggested: splitting out a peak_loop_1 that takes all the restrict pointers as arguments. I just realised that I never pushed that change back up to bzr, so I've done it now. Probably a write-only change, since I doubt anyone's going to be using the benchmark again, but just in case :-) Richard

13 years, 5 months

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Patch drop: auto-inc-dec.c rewrite

by Richard Sandiford

This is my current 4.7 auto-inc-dec.c patch. I submitted an RFC in July: http://article.gmane.org/gmane.comp.gcc.patches/241779/ and updated the patch in line with the feedback I got. Steven Bosscher sent some very useful comments in private email, so the update deals with those as well as Bernd's public ones. If we do go ahead with this rewrite, it depends on the A9 pipeline description changes. I submitted some A8 and A9 changes here: http://article.gmane.org/gmane.comp.gcc.patches/244238/ http://article.gmane.org/gmane.comp.gcc.patches/244242/ but because I later noticed that the A9 didn't behave quite as I thought, I decided not to apply them. Ramana asked around internally about what the A9 actually does (thanks) and had some ideas. The patch also relies on the MEM rtx_costs patch that I just posted: http://lists.linaro.org/pipermail/linaro-toolchain/2011-December/001944.html Richard gcc/ * Makefile.in (auto-inc-dec.o): Depends on $(OPTABS_H) and addresses.h. * auto-inc-dec.c: Rewrite. Index: gcc/Makefile.in =================================================================== --- gcc/Makefile.in 2011-12-07 11:43:29.549238252 +0000 +++ gcc/Makefile.in 2011-12-29 09:24:51.066303201 +0000 @@ -3145,7 +3145,8 @@ alloc-pool.o : alloc-pool.c $(CONFIG_H) auto-inc-dec.o : auto-inc-dec.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(TREE_H) $(RTL_H) $(TM_P_H) hard-reg-set.h $(BASIC_BLOCK_H) insn-config.h \ $(REGS_H) $(FLAGS_H) output.h $(FUNCTION_H) $(EXCEPT_H) $(DIAGNOSTIC_CORE_H) $(RECOG_H) \ - $(EXPR_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) $(TARGET_H) + $(EXPR_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) $(TARGET_H) \ + $(OPTABS_H) addresses.h cfg.o : cfg.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(FLAGS_H) \ $(REGS_H) hard-reg-set.h output.h $(DIAGNOSTIC_CORE_H) $(FUNCTION_H) $(EXCEPT_H) $(GGC_H) \ $(TM_P_H) $(TIMEVAR_H) $(OBSTACK_H) $(TREE_H) alloc-pool.h \

13 years, 5 months

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Patch drop: Rework MEM rtx_costs

by Richard Sandiford

I originally wrote this patch as part of the auto-inc-dec work. I didn't submit it because I wasn't sure what value of extra_writeback_latency was appropriate for A9. (I was hoping to crib it from Ramana's pipeline description.) The patch introduces three new fields to the costs structure: one to control the latency of core loads, one to control the latency of NEON loads, and one to control the penalty of address writeback. The patch includes a tweak for cases where we use two VLDRs. That part should obviously be dropped if we change the move patterns to use something else. Richard gcc/ * config/arm/arm-protos.h (tune_params): Add core_mem_latency, neon_mem_latency and extra_writeback_latency. * config/arm/arm.c (arm_slowmul_tune, arm_fastmul_tune) (arm_strongarm_tune, arm_xscale_tune, arm_9e_tune, arm_v6t2_tune) (arm_cortex_tune, arm_cortex_a5_tune, arm_cortex_a9_tune) (arm_fa726te_tune): Populate the new tune_params fields. (arm_mem_cost): New function. (arm_rtx_costs_1): Use it. Index: gcc/config/arm/arm-protos.h =================================================================== --- gcc/config/arm/arm-protos.h 2011-08-09 15:01:14.000000000 +0100 +++ gcc/config/arm/arm-protos.h 2011-08-09 15:04:58.121984034 +0100 @@ -236,6 +236,9 @@ struct tune_params int l1_cache_size; int l1_cache_line_size; bool prefer_constant_pool; + int core_mem_latency; + int neon_mem_latency; + int extra_writeback_latency; int (*branch_cost) (bool, bool); }; Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c 2011-08-09 15:01:14.000000000 +0100 +++ gcc/config/arm/arm.c 2011-08-09 15:07:07.215103271 +0100 @@ -840,6 +840,9 @@ const struct tune_params arm_slowmul_tun 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -851,6 +854,9 @@ const struct tune_params arm_fastmul_tun 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -865,6 +871,9 @@ const struct tune_params arm_strongarm_t 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -876,6 +885,9 @@ const struct tune_params arm_xscale_tune 3, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -887,6 +899,9 @@ const struct tune_params arm_9e_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -898,6 +913,9 @@ const struct tune_params arm_v6t2_tune = 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -910,6 +928,9 @@ const struct tune_params arm_cortex_tune 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ + 2, + 2, + 1, arm_default_branch_cost }; @@ -924,6 +945,9 @@ const struct tune_params arm_cortex_a5_t 1, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ + 2, + 2, + 0, arm_cortex_a5_branch_cost }; @@ -935,6 +959,9 @@ const struct tune_params arm_cortex_a9_t 5, /* Max cond insns. */ ARM_PREFETCH_BENEFICIAL(4,32,32), false, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -946,6 +973,9 @@ const struct tune_params arm_fa726te_tun 5, /* Max cond insns. */ ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ + 2, + 2, + 0, arm_default_branch_cost }; @@ -6848,6 +6878,41 @@ thumb1_rtx_costs (rtx x, enum rtx_code c } } +/* Return the cost in insns of a memory reference of mode MODE to + address ADDR. */ + +static int +arm_mem_cost (enum machine_mode mode, rtx addr) +{ + int count, base; + + count = ARM_NUM_REGS (mode); + if (TARGET_NEON + && (VALID_NEON_DREG_MODE (mode) + || VALID_NEON_QREG_MODE (mode) + || VALID_NEON_STRUCT_MODE (mode))) + { + base = current_tune->neon_mem_latency; + + if (count == 4 && (GET_CODE (addr) == PLUS || CONSTANT_P (addr))) + /* In this case we use two VLDRs. */ + return COSTS_N_INSNS (base + 2); + + /* Assume that one quad can be accessed each cycle. */ + return COSTS_N_INSNS (base + (count + 3) / 4); + } + + base = current_tune->core_mem_latency; + + if (count == 1 && GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC) + /* On some targets (like A8), core accesses chained by address + register writeback cannot issue in consecutive cycles. + Pessimize writeback to account for this. */ + base += current_tune->extra_writeback_latency; + + return COSTS_N_INSNS (base + count); +} + static inline bool arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) { @@ -6860,9 +6925,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou switch (code) { case MEM: - /* Memory costs quite a lot for the first word, but subsequent words - load at the equivalent of a single insn each. */ - *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode)); + *total = arm_mem_cost (mode, XEXP (x, 0)); return true; case DIV:

13 years, 5 months

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Goodbye

by Ira Rosen

Hi, Thank you all for an interesting and pleasant experience. I am very grateful to Linaro for the opportunity to meet and work with such an amazing group of people. I wish you all the best, and hope to meet you again (at least online). You can find me at irar(a)il.ibm.com or ira.rsn(a)gmail.com. Ira

13 years, 5 months

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[ACTIVITY] WW51

by Zhenqiang Chen

Summary: * Read armV7-A/R reference manual; crosstool-ng patches and wrapper scripts. Details: 1. Patches for crosstool-ng: * Fix symlink issue when CT_USE_SYSROOT is not enabled. * Update sample/linaro-arm-none-eabi (baremetal) to disable SYSROOT. So that both include and lib files are in the same dir. 2. Study armV7-A/R reference manual. 3. Validate embedded toolchain Dec. release. 4. Enhance the wrapper to use crosstool-ng for embedded toolchain. Plan: * Ramp-up on gcc. Best regards! -Zhenqiang

13 years, 5 months

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[ACTIVITY] weekly status

by Revital Eres

Submitting patch for Bug #879725: http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01459.html Looking at the performance results running SMS with automatic testing. This is my last week in Linaro so I would also like to thank you all for the interesting year -- it was a great experience for me to work in this project. I wish you all good luck and happy holidays! Revital

13 years, 5 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, OpenEmbedded-Core: * No response on the CSL patches I posted to the ml yet * khem says someone (other than me) needs to try them * Linaro binary toolchain * Runs on Oneiric-X86_64 after installing lsb-core (interpreter: /lib/ld-lsb.so.3) * The do_rootfs tasks fails with runtine dependecy issues when using the external-linaro-toolchain_arm-2011.11.bb recipe. When re-using my CSL 2011.03 recipe with the linaro toolchain the error doesn't show up - strange. * OE-Core build gets confused by the (arm-linux-gnueabi-)pkg-config of the external linaro toolchain. As a workaround I just renamed this script. * The qemuarm MACHINE configuration uses "-march=armv5te -mno-thumb" Since the linaro toolchain defaults to thumb and -mno-thumb has no effect some inline assemblies are failing (i.e. on the umull insn). GNU #47930 suggests using -marm instead -> OE-Core patch posted. * Got the core-image-minimal to build, but it doesn't run yet (I suspect some basic runtime dependencies like libc again) * The build of the sato image fails (seems libtool and/or C++ related - need to investigate) Regards Ken

13 years, 5 months

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Fwd: [ACTIVITY] w51

by Asa Sandahl

Hi, * Continued with comparison of eembc results for gcc4.4 and gcc 4.6 (FSF and Linaro). Collecting results for 4.6 with loop-unrolling turned off. * Working on a plotbench.py script that will use matplotlib for plotting the results. Right now the script plots the geomean value, for instance for eembc. I now try to make it plot all subtest as well. Then it should also show relative improvements instead of just the numbers, and then also sorted from best to worse. This script depends on Michaels script libtabulate.py for transforming the tabulated file back to python records. * Will be back January 9 /Regards Åsa

13 years, 5 months

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[ACTIVITY] Nov 19 - Dec 22

by Ulrich Weigand

== GDB == * Ongoing work on remote support for "info proc" and core file generation. Completed implementation of latest solution via accessing arbitrary files on the remote site, only to run into a fundamental design problem ... so it's probably back to the previous approach. Discussion on the list is ongoing. * Fixed a GDB 7.4 test suite failure on ARM: PR tdep/12797 * Fixed another GBD 7.4 test suite failure on ARM, by enabling pthread_t thread debugging on core files. == GCC == * Patch review week. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

13 years, 5 months

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