Summary:
* Exercise crosstool-ng and summarize the gaps.
Details:
* Exercise crosstool-ng
(1) Sync with lp:~linaro-toolchain-dev/crosstool-ng/linaro.
(2) Try to config linux-host-baremental-target an
mingw32-host-baremental-target.
(3) Try to build the toolchain for both embedded toolchain and
linaro-gcc-4.6-2011.10 with the config.
. C compiler for linux and mingw32 hosts and c++ compiler for
linux host can be built without any change.
. C++ compiler for mingw32 host can be built after PCH is disabled.
. GDB-cross build fail due to dependence packages.
* Gaps in crosstool-ng
(1) Improve GDB-cross scripts to download and build the dependence
packages: expat and ncurses. Or put expat and ncurses as
companion_libraries.
(2) To remove dependence, embedded toolchain requires more
prerequisites like zlib.
New config and scripts are required to support the packages.
(3) Currently, the embedded toolchain source packages are released
as a tarball, which includes gcc, gmp, etc. New scripts are required
to support it.
(4) To make sure the toolchain can run with lower version glibc like
redhat4/5, the embedded toolchain requires lower version native
gcc4.3.6 to build it.
To support it,
. Users can build the native gcc manually, or
. Enhance the scripts to add one step to build native gcc.
(5) All the default package configurations are different from
embedded toolchain internal build scripts.
Since the configurations in embedded toolchain had been tuned
and tested, we will change the configurations in crosstool-ng if they
do not match and not configurable.
The same rule will apply for linaro toolchain.
Plans:
* Write scripts to re-pack the embedded toolchain source packages.
* Add the supports for all prerequisites in crosstool-ng menuconfig.
Thanks!
-Zhenqiang
Posted a patch upstream to fix big-endian for generic tuning. This was a
simple omission from my previous patches.
Merged GCC 4.6.2 to Linaro GCC. It's still in testing now, so I'll have
to commit it sometime over the weekend or next week.
Looked at the benchmark results from Spec2000 running on both A8 and A9
systems, with and with NEON, and with various compiler options. Posted
the results in a spreadsheet (visible within Linaro only).
Begun making adjustments to generic tuning and started new spec2k runs
to see if they are beneficial. First, I'm trying A9 prefetch settings on
A8 to see how much damage it does. Next I'll try enabling the A8 NEON
tuning settings on A9 to see what happens there.
Prepared for travel next week.
Vacation Friday
Hi,
- Merged to gcc-linaro:
- widening shifts
- SLP features: support loads with different offsets and swap
operands if necessary
- Started rewriting SLP analysis to support operations with more than
two operands (towards SLP of conditions)
- Updated NEON presentation following Ramana's suggestions (thanks!)
- Suggested to Ramana to implement vcond with mixed types, created a
blueprint: https://blueprints.launchpad.net/gcc-linaro/+spec/vcond-with-mixed-types
- Vectorizer:
- updated vectorizer's webpage
- updated vectorizer's wiki page
- the usual maintenance
- Committed upstream two SLP data-ref analysis improvements: PR 50730
and PR 50819
Ira
Hi there. Connect is just around the corner. Have a look at:
https://wiki.linaro.org/MichaelHope/Sandbox/Q4.11Plans
for a summary of the toolchain sessions and hacking topics.
It would be great to have kernel and OCTO input in the ARM STM driver,
Kernel debugging, and KVM sessions.
-- Michael
Hi Folks,
Draft agenda for the performance meeting next week at Connect -
https://blueprints.launchpad.net/gcc-linaro/+spec/linaro-toolchain-performa…
Are there any topics that people would like to bring up during this
meeting other than the ones listed here ? I suspect that we'll
probably just have about 10-15 minutes for a topic in this case. I am
not considering discussing PGO related stuff in this session given
that we've got another session in which we can discuss this.
Thoughts ?
cheers
Ramana
Hi Folks,
I've been trying to capture what we want to do in terms of hacking
time and some of the performance related backlog that we have in the
system. I have done so here.
https://wiki.linaro.org/RamanaRadhakrishnan/Sandbox/Q411ConnectGCCPerfPlan
I'm on vacation tomorrow but should be picking email for sometime
during the day.
Thoughts about what else we could be doing in this area or if there's
a better way we could use our hacking time.
cheers
Ramana
---
At the moment ARM eglibc doesn't support the functions declared
in ucontext.h: getcontext(), setcontext(), swapcontext() and
makecontext(). Instead you get implementations which always
fail and set errno to ENOSYS.
QEMU uses these functions to implement coroutines. Although there
is a fallback implementation in terms of threads, there are reasons
why using the fallback is suboptimal:
* its performance is worse
* it will be less tested, because x86_64 and i386 both implement
the ucontext functions and so QEMU on those hosts will be using
different code paths
* I'm not aware of a good way at configure time to detect whether
getcontext() et al will always fail without actually running a
test binary, which won't work in a cross-compile setup. (If eglibc
just didn't provide the functions at all this would be much
simpler...)
We're going to care about performance and reliability of QEMU on
ARM hosts as we start to support KVM on Cortex-A15, so it would
be good if we could add ucontext function support to eglibc as
part of that effort.
Opinions? Have I missed some good reason why there isn't an
ARM implementation of these functions?
(I'm aware that the ucontext functions have been removed from
the latest version of the POSIX spec; however AFAIK there's no
equivalent functionality that replaces them so I think they're
still worth having implementations of for parity with other
architectures.)
-- PMM
==Progress===
* Some upstream patch review.
* Spent time looking at LP 836588 which is a case where CSE removes a
particular label access in one case but doesn't remove it from the
list of things in the constant pool which is quite bizarre. Will
probably need some help with looking into this one.
* Sent out vcvt.f32 and vcvt.f64 patches .
* Connect preparation - laptop cleanup and getting it finally onto an
x86_64 distribution.
* Looked at some of the vec_perm / vec_rev cases in Neon with Ira.
* Spent some time looking at some of Andrew's issues with generic-v7a
tuning especially the cases where it was doing better and gave some
suggestions.
=== Plans ===
* Prepare for Connect.
* Prepare by looking at some of the large differences between
various comparative benchmarks.
* Some research into PGO related stuff.
* Try to upstream some more of my patches in the backlog before the
end of the week.
* Finish off some internal paperwork.
* I'm off on 26th - Wednesday.
Absences.
* 26th Oct - Day off.
* 31st Oct - 4th Nov - Linaro Connect Q4.11
* 08 Nov - 11 Nov - Tentatively booked
* Dec 19 - 31st Dec - Tentatively booked
Continued looking at my constant reuse optimization. I've identified a
couple of hundred optimization opportunities in the whole of gcc itself,
which is fewer than I had hoped. There are almost no opportunities when
compiling for size as constants are always loaded from a constant pool
in that case (I'm not sure why that's the case, given that this isn't
any more space efficient than movw+movt, unless it can share the
constant in more than one place).
Backported my -mtune=native patch to Linaro GCC.
Backported my generic tuning patch to Linaro GCC.
Backported my pr50717 patch to Linaro, and pushed to Launchpad for testing.
Analysed my benchmark results I made to aid generic tuning.
Disappointingly the A8/A9 tuning is not as beneficial as one would like.
In fact, the existing generic tuning patch (which was supposed to be a
framework only) is actually quite competitive and gives better
performance in some cases.
Set more benchmarks running, this time with NEON enabled. That's about
36 hour's worth on A9, and more like 90 hours on my A8 (obviously,
there's some difference in the clock speeds there).
Discovered that my native tuning code won't compile with a C++ compiler
(GCC Bugzilla PR50809). Tested and committed a fix upstream.
== GDB ==
* Worked on support for cross-platform core file generation.
Posted initial set of patches for comments.
* Created "Toolchain support for kernel debugging" blueprint.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi,
I made some progress on transforming the hacks I did to get libunwind
working on Android into proper patches that can go upstream. Things learned:
* bionic employs OpenBSD header files that therefore lack some GNU and
ARM specific defines (only small fix needed - plan is to change
libunwind to work with non-patched bionic too)
* Android basically provides all the functionality that is required
for libunwind-ptrace - but...
* no one seems to build libunwind with remote unwind functionality
(including libunwind-ptrace) only
* most of the issues can be avoided by changing libunwind to be more
portable
Regards
Ken
* Still having trouble with using multistrap/pdebuild-cross for
cross-compiling Firefox - it looks like only x86 packages get downloaded,
not armel. I have asked Wookey for advice, and he will try to reproduce the
build.
* Falling back to native compiling until the cross-compiling set up has been
sorted out. I will now take a look at how to pass different compiler options
to the Mozilla build system and how to build different parts of the program.
Best Regards
Åsa
(short week: 4 days)
RAG:
Red:
Amber:
Green: blog started :-) http://translatedcode.wordpress.com/
Current Milestones:
|| || Planned || Estimate || Actual ||
||a15-usermode-support || 2011-11-10 || 2011-11-10 || ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-11-10 || ||
Historical Milestones:
||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 ||
||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 ||
||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || 2011-09-15 ||
||add-omap3-networking || 2011-10-13 || 2011-10-13 || 2011-10-13 ||
||a15-systemmode-planning || 2011-10-13 || 2011-10-13 || 2011-09-22 ||
== other ==
* upstream patch review, putting together pull requests
* more time spent on qemu on ARM host apparent memory corruption
bug (no luck yet :-(); found a Valgrind bug in the process,
though (KDE:284472). This ate up way too much of this week.
* A15 KVM planning work
* meetings etc
* moved over to patches.linaro for QEMU patch tracking
-- PMM
Hi,
* widening shifts - finally committed upstream
* SLP loads with different offsets and operand swaps - committed upstream
* SLP with multiple types - merged to gcc-linaro-4.6
* vectorizer stuff: patch review, test fixes, discussions, bug fix
* Ramana and I discussed what can be done with VEC_PERM_EXPR for NEON,
and created https://blueprints.launchpad.net/gcc-linaro/+spec/support-vec-perm
for this issue.
Ira
Following on from last night's performance call, I had a look at how
64 bit integer operations are mapped to NEON instructions. The
summary is:
* add - fine
* subtract - fine
* bitwise and - fine
* bitwise or - fine
* bitwise xor - fine
* multiply - can't as the instruction tops out at 32 bits. Might be
able to compose using VMLAL
* div, mod - no instruction
* negate - instruction tops out at 32 bits, but could be turned into
vmov #0, vsub
* left shift constant - missing
* right shift constant - missing
* right arithmetic shift constant - missing
* left shift register - missing
* right shift register - tricky, as you do this as a left shift -register
* not - no instruction, but could be done through a vceq, #0?
* bitwise not - missing
I also noticed that the replicated constants aren't being used. A
pre-increment is load constant pool; vadd but could be done as a vmov,
#-1; vsub. The same with pre-decrement - it could be done as a vmov,
#-1; vadd.
This seems worth blueprinting.
-- Michael
limits-fndefn.c takes an impressively long time to run. On an idle
machine, -O3 -g -c takes 17:31 and -O2 -g -c takes The test already
has a dg-timeout-factor of 4 giving a total timeout of 20 minutes.
Removing the -g brings this down to 30 s. Keeping the -g and adding
-fno-var-tracking brings this down to 45 s.
We could bump the multiplier up to 8 but it's getting a bit
ridiculous. Any thoughts?
-- Michael
== Last week and today ==
* Backported fix for returning std::pair<bool, bool>. Unfortunately
this showed up a regression on 4.5. I couldn't reproduce it cross,
and the testcase itself looks innocuous, so I'm wondering whether
the patch might trigger a miscompilation of cc1plus.
* Committed SMS register-scheduling patches upstream and backported
to Linaro 4.6.
* Most of the week spent on -fsched-pressure. Still trying a few
variations in order to get the right balance. (My local haifa-sched.c
now has about 20 new toggles.) Still feel like I'm making progress,
rather than hitting the point of diminishing returns.
Hope Connect goes well. See everyone in a few weeks' time.
Richard
Completed the 4.5 and 4.6 FSF to Linaro merges.
Spun the Linaro GCC release tarballs, uploaded them to the test farm,
and set off the test builds.
Continued looking at the constant reuse optimization. This time I've
build GCC itself with the new pass to see how many optimization
opportunities there are. This shook out a lot more small bugs, which was
useful.
Backported my negative-shifts patch to Linaro 4.6, pushed it to
Launchpad for testing, and then committed it to 4.6 once in was approved.
Experimented with running SPEC2K on A8 and A9 boards in order to
establish a baseline for the generic tuning tweaks. A short test doesn't
give much clue as to what can be achieved, and a long test takes way too
long. The problem is also complicated by the benchmarks where the A8
tuning works better on A9 than A9 tuning does. :S
Received a bug report (GCC bugzilla 50717) for my widening multiplies
patches. Analysed the problem, developed a patch, and posted it to
gcc-patches.
<Short week with 2 days gone on an internal training course>
==Progress===
* Some patch review.
* Spent time looking at LP 836588.
* Tried some different approaches for the vcvt.f64.s32 case and it
looks like the simple solution is the best one unfortunately :(
* 2 days off at internal training course.
=== Plans ===
* continue looking into LP 836588
* Patch review week/
* Work on getting vcvt.f* case done and finish some of the backlog.
Absences.
* 31st Oct - 4th Nov - Linaro Summit Orlando - Travel booked -
* 08 Nov - 11 Nov - Tentatively booked
* Dec 19 - 31st Dec - Tentatively booked
I've just tried rerunning some benchmarks on my panda, which I
reinstalled recently and am getting
some odd behaviour:
The kernel is 3.0.0-1404-linaro-lt-omap
For example:
simple_strlen: ,102400, loops of ,62, bytes=6.054688 MB, transferred
in ,20324707.000000 ns, giving, 297.897898 MB/s
simple_strlen: ,102400, loops of ,32, bytes=3.125000 MB, transferred
in ,7904053.000000 ns, giving, 395.366782 MB/s
simple_strlen: ,102400, loops of ,16, bytes=1.562500 MB, transferred
in ,7354736.000000 ns, giving, 212.448142 MB/s
simple_strlen: ,102400, loops of ,8, bytes=0.781250 MB, transferred in
,91553.000000 ns, giving, 8533.308575 MB/s
simple_strlen: ,102400, loops of ,4, bytes=0.390625 MB, transferred in
,1495361.000000 ns, giving, 261.224547 MB/s
simple_strlen: ,102400, loops of ,2, bytes=0.195312 MB, transferred in
,1983643.000000 ns, giving, 98.461518 MB/s
Note the 8 byte one apparently 40 times faster, and for true oddness:
smarter_strlen_ldrd: ,102400, loops of ,62, bytes=6.054688 MB,
transferred in ,3936768.000000 ns, giving, 1537.984331 MB/s
smarter_strlen_ldrd: ,102400, loops of ,32, bytes=3.125000 MB,
transferred in ,0.000000 ns, giving, inf MB/s
smarter_strlen_ldrd: ,102400, loops of ,16, bytes=1.562500 MB,
transferred in ,4180909.000000 ns, giving, 373.722557 MB/s
Now, while I like infinite transfer rates, I suspect they're wrong.
Anyone else seeing this?
Dave
Implementing estimating register pressure in SMS.
Experimenting with the implementation on libav microbench.
Discussed with Richard some issue raised while implementing.
== GDB ==
* Created and published Linaro GDB 7.3-2011.10 release.
* Fixed LP #871901 (Linaro GDB crashes on 3.x kernels) in
mainline and Linaro GDB 7.3.
* Backported mainline fix for LP #829595 (Separate debuginfo
misidentified with "remote:" access) to Linaro GDB 7.3.
* Completed blueprint "GDB as a cross-debugger".
* Worked on support for cross-platform core file generation.
== GCC ==
* Patch review week.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
== 64 bit atomics ==
* Thanks to Ramana for OKing my gcc patches; and Richard for
committing them - I've backported these to the gcc-linaro branch
and pushed it - hopefully those will pass OK!
== String routines ==
* Sent my memchr patch to upstream newlib, received comments,
tweeked, and resent
* Sent strlen patch to upstream newlib
* Spent some time getting confused by timing issues on our Panda; it
got reinstalled with 11.09 a few
weeks ago and is now showing some odd behaviours. In particular I'm
seeing some tests show completion in 0ns
(and my code isn't -that- fast!), and others where the times vary
wildly - it's almost as if a timer interrupt is delayed
or missing; my same test binary works fine on one of Michael's Ursa's
running an older install.
== QEMU ==
* Tested Peters QEMU image for release
== Other ==
* Spent an afternoon reading through the System trace docs
On holiday next week; I'll poll email occasionally.
Dave
Hi,
* working through my inbox after being away
* a former patch of mine accidentally broke remote unwinding on IA64
* maintainer made a quick fix that made things worse for ARM
* posted a patch that aims to fix things up for all archs
* identified and submitted libunwind-android patches that could go upstream
* sent patch that lets another testcase pass on ARM Linux
* tried to help people on the mailing list with various issues
Regards
Ken
RAG:
Red:
Amber:
Green:
Current Milestones:
|| || Planned || Estimate || Actual ||
||add-omap3-networking || 2011-10-13 || 2011-10-13 || 2011-10-13 ||
||a15-systemmode-planning || 2011-10-13 || 2011-10-13 || 2011-09-22 ||
||a15-usermode-support || 2011-11-10 || 2011-11-10 || ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-11-10 || ||
Historical Milestones:
||qemu-linaro 2011-04 || 2011-04-21 || 2011-04-21 || 2011-04-21 ||
||qemu-linaro 2011-05 || 2011-05-19 || 2011-05-19 || n/a ||
||close out 1105 blueprints || 2011-05-28 || 2011-05-28 || 2011-05-19 ||
||complete 1111 planning || 2011-05-28 || 2011-05-28 || 2011-05-27 ||
||qemu-linaro-2011-06 || 2011-06-16 || 2011-06-16 || 2011-06-16 ||
||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 ||
||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 ||
||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || 2011-09-15 ||
== add-omap3-networking ==
* patches pushed into qemu-linaro and final testing done
== a15-usermode-support ==
* this is now in qemu-linaro 2011.10; only remaining thing is
for the patches to be taken upstream (no major review issues)
== linaro-qemu-11.11 ==
* qemu-linaro 2011.10 released
== other ==
* completed a desk move
* some sw/hw archaeology to answer a question about the FIFO size of
the PL041 on ARM devboards as part of reviewing audio support patch
* trying to track down a really weird problem where qemu on ARM host
dies with apparent memory corruption
* Working on using pdebuildcross/multistrap when cross compiling Firefox.
With multistrap all dependencies should be sorted out automatically.
The current status is that pdebuild-cross for armel is set up and the
compilation of the Firefox package starts. Does not come all the way though,
because some dependencies (for X11) are not in place after all. Will
continue investigation.
Best Regards
Åsa
The Linaro Toolchain Working Group is pleased to announce the
release of Linaro QEMU 2011.10.
Linaro QEMU 2011.10 is the latest monthly release of
qemu-linaro. Based off upstream (trunk) QEMU, it includes a
number of ARM-focused bug fixes and enhancements.
New in this month's release:
- Instructions introduced with the Cortex-A15 (ARM mode
SDIV and UDIV, and the VFPv4 fused multiply-accumulate
instructions VFMA, VFMS, VFNMA, VFNMS) are now supported
in linux-user mode
- Beagle models now support USB networking (run the model with
"-usb -device usb-net,netdev=mynet -netdev user,id=mynet")
Known issues:
- There may be some problems with running multithreaded programs in
linux-user mode (LP:823902)
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2011.10
Binary builds of this qemu-linaro release are being prepared and
will be available shortly for users of Ubuntu. Packages will be in
the linaro-maintainers tools ppa:
https://launchpad.net/~linaro-maintainers/+archive/tools/
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
The Linaro Toolchain Working Group is pleased to announce the 2011.10
release of both Linaro GCC 4.6 and Linaro GCC 4.5.
Linaro GCC 4.6 2011.10 is the eighth release in the 4.6 series. Based
off the latest GCC 4.6.1+svn179483, it contains a range of vectoriser
performance improvements and general bug fixes.
Interesting changes include:
* Updates to 4.6.1+svn179483
* Vectorises more straight-line code with data dependencies
* Now picks the best vector width when vectorising straight line code
* Better handles handling auto increment addresses in SMS
* Changes the default vector width from double word to quad word
* Better handling extracting the top or bottom half of a quad word vector
* Now supports the NEON absolute difference instruction
Fixes:
* LP: #689887 ICE in get_arm_condition_code
* LP: #809761 oss4 version 4.2-build2004-1ubuntu1 failed to build on armel
Linaro GCC 4.5 2011.10 is the fifteenth release in the 4.5
series. Based off the latest GCC 4.5.3+svn179438, this is a
maintenance focused release.
Interesting changes in 4.5 include:
* Updates to 4.5.3+svn179438
Fixes:
* LP: #689887 ICE in get_arm_condition_code
The source tarballs are available from:
https://launchpad.net/gcc-linaro/+milestone/4.6-2011.10https://launchpad.net/gcc-linaro/+milestone/4.5-2011.10
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
More information on the features and issues are available from the
release page:
https://launchpad.net/gcc-linaro/4.6/4.6-2011.10https://launchpad.net/gcc-linaro/4.5/4.5-2011.10
Mailing list: http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Bugs: https://bugs.launchpad.net/gcc-linaro/
Questions? https://ask.linaro.org/
Interested in commercial support? inquire at support(a)linaro.org
-- Michael
The Linaro Toolchain Working Group is pleased to announce the release
of Linaro GDB 7.3.
Linaro GDB 7.3 2011.10 is the third release in the 7.3 series. Based
off the latest GDB 7.3, it includes a number of ARM-focused bug fixes
and enhancements.
This release contains:
* Support for disabling address space randomization in gdbserver
* Fix for GDB crashes on 3.x kernels
* Fix spurious "CRC mismatch" warnings when using "remote:" sysroot
The source tarball is available at:
https://launchpad.net/gdb-linaro/+milestone/7.3-2011.10
More information on Linaro GDB is available at:
https://launchpad.net/gdb-linaro
Hi,
* Finished a presentation for NEON forum. Revital and Richard kindly
agreed to take a look and gave me some valuable comments. Thanks!
* widen-shifts:
- While preparing the presentation I found some room for improvement
in the pattern detection, so I implemented it. It gave additional 13%
to rgb24tobgr16.
- Ramana suggested a solution on how to check the constant operand of vshll.
Testing these two things on ARM.
* SLP improvements:
- Implemented a patch that swaps operands if necessary to make the
operations isomorphic, and supports loads with different offsets.
Testing it now.
- The three relevant libav loops now get vectorized giving 42%-57% speedup.
Next week holidays: half days Sunday-Wednesday and Thursday.
Ira
Here's my summary from Monday's meeting on the harder parts of binary
toolchains.
Using a 4.6 compiler against a 4.5 based sysroot such as Natty:
* libgcc and libstdc++ are part of the compiler
* The compiler expects features that are in the corresponding runtime
* You can't reliably run or validate against an earlier runtime
The solution is to upgrade the runtime on the sysroot to 4.6. 4.6 is
backwards compatible. Ubuntu did this with Maverick and it caused no
problems, although problems such as Debian #622783 have been seen.
Multiarch:
* The Ubuntu multiarch patch should work with a sysroot
* Multiarch and multilib should work together
Multilib:
* The current ARM multilib rules are old and not very relevant
* Multilib means you need multiple sysroots as well
* Skip multilib for the first release
Other:
* Anything we support in cross we should support native first
* Check that we don't have to directly supply the source that goes
with the binary sysroot
-- Michael
==Progress===
* Out of office for a day.
* Wrote a quick patch to do vcvt.f32.s32 with fractional bits where we
can. Tested no regressions, need to commit this after review upstream.
* Desk move and packing for that.
* Looked at a bug report LP 836588 appears to go away with fno-gcse.
Needs more digging.
=== Plans ===
* Look at LP 836588.
* Finish auto-inc-dec pipeline scheduling work.
* Clear out some of the old patches (POST_MODIFY_DISP for vfp, BRANCH_COST )
* Settle into new desk.
* Again a short week as I'm away for 2 days for an internal training event.
Meetings:
* 1-1s
* TCWG calls
Absences.
* 5th October - out of office.
* 13th - 14th October - Out of Office - Internal training event.
* 31st Oct - 4th Nov - Linaro Summit Orlando - Travel booked -
* 08 Nov - 11 Nov - Tentatively booked
* Dec 19 - 31st Dec - Tentatively booked
== Last week ==
* Patch review.
* Backported second attempt to fix get_arm_condition_code ICE.
* Worked on -fsched-pressure. Experimented with various combinations
of ideas. This is giving some good results (e.g. a 2x improvement
in libav's put_h264_qpel8_hv_lowpass_8) but needs a bit more work
to fix some outliers.
I'll be away from 18th Oct to 14th Nov.
Richard
Random data for the day: Dave Pigott has installed some new PandaBoard
build machines in the validation lab. They're identical to mine
except that root is on USB Flash instead of NFS, and they have a much
faster flash drive for the build area.
The time taken to bootstrap and test gcc-linaro-2011.09 with C, C++,
Fortran, and LTO is:
* ursa3, ursa4 (Toshiba USB stick): 301 minutes build / 369 test
* ursa2 (no-name USB stick): 324 minutes build / 422 test
* tcpanda (fast USB stick): 274 minutes build / 265 test
So the new combo gives a 1.38 x faster build. I'm surprised as I
though the build was CPU bound. I'd hate to see what building on an
SD card is like.
Note that /tmp is in RAM, /scratch is ext4, the new boards use
noatime, and the kernel doesn't have the new USB performance fix.
-- Michael
Continue working on estimating register pressure with SMS:
- Discussed current approach with Richard which gave useful leads.
- Started to implement this approach.
- Doing experiments on libav microbench.
The unaligned accesses in libpng are, for the large copies, a bug. Our attempt to align the row buffer to a 16 byte boundary was off-by-one so we end up always mis-aligning it. I've posted a patch on the png-mng-implement list:
http://sourceforge.net/mailarchive/message.php?msg_id=28194444
The time spent in memcpy() is probably an illusion. The data out of zlib gets copied to one row buffer where it is unfiltered (if necessary) then a copy is made in a separate buffer that is only used for the filter handling. If you test using images with large rows (I don't know what pngbench does) the copy buffer may well get flushed out of the second level cache between each row, then the memcpy will stall bringing it back in.
If you have machine level profiling you may see this as a massive time spike on some probably unrelated instruction which just happens to be in the PC when the stall stops everything.
Anyway, I have several ideas of how to avoid the copy when it isn't required.
John Bowler <jbowler(a)acm.org>
-----Original Message-----
From: Glenn Randers-Pehrson [mailto:glennrp@gmail.com]
Sent: Monday, October 03, 2011 1:15 PM
To: PNG/MNG implementation discussion list
Subject: [png-mng-implement] Use of memcpy() in libpng [Fwd from linaro-toolchain list]
Re: Use of memcpy() in libpng
David Gilbert
Tue, 27 Sep 2011 06:20:14 -0700
On 27 September 2011 14:16, Christian Robottom Reis <k...(a)linaro.org> wrote:
> On Tue, Sep 27, 2011 at 09:47:33AM +0100, Ramana Radhakrishnan wrote:
>> On 26 September 2011 21:51, Michael Hope <michael.h...(a)linaro.org> wrote:
>> > Saw this on the linaro-multimedia list:
>> >
>> > http://lists.linaro.org/pipermail/linaro-multimedia/2011-September/
>> > 000074.html
>> >
>> > libpng spends a significant amount of time in memcpy(). This might
>> > tie in with Ramana's investigation or the unaligned access work by
>> > allowing more memcpy()s to be inlined.
>>
>> It's the unaligned access and the change / improvements to the memcpy
>> that *might* help in this case. But that ofcourse depends on the
>> compiler knowing when it can do such a thing. Ofcourse what might be
>> more interesting is the kind of workload analysis that Dave's done in
>> the past with memcpy to know what the alignment and size of the
>> buffer being copied is.
>
> If you guys could take a look at this there is a potential requirement
> for the MMWG around libpng optimization; we could fit this in along
> with other work (possible vectorizing, etc) on that component.
It wouldn't take long to analyse the memcpy calls - life would be easier if we had the test program and some details on things like what size of images were used in these benchmarks.
Dave
Continued work on my constant reuse optimizations. Not too much this
week though. I've now fixed some issues with the ARM size-costs code
that was causing it to wildly over-estimate the cost of a MOVT
instruction. I'll have to post this upstream sometime soon.
Took another look at the shift-amount bug. Discussed the issue with Paul
Brook. I've now fixed the original bug, and fixed the new bug introduced
by Paul's original fix, and committed that upstream. I still need to
backport it to Linaro GCC though, and the latent bug that Richard S
spotted is still being analysed.
Did a merge from FSF 4.5 & 4.6 to Linaro, and pushed them the Launchpad
branches for testing.
Begun work benchmarking different setups for the generic tuning patches.
I had a lot of trouble trying to set up SPEC2000 though. Hopefully these
issues are now resolved, with some help from Michael, and I have
established some baseline figures on both A8 and A9 to work from.
No progress on native tuning. I'm still waiting for upstream review.
In other news: Mentor's contract with Linaro has now been extended for
another 6 months. :)
== String Routines ==
* Built and tested a newlib with my memchr in - ready to go with a
bit of tidy up.
* Followed up on my eglibc patch submission by a comment suggesting
the use of --with-cpu pointing back at the previous discussion.
== 64 Bit atomics ==
* Updated gcc patch based on Ramana's comments, retested and posted
new version
- Lost half a day to a failing SD card in our panda.
== QEMU ==
* Posted a patch that made one variable thread local using __thread
that fixes multi threaded user mode ARM programs (e.g. firefox); this
seems to have mutated on the list into a patch for more general thread
local support.
Dave
== GDB ==
* Reimplemented patch to disable address space randomization
in gdbserver to respect the "set disable-randomization"
command, and checked it in to mainline and Linaro GDB 7.3
* Worked on support for cross-platform core file generation.
== GCC ==
* Checked in mainline fix for PR 50305.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi,
- worked on the RTL part of the widen-shift patch
- backported to linaro 2/3 of the SLP patches, and proposed the third one
- worked on additional SLP improvements:
- swap operands to make statements isomorphic
- support load with offset 1 (after load from 0)
- started working on presentation for NEON forum
Upcoming holidays:
Oct 12, Wed - half day
Oct 13, Thu
Oct 16-19, Sun-Wed - half day
Oct 20, Thu
Ira
Hi,
So one of the things Michael pointed out in today's call was that the
ARM backend doesn't generate vcvt.f32.s<type> where you have an idiom
conversion from fixed to floating point as in the example below. I've
chosen to implement this in the following manner in the backend using
these interfaces from real.c . The reason I've chosen to not allow
this transformation in case flag_rounding_math is true is because this
instruction always ends up rounding using round-to-nearest rather than
obeying whats in the FPSCR and thus is not safe for programs that want
to dynamically set their rounding modes.
The benefits are quite obvious in that we eliminate a load from the
constant pool and a floating point multiply and thus essentially
shaving off a floating point multiply + Load latency off these
sequences. This instruction can only write the output into the same
register as the input register which is why I've modelled it as below
by tying op1 into op0.
If there's a simpler way of using the interfaces into real.c then I'm all ears ?
Thoughts ? I believe such idioms are used in libav from where the
original report appears to have come and thus it's a worthwhile gain
where we can have it. Any other places where folks might have noticed
this.
I will post upstream as well once I finish testing this patch. I'm
posting this here to get some feedback as well to let anyone who is
really really keen about trying this out have a go given I'm out
tomorrow.
( I took a quick look at the short -> f32 case as well but the fact
remains that loads either zero or sign extend anyway so there's
probably not much gain in modelling that right away and the win really
is in getting rid of that fp mul and the constant pool load. There's
probably some gain in going from i64-> f64 as well so those patterns
need to be written up at some point for completeness )
cheers
Ramana
2011-10-04 Ramana Radhakrishnan <ramana.radhakrishnan(a)linaro.org>
* config/arm/arm.c (vfp3_const_double_for_fract_bits): Define.
* config/arm/arm-protos.h (vfp3_const_double_for_fract_bits): Declare.
* config/arm/constraints.md ("Dt"): New constraint.
* config/arm/predicates.md (const_double_vcvt_power_of_two_reciprocal):
New.
* config/arm/vfp.md (*arm_combine_vcvt_f32_s32): New.
(*arm_combine_vcvt_f32_u32): New.
For the following testcases I see the code as follows with
-mfloat-abi=hard -mfpu=vfpv3 and -mcpu=cortex-a9
float foo (int i)
{
float v = (float)i / (1 << 11);
return v;
}
float foa_unsigned (unsigned int i)
{
float v = (float)i / (1 << 5);
return v;
}
After patch .
foo:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
fmsr s0, r0 @ int
vcvt.f32.s32 s0, s0, #11
bx lr
.size foo, .-foo
.align 2
.global foa_unsigned
.type foa_unsigned, %function
foa_unsigned:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
fmsr s0, r0 @ int
vcvt.f32.u32 s0, s0, #5
bx lr
.size foa_unsigned, .-foa_unsigned
.align 2
.global foo1
.type foo1, %function
rather than
.type foo, %function
foo:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
fmsr s15, r0 @ int
fsitos s0, s15
flds s15, .L2
fmuls s0, s0, s15
bx lr
.L3:
.align 2
.L2:
.word 973078528
.size foo, .-foo
.align 2
.global foa_unsigned
.type foa_unsigned, %function
foa_unsigned:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
fmsr s15, r0 @ int
fuitos s0, s15
flds s15, .L5
fmuls s0, s0, s15
bx lr
.L6:
.align 2
.L5:
.word 1023410176
* Vacation
Monday, Tuesday, and Wednesday.
* GCC
Continued work on my constant reuse optimizations. Disappointingly, I've
found that there are very few optimization opportunities in EEMBC
(ARM/Thumb V7-A), although it's not difficult to write testcases that
the optimization could improve. I also discovered that the data-flow
chains don't work exactly how I thought (with respect to if-then-else
cases) so I need to do a little more work.
Pinged the native tuning patches; they're still waiting for upstream review.
Still can't get the generic tuning work done as the CodeSourcery panda
boards appear to be still offline.
Committed to mainline the patch to support instructions with auto-inc
operations in SMS after addressing Ayal's comments. The patch contains
two parts; one of them fixes a bug revealed during bootstrapping with
the patch and SMS flags.
http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01988.htmlhttp://gcc.gnu.org/ml/gcc-patches/2011-09/msg01987.html
Looking at estimating register pressure with SMS: based on previous
discussion with Richard the current approach is to try and use the
register pressure estimation in loop invariant pass.
I'm compiling an application built with TI's DVSDK 3 *[0].
/home/user/ti/dvsdk/dvsdk_3_01_00_10/linuxutils_2_25_02_08/packages/ti/sdo/linuxutils/cmem/lib/cmem.a470MV(cmem.o470MV):(.ARM.exidx+0x0):
undefined reference to `__aeabi_unwind_cpp_pr0'
arm-linux-gnueabi-gcc --version
arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.5.2-5ubuntu2~ppa1) 4.5.2
arm-linux-gnueabi-ld --version
GNU ld (GNU Binutils for Ubuntu) 2.21.0.20110302
More full output is here (but it isn't particularly helpful due to TI's RTSC
make system's black-magic)
https://gist.github.com/925674
FYI: the MV in cmem.a470MV stands for MontaVista.
This name is hard-coded somewhere even though it's not being linked against
a MontaVista system.
I believe the 470 means that it should work with ARMv4 through ARMv7, but
I'm not positive.
My googling suggest that this is a toolchain bug and that the best way
around the issue is to create a file which defines the function as a void
dummy and include it.
http://www.codesourcery.com/archives/arm-gnu/msg03604.htmlhttp://comments.gmane.org/gmane.comp.boot-loaders.u-boot/78649http://www.cs.fsu.edu/~baker/devices/lxr/http/ident?i=__aeabi_unwind_cpp_pr0
I have a script that I'll post shortly with instructions as to how to setup
TI's DVSDK with Linaro
AJ ONeal
[0] I'm not using the latest DVSDK version 4 because the paths and such are
so hard-coded for the 2009q3 version of codesourcery on ubuntu 10.04 LTS
that I don't know where to start fixing it.
===Progress===
* Patch review week.
* Looked at bootstrap issue for a while but Richard Sandiford picked
it up and sorted it out (Thanks Richard).
* Fun and games with some paperwork.
* Some backporting and testing patches. (50099 and 50186) underway.
=== Plans ===
* Clear out some of the old patches (POST_MODIFY_DISP for vfp,
BRANCH_COST ) and finish on auto-inc-dec patch from last week.
* Away for 1 day next week.
Meetings:
* 1-1s
* TCWG calls
Absences.
* 5th October -Out of Office.
* 13th - 14th October - Internal training.
* 31st Oct - 4th Nov - Linaro Summit Orlando.
* 08 Nov - 11 Nov - Tentatively booked
* Dec 19 - 31st Dec - Tentatively booked