==Progress===
* Some upstream patch review.
* Spent time looking at LP 836588 which is a case where CSE removes a
particular label access in one case but doesn't remove it from the
list of things in the constant pool which is quite bizarre. Will
probably need some help with looking into this one.
* Sent out vcvt.f32 and vcvt.f64 patches .
* Connect preparation - laptop cleanup and getting it finally onto an
x86_64 distribution.
* Looked at some of the vec_perm / vec_rev cases in Neon with Ira.
* Spent some time looking at some of Andrew's issues with generic-v7a
tuning especially the cases where it was doing better and gave some
suggestions.
=== Plans ===
* Prepare for Connect.
* Prepare by looking at some of the large differences between
various comparative benchmarks.
* Some research into PGO related stuff.
* Try to upstream some more of my patches in the backlog before the
end of the week.
* Finish off some internal paperwork.
* I'm off on 26th - Wednesday.
Absences.
* 26th Oct - Day off.
* 31st Oct - 4th Nov - Linaro Connect Q4.11
* 08 Nov - 11 Nov - Tentatively booked
* Dec 19 - 31st Dec - Tentatively booked
Continued looking at my constant reuse optimization. I've identified a
couple of hundred optimization opportunities in the whole of gcc itself,
which is fewer than I had hoped. There are almost no opportunities when
compiling for size as constants are always loaded from a constant pool
in that case (I'm not sure why that's the case, given that this isn't
any more space efficient than movw+movt, unless it can share the
constant in more than one place).
Backported my -mtune=native patch to Linaro GCC.
Backported my generic tuning patch to Linaro GCC.
Backported my pr50717 patch to Linaro, and pushed to Launchpad for testing.
Analysed my benchmark results I made to aid generic tuning.
Disappointingly the A8/A9 tuning is not as beneficial as one would like.
In fact, the existing generic tuning patch (which was supposed to be a
framework only) is actually quite competitive and gives better
performance in some cases.
Set more benchmarks running, this time with NEON enabled. That's about
36 hour's worth on A9, and more like 90 hours on my A8 (obviously,
there's some difference in the clock speeds there).
Discovered that my native tuning code won't compile with a C++ compiler
(GCC Bugzilla PR50809). Tested and committed a fix upstream.
== GDB ==
* Worked on support for cross-platform core file generation.
Posted initial set of patches for comments.
* Created "Toolchain support for kernel debugging" blueprint.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi,
I made some progress on transforming the hacks I did to get libunwind
working on Android into proper patches that can go upstream. Things learned:
* bionic employs OpenBSD header files that therefore lack some GNU and
ARM specific defines (only small fix needed - plan is to change
libunwind to work with non-patched bionic too)
* Android basically provides all the functionality that is required
for libunwind-ptrace - but...
* no one seems to build libunwind with remote unwind functionality
(including libunwind-ptrace) only
* most of the issues can be avoided by changing libunwind to be more
portable
Regards
Ken
* Still having trouble with using multistrap/pdebuild-cross for
cross-compiling Firefox - it looks like only x86 packages get downloaded,
not armel. I have asked Wookey for advice, and he will try to reproduce the
build.
* Falling back to native compiling until the cross-compiling set up has been
sorted out. I will now take a look at how to pass different compiler options
to the Mozilla build system and how to build different parts of the program.
Best Regards
Åsa
(short week: 4 days)
RAG:
Red:
Amber:
Green: blog started :-) http://translatedcode.wordpress.com/
Current Milestones:
|| || Planned || Estimate || Actual ||
||a15-usermode-support || 2011-11-10 || 2011-11-10 || ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-11-10 || ||
Historical Milestones:
||qemu-linaro-2011-07 || 2011-07-21 || 2011-07-21 || 2011-07-21 ||
||qemu-linaro 2011-08 || 2011-08-18 || 2011-08-18 || 2011-08-18 ||
||qemu-linaro 2011-09 || 2011-09-15 || 2011-09-15 || 2011-09-15 ||
||add-omap3-networking || 2011-10-13 || 2011-10-13 || 2011-10-13 ||
||a15-systemmode-planning || 2011-10-13 || 2011-10-13 || 2011-09-22 ||
== other ==
* upstream patch review, putting together pull requests
* more time spent on qemu on ARM host apparent memory corruption
bug (no luck yet :-(); found a Valgrind bug in the process,
though (KDE:284472). This ate up way too much of this week.
* A15 KVM planning work
* meetings etc
* moved over to patches.linaro for QEMU patch tracking
-- PMM
Hi,
* widening shifts - finally committed upstream
* SLP loads with different offsets and operand swaps - committed upstream
* SLP with multiple types - merged to gcc-linaro-4.6
* vectorizer stuff: patch review, test fixes, discussions, bug fix
* Ramana and I discussed what can be done with VEC_PERM_EXPR for NEON,
and created https://blueprints.launchpad.net/gcc-linaro/+spec/support-vec-perm
for this issue.
Ira
Following on from last night's performance call, I had a look at how
64 bit integer operations are mapped to NEON instructions. The
summary is:
* add - fine
* subtract - fine
* bitwise and - fine
* bitwise or - fine
* bitwise xor - fine
* multiply - can't as the instruction tops out at 32 bits. Might be
able to compose using VMLAL
* div, mod - no instruction
* negate - instruction tops out at 32 bits, but could be turned into
vmov #0, vsub
* left shift constant - missing
* right shift constant - missing
* right arithmetic shift constant - missing
* left shift register - missing
* right shift register - tricky, as you do this as a left shift -register
* not - no instruction, but could be done through a vceq, #0?
* bitwise not - missing
I also noticed that the replicated constants aren't being used. A
pre-increment is load constant pool; vadd but could be done as a vmov,
#-1; vsub. The same with pre-decrement - it could be done as a vmov,
#-1; vadd.
This seems worth blueprinting.
-- Michael
