On Thu, Nov 10, 2016 at 09:52:14PM +0800, Heyi Guo wrote:
Order of timing parameters of structure DDR_CHANNEL are changed to be alphabetical, to make it easier to find certain parameter.
Thanks!
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Chips/Hisilicon/Include/Library/HwMemInitLib.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 8968b21..e6c0fd4 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -186,20 +186,20 @@ typedef struct _DDR_Channel{ UINT32 MemSize; UINT32 CLSupport; UINT32 minTck;
- UINT32 nAA; UINT32 nCL;
- UINT32 nWR;
- UINT32 nCCDL;
- UINT32 nFAW; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC;
- UINT32 nWTR; UINT32 nRTP;
- UINT32 nAA;
- UINT32 nFAW; UINT32 nRP;
- UINT32 nCCDL;
- UINT32 nWR;
- UINT32 nWTR; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en;
-- 1.9.1