Hisilicon new platform D05 will be pushed to Linaro Reference Platform 16.12 release, and these patches are to enable Hisilicon D05 in OPP.
Patch 25 if for binary and too large to be sent, try to use --no-binary, but failed. please find it in the below git repo. Code can also be found in my linaro repo: http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git branch: rp-16.12-12-d05
Changelog v2>v3:
* Improve the code according to Leif's comments - Rename Pv660 related files to Hisilicon common files - Switch to generic BDS - AcpiPlatformDxe patch is split into separate patches - Other code format improvemen
Chenhui Sun (2): Hisilicon: perform memorytest to promote reserved memory Hisilicon/UpdateFdtDxe: Add GenericMemTestProtocol dependency
Heyi Guo (23): Hisilicon/Hi1610/PCIe: Add performace tuning Hisilicon/PCIe: extend support for maximum 8 root ports Hisilicon/PCIe: support different memory address in PCIe domain Hisilicon/PCIe: support multiple MSI target addresses Hisilicon/PCIeInit: Remove unused function PciePortReset Hisilicon/PCIeInit: fix PciePcsInit bug Hisilicon/I2CLib: Extend to support Hi1616 Hisilicon/HwMemInitLib.h: fix typo for phyDqsFallRiseDelay Hisilicon: Reorder DDR timing parameters by alphabetical Hisilicon: update memory init data structure to support D05 Hisilicon/PlatformSysCtrlLib: add more interfaces to support D05 Platforms/Hisilicon: Add definition of NUMA related structures Platforms/Hisilicon: add D05 ACPI tables Platform/Hisilicon: Import AcpiPlatformDxe driver from MdeModulePkg D03/OemMiscLib: Add interface for SAS driver D03/OemNicConfig: add CpldIoLib to avoid potential build error Hisilicon: Rename Pv660.dsc.inc to be Hisilicon common include Hisilicon: Rename ArmPlatformLibPv660 to Hisilicon common ArmPlatformLib Hisilicon: Remove ArmVExpress including from build option Platforms/Hisilicon: add D05 platform modules and files Platforms/Hisilicon: add D05 binary module INF files Platforms/Hisilicon: Add D05 binary files Hisilicon/ACPI: Update SRAT from real memory configuration
Peicong Li (2): Hisilicon/Serdes: add support for D05 D03/D05: Change to access EEPROM data by checking page boundary
.../Library/Hi1616Serdes/Hi1616SerdesLib.inf | 48 + .../Library/Hi1616Serdes/Hi1616SerdesLib.lib | Bin 0 -> 707246 bytes .../PlatformSysCtrlLibHi1616.inf | 54 + .../PlatformSysCtrlLibHi1616.lib | Bin 0 -> 358602 bytes .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 273 +++++ .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni | 22 + .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 62 + .../HisiAcpiPlatformDxe/AcpiPlatformExtra.uni | 20 + .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 137 +++ .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 216 +++- .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 + .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 6 +- .../Hisilicon/Drivers/PlatformBoot/PlatformBoot.c | 58 + .../Drivers/PlatformBoot/PlatformBoot.inf | 42 + .../Type09/MiscSystemSlotDesignationFunction.c | 23 +- .../Drivers/UpdateFdtDxe/UpdateFdtDxe.inf | 4 +- .../Hi1610/Drivers/PcieInit1610/PcieInit.c | 59 +- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 6 +- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 230 ++-- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 15 +- .../Hi1610/Drivers/PcieInit1610/PcieKernelApi.h | 2 - Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 58 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 651 +++++++++++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 127 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 64 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 129 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 280 +++++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 36 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 1236 ++++++++++++++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 58 + .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 438 +++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 584 +++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 247 ++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl | 135 +++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 31 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 91 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 95 ++ .../Hi1616/D05AcpiTables/Hi1616Platform.h | 48 + .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 282 +++++ Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 78 ++ Chips/Hisilicon/HisiPkg.dec | 116 +- Chips/Hisilicon/Hisilicon.dsc.inc | 371 ++++++ Chips/Hisilicon/Hisilicon.fdf.inc | 139 +++ Chips/Hisilicon/Include/Library/AcpiNextLib.h | 19 +- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 60 +- Chips/Hisilicon/Include/Library/I2CLib.h | 2 +- Chips/Hisilicon/Include/Library/OemMiscLib.h | 1 + Chips/Hisilicon/Include/Library/PlatformPciLib.h | 142 ++- .../Hisilicon/Include/Library/PlatformSysCtrlLib.h | 9 + Chips/Hisilicon/Include/PlatformArch.h | 2 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 1 + .../ArmPlatformLibHisilicon/AArch64/Helper.S | 61 + .../ArmPlatformLibHisilicon/ArmPlatformLib.c | 107 ++ .../ArmPlatformLibHisilicon/ArmPlatformLib.inf | 69 ++ .../ArmPlatformLibHisilicon/ArmPlatformLibMem.c | 97 ++ .../ArmPlatformLibHisilicon/ArmPlatformLibSec.inf | 56 + .../Library/ArmPlatformLibPv660/AArch64/Helper.S | 61 - .../Library/ArmPlatformLibPv660/ArmPlatformLib.c | 108 -- .../Library/ArmPlatformLibPv660/ArmPlatformLib.inf | 69 -- .../ArmPlatformLibPv660/ArmPlatformLibMem.c | 98 -- .../ArmPlatformLibPv660/ArmPlatformLibSec.inf | 56 - Chips/Hisilicon/Library/I2CLib/I2CHw.h | 1 + Chips/Hisilicon/Library/I2CLib/I2CLib.c | 50 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- Chips/Hisilicon/Pv660/Pv660.dsc.inc | 371 ------ Chips/Hisilicon/Pv660/Pv660.fdf.inc | 139 --- .../Drivers/GetInfoFromBmc/GetInfoFromBmc.depex | Bin 0 -> 2 bytes .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi | Bin 0 -> 19552 bytes .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf | 26 + .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex | Bin 0 -> 2 bytes .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi | Bin 0 -> 25696 bytes .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf | 28 + .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi | Bin 0 -> 22528 bytes .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf | 32 + .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi | Bin 0 -> 23136 bytes .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex | Bin 0 -> 2 bytes .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf | 27 + .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex | Bin 0 -> 2 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi | Bin 0 -> 15968 bytes .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf | 27 + .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf | 29 + .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf | 28 + .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf | 27 + .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi | Bin 0 -> 56512 bytes .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf | 27 + .../Binary/D05/Drivers/OhciDxe/NativeOhci.efi | Bin 0 -> 48000 bytes .../Binary/D05/Drivers/OhciDxe/OhciDxe.inf | 26 + .../ReportPciePlugDidVidToBmc.depex | Bin 0 -> 2 bytes .../ReportPciePlugDidVidToBmc.efi | Bin 0 -> 21536 bytes .../ReportPciePlugDidVidToBmc.inf | 25 + .../Binary/D05/Drivers/SFC/SFCDriver.depex | Bin 0 -> 2 bytes .../Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi | Bin 0 -> 262144 bytes .../Binary/D05/Drivers/SFC/SfcDxeDriver.inf | 29 + .../Binary/D05/Drivers/Sas/SasDriverDxe.efi | Bin 0 -> 210400 bytes .../Binary/D05/Drivers/Sas/SasDxeDriver.inf | 28 + .../D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi | Bin 0 -> 35904 bytes .../Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf | 32 + .../TransferSmbiosInfo/TransSmbiosInfo.depex | Bin 0 -> 2 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi | Bin 0 -> 16576 bytes .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf | 26 + Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi | Bin 0 -> 141344 bytes Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf | 32 + .../D05/Library/FdtUpdateLib/FdtUpdateLib.inf | 51 + .../D05/Library/FdtUpdateLib/FdtUpdateLib.lib | Bin 0 -> 108418 bytes .../Library/OemAddressMapD05/OemAddressMapD05.inf | 44 + .../Library/OemAddressMapD05/OemAddressMapD05.lib | Bin 0 -> 42136 bytes .../Binary/D05/MemoryInitPei/MemoryInit.efi | Bin 0 -> 273312 bytes .../Binary/D05/MemoryInitPei/MemoryInitPeim.inf | 33 + Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv | Bin 0 -> 262144 bytes Platforms/Hisilicon/Binary/D05/bl1.bin | Bin 0 -> 12296 bytes Platforms/Hisilicon/Binary/D05/fip.bin | Bin 0 -> 41493 bytes .../D02/Library/OemMiscLibD02/BoardFeatureD02.c | 9 +- .../D02/Library/PlatformPciLib/PlatformPciLib.c | 32 +- .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 118 +- Platforms/Hisilicon/D02/Pv660D02.dsc | 10 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- Platforms/Hisilicon/D03/D03.dsc | 13 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- .../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 35 +- .../OemNicConfig2PHi1610/OemNicConfig2P.inf | 1 + .../Library/OemMiscLib2P/BoardFeature2PHi1610.c | 7 +- .../D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 + .../D03/Library/PlatformPciLib/PlatformPciLib.c | 41 +- .../D03/Library/PlatformPciLib/PlatformPciLib.inf | 118 +- Platforms/Hisilicon/D05/D05.dsc | 684 +++++++++++ Platforms/Hisilicon/D05/D05.fdf | 369 ++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 61 + .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 + .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 218 ++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 + .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 + .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 +++ 140 files changed, 10115 insertions(+), 1168 deletions(-) create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.lib create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.lib create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c create mode 100644 Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c create mode 100644 Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf mode change 100755 => 100644 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Chips/Hisilicon/Hisilicon.dsc.inc create mode 100644 Chips/Hisilicon/Hisilicon.fdf.inc create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf delete mode 100644 Chips/Hisilicon/Pv660/Pv660.dsc.inc delete mode 100644 Chips/Hisilicon/Pv660/Pv660.fdf.inc create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/NativeOhci.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SFCDriver.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/SmiGraphicsOutput.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.efi create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.lib create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.lib create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInit.efi create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv create mode 100644 Platforms/Hisilicon/Binary/D05/bl1.bin create mode 100644 Platforms/Hisilicon/Binary/D05/fip.bin create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
Modify PCIe transaction memory attribute to improve performance, like SMMU bypass, cache snoopy, etc.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang wanghuiqiang@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 ++ .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 52 ++++++++++++++++++++++ Chips/Hisilicon/HisiPkg.dec | 1 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 1 + Platforms/Hisilicon/D03/D03.dsc | 1 + 5 files changed, 58 insertions(+) mode change 100755 => 100644 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 63d8bb1..8659e29 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -53,6 +53,9 @@ gHisiTokenSpaceGuid.Pcdsoctype gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress
+[FeaturePcd] + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable + [depex] TRUE
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c old mode 100755 new mode 100644 index 06ecf87..39b9ea7 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -21,6 +21,8 @@ #include <Library/IoLib.h> #include <Library/TimerLib.h>
+#define PCIE_SYS_REG_OFFSET 0x1000 + static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000}; @@ -185,6 +187,50 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
}
+STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +{ + UINT32 Value; + UINTN RegSegmentOffset; + + if (Port >= PCIE_MAX_ROOTBRIDGE) { + DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port)); + return EFI_INVALID_PARAMETER; + } + + RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET; + + //Enable SMMU bypass for translation + RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); + //BIT13: controller master read SMMU bypass + //BIT12: controller master write SMMU bypass + //BIT10: SMMU bypass enable + Value |= (BIT13 | BIT12 | BIT10); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); + + //Switch strongly order (SO) to relaxed order (RO) for write transaction + RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value); + //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge + Value |= (BIT13 | BIT12); + //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction + Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17); + RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value); + + //Force streamID for controller read operation + RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); + //Force using streamID in PCIE_SYS_CTRL54_REG + Value &= ~(BIT30); + //Set streamID to 0, bit[0:15] is for request ID and should be kept + Value &= ~(0xff << 16); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); + + //Enable read and write snoopy + RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); + Value |= (BIT30 | BIT28); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); + + return EFI_SUCCESS; +} + EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { PCIE_CTRL_7_U pcie_ctrl7; @@ -939,6 +985,12 @@ PciePortInit (
/* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); + if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { + //PCIe will still work even if performance tuning fails, + //and there is warning message inside the function to print + //detailed error if there is. + (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex); + }
PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 8e46e0d..2ce60d9 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -161,6 +161,7 @@ gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056
[PcdsFeatureFlag] + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066
diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bdd80f8..539d567 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8981,6 +8981,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4) #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) +#define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 6d82627..942b2b8 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -111,6 +111,7 @@ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE
[PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
1.Hi1616 has 8 root ports for each SOC (Host bridge), so we first extend PCIe related modules to support maximum 8 root ports. And the Pcie related base addresses are different between Hi1610 and Hi1616, so we move the Pcie address definitions to PlatformPciLib which is a platform lib. 2.PCIE_MAX_ROOTBRIDGE and PCIE_MAX_PORT_NUM are duplicated macro difinitions; unify to use PCIE_MAX_ROOTBRIDGE only. 3.PCIE_MAX_HOSTBRIDGE and PCIE_HOST_BRIDGE_NUM are duplicated; unify to use PCIE_MAX_HOSTBRIDGE.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 216 ++++++++++++++++++++- .../Hi1610/Drivers/PcieInit1610/PcieInit.c | 59 +++++- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 120 ++++++------ .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 13 +- .../Hi1610/Drivers/PcieInit1610/PcieKernelApi.h | 2 - Chips/Hisilicon/HisiPkg.dec | 110 +++++++++++ Chips/Hisilicon/Include/Library/PlatformPciLib.h | 140 +++++++++++-- .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 118 ++++++++++- .../D03/Library/PlatformPciLib/PlatformPciLib.c | 8 + .../D03/Library/PlatformPciLib/PlatformPciLib.inf | 118 ++++++++++- 10 files changed, 791 insertions(+), 113 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index ccc263e..a970da6 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -30,12 +30,20 @@ UINT64 RootBridgeAttribute[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, }, { //Host Bridge1 EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, } };
@@ -136,6 +144,102 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] 0 } } + }, + /* Port 4 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A07), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + /* Port 5 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A08), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + /* Port 6 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A09), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + /* Port 7 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A0A), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } } }, { // Host Bridge1 @@ -150,7 +254,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } }, - EISA_PNP_ID(0x0A07), + EISA_PNP_ID(0x0A0B), 0 },
@@ -174,7 +278,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } }, - EISA_PNP_ID(0x0A08), + EISA_PNP_ID(0x0A0C), 0 },
@@ -198,7 +302,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } }, - EISA_PNP_ID(0x0A09), + EISA_PNP_ID(0x0A0D), 0 },
@@ -222,7 +326,103 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE] (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) } }, - EISA_PNP_ID(0x0A0A), + EISA_PNP_ID(0x0A0E), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + /* Port 4 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A0F), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + /* Port 5 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A10), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + /* Port 6 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A11), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + /* Port 7 */ + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A12), 0 },
@@ -286,7 +486,6 @@ InitializePciHostBridge ( if (!OemIsMpBoot()) { PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask); - PcieRootBridgeMask &= 0xf; } else { @@ -297,9 +496,10 @@ InitializePciHostBridge ( // // Create Host Bridge Device Handle // - + //Each Host Bridge have 8 Root Bridges max, every bits of 0xFF(8 bit) stands for the according PCIe Port + //is enable or not for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) { - if (((PcieRootBridgeMask >> (4 * Loop1)) & 0xF ) == 0) { + if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) { continue; }
@@ -326,7 +526,7 @@ InitializePciHostBridge ( // Create Root Bridge Device Handle in this Host Bridge // for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) { - if (!(((PcieRootBridgeMask >> (4 * Loop1)) >> Loop2 ) & 0x01)) { + if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) { continue; }
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c index 284fa3f..5fc0ead 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c @@ -17,13 +17,14 @@ #include <Library/UefiBootServicesTableLib.h> #include <Library/PcdLib.h> #include <Library/OemMiscLib.h> +#include <Library/PlatformPciLib.h>
extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value); extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port); extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
-PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] = +PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] = { //Port 0 { @@ -69,6 +70,46 @@ PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] = },
}, + //Port 4 + { + 0x4, //Portindex + { + PCIE_ROOT_COMPLEX, //PortType + PCIE_WITDH_X8, //PortWidth + PCIE_GEN3_0, //PortGen + }, + + }, + //Port 5 + { + 0x5, //Portindex + { + PCIE_ROOT_COMPLEX, //PortType + PCIE_WITDH_X8, //PortWidth + PCIE_GEN3_0, //PortGen + }, + + }, + //Port 6 + { + 0x6, //Portindex + { + PCIE_ROOT_COMPLEX, //PortType + PCIE_WITDH_X8, //PortWidth + PCIE_GEN3_0, //PortGen + }, + + }, + //Port 7 + { + 0x7, //Portindex + { + PCIE_ROOT_COMPLEX, //PortType + PCIE_WITDH_X8, //PortWidth + PCIE_GEN3_0, //PortGen + }, + + }, };
EFI_STATUS @@ -88,7 +129,6 @@ PcieInitEntry ( if (!OemIsMpBoot()) { PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask); - PcieRootBridgeMask &= 0xf; } else { @@ -96,12 +136,15 @@ PcieInitEntry ( }
soctype = PcdGet32(Pcdsoctype); - for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++) - { - for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++) - { - if (!(((( PcieRootBridgeMask >> (4 * HostBridgeNum))) >> Port) & 0x1)) - { + for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) { + for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) { + /* + Host Bridge may contain lots of root bridges. + Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges + PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits, + and each bit stands for this PCIe Port is enable or not + */ + if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) { continue; }
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 39b9ea7..e58d87c 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -19,23 +19,20 @@ #include <Library/BaseLib.h> #include <Library/BaseMemoryLib.h> #include <Library/IoLib.h> +#include <Library/PlatformPciLib.h> #include <Library/TimerLib.h>
#define PCIE_SYS_REG_OFFSET 0x1000
static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; -UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000}; UINT64 io_sub0_base = 0xa0000000; UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000}; #define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000)) -UINT64 PCIE_APB_SLAVE_BASE_1610[2][4] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000}, - {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}}; -UINT64 PCIE_PHY_BASE_1610[2][4] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000}, - {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}}; UINT32 loop_test_flag[4] = {0,0,0,0}; UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR; #define PcieMaxLanNum 8 +#define PCIE_PORT_NUM_IN_SICL 4 //SICL: Super IO Cluster
extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; @@ -158,8 +155,7 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0;
- if(Port >= PCIE_MAX_PORT_NUM) - { + if (Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
@@ -236,8 +232,7 @@ EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0;
- if(Port >= PCIE_MAX_PORT_NUM) - { + if(Port >= PCIE_MAX_ROOTBRIDGE) { return PCIE_ERR_PARAM_INVALID; }
@@ -269,8 +264,7 @@ EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed) { PCIE_EP_PCIE_CAP12_U pcie_cap12;
- if(Port >= PCIE_MAX_PORT_NUM) - { + if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
@@ -293,8 +287,7 @@ EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width) PCIE_EP_PORT_LOGIC4_U pcie_logic4; PCIE_EP_PORT_LOGIC22_U logic22;
- if(Port >= PCIE_MAX_PORT_NUM) - { + if(Port >= PCIE_MAX_ROOTBRIDGE) { return PCIE_ERR_PARAM_INVALID; }
@@ -353,8 +346,7 @@ EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width) PCIE_EP_PORT_LOGIC22_U logic22; PCIE_EEP_PCI_CFG_HDR15_U hdr15; UINT32 Value = 0; - if(Port >= PCIE_MAX_PORT_NUM) - { + if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
@@ -440,8 +432,7 @@ EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_P { PCIE_CTRL_0_U str_pcie_ctrl_0;
- if(Port >= PCIE_MAX_PORT_NUM) - { + if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
@@ -622,8 +613,8 @@ EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { - if(Port >= PCIE_MAX_PORT_NUM) - { + UINT32 PortIndexInSicl; + if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
@@ -634,14 +625,14 @@ EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port
if (0x1610 == soctype) { - if(Port <= 2) - { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x3); + PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; + if (PortIndexInSicl <= 2) { + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3); MicroSecondDelay(0x1000); } else { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3); MicroSecondDelay(0x1000); } } @@ -664,8 +655,8 @@ EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port
EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { - if(Port >= PCIE_MAX_PORT_NUM) - { + UINT32 PortIndexInSicl; + if(Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
@@ -676,14 +667,14 @@ EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Po
if (0x1610 == soctype) { - if(Port <= 2) - { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x3); + PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; + if (PortIndexInSicl <= 2) { + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3); MicroSecondDelay(0x1000); } else { - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x3); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG, 0x3); MicroSecondDelay(0x1000); } } @@ -707,20 +698,21 @@ EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Po EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { u_sc_pcie_hilink_pcs_reset_req reset_req; + UINT32 PortIndexInSicl; if (0x1610 == soctype) { - if(Port <= 3) - { - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32); - - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port)); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32); - MicroSecondDelay(0x1000); - } + PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; + reset_req.UInt32 = 0; + reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32); + + reset_req.UInt32 = 0; + reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl)); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32); + //0x1000 microseconds delay comes from experiment and + //should be fairly enough for this operation. + MicroSecondDelay(0x1000); } else { @@ -742,20 +734,21 @@ EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { u_sc_pcie_hilink_pcs_reset_req reset_req; + UINT32 PortIndexInSicl; if (0x1610 == soctype) { - if(Port <= 3) - { - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + 0xacc, reset_req.UInt32); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32); - - reset_req.UInt32 = 0; - reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port)); - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32); - MicroSecondDelay(0x1000); - } + PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; + reset_req.UInt32 = 0; + reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32); + + reset_req.UInt32 = 0; + reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl)); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32); + //0x1000 microseconds delay comes from experimenti + // and should be fairly enough for this operation. + MicroSecondDelay(0x1000); } else { @@ -779,21 +772,22 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, { UINT32 reg_clock_disable; UINT32 reg_clock_enable; - - if (Port == 3) { + UINT32 PortIndexInSicl; + PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL; + if (PortIndexInSicl == 3) { reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG; reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG; } else { - reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port); - reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port); + reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(PortIndexInSicl); + reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(PortIndexInSicl); }
if (0x1610 == soctype) { if (Clock) - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + reg_clock_enable, 0x7); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7); else - RegWrite(pcie_subctrl_base_1610[HostBridgeNum] + reg_clock_disable, 0x7); + RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7); } else { @@ -933,15 +927,14 @@ PciePortInit ( UINT16 Count = 0; UINT32 PortIndex = PcieCfg->PortIndex;
- if(PortIndex >= PCIE_MAX_PORT_NUM) - { + if (PortIndex >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
if (0x1610 == soctype) { mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex]; - DEBUG((EFI_D_INFO, "Soc type is 1610\n")); + DEBUG((DEBUG_INFO, "Soc type is 161x\n")); } else { @@ -1024,8 +1017,7 @@ EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable) { PCIE_SYS_CTRL20_U dbi_ro_enable;
- if(Port >= PCIE_MAX_PORT_NUM) - { + if (Port >= PCIE_MAX_ROOTBRIDGE) { return EFI_INVALID_PARAMETER; }
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 5824b1a..1e8db97 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -19,6 +19,7 @@
#include <Uefi.h> #include <Library/IoLib.h> +#include <Library/PlatformPciLib.h> #include <Regs/HisiPcieV1RegOffset.h> #include "PcieKernelApi.h"
@@ -147,12 +148,12 @@ typedef struct { } PCIE_MAPPED_IATU_ADDR;
typedef struct { - BOOLEAN PortIsInitilized[PCIE_MAX_PORT_NUM]; - DRIVER_CFG_U Dev[PCIE_MAX_PORT_NUM]; - VOID *DmaResource[PCIE_MAX_PORT_NUM]; - UINT32 DmaChannel[PCIE_MAX_PORT_NUM][2]; - VOID *RegResource[PCIE_MAX_PORT_NUM]; - VOID *CfgResource[PCIE_MAX_PORT_NUM]; + BOOLEAN PortIsInitilized[PCIE_MAX_ROOTBRIDGE]; + DRIVER_CFG_U Dev[PCIE_MAX_ROOTBRIDGE]; + VOID *DmaResource[PCIE_MAX_ROOTBRIDGE]; + UINT32 DmaChannel[PCIE_MAX_ROOTBRIDGE][PCIE_DMA_CHANNEL_NUM]; + VOID *RegResource[PCIE_MAX_ROOTBRIDGE]; + VOID *CfgResource[PCIE_MAX_ROOTBRIDGE]; } PCIE_INIT_CFG;
typedef enum { diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h index d1ba1c8..db89597 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieKernelApi.h @@ -16,8 +16,6 @@ #ifndef __PCIE_KERNEL_API_H__ #define __PCIE_KERNEL_API_H__
-#define PCIE_HOST_BRIDGE_NUM (1) -#define PCIE_MAX_PORT_NUM (4) #define PCIE_MAX_OUTBOUND (6) #define PCIE_MAX_INBOUND (4) #define PCIE3_MAX_OUTBOUND (16) diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 2ce60d9..fca0b70 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -121,40 +121,150 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0|UINT64|0x00000057 gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000058 gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0|UINT64|0x00000059 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000152 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0|UINT64|0x00000153 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000154 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0|UINT64|0x00000155 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000156 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0|UINT64|0x00000157 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000158 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0|UINT64|0x00000159 + + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0|UINT64|0x00000252 + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0|UINT64|0x00000253 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0|UINT64|0x00000254 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0|UINT64|0x00000255 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0|UINT64|0x00000256 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0|UINT64|0x00000257 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0|UINT64|0x00000258 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0|UINT64|0x00000259 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0|UINT64|0x00000352 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0|UINT64|0x00000353 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0|UINT64|0x00000354 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0|UINT64|0x00000355 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0|UINT64|0x00000356 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0|UINT64|0x00000357 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0|UINT64|0x00000358 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0|UINT64|0x00000359
gHisiTokenSpaceGuid.PciHb0Rb0Base|0|UINT64|0x0000005a gHisiTokenSpaceGuid.PciHb0Rb1Base|0|UINT64|0x0000005b gHisiTokenSpaceGuid.PciHb0Rb2Base|0|UINT64|0x0000005c gHisiTokenSpaceGuid.PciHb0Rb3Base|0|UINT64|0x0000005d + gHisiTokenSpaceGuid.PciHb0Rb4Base|0|UINT64|0x0100005a + gHisiTokenSpaceGuid.PciHb0Rb5Base|0|UINT64|0x0100005b + gHisiTokenSpaceGuid.PciHb0Rb6Base|0|UINT64|0x0100005c + gHisiTokenSpaceGuid.PciHb0Rb7Base|0|UINT64|0x0100005d + gHisiTokenSpaceGuid.PciHb1Rb0Base|0|UINT64|0x0200005a + gHisiTokenSpaceGuid.PciHb1Rb1Base|0|UINT64|0x0200005b + gHisiTokenSpaceGuid.PciHb1Rb2Base|0|UINT64|0x0200005c + gHisiTokenSpaceGuid.PciHb1Rb3Base|0|UINT64|0x0200005d + gHisiTokenSpaceGuid.PciHb1Rb4Base|0|UINT64|0x0300005a + gHisiTokenSpaceGuid.PciHb1Rb5Base|0|UINT64|0x0300005b + gHisiTokenSpaceGuid.PciHb1Rb6Base|0|UINT64|0x0300005c + gHisiTokenSpaceGuid.PciHb1Rb7Base|0|UINT64|0x0300005d + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0|UINT64|0x8000005a gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0|UINT64|0x8000005b gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0|UINT64|0x8000005c gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0|UINT64|0x8000005d + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0|UINT64|0x8000005e + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0|UINT64|0x8000005f + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0|UINT64|0x80000060 + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0|UINT64|0x80000061 + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0|UINT64|0x80000062 + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0|UINT64|0x80000063 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0|UINT64|0x80000064 + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0|UINT64|0x80000065 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0|UINT64|0x80000066 + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0|UINT64|0x80000067 + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0|UINT64|0x80000068 + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0|UINT64|0x80000069
gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0|UINT64|0x6000005a gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0|UINT64|0x6000005b gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0|UINT64|0x6000005c gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0|UINT64|0x6000005d + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0|UINT64|0x6000005e + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0|UINT64|0x6000005f + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0|UINT64|0x60000060 + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0|UINT64|0x60000061 + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0|UINT64|0x60000062 + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0|UINT64|0x60000063 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0|UINT64|0x60000064 + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0|UINT64|0x60000065 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0|UINT64|0x60000066 + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0|UINT64|0x60000067 + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0|UINT64|0x60000068 + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0|UINT64|0x60000069
gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0|UINT64|0x7000005a gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0|UINT64|0x7000005b gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0|UINT64|0x7000005c gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0|UINT64|0x7000005d + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0|UINT64|0x7000005e + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0|UINT64|0x7000005f + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0|UINT64|0x70000060 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0|UINT64|0x70000061 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0|UINT64|0x70000062 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0|UINT64|0x70000063 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0|UINT64|0x70000064 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0|UINT64|0x70000065 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0|UINT64|0x70000066 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0|UINT64|0x70000067 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0|UINT64|0x70000068 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0|UINT64|0x70000069
gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0|UINT64|0x3000005a gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0|UINT64|0x3000005b gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0|UINT64|0x3000005c gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0|UINT64|0x3000005d + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0|UINT64|0x3000005e + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0|UINT64|0x30000070 + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0|UINT64|0x30000061 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0|UINT64|0x30000062 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0|UINT64|0x30000063 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0|UINT64|0x30000064 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0|UINT64|0x30000065 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0|UINT64|0x30000066 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0|UINT64|0x30000067 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0|UINT64|0x30000068 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0|UINT64|0x30000069 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0|UINT64|0x3000006a
gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0|UINT64|0x9000005a gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0|UINT64|0x9000005b gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0|UINT64|0x9000005c gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0|UINT64|0x9000005d + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0|UINT64|0x9100005a + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0|UINT64|0x9100005b + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0|UINT64|0x9100005c + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0|UINT64|0x9100005d + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0|UINT64|0x9010005a + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0|UINT64|0x9010005b + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0|UINT64|0x9010005c + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0|UINT64|0x9010005d + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0|UINT64|0x9110005a + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0|UINT64|0x9110005b + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0|UINT64|0x9110005c + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0|UINT64|0x9110005d
gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0|UINT64|0x2000005a gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0|UINT64|0x2000005b gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0|UINT64|0x2000005c gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0|UINT64|0x2000005d + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0|UINT64|0x2100005a + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0|UINT64|0x2100005b + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0|UINT64|0x2100005c + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0|UINT64|0x2100005d + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0|UINT64|0x2010005a + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0|UINT64|0x2010005b + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0|UINT64|0x2010005c + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0|UINT64|0x2010005d + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0|UINT64|0x2110005a + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0|UINT64|0x2110005b + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0|UINT64|0x2110005c + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d
gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061 gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064 diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h index 72d2d21..e3228db 100644 --- a/Chips/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h @@ -17,17 +17,31 @@ #define _PLATFORM_PCI_LIB_H_
#define PCIE_MAX_HOSTBRIDGE 2 -#define PCIE_MAX_ROOTBRIDGE 4 +#define PCIE_MAX_ROOTBRIDGE 8 +//The extern pcie addresses will be initialized by oemmisclib +extern UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; +extern UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; +extern UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; +extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; +
#define PCI_HB0RB0_PCI_BASE FixedPcdGet64(PciHb0Rb0Base) #define PCI_HB0RB1_PCI_BASE FixedPcdGet64(PciHb0Rb1Base) #define PCI_HB0RB2_PCI_BASE FixedPcdGet64(PciHb0Rb2Base) #define PCI_HB0RB3_PCI_BASE FixedPcdGet64(PciHb0Rb3Base) +#define PCI_HB0RB4_PCI_BASE FixedPcdGet64(PciHb0Rb4Base) +#define PCI_HB0RB5_PCI_BASE FixedPcdGet64(PciHb0Rb5Base) +#define PCI_HB0RB6_PCI_BASE FixedPcdGet64(PciHb0Rb6Base) +#define PCI_HB0RB7_PCI_BASE FixedPcdGet64(PciHb0Rb7Base)
-#define PCI_HB1RB0_PCI_BASE 0xb0090000 -#define PCI_HB1RB1_PCI_BASE 0xb0200000 -#define PCI_HB1RB2_PCI_BASE 0xb00a0000 -#define PCI_HB1RB3_PCI_BASE 0xb00b0000 +#define PCI_HB1RB0_PCI_BASE FixedPcdGet64(PciHb1Rb0Base) +#define PCI_HB1RB1_PCI_BASE FixedPcdGet64(PciHb1Rb1Base) +#define PCI_HB1RB2_PCI_BASE FixedPcdGet64(PciHb1Rb2Base) +#define PCI_HB1RB3_PCI_BASE FixedPcdGet64(PciHb1Rb3Base) +#define PCI_HB1RB4_PCI_BASE FixedPcdGet64(PciHb1Rb4Base) +#define PCI_HB1RB5_PCI_BASE FixedPcdGet64(PciHb1Rb5Base) +#define PCI_HB1RB6_PCI_BASE FixedPcdGet64(PciHb1Rb6Base) +#define PCI_HB1RB7_PCI_BASE FixedPcdGet64(PciHb1Rb7Base)
#define PCI_HB0RB0_ECAM_BASE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceBaseAddress) #define PCI_HB0RB0_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb0PciConfigurationSpaceSize) @@ -37,15 +51,32 @@ #define PCI_HB0RB2_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb2PciConfigurationSpaceSize) #define PCI_HB0RB3_ECAM_BASE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceBaseAddress) #define PCI_HB0RB3_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb3PciConfigurationSpaceSize) +#define PCI_HB0RB4_ECAM_BASE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB4_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb4PciConfigurationSpaceSize) +#define PCI_HB0RB5_ECAM_BASE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB5_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb5PciConfigurationSpaceSize) +#define PCI_HB0RB6_ECAM_BASE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB6_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb6PciConfigurationSpaceSize) +#define PCI_HB0RB7_ECAM_BASE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceBaseAddress) +#define PCI_HB0RB7_ECAM_SIZE FixedPcdGet64 (PcdHb0Rb7PciConfigurationSpaceSize) + +#define PCI_HB1RB0_ECAM_BASE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB0_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb0PciConfigurationSpaceSize) +#define PCI_HB1RB1_ECAM_BASE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB1_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb1PciConfigurationSpaceSize) +#define PCI_HB1RB2_ECAM_BASE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB2_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb2PciConfigurationSpaceSize) +#define PCI_HB1RB3_ECAM_BASE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB3_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb3PciConfigurationSpaceSize) +#define PCI_HB1RB4_ECAM_BASE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB4_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb4PciConfigurationSpaceSize) +#define PCI_HB1RB5_ECAM_BASE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB5_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb5PciConfigurationSpaceSize) +#define PCI_HB1RB6_ECAM_BASE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB6_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb6PciConfigurationSpaceSize) +#define PCI_HB1RB7_ECAM_BASE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceBaseAddress) +#define PCI_HB1RB7_ECAM_SIZE FixedPcdGet64 (PcdHb1Rb7PciConfigurationSpaceSize)
-#define PCI_HB1RB0_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB0_ECAM_BASE) -#define PCI_HB1RB0_ECAM_SIZE PCI_HB0RB0_ECAM_SIZE -#define PCI_HB1RB1_ECAM_BASE (FixedPcdGet64 (PcdHb1BaseAddress) + PCI_HB0RB1_ECAM_BASE) -#define PCI_HB1RB1_ECAM_SIZE PCI_HB0RB1_ECAM_SIZE -#define PCI_HB1RB2_ECAM_BASE 0xb8000000 -#define PCI_HB1RB2_ECAM_SIZE 0x4000000 -#define PCI_HB1RB3_ECAM_BASE 0xbc000000 -#define PCI_HB1RB3_ECAM_SIZE 0x4000000 #define PCI_HB0RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb0PciRegionBaseAddress)) #define PCI_HB0RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb0PciRegionSize)) #define PCI_HB0RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb1PciRegionBaseAddress)) @@ -54,26 +85,109 @@ #define PCI_HB0RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb2PciRegionSize)) #define PCI_HB0RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb3PciRegionBaseAddress)) #define PCI_HB0RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb3PciRegionSize)) +#define PCI_HB0RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb4PciRegionBaseAddress)) +#define PCI_HB0RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb4PciRegionSize)) +#define PCI_HB0RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb5PciRegionBaseAddress)) +#define PCI_HB0RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb5PciRegionSize)) +#define PCI_HB0RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb6PciRegionBaseAddress)) +#define PCI_HB0RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb6PciRegionSize)) +#define PCI_HB0RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb0Rb7PciRegionBaseAddress)) +#define PCI_HB0RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb0Rb7PciRegionSize)) + +#define PCI_HB1RB0_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb0PciRegionBaseAddress)) +#define PCI_HB1RB0_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb0PciRegionSize)) +#define PCI_HB1RB1_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb1PciRegionBaseAddress)) +#define PCI_HB1RB1_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb1PciRegionSize)) +#define PCI_HB1RB2_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb2PciRegionBaseAddress)) +#define PCI_HB1RB2_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb2PciRegionSize)) +#define PCI_HB1RB3_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb3PciRegionBaseAddress)) +#define PCI_HB1RB3_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb3PciRegionSize)) +#define PCI_HB1RB4_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb4PciRegionBaseAddress)) +#define PCI_HB1RB4_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb4PciRegionSize)) +#define PCI_HB1RB5_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb5PciRegionBaseAddress)) +#define PCI_HB1RB5_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb5PciRegionSize)) +#define PCI_HB1RB6_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb6PciRegionBaseAddress)) +#define PCI_HB1RB6_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb6PciRegionSize)) +#define PCI_HB1RB7_PCIREGION_BASE (FixedPcdGet64 (PcdHb1Rb7PciRegionBaseAddress)) +#define PCI_HB1RB7_PCIREGION_SIZE (FixedPcdGet64 (PcdHb1Rb7PciRegionSize)) +
#define PCI_HB0RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuMemRegionBase)) #define PCI_HB0RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuMemRegionBase)) #define PCI_HB0RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuMemRegionBase)) #define PCI_HB0RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuMemRegionBase)) +#define PCI_HB0RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuMemRegionBase)) +#define PCI_HB0RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuMemRegionBase)) +#define PCI_HB0RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuMemRegionBase)) +#define PCI_HB0RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuMemRegionBase)) + +#define PCI_HB1RB0_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuMemRegionBase)) +#define PCI_HB1RB1_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuMemRegionBase)) +#define PCI_HB1RB2_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuMemRegionBase)) +#define PCI_HB1RB3_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuMemRegionBase)) +#define PCI_HB1RB4_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuMemRegionBase)) +#define PCI_HB1RB5_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuMemRegionBase)) +#define PCI_HB1RB6_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuMemRegionBase)) +#define PCI_HB1RB7_CPUMEMREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuMemRegionBase)) +
#define PCI_HB0RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb0CpuIoRegionBase)) #define PCI_HB0RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb1CpuIoRegionBase)) #define PCI_HB0RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb2CpuIoRegionBase)) #define PCI_HB0RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb3CpuIoRegionBase)) +#define PCI_HB0RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb4CpuIoRegionBase)) +#define PCI_HB0RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb5CpuIoRegionBase)) +#define PCI_HB0RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb6CpuIoRegionBase)) +#define PCI_HB0RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb0Rb7CpuIoRegionBase)) + +#define PCI_HB1RB0_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb0CpuIoRegionBase)) +#define PCI_HB1RB1_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb1CpuIoRegionBase)) +#define PCI_HB1RB2_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb2CpuIoRegionBase)) +#define PCI_HB1RB3_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb3CpuIoRegionBase)) +#define PCI_HB1RB4_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb4CpuIoRegionBase)) +#define PCI_HB1RB5_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb5CpuIoRegionBase)) +#define PCI_HB1RB6_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb6CpuIoRegionBase)) +#define PCI_HB1RB7_CPUIOREGIONBASE (FixedPcdGet64 (PcdHb1Rb7CpuIoRegionBase)) + +
#define PCI_HB0RB0_IO_BASE (FixedPcdGet64 (PcdHb0Rb0IoBase)) #define PCI_HB0RB1_IO_BASE (FixedPcdGet64 (PcdHb0Rb1IoBase)) #define PCI_HB0RB2_IO_BASE (FixedPcdGet64 (PcdHb0Rb2IoBase)) #define PCI_HB0RB3_IO_BASE (FixedPcdGet64 (PcdHb0Rb3IoBase)) +#define PCI_HB0RB4_IO_BASE (FixedPcdGet64 (PcdHb0Rb4IoBase)) +#define PCI_HB0RB5_IO_BASE (FixedPcdGet64 (PcdHb0Rb5IoBase)) +#define PCI_HB0RB6_IO_BASE (FixedPcdGet64 (PcdHb0Rb6IoBase)) +#define PCI_HB0RB7_IO_BASE (FixedPcdGet64 (PcdHb0Rb7IoBase)) + +#define PCI_HB1RB0_IO_BASE (FixedPcdGet64 (PcdHb1Rb0IoBase)) +#define PCI_HB1RB1_IO_BASE (FixedPcdGet64 (PcdHb1Rb1IoBase)) +#define PCI_HB1RB2_IO_BASE (FixedPcdGet64 (PcdHb1Rb2IoBase)) +#define PCI_HB1RB3_IO_BASE (FixedPcdGet64 (PcdHb1Rb3IoBase)) +#define PCI_HB1RB4_IO_BASE (FixedPcdGet64 (PcdHb1Rb4IoBase)) +#define PCI_HB1RB5_IO_BASE (FixedPcdGet64 (PcdHb1Rb5IoBase)) +#define PCI_HB1RB6_IO_BASE (FixedPcdGet64 (PcdHb1Rb6IoBase)) +#define PCI_HB1RB7_IO_BASE (FixedPcdGet64 (PcdHb1Rb7IoBase))
#define PCI_HB0RB0_IO_SIZE (FixedPcdGet64 (PcdHb0Rb0IoSize)) #define PCI_HB0RB1_IO_SIZE (FixedPcdGet64 (PcdHb0Rb1IoSize)) #define PCI_HB0RB2_IO_SIZE (FixedPcdGet64 (PcdHb0Rb2IoSize)) #define PCI_HB0RB3_IO_SIZE (FixedPcdGet64 (PcdHb0Rb3IoSize)) +#define PCI_HB0RB4_IO_SIZE (FixedPcdGet64 (PcdHb0Rb4IoSize)) +#define PCI_HB0RB5_IO_SIZE (FixedPcdGet64 (PcdHb0Rb5IoSize)) +#define PCI_HB0RB6_IO_SIZE (FixedPcdGet64 (PcdHb0Rb6IoSize)) +#define PCI_HB0RB7_IO_SIZE (FixedPcdGet64 (PcdHb0Rb7IoSize)) + +#define PCI_HB1RB0_IO_SIZE (FixedPcdGet64 (PcdHb1Rb0IoSize)) +#define PCI_HB1RB1_IO_SIZE (FixedPcdGet64 (PcdHb1Rb1IoSize)) +#define PCI_HB1RB2_IO_SIZE (FixedPcdGet64 (PcdHb1Rb2IoSize)) +#define PCI_HB1RB3_IO_SIZE (FixedPcdGet64 (PcdHb1Rb3IoSize)) +#define PCI_HB1RB4_IO_SIZE (FixedPcdGet64 (PcdHb1Rb4IoSize)) +#define PCI_HB1RB5_IO_SIZE (FixedPcdGet64 (PcdHb1Rb5IoSize)) +#define PCI_HB1RB6_IO_SIZE (FixedPcdGet64 (PcdHb1Rb6IoSize)) +#define PCI_HB1RB7_IO_SIZE (FixedPcdGet64 (PcdHb1Rb7IoSize)) + +
typedef struct { UINT64 Ecam; diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf index 5040a04..c9ce45f 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf @@ -40,37 +40,143 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize gHisiTokenSpaceGuid.PciHb0Rb0Base gHisiTokenSpaceGuid.PciHb0Rb1Base gHisiTokenSpaceGuid.PciHb0Rb2Base gHisiTokenSpaceGuid.PciHb0Rb3Base + gHisiTokenSpaceGuid.PciHb0Rb4Base + gHisiTokenSpaceGuid.PciHb0Rb5Base + gHisiTokenSpaceGuid.PciHb0Rb6Base + gHisiTokenSpaceGuid.PciHb0Rb7Base + gHisiTokenSpaceGuid.PciHb1Rb0Base + gHisiTokenSpaceGuid.PciHb1Rb1Base + gHisiTokenSpaceGuid.PciHb1Rb2Base + gHisiTokenSpaceGuid.PciHb1Rb3Base + gHisiTokenSpaceGuid.PciHb1Rb4Base + gHisiTokenSpaceGuid.PciHb1Rb5Base + gHisiTokenSpaceGuid.PciHb1Rb6Base + gHisiTokenSpaceGuid.PciHb1Rb7Base gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize - - gHisiTokenSpaceGuid.PcdHb0Rb2IoBase - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize gHisiTokenSpaceGuid.PcdHb0Rb0IoBase gHisiTokenSpaceGuid.PcdHb0Rb0IoSize gHisiTokenSpaceGuid.PcdHb0Rb1IoBase gHisiTokenSpaceGuid.PcdHb0Rb1IoSize gHisiTokenSpaceGuid.PcdHb0Rb2IoBase gHisiTokenSpaceGuid.PcdHb0Rb2IoSize - + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index 5ce7731..a08b461 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -15,6 +15,14 @@
#include <Library/PcdLib.h> #include <Library/PlatformPciLib.h> +UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000}, + {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}}; +UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000}, + {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}}; +UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000}, + {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}}; +UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}, + {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}};
PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { {// HostBridge 0 diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf index 5040a04..c9ce45f 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf @@ -40,37 +40,143 @@ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize gHisiTokenSpaceGuid.PciHb0Rb0Base gHisiTokenSpaceGuid.PciHb0Rb1Base gHisiTokenSpaceGuid.PciHb0Rb2Base gHisiTokenSpaceGuid.PciHb0Rb3Base + gHisiTokenSpaceGuid.PciHb0Rb4Base + gHisiTokenSpaceGuid.PciHb0Rb5Base + gHisiTokenSpaceGuid.PciHb0Rb6Base + gHisiTokenSpaceGuid.PciHb0Rb7Base + gHisiTokenSpaceGuid.PciHb1Rb0Base + gHisiTokenSpaceGuid.PciHb1Rb1Base + gHisiTokenSpaceGuid.PciHb1Rb2Base + gHisiTokenSpaceGuid.PciHb1Rb3Base + gHisiTokenSpaceGuid.PciHb1Rb4Base + gHisiTokenSpaceGuid.PciHb1Rb5Base + gHisiTokenSpaceGuid.PciHb1Rb6Base + gHisiTokenSpaceGuid.PciHb1Rb7Base gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize - - gHisiTokenSpaceGuid.PcdHb0Rb2IoBase - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize gHisiTokenSpaceGuid.PcdHb0Rb0IoBase gHisiTokenSpaceGuid.PcdHb0Rb0IoSize gHisiTokenSpaceGuid.PcdHb0Rb1IoBase gHisiTokenSpaceGuid.PcdHb0Rb1IoSize gHisiTokenSpaceGuid.PcdHb0Rb2IoBase gHisiTokenSpaceGuid.PcdHb0Rb2IoSize - + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
Most of PCIe memory BARs can only be mapped to 4G above system address, for there is not enough address space under 4G. However, some legacy PCIe devices may require to be mapped into 32bit address. To support such devices, a pair of new parameters is introduced to expose memory address under 4G in PCIe domain, which can be different from the address in system domain, by setting iATU accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 2 ++ .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 6 ++-- Chips/Hisilicon/Include/Library/PlatformPciLib.h | 2 ++ .../D02/Library/PlatformPciLib/PlatformPciLib.c | 32 +++++++++++++++------ .../D03/Library/PlatformPciLib/PlatformPciLib.c | 33 ++++++++++++++++------ 5 files changed, 57 insertions(+), 18 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index 99c97cf..cddda6b 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -478,6 +478,8 @@ typedef struct { UINT32 SocType; UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase; + UINT64 PciRegionBase; + UINT64 PciRegionLimit;
EFI_DEVICE_PATH_PROTOCOL *DevicePath; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 01aa1e0..03edcf1 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -730,7 +730,7 @@ void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT6
VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private) { - SetAtuMemRW (Private->RbPciBar, Private->MemBase, Private->MemLimit, Private->CpuMemRegionBase, 0); + SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0); SetAtuConfig0RW (Private, 1); SetAtuConfig1RW (Private, 2); SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3); @@ -800,6 +800,8 @@ RootBridgeConstructor ( PrivateData->Ecam = ResAppeture->Ecam; PrivateData->CpuMemRegionBase = ResAppeture->CpuMemRegionBase; PrivateData->CpuIoRegionBase = ResAppeture->CpuIoRegionBase; + PrivateData->PciRegionBase = ResAppeture->PciRegionBase; + PrivateData->PciRegionLimit = ResAppeture->PciRegionLimit;
// // Bus Appeture for this Root Bridge (Possible Range) @@ -1058,7 +1060,7 @@ RootBridgeIoMemRW (
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); /* Address is bus resource */ - Address -= PrivateData->MemBase; + Address -= PrivateData->PciRegionBase; Address += PrivateData->CpuMemRegionBase;
PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address); diff --git a/Chips/Hisilicon/Include/Library/PlatformPciLib.h b/Chips/Hisilicon/Include/Library/PlatformPciLib.h index e3228db..9d28fec 100644 --- a/Chips/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformPciLib.h @@ -200,6 +200,8 @@ typedef struct { UINT64 CpuMemRegionBase; UINT64 CpuIoRegionBase; UINT64 RbPciBar; + UINT64 PciRegionBase; + UINT64 PciRegionLimit; } PCI_ROOT_BRIDGE_RESOURCE_APPETURE;
extern PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; diff --git a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c index b487b5f..797163a 100644 --- a/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c @@ -29,7 +29,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB0RB0_PCI_BASE) //RbPciBar + (PCI_HB0RB0_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 1 */ { @@ -42,7 +44,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE, - (PCI_HB0RB1_PCI_BASE) //RbPciBar + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 }, /* Port 2 */ { @@ -55,7 +59,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, PCI_HB0RB2_CPUIOREGIONBASE, - (PCI_HB0RB2_PCI_BASE) //RbPciBar + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE , + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 },
/* Port 3 */ @@ -69,7 +75,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB0RB3_PCI_BASE) //RbPciBar + (PCI_HB0RB3_PCI_BASE), //RbPciBar + 0, + 0 } }, {// HostBridge 1 @@ -84,7 +92,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB0_PCI_BASE) //RbPciBar + (PCI_HB1RB0_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 1 */ { @@ -97,7 +107,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB1_PCI_BASE) //RbPciBar + (PCI_HB1RB1_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 2 */ { @@ -110,7 +122,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB2_PCI_BASE) //RbPciBar + (PCI_HB1RB2_PCI_BASE), //RbPciBar + 0, + 0 },
/* Port 3 */ @@ -124,7 +138,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB3_PCI_BASE) //RbPciBar + (PCI_HB1RB3_PCI_BASE), //RbPciBar + 0, + 0 } } }; diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index a08b461..c58118f 100644 --- a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -37,7 +37,10 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB0_PCI_BASE) //RbPciBar + (PCI_HB0RB0_PCI_BASE), //RbPciBar + PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit + }, /* Port 1 */ { @@ -50,7 +53,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB1_PCI_BASE) //RbPciBar + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit }, /* Port 2 */ { @@ -63,7 +68,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase - (PCI_HB0RB2_PCI_BASE) //RbPciBar + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit },
/* Port 3 */ @@ -77,7 +84,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB0RB3_PCI_BASE) //RbPciBar + (PCI_HB0RB3_PCI_BASE), //RbPciBar + 0, + 0 } }, {// HostBridge 1 @@ -92,7 +101,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB0_PCI_BASE) //RbPciBar + (PCI_HB1RB0_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 1 */ { @@ -105,7 +116,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB1_PCI_BASE) //RbPciBar + (PCI_HB1RB1_PCI_BASE), //RbPciBar + 0, + 0 }, /* Port 2 */ { @@ -118,7 +131,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB2_PCI_BASE) //RbPciBar + (PCI_HB1RB2_PCI_BASE), //RbPciBar + 0, + 0 },
/* Port 3 */ @@ -132,7 +147,9 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (0), //IoLimit 0, 0, - (PCI_HB1RB3_PCI_BASE) //RbPciBar + (PCI_HB1RB3_PCI_BASE), //RbPciBar + 0, + 0 } } };
There might be multiple PCIe associated ITS in the system, so we change PCD of MSI target address to a feature PCD and specify the addresses in the code. If ITS is not supported by OS, MSI target address will be set to GIC distributor.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 ++- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 12 +++++++++--- Chips/Hisilicon/HisiPkg.dec | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 4 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 8659e29..8b10dbc 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -51,9 +51,10 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P gHisiTokenSpaceGuid.Pcdsoctype - gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress + gArmTokenSpaceGuid.PcdGicDistributorBase
[FeaturePcd] + gHisiTokenSpaceGuid.PcdIsItsSupported gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
[depex] diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index e58d87c..445b997 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -906,9 +906,15 @@ VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 Value = 0; - - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress)); - RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0); + if (FeaturePcdGet (PcdIsItsSupported)) { + //PCIE_SYS_CTRL24_REG is MSI Low address register + //PCIE_SYS_CTRL28_REG is MSI High addres register + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32); + } else { + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PcdGet64 (PcdGicDistributorBase) + 0x40); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, (PcdGet64 (PcdGicDistributorBase) + 0x40) >> 32); + } RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); Value |= (1 << 12); RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index fca0b70..39dd75a 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -267,11 +267,11 @@ gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d
gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061 - gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064 gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056
[PcdsFeatureFlag] gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066 + gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 942b2b8..7c72c84 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -112,6 +112,7 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE + gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
[PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" @@ -309,7 +310,6 @@ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0xc6010040
################################################################################ #
On Thu, Nov 10, 2016 at 09:52:08PM +0800, Heyi Guo wrote:
There might be multiple PCIe associated ITS in the system, so we change PCD of MSI target address to a feature PCD and specify the addresses in the code. If ITS is not supported by OS, MSI target address will be set to GIC distributor.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 ++- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 12 +++++++++--- Chips/Hisilicon/HisiPkg.dec | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 4 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 8659e29..8b10dbc 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -51,9 +51,10 @@ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P gHisiTokenSpaceGuid.Pcdsoctype
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress
- gArmTokenSpaceGuid.PcdGicDistributorBase
[FeaturePcd]
- gHisiTokenSpaceGuid.PcdIsItsSupported gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
[depex] diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index e58d87c..445b997 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -906,9 +906,15 @@ VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 Value = 0;
- RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11b4, PcdGet64 (PcdPcieMsiTargetAddress));
- RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c4, 0);
- if (FeaturePcdGet (PcdIsItsSupported)) {
//PCIE_SYS_CTRL24_REG is MSI Low address register
//PCIE_SYS_CTRL28_REG is MSI High addres register
RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]);
RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32);
- } else {
RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PcdGet64 (PcdGicDistributorBase) + 0x40);
What's the 0x40?
RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, (PcdGet64 (PcdGicDistributorBase) + 0x40) >> 32);
Could you create a SysRegWrite(UINT32 Bridge, UINT32 Port, UINT32 Register, UINT32 Value) helper? So that the line above turns into SysRegWrite (HostBridgeNum, Port, PCIE_SYS_CTRL28_REG, (PcdGet64 (PcdGicDistributorBase) + 0x40) >> 32); ?
- } RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value); Value |= (1 << 12); RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index fca0b70..39dd75a 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -267,11 +267,11 @@ gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0|UINT64|0x2110005d gHisiTokenSpaceGuid.Pcdsoctype|0|UINT32|0x00000061
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0x0|UINT64|0x00000064 gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056
[PcdsFeatureFlag] gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066
- gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065
Insert sorted?
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 942b2b8..7c72c84 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -112,6 +112,7 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
Insert sorted?
[PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" @@ -309,7 +310,6 @@ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000
- gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0xc6010040
################################################################################
#
1.9.1
The PciePortReset function is unused, so we remove it.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 38 ---------------------- 1 file changed, 38 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 445b997..88810ce 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -573,44 +573,6 @@ VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) }
-EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - if(Port >= PCIE_MAX_PORT_NUM) - { - return EFI_INVALID_PARAMETER; - } - - - if(PcieIsLinkUp(soctype, HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port]) - { - (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port); - } - - mPcieIntCfg.PortIsInitilized[Port] = FALSE; - mPcieIntCfg.DmaResource[Port] = (VOID *)NULL; - mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0; - mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0; - ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U)); - - if(Port <= 2) - { - RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1); - MicroSecondDelay(0x1000); - } - else - { - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1); - MicroSecondDelay(0x1000); - - RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1); - MicroSecondDelay(0x1000); - } - return EFI_SUCCESS; -} - EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { UINT32 PortIndexInSicl;
There are 8 phys at each Pcie Controller, so it should be set for 8 times loop.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 8 +++++--- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 ++ 2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 88810ce..4519cd0 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -466,9 +466,11 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) UINT32 Value = 0; if (0x1610 == soctype) { - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); - Value |= (1 << 20); - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); + for (i = 0; i < PcieMaxLanNum; i++) { + RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + Value |= (1 << 20); //bit 20: rxvalid enable + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); } diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 1e8db97..9671c57 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -68,6 +68,8 @@ #define PCIE_BAR_TYPE_64 (2) #define PCIE_BAR_PREFETCH_MODE (1)
+#define PCS_SDS_CFG_REG 0x204 +#define SDS_CFG_STRIDE 0x4 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr))
On Thu, Nov 10, 2016 at 09:52:10PM +0800, Heyi Guo wrote:
There are 8 phys at each Pcie Controller, so it should be set for 8 times loop.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 8 +++++--- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 ++ 2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 88810ce..4519cd0 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -466,9 +466,11 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) UINT32 Value = 0; if (0x1610 == soctype) {
RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
Value |= (1 << 20);
RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
for (i = 0; i < PcieMaxLanNum; i++) {
RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
Value |= (1 << 20); //bit 20: rxvalid enable
RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
}} PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 1e8db97..9671c57 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -68,6 +68,8 @@ #define PCIE_BAR_TYPE_64 (2) #define PCIE_BAR_PREFETCH_MODE (1) +#define PCS_SDS_CFG_REG 0x204 +#define SDS_CFG_STRIDE 0x4 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr)) -- 1.9.1
Hi1616 has 10 I2C ports and the IP of I2C controller is DesignWare v2, which requires to write I2C_CMD_STOP bit (BIT9) for the last transfer.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Include/Library/I2CLib.h | 2 +- Chips/Hisilicon/Library/I2CLib/I2CHw.h | 1 + Chips/Hisilicon/Library/I2CLib/I2CLib.c | 50 +++++++++----------------------- 3 files changed, 15 insertions(+), 38 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/I2CLib.h b/Chips/Hisilicon/Include/Library/I2CLib.h index c3597f6..36e9f5f 100644 --- a/Chips/Hisilicon/Include/Library/I2CLib.h +++ b/Chips/Hisilicon/Include/Library/I2CLib.h @@ -33,7 +33,7 @@ typedef enum { }SPEED_MODE;
-#define I2C_PORT_MAX 9 +#define I2C_PORT_MAX 10
diff --git a/Chips/Hisilicon/Library/I2CLib/I2CHw.h b/Chips/Hisilicon/Library/I2CLib/I2CHw.h index 0937997..aa561e9 100644 --- a/Chips/Hisilicon/Library/I2CLib/I2CHw.h +++ b/Chips/Hisilicon/Library/I2CLib/I2CHw.h @@ -26,6 +26,7 @@ #define I2C_TXRX_THRESHOLD 0x7 #define I2C_SS_SCLHCNT 0x493 #define I2C_SS_SCLLCNT 0x4fe +#define I2C_CMD_STOP_BIT BIT9
#define I2C_REG_WRITE(reg,data) \ MmioWrite32 ((reg), (data)) diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLib.c b/Chips/Hisilicon/Library/I2CLib/I2CLib.c index 087a4ba..b5b388d 100644 --- a/Chips/Hisilicon/Library/I2CLib/I2CLib.c +++ b/Chips/Hisilicon/Library/I2CLib/I2CLib.c @@ -360,7 +360,12 @@ I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf) ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port); }
- I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++); + if (Idx < ulLength - 1) { + I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++)); + } else { + //Send command stop bit for the last transfer + I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++) | I2C_CMD_STOP_BIT); + } }
ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port); @@ -386,13 +391,10 @@ EFI_STATUS EFIAPI I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf) { - UINT32 ulCnt; - UINT16 usTotalLen = 0; UINT32 ulFifo; UINT32 ulTimes = 0; UINT8 I2CWAddr[2]; EFI_STATUS Status; - UINT32 BytesLeft; UINT32 Idx = 0; UINTN Base;
@@ -441,42 +443,14 @@ I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf) ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port); }
- usTotalLen = ulRxLen; - BytesLeft = usTotalLen; - - while(BytesLeft >= I2C_DRV_ONCE_READ_BYTES_NUM){ - - - for(ulCnt = 0; ulCnt < I2C_DRV_ONCE_READ_BYTES_NUM; ulCnt++) { + while (ulRxLen > 0) { + if (ulRxLen > 1) { I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL); + } else { + //Send command stop bit for the last transfer + I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT); }
- - for(ulCnt = 0; ulCnt < I2C_DRV_ONCE_READ_BYTES_NUM; ulCnt++) { - ulTimes = 0; - do { - I2C_Delay(2); - - while(++ulTimes > I2C_READ_TIMEOUT) { - (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port); - return EFI_TIMEOUT; - } - ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port); - - }while(0 == ulFifo); - - I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]); - } - BytesLeft -= I2C_DRV_ONCE_READ_BYTES_NUM; - } - - - for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) { - I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL); - } - - - for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) { ulTimes = 0; do { I2C_Delay(2); @@ -489,6 +463,8 @@ I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf) }while(0 == ulFifo);
I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]); + + ulRxLen --; } (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
Modify OemGetSerdesParam interface to support D05, for it has 2 sockets on the board, and each socket has 2 IO super clusters. The interface is modified to support getting serdes parameter for both IO super clusters (denoted as A and B) on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Type09/MiscSystemSlotDesignationFunction.c | 23 ++++++++++------------ Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- .../D02/Library/OemMiscLibD02/BoardFeatureD02.c | 9 ++++----- .../Library/OemMiscLib2P/BoardFeature2PHi1610.c | 7 +++---- 5 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index a0e3de3..62e4b7f 100644 --- a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -73,9 +73,10 @@ UpdateSlotUsage( ) { EFI_STATUS Status; - serdes_param_t sSerdesParam; + serdes_param_t SerdesParamA; + serdes_param_t SerdesParamB;
- Status = OemGetSerdesParam (&sSerdesParam); + Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0); if(EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status)); @@ -85,8 +86,8 @@ UpdateSlotUsage( // // PCIE0 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE) - { + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) + && SerdesParamA.hilink1_mode == EM_HILINK1_PCIE0_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; }
@@ -95,8 +96,7 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) - { + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; } } @@ -106,13 +106,10 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) - { + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; InputData->CurrentUsage = SlotUsageAvailable; - } - else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE) - { + } else if (SerdesParamA.hilink2_mode == EM_HILINK2_PCIE2_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; } } @@ -120,8 +117,8 @@ UpdateSlotUsage( // // PCIE3 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE) - { + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) + && SerdesParamA.hilink5_mode == EM_HILINK5_PCIE3_4LANE) { InputData->CurrentUsage = SlotUsageAvailable; } } diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 700d40e..3bd5a0f 100755 --- a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -82,7 +82,7 @@ typedef struct { UINT32 DsCfg; } SERDES_POLARITY_INVERT;
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h index 070934b..b6c7e20 100644 --- a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h @@ -76,7 +76,7 @@ typedef struct { } SERDES_POLARITY_INVERT;
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c index d4aa84a..7526644 100644 --- a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c +++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c @@ -59,15 +59,14 @@ serdes_param_t gSerdesParam = { .hilink5_mode = EM_HILINK5_SAS1_4LANE, };
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) - { - DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + if (ParamA == NULL) { + DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; }
- (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; }
diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 23c55e1..a54e76f 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -75,15 +75,14 @@ serdes_param_t gSerdesParam1 = { .use_ssc = 0, };
-EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) - { + if (ParamA == NULL) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; }
- (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; }
On Thu, Nov 10, 2016 at 09:52:12PM +0800, Heyi Guo wrote:
Modify OemGetSerdesParam interface to support D05, for it has 2 sockets on the board, and each socket has 2 IO super clusters. The interface is modified to support getting serdes parameter for both IO super clusters (denoted as A and B) on each socket.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
.../Type09/MiscSystemSlotDesignationFunction.c | 23 ++++++++++------------ Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- .../D02/Library/OemMiscLibD02/BoardFeatureD02.c | 9 ++++----- .../Library/OemMiscLib2P/BoardFeature2PHi1610.c | 7 +++---- 5 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index a0e3de3..62e4b7f 100644 --- a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -73,9 +73,10 @@ UpdateSlotUsage( ) { EFI_STATUS Status;
- serdes_param_t sSerdesParam;
- serdes_param_t SerdesParamA;
- serdes_param_t SerdesParamB;
- Status = OemGetSerdesParam (&sSerdesParam);
- Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0); if(EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status));
@@ -85,8 +86,8 @@ UpdateSlotUsage( // // PCIE0 //
- if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE)
- {
- if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data)
}&& SerdesParamA.hilink1_mode == EM_HILINK1_PCIE0_8LANE) { InputData->CurrentUsage = SlotUsageAvailable;
@@ -95,8 +96,7 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) {
if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE)
{
}if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; }
@@ -106,13 +106,10 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) {
if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE)
{
if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; InputData->CurrentUsage = SlotUsageAvailable;
}
else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE)
{
}} else if (SerdesParamA.hilink2_mode == EM_HILINK2_PCIE2_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; }
@@ -120,8 +117,8 @@ UpdateSlotUsage( // // PCIE3 //
- if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE)
- {
- if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data)
}&& SerdesParamA.hilink5_mode == EM_HILINK5_PCIE3_4LANE) { InputData->CurrentUsage = SlotUsageAvailable;
} diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 700d40e..3bd5a0f 100755 --- a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -82,7 +82,7 @@ typedef struct { UINT32 DsCfg; } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h index 070934b..b6c7e20 100644 --- a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h @@ -76,7 +76,7 @@ typedef struct { } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c index d4aa84a..7526644 100644 --- a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c +++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c @@ -59,15 +59,14 @@ serdes_param_t gSerdesParam = { .hilink5_mode = EM_HILINK5_SAS1_4LANE, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) {
- if (NULL == Param)
- {
- DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- if (ParamA == NULL) {
- DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; }
- (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param));
- (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS;
} diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 23c55e1..a54e76f 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -75,15 +75,14 @@ serdes_param_t gSerdesParam1 = { .use_ssc = 0, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) {
- if (NULL == Param)
- {
- if (ParamA == NULL) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; }
- (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param));
- (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS;
} -- 1.9.1
phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the typo.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index f424ae9..8968b21 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -228,7 +228,7 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig; - UINT32 phyDqsFailRiseDelay; + UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;
On Thu, Nov 10, 2016 at 09:52:13PM +0800, Heyi Guo wrote:
phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the typo.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index f424ae9..8968b21 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -228,7 +228,7 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig;
- UINT32 phyDqsFailRiseDelay;
- UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;
Like last time around, I am happy with the correction in itself. But on rp-16.12-12-d05, I still get:
OpenPlatformPkg$ grep -r phyDqsFailRiseDelay * Binary file Chips/Hisilicon/Binary/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.lib matches Binary file Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.lib matches Binary file Platforms/Hisilicon/Binary/D02/MemoryInitPei/MemoryInit.efi matches Binary file Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi matches
Can you rebuild these please?
Regards,
Leif
Order of timing parameters of structure DDR_CHANNEL are changed to be alphabetical, to make it easier to find certain parameter.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 8968b21..e6c0fd4 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -186,20 +186,20 @@ typedef struct _DDR_Channel{ UINT32 MemSize; UINT32 CLSupport; UINT32 minTck; + UINT32 nAA; UINT32 nCL; - UINT32 nWR; + UINT32 nCCDL; + UINT32 nFAW; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC; - UINT32 nWTR; UINT32 nRTP; - UINT32 nAA; - UINT32 nFAW; UINT32 nRP; - UINT32 nCCDL; + UINT32 nWR; + UINT32 nWTR; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en;
On Thu, Nov 10, 2016 at 09:52:14PM +0800, Heyi Guo wrote:
Order of timing parameters of structure DDR_CHANNEL are changed to be alphabetical, to make it easier to find certain parameter.
Thanks!
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Chips/Hisilicon/Include/Library/HwMemInitLib.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 8968b21..e6c0fd4 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -186,20 +186,20 @@ typedef struct _DDR_Channel{ UINT32 MemSize; UINT32 CLSupport; UINT32 minTck;
- UINT32 nAA; UINT32 nCL;
- UINT32 nWR;
- UINT32 nCCDL;
- UINT32 nFAW; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC;
- UINT32 nWTR; UINT32 nRTP;
- UINT32 nAA;
- UINT32 nFAW; UINT32 nRP;
- UINT32 nCCDL;
- UINT32 nWR;
- UINT32 nWTR; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en;
-- 1.9.1
Memory initialization module has a lot of changes to support D05, so the data structure definition has several changes accordingly: 1. Type of nRCD and nRP is changed to UINT32, to hold timing value in pico seconds rather than in clock cycles, to be more accurate. 2. More parameters are added to hold additional timing values, training result, additional mode registers and maximum DDR device frequency. 3. NUMA information is exposed to DXE ACPI driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 48 ++++++++++++++++++++++++-- Chips/Hisilicon/Include/PlatformArch.h | 2 ++ 2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index e6c0fd4..c24930f 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -123,8 +123,8 @@ typedef struct _DDR_DIMM{ UINT8 MtbDividend; UINT8 MtbDivsor; UINT8 nCL; - UINT8 nRCD; - UINT8 nRP; + UINT32 nRCD; + UINT32 nRP; UINT8 SPDftb; UINT8 SpdMinTCK; UINT8 SpdMinTCKFtb; @@ -173,8 +173,14 @@ typedef struct { UINT32 ddrcTiming5; UINT32 ddrcTiming6; UINT32 ddrcTiming7; + UINT32 ddrcTiming8; }DDRC_TIMING;
+typedef struct _MARGIN_RESULT{ + UINT32 OptimalDramVref[12]; + UINT32 optimalPhyVref[18]; +}MARGIN_RESULT; + typedef struct _DDR_Channel{ BOOLEAN Status; UINT8 CurrentDimmNum; @@ -184,22 +190,42 @@ typedef struct _DDR_Channel{ UINT8 DramWidth; UINT8 ModuleType; UINT32 MemSize; + UINT32 tck; + UINT32 ratio; UINT32 CLSupport; UINT32 minTck; + UINT32 taref; UINT32 nAA; + UINT32 nAOND; + UINT32 nCKE; UINT32 nCL; UINT32 nCCDL; + UINT32 nCKSRX; + UINT32 nCKSRE; + UINT32 nCCDNSW; + UINT32 nCCDNSR; UINT32 nFAW; + UINT32 nMRD; + UINT32 nMOD; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC; + UINT32 nRFCAB; UINT32 nRTP; + UINT32 nRTW; UINT32 nRP; + UINT32 nSRE; + UINT32 nWL; UINT32 nWR; UINT32 nWTR; + UINT32 nWTRL; + UINT32 nXARD; + UINT32 nZQPRD; + UINT32 nZQINIT; + UINT32 nZQCS; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en; @@ -232,11 +258,19 @@ typedef struct _DDR_Channel{ UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency; + UINT32 dimm_parity_en; DDRC_TIMING ddrcTiming; DDR_DIMM Dimm[MAX_DIMM]; + MARGIN_RESULT sMargin; }DDR_CHANNEL;
typedef struct _NVRAM_RANK{ + UINT16 MR0; + UINT16 MR1; + UINT16 MR2; + UINT16 MR3; + UINT16 MR4; + UINT16 MR5; UINT16 MR6[9]; }NVRAM_RANK;
@@ -306,6 +340,14 @@ typedef struct _MEMORY{ UINT32 Config2; }MEMORY;
+typedef struct _NUMAINFO{ + UINT8 NodeId; + UINT64 Base; + UINT64 Length; + UINT32 ScclInterleaveEn; +}NUMAINFO; + + typedef struct _GBL_DATA { DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL]; @@ -319,6 +361,7 @@ typedef struct _GBL_DATA UINT32 SpdTck; UINT32 Tck; UINT32 DdrFreqIdx; + UINT32 DevParaFreqIdx; //Maximum frequency of DDR device UINT32 MemSize; UINT32 EccEn;
@@ -365,6 +408,7 @@ typedef struct _GBL_DATA BOOLEAN chipIsEc; NVRAM nvram; MEMORY mem; + NUMAINFO NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
}GBL_DATA, *pGBL_DATA;
diff --git a/Chips/Hisilicon/Include/PlatformArch.h b/Chips/Hisilicon/Include/PlatformArch.h index f1ccbb6..45995c5 100644 --- a/Chips/Hisilicon/Include/PlatformArch.h +++ b/Chips/Hisilicon/Include/PlatformArch.h @@ -26,6 +26,8 @@ #define MAX_DIMM 3 #define MAX_RANK_CH 12 #define MAX_RANK_DIMM 4 +// Max NUMA node number for each node type +#define MAX_NUM_PER_TYPE 8
#define S1_BASE 0x40000000000
On Thu, Nov 10, 2016 at 09:52:15PM +0800, Heyi Guo wrote:
Memory initialization module has a lot of changes to support D05, so the data structure definition has several changes accordingly:
- Type of nRCD and nRP is changed to UINT32, to hold timing value in pico seconds rather than in clock cycles, to be more accurate.
- More parameters are added to hold additional timing values, training result, additional mode registers and maximum DDR device frequency.
- NUMA information is exposed to DXE ACPI driver.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Chips/Hisilicon/Include/Library/HwMemInitLib.h | 48 ++++++++++++++++++++++++-- Chips/Hisilicon/Include/PlatformArch.h | 2 ++ 2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index e6c0fd4..c24930f 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -123,8 +123,8 @@ typedef struct _DDR_DIMM{ UINT8 MtbDividend; UINT8 MtbDivsor; UINT8 nCL;
- UINT8 nRCD;
- UINT8 nRP;
- UINT32 nRCD;
- UINT32 nRP; UINT8 SPDftb; UINT8 SpdMinTCK; UINT8 SpdMinTCKFtb;
@@ -173,8 +173,14 @@ typedef struct { UINT32 ddrcTiming5; UINT32 ddrcTiming6; UINT32 ddrcTiming7;
- UINT32 ddrcTiming8;
}DDRC_TIMING; +typedef struct _MARGIN_RESULT{
- UINT32 OptimalDramVref[12];
- UINT32 optimalPhyVref[18];
+}MARGIN_RESULT;
typedef struct _DDR_Channel{ BOOLEAN Status; UINT8 CurrentDimmNum; @@ -184,22 +190,42 @@ typedef struct _DDR_Channel{ UINT8 DramWidth; UINT8 ModuleType; UINT32 MemSize;
- UINT32 tck;
- UINT32 ratio; UINT32 CLSupport; UINT32 minTck;
- UINT32 taref; UINT32 nAA;
- UINT32 nAOND;
- UINT32 nCKE; UINT32 nCL; UINT32 nCCDL;
- UINT32 nCKSRX;
- UINT32 nCKSRE;
- UINT32 nCCDNSW;
- UINT32 nCCDNSR; UINT32 nFAW;
- UINT32 nMRD;
- UINT32 nMOD; UINT32 nRCD; UINT32 nRRD; UINT32 nRRDL; UINT32 nRAS; UINT32 nRC; UINT32 nRFC;
- UINT32 nRFCAB; UINT32 nRTP;
- UINT32 nRTW; UINT32 nRP;
- UINT32 nSRE;
- UINT32 nWL; UINT32 nWR; UINT32 nWTR;
- UINT32 nWTRL;
- UINT32 nXARD;
- UINT32 nZQPRD;
- UINT32 nZQINIT;
- UINT32 nZQCS; UINT8 cwl; //tWL? UINT8 pl; //parity latency UINT8 wr_pre_2t_en;
@@ -232,11 +258,19 @@ typedef struct _DDR_Channel{ UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;
- UINT32 dimm_parity_en; DDRC_TIMING ddrcTiming; DDR_DIMM Dimm[MAX_DIMM];
- MARGIN_RESULT sMargin;
}DDR_CHANNEL; typedef struct _NVRAM_RANK{
- UINT16 MR0;
- UINT16 MR1;
- UINT16 MR2;
- UINT16 MR3;
- UINT16 MR4;
- UINT16 MR5; UINT16 MR6[9];
}NVRAM_RANK; @@ -306,6 +340,14 @@ typedef struct _MEMORY{ UINT32 Config2; }MEMORY; +typedef struct _NUMAINFO{
- UINT8 NodeId;
- UINT64 Base;
- UINT64 Length;
- UINT32 ScclInterleaveEn;
+}NUMAINFO;
typedef struct _GBL_DATA { DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL]; @@ -319,6 +361,7 @@ typedef struct _GBL_DATA UINT32 SpdTck; UINT32 Tck; UINT32 DdrFreqIdx;
- UINT32 DevParaFreqIdx; //Maximum frequency of DDR device UINT32 MemSize; UINT32 EccEn;
@@ -365,6 +408,7 @@ typedef struct _GBL_DATA BOOLEAN chipIsEc; NVRAM nvram; MEMORY mem;
- NUMAINFO NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
}GBL_DATA, *pGBL_DATA; diff --git a/Chips/Hisilicon/Include/PlatformArch.h b/Chips/Hisilicon/Include/PlatformArch.h index f1ccbb6..45995c5 100644 --- a/Chips/Hisilicon/Include/PlatformArch.h +++ b/Chips/Hisilicon/Include/PlatformArch.h @@ -26,6 +26,8 @@ #define MAX_DIMM 3 #define MAX_RANK_CH 12 #define MAX_RANK_DIMM 4 +// Max NUMA node number for each node type +#define MAX_NUM_PER_TYPE 8 #define S1_BASE 0x40000000000 -- 1.9.1
System initialization on D05 has some differences from that on D02 and D03, so we extract more platform system control interfaces to support D05 within the same architectural modules.
The actual function definitions are in PlatformSysCtrlLib which is a binary, and will be updated later.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h index f374112..ec2b9a3 100644 --- a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h @@ -90,8 +90,17 @@ VOID DResetUsb (); UINT32 PlatformGetEhciBase (); UINT32 PlatformGetOhciBase (); VOID PlatformPllInit(); +// PLL initialization for super IO clusters. +VOID SiclPllInit(UINT32 SclId); VOID PlatformDeviceDReset(); VOID PlatformGicdInit(); VOID PlatformLpcInit(); +// Synchronize architecture timer counter between different super computing +// clusters. +VOID PlatformArchTimerSynchronize(VOID); +VOID PlatformEventBroadcastConfig(VOID); +UINTN GetDjtagRegBase(UINT32 NodeId); +VOID LlcCleanInvalidateAsm(VOID); +VOID PlatformMdioInit(VOID);
#endif
On Thu, Nov 10, 2016 at 09:52:16PM +0800, Heyi Guo wrote:
System initialization on D05 has some differences from that on D02 and D03, so we extract more platform system control interfaces to support D05 within the same architectural modules.
The actual function definitions are in PlatformSysCtrlLib which is a binary, and will be updated later.
I want to see this submitted as as ingle patch together with the binary library version that uses it, and the .inf that describes it.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h index f374112..ec2b9a3 100644 --- a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h @@ -90,8 +90,17 @@ VOID DResetUsb (); UINT32 PlatformGetEhciBase (); UINT32 PlatformGetOhciBase (); VOID PlatformPllInit(); +// PLL initialization for super IO clusters. +VOID SiclPllInit(UINT32 SclId); VOID PlatformDeviceDReset(); VOID PlatformGicdInit(); VOID PlatformLpcInit(); +// Synchronize architecture timer counter between different super computing +// clusters. +VOID PlatformArchTimerSynchronize(VOID); +VOID PlatformEventBroadcastConfig(VOID); +UINTN GetDjtagRegBase(UINT32 NodeId); +VOID LlcCleanInvalidateAsm(VOID); +VOID PlatformMdioInit(VOID);
#endif
1.9.1
Update gicc and memory affinity structure version to ACPI 6.0 and add NUMA related structure.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 639b702..5a810ec 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -32,14 +32,14 @@ GicRBase, GicRlength \ }
-#define EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \ 3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ }
-#define EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ { \ 1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ @@ -47,6 +47,21 @@ EFI_ACPI_RESERVED_QWORD \ }
+#pragma pack(1) +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64 +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
+ +typedef struct { + EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]; + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT]; +} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; + +#pragma pack() #endif
On Thu, Nov 10, 2016 at 09:52:17PM +0800, Heyi Guo wrote:
Update gicc and memory affinity structure version to ACPI 6.0 and add NUMA related structure.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Include/Library/AcpiNextLib.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 639b702..5a810ec 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -32,14 +32,14 @@ GicRBase, GicRlength \ } -#define EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT( \
rp-16.12-12-d05 still contains source code using these macros under their old names, although it seems those files are not used. Can you send a new patch deleting those Chips/Hisilicon/Pv660/Pv660AcpiTables/Srat.aslc, and any other unused ACPI source files?
+#define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \ 3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ } -#define EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ { \ 1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ @@ -47,6 +47,21 @@ EFI_ACPI_RESERVED_QWORD \ } +#pragma pack(1) +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64 +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
+typedef struct {
- EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+#pragma pack() #endif -- 1.9.1
On Thu, Nov 10, 2016 at 09:52:17PM +0800, Heyi Guo wrote:
Update gicc and memory affinity structure version to ACPI 6.0 and add NUMA related structure.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Include/Library/AcpiNextLib.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 639b702..5a810ec 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -32,14 +32,14 @@ GicRBase, GicRlength \ } -#define EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \ 3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ } -#define EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ { \ 1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ @@ -47,6 +47,21 @@ EFI_ACPI_RESERVED_QWORD \ }
The general scheme in edk2 codebase for these type of _INIT macros seems to be to keep the version at the ACPI spec level the subtable was introduced in. There seems to be no functional different in 6.0 so they would stay at 5.X levels.
But as this is a private header this should not block upstreaming I think.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
+#pragma pack(1) +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64 +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
+typedef struct {
- EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+#pragma pack() #endif -- 1.9.1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 58 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 651 +++++++++++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 127 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 64 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 129 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 280 +++++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 36 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 1236 ++++++++++++++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 58 + .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 438 +++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 584 +++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 247 ++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl | 135 +++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 31 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 91 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 95 ++ .../Hi1616/D05AcpiTables/Hi1616Platform.h | 48 + .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 282 +++++ 20 files changed, 4682 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf new file mode 100644 index 0000000..68379c5 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf @@ -0,0 +1,58 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Hi1616AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt/DsdtHi1616.asl + Facs.aslc + Fadt.aslc + Gtdt.aslc + MadtHi1616.aslc + D05Mcfg.aslc + D05Iort.asl + D05Slit.aslc + D05Srat.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl new file mode 100644 index 0000000..61a3c33 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -0,0 +1,651 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20151124-64 + * Copyright (c) 2000 - 2015 Intel Corporation + * + * Template for [IORT] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 000002e4 +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP07 " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124 + +[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00 + +/* ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 +//4c +/* ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000001 +//64 +/* ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000002 +//7c +/* ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000003 +//94 +/*Sec CPU ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000004 +//ac +/* SEC CPU ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000005 +//c4 +/* SEC CPU ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000006 +//dc +/* SEC CPU ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000007 + + + +/* mbi-gen peri b, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI0" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 000120c7 //device id +[0004] Output Reference : 0000004C +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI1" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI9" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen dsa a - usb named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI5" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI2" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI3" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI4" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 alg a, i2c 0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI6" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B0E //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 alg a, i2c 2 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI7" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B10 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/*1P NA PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002 + +[0004] Input base : 00008000 +[0004] ID Count : 00000800 +[0004] Output Base : 00008000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 1P NB PCIe0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000004 + +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 1P NB PCIe1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000005 + +[0004] Input base : 00000000 +[0004] ID Count : 00000800 +[0004] Output Base : 00000000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 1P NB PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000006 + +[0004] Input base : 0000c000 +[0004] ID Count : 00000800 +[0004] Output Base : 0000c000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 1P NB PCIe3 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000007 + +[0004] Input base : 00009000 +[0004] ID Count : 00000800 +[0004] Output Base : 00009000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 2P NA PCIe2*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000a + +[0004] Input base : 00001000 +[0004] ID Count : 00001000 +[0004] Output Base : 00001000 +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 2P NB PCIe0*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000c + +[0004] Input base : 00002000 +[0004] ID Count : 00001000 +[0004] Output Base : 00002000 +[0004] Output Reference : 000000dc +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + + /* 2P NB PCIe1*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000d + +[0004] Input base : 00003000 +[0004] ID Count : 00001000 +[0004] Output Base : 00003000 +[0004] Output Reference : 000000dc +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* mbi-gen1 P1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI8" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00044800 //device id +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc new file mode 100644 index 0000000..9255037 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2016 Hisilicon Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + */ + +#include <IndustryStandard/Acpi.h> +#include "Hi1616Platform.h" + +#define ACPI_5_0_MCFG_VERSION 0x1 + +#pragma pack(1) +typedef struct +{ + UINT64 ullBaseAddress; + UINT16 usSegGroupNum; + UINT8 ucStartBusNum; + UINT8 ucEndBusNum; + UINT32 Reserved2; +}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; + +typedef struct +{ + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved1; +}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; + +typedef struct +{ + EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[8]; +}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack() + +EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{ + { + { + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_5_0_MCFG_VERSION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION + }, + 0x0000000000000000, //Reserved + }, + { + //1p NA PCIe2 + { + 0xa0000000, //Base Address + 0x2, //Segment Group Number + 0x80, //Start Bus Number + 0x87, //End Bus Number + 0x00000000, //Reserved + }, + //1p NB PCIe0 + { + 0x8a0000000, //Base Address + 0x4, //Segment Group Number + 0x88, //Start Bus Number + 0x8f, //End Bus Number + 0x00000000, //Reserved + }, + //1p NB PCIe1 + { + 0x8b0000000, //Base Address + 0x5, //Segment Group Number + 0x0, //Start Bus Number + 0x7, //End Bus Number + 0x00000000, //Reserved + }, + //1p NB PCIe2 + { + 0x8a0000000, //Base Address + 0x6, //Segment Group Number + 0xc0, //Start Bus Number + 0xc7, //End Bus Number + 0x00000000, //Reserved + }, + //1p NB PCIe3 + { + 0x8b0000000, //Base Address + 0x7, //Segment Group Number + 0x90, //Start Bus Number + 0x97, //End Bus Number + 0x00000000, //Reserved + }, + //2P NA PCIe2 + { + 0x64000000000, //Base Address + 0xa, //Segment Group Number + 0x10, //Start Bus Number + 0x1f, //End Bus Number + 0x00000000, //Reserved + }, + //2P NB PCIe0 + { + 0x74000000000, //Base Address + 0xc, //Segment Group Number + 0x20, //Start Bus Number + 0x2f, //End Bus Number + 0x00000000, //Reserved + }, + //2P NB PCIe1 + { + 0x78000000000, //Base Address + 0xd, //Segment Group Number + 0x30, //Start Bus Number + 0x3f, //End Bus Number + 0x00000000, //Reserved + }, + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc new file mode 100644 index 0000000..2276240 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org +*/ + +#include <IndustryStandard/Acpi.h> +#include "Hi1616Platform.h" + +#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004 + +#pragma pack(1) +typedef struct { + UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; +} EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; + +typedef struct { + EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; + EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; + +} EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +#pragma pack() + +// +// System Locality Information Table +// Please modify all values in Slit.h only. +// +EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { + { + { + EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE), + EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION, + }, + // + // Beginning of SLIT specific fields + // + EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT, + }, + { + {{0x0A, 0x10, 0x20, 0x21}}, //Locality 0 + {{0x10, 0x0A, 0x19, 0x20}}, //Locality 1 + {{0x20, 0x19, 0x0A, 0x10}}, //Locality 2 + {{0x21, 0x20, 0x10, 0x0A}}, //Locality 3 + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Slit; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc new file mode 100644 index 0000000..f7ea15e --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2013 Linaro Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * + * Contributors: + * Yi Li - yi.li@linaro.org + * + * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +*/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> +#include "Hi1616Platform.h" + + +// +// Static Resource Affinity Table definition +// +EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = { + { + {EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE), + EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + {EFI_ACPI_ARM_OEM_ID}, + EFI_ACPI_ARM_OEM_TABLE_ID, + EFI_ACPI_ARM_OEM_REVISION, + EFI_ACPI_ARM_CREATOR_ID, + EFI_ACPI_ARM_CREATOR_REVISION}, + /*Reserved*/ + 0x00000001, // Reserved to be 1 for backward compatibility + EFI_ACPI_RESERVED_QWORD + }, + + // + // + // Memory Affinity + // + { + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + }, + + { + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62 + EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63 + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Srat; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..5ecbf50 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,280 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + // + // A57x16 Processor declaration + // + Device(CPU0) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + Device(CPU1) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + Device(CPU2) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + Device(CPU3) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + Device(CPU4) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + Device(CPU5) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + Device(CPU6) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + Device(CPU7) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } + Device(CPU8) { + Name(_HID, "ACPI0007") + Name(_UID, 8) + } + Device(CPU9) { + Name(_HID, "ACPI0007") + Name(_UID, 9) + } + Device(CP10) { + Name(_HID, "ACPI0007") + Name(_UID, 10) + } + Device(CP11) { + Name(_HID, "ACPI0007") + Name(_UID, 11) + } + Device(CP12) { + Name(_HID, "ACPI0007") + Name(_UID, 12) + } + Device(CP13) { + Name(_HID, "ACPI0007") + Name(_UID, 13) + } + Device(CP14) { + Name(_HID, "ACPI0007") + Name(_UID, 14) + } + Device(CP15) { + Name(_HID, "ACPI0007") + Name(_UID, 15) + } + Device(CP16) { + Name(_HID, "ACPI0007") + Name(_UID, 16) + } + Device(CP17) { + Name(_HID, "ACPI0007") + Name(_UID, 17) + } + Device(CP18) { + Name(_HID, "ACPI0007") + Name(_UID, 18) + } + Device(CP19) { + Name(_HID, "ACPI0007") + Name(_UID, 19) + } + Device(CP20) { + Name(_HID, "ACPI0007") + Name(_UID, 20) + } + Device(CP21) { + Name(_HID, "ACPI0007") + Name(_UID, 21) + } + Device(CP22) { + Name(_HID, "ACPI0007") + Name(_UID, 22) + } + Device(CP23) { + Name(_HID, "ACPI0007") + Name(_UID, 23) + } + Device(CP24) { + Name(_HID, "ACPI0007") + Name(_UID, 24) + } + Device(CP25) { + Name(_HID, "ACPI0007") + Name(_UID, 25) + } + Device(CP26) { + Name(_HID, "ACPI0007") + Name(_UID, 26) + } + Device(CP27) { + Name(_HID, "ACPI0007") + Name(_UID, 27) + } + Device(CP28) { + Name(_HID, "ACPI0007") + Name(_UID, 28) + } + Device(CP29) { + Name(_HID, "ACPI0007") + Name(_UID, 29) + } + Device(CP30) { + Name(_HID, "ACPI0007") + Name(_UID, 30) + } + Device(CP31) { + Name(_HID, "ACPI0007") + Name(_UID, 31) + } + Device(CP32) { + Name(_HID, "ACPI0007") + Name(_UID, 32) + } + Device(CP33) { + Name(_HID, "ACPI0007") + Name(_UID, 33) + } + Device(CP34) { + Name(_HID, "ACPI0007") + Name(_UID, 34) + } + Device(CP35) { + Name(_HID, "ACPI0007") + Name(_UID, 35) + } + Device(CP36) { + Name(_HID, "ACPI0007") + Name(_UID, 36) + } + Device(CP37) { + Name(_HID, "ACPI0007") + Name(_UID, 37) + } + Device(CP38) { + Name(_HID, "ACPI0007") + Name(_UID, 38) + } + Device(CP39) { + Name(_HID, "ACPI0007") + Name(_UID, 39) + } + Device(CP40) { + Name(_HID, "ACPI0007") + Name(_UID, 40) + } + Device(CP41) { + Name(_HID, "ACPI0007") + Name(_UID, 41) + } + Device(CP42) { + Name(_HID, "ACPI0007") + Name(_UID, 42) + } + Device(CP43) { + Name(_HID, "ACPI0007") + Name(_UID, 43) + } + Device(CP44) { + Name(_HID, "ACPI0007") + Name(_UID, 44) + } + Device(CP45) { + Name(_HID, "ACPI0007") + Name(_UID, 45) + } + Device(CP46) { + Name(_HID, "ACPI0007") + Name(_UID, 46) + } + Device(CP47) { + Name(_HID, "ACPI0007") + Name(_UID, 47) + } + Device(CP48) { + Name(_HID, "ACPI0007") + Name(_UID, 48) + } + Device(CP49) { + Name(_HID, "ACPI0007") + Name(_UID, 49) + } + Device(CP50) { + Name(_HID, "ACPI0007") + Name(_UID, 50) + } + Device(CP51) { + Name(_HID, "ACPI0007") + Name(_UID, 51) + } + Device(CP52) { + Name(_HID, "ACPI0007") + Name(_UID, 52) + } + Device(CP53) { + Name(_HID, "ACPI0007") + Name(_UID, 53) + } + Device(CP54) { + Name(_HID, "ACPI0007") + Name(_UID, 54) + } + Device(CP55) { + Name(_HID, "ACPI0007") + Name(_UID, 55) + } + Device(CP56) { + Name(_HID, "ACPI0007") + Name(_UID, 56) + } + Device(CP57) { + Name(_HID, "ACPI0007") + Name(_UID, 57) + } + Device(CP58) { + Name(_HID, "ACPI0007") + Name(_UID, 58) + } + Device(CP59) { + Name(_HID, "ACPI0007") + Name(_UID, 59) + } + Device(CP60) { + Name(_HID, "ACPI0007") + Name(_UID, 60) + } + Device(CP61) { + Name(_HID, "ACPI0007") + Name(_UID, 61) + } + Device(CP62) { + Name(_HID, "ACPI0007") + Name(_UID, 62) + } + Device(CP63) { + Name(_HID, "ACPI0007") + Name(_UID, 63) + } +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000..b7c4905 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl @@ -0,0 +1,36 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "PL011") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x602B0000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI0") { 807 } + }) + Name(_DSD, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package() {"interrupt-parent",Package() {_SB.MBI0}}, + } + }) + } +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl new file mode 100644 index 0000000..e855e5d --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -0,0 +1,1236 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2016, Hisilicon Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + Device (MDIO) + { + OperationRegion(CLKR, SystemMemory, 0x60000550, 8) + Field(CLKR, DWordAcc, NoLock, Preserve) { + CLKE, 1, // clock enable + , 31, + CLKD, 1, // clode disable + , 31, + } + OperationRegion(RSTR, SystemMemory, 0x60000c40, 8) + Field(RSTR, DWordAcc, NoLock, Preserve) { + RSTE, 1, // reset + , 31, + RSTD, 1, // de-reset + , 31, + } + + Name(_HID, "HISI0141") + Name(_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000) + }) + + Method(_RST, 0, Serialized) { + Store (0x1, RSTE) + Sleep (10) + Store (0x1, CLKD) + Sleep (10) + Store (0x1, RSTD) + Sleep (10) + Store (0x1, CLKE) + Sleep (10) + } + } + + Device (DSF0) + { + OperationRegion(H3SR, SystemMemory, 0xC0000184, 4) + Field(H3SR, DWordAcc, NoLock, Preserve) { + H3ST, 1, + , 31, //RESERVED + } + OperationRegion(H4SR, SystemMemory, 0xC0000194, 4) + Field(H4SR, DWordAcc, NoLock, Preserve) { + H4ST, 1, + , 31, //RESERVED + } + // DSAF RESET + OperationRegion(DRER, SystemMemory, 0xC0000A00, 8) + Field(DRER, DWordAcc, NoLock, Preserve) { + DRTE, 1, + , 31, //RESERVED + DRTD, 1, + , 31, //RESERVED + } + // NT RESET + OperationRegion(NRER, SystemMemory, 0xC0000A08, 8) + Field(NRER, DWordAcc, NoLock, Preserve) { + NRTE, 1, + , 31, //RESERVED + NRTD, 1, + , 31, //RESERVED + } + // XGE RESET + OperationRegion(XRER, SystemMemory, 0xC0000A10, 8) + Field(XRER, DWordAcc, NoLock, Preserve) { + XRTE, 31, + , 1, //RESERVED + XRTD, 31, + , 1, //RESERVED + } + + // GE RESET + OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16) + Field(GRTR, DWordAcc, NoLock, Preserve) { + GR0E, 30, + , 2, //RESERVED + GR0D, 30, + , 2, //RESERVED + GR1E, 18, + , 14, //RESERVED + GR1D, 18, + , 14, //RESERVED + } + // PPE RESET + OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8) + Field(PRTR, DWordAcc, NoLock, Preserve) { + PRTE, 10, + , 22, //RESERVED + PRTD, 10, + , 22, //RESERVED + } + + // RCB PPE COM RESET + OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8) + Field(RRTR, DWordAcc, NoLock, Preserve) { + RRTE, 1, + , 31, //RESERVED + RRTD, 1, + , 31, //RESERVED + } + + // DSAF Channel RESET + OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8) + Field(DCRR, DWordAcc, NoLock, Preserve) { + DCRE, 1, + , 31, //RESERVED + DCRD, 1, + , 31, //RESERVED + } + + // RoCE RESET + OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8) + Field(RKRR, DWordAcc, NoLock, Preserve) { + RKRE, 1, + , 31, //RESERVED + RKRD, 1, + , 31, //RESERVED + } + + // RoCE Clock enable/disable + OperationRegion(RKCR, SystemMemory, 0xC0000328, 8) + Field(RKCR, DWordAcc, NoLock, Preserve) { + RCLE, 1, + , 31, //RESERVED + RCLD, 1, + , 31, //RESERVED + } + + // Hilink access sel cfg reg + OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4) + Field(HSER, DWordAcc, NoLock, Preserve) { + HSEL, 2, // hilink_access_sel & hilink_access_wr_pul + , 30, // RESERVED + } + + // Serdes + OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000) + Field(H4LR, DWordAcc, NoLock, Preserve) { + H4L0, 16, // port0 + , 16, //RESERVED + Offset (0x400), + H4L1, 16, // port1 + , 16, //RESERVED + Offset (0x800), + H4L2, 16, // port2 + , 16, //RESERVED + Offset (0xc00), + H4L3, 16, // port3 + , 16, //RESERVED + } + OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800) + Field(H3LR, DWordAcc, NoLock, Preserve) { + H3L2, 16, // port4 + , 16, //RESERVED + Offset (0x400), + H3L3, 16, // port5 + , 16, //RESERVED + } + Name (_HID, "HISI00B2") + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000) + Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"mode", "6port-16rss"}, + Package () {"buf-size", 4096}, + Package () {"desc-num", 1024}, + Package () {"interrupt-parent", Package() {_SB.MBI1}}, + } + }) + + //reset XGE port + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XRST, 2, Serialized) { + ShiftLeft (0x2082082, Arg0, Local0) + Or (Local0, 0x1, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset XGE core + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XCRT, 2, Serialized) { + ShiftLeft (0x2080, Arg0, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset GE port + //Arg0 : GE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(GRST, 2, Serialized) { + If (LLessEqual (Arg0, 5)) { + //Service port + ShiftLeft (0x2082082, Arg0, Local0) + ShiftLeft (0x1, Arg0, Local1) + + If (LEqual (Arg1, 0)) { + Store(Local1, GR1E) + Store(Local0, GR0E) + } Else { + Store(Local0, GR0D) + Store(Local1, GR1D) + } + } + } + + //reset PPE port + //Arg0 : PPE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(PRST, 2, Serialized) { + ShiftLeft (0x1, Arg0, Local0) + If (LEqual (Arg1, 0)) { + Store(Local0, PRTE) + } Else { + Store(Local0, PRTD) + } + } + + //reset DSAF channels + //Arg0 : mask + //Arg1 : 0 reset, 1 de-reset + Method(DCRT, 2, Serialized) { + If (LEqual (Arg1, 0)) { + Store(Arg0, DCRE) + } Else { + Store(Arg0, DCRD) + } + } + + //reset RoCE + //Arg0 : 0 reset, 1 de-reset + Method(RRST, 1, Serialized) { + If (LEqual (Arg0, 0)) { + Store(0x1, RKRE) + } Else { + Store(0x1, RCLD) + Store(0x1, RKRD) + sleep(20) + Store(0x1, RCLE) + } + } + + // Set Serdes Loopback + //Arg0 : port + //Arg1 : 0 disable, 1 enable + Method(SRLP, 2, Serialized) { + ShiftLeft (Arg1, 10, Local0) + Switch (ToInteger(Arg0)) + { + case (0x0){ + Store (0, HSEL) + Store (H4L0, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L0) + } + case (0x1){ + Store (0, HSEL) + Store (H4L1, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L1) + } + case (0x2){ + Store (0, HSEL) + Store (H4L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L2) + } + case (0x3){ + Store (0, HSEL) + Store (H4L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L3) + } + case (0x4){ + Store (3, HSEL) + Store (H3L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L2) + } + case (0x5){ + Store (3, HSEL) + Store (H3L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L3) + } + } + } + + //Reset + //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:ge; 6:dchan; 7:RoCE) + //Arg1 : port + //Arg2 : 0 disable, 1 enable + Method(DRST, 3, Serialized) + { + Switch (ToInteger(Arg0)) + { + //DSAF reset + case (0x1) + { + Store (Arg2, Local0) + If (LEqual (Local0, 0)) + { + Store (0x1, DRTE) + Store (0x1, NRTE) + Sleep (10) + Store (0x1, RRTE) + } + Else + { + Store (0x1, DRTD) + Store (0x1, NRTD) + Sleep (10) + Store (0x1, RRTD) + } + } + //Reset PPE port + case (0x2) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + PRST (Local0, Local1) + } + + //Reset XGE core + case (0x3) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XCRT (Local0, Local1) + } + //Reset XGE port + case (0x4) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XRST (Local0, Local1) + } + + //Reset GE port + case (0x5) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + GRST (Local0, Local1) + } + + //Reset DSAF Channels + case (0x6) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + DCRT (Local0, Local1) + } + + //Reset RoCE + case (0x7) + { + // Discarding Arg1 as it is always 0 + Store (Arg2, Local0) + RRST (Local0) + } + } + } + + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // 0 : Return Supported Functions bit mask + // 1 : Reset Sequence + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge; 6:dchan; 7:RoCE) + // Arg3[1] : port index in dsaf + // Arg3[2] : 0 reset, 1 cancle reset + // 2 : Set Serdes Loopback + // Arg3[0] : port + // Arg3[1] : 0 disable, 1 enable + // 3 : LED op set + // Arg3[0] : op type + // Arg3[1] : port + // Arg3[2] : para + // 4 : Get port type (GE or XGE) + // Arg3[0] : port index in dsaf + // Return : 0 GE, 1 XGE + // 5 : Get sfp status + // Arg3[0] : port index in dsaf + // Return : 0 no sfp, 1 have sfp + // Arg3: Package Parameters + Method (_DSM, 4, Serialized) + { + If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) + { + If (LEqual (Arg1, 0x00)) + { + Switch (ToInteger(Arg2)) + { + case (0x0) + { + Return (Buffer () {0x3F}) + } + + //Reset Sequence + case (0x1) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + Store (DeRefOf (Index (Arg3, 2)), Local2) + DRST (Local0, Local1, Local2) + } + + //Set Serdes Loopback + case (0x2) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + SRLP (Local0, Local1) + } + + //LED op set + case (0x3) + { + + } + + // Get port type (GE or XGE) + case (0x4) + { + Store (0, Local1) + Store (DeRefOf (Index (Arg3, 0)), Local0) + If (LLessEqual (Local0, 3)) + { + // mac0: Hilink4 Lane0 + // mac1: Hilink4 Lane1 + // mac2: Hilink4 Lane2 + // mac3: Hilink4 Lane3 + Store (H4ST, Local1) + } + ElseIf (LLessEqual (Local0, 5)) + { + // mac4: Hilink3 Lane2 + // mac5: Hilink3 Lane3 + Store (H3ST, Local1) + } + + Return (Local1) + } + + //Get sfp status + case (0x5) + { + + } + } + } + } + Return (Buffer() {0x00}) + } + Device (PRT0) + { + Name (_ADR, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 0}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT1) + { + Name (_ADR, 0x1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 1}, + Package () {"media-type", "fiber"}, + } + }) + } + + Device (PRT2) + { + Name (_ADR, 0x2) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 2}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT3) + { + Name (_ADR, 0x3) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 3}, + Package () {"media-type", "fiber"}, + } + }) + } + + Device (PRT4) + { + Name (_ADR, 0x4) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 4}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 0}, + Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + Device (PRT5) + { + Name (_ADR, 0x5) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 5}, + Package () {"phy-mode", "sgmii"}, + Package () {"phy-addr", 1}, + Package () {"mdio-node", Package (){_SB.MDIO}}, + Package () {"media-type", "copper"}, + } + }) + } + } + Device (ETH4) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 4}, + } + }) + } + Device (ETH5) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 5}, + } + }) + } + Device (ETH0) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 0}, + } + }) + } + Device (ETH1) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 1}, + } + }) + } + + Device (ETH2) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 2}, + } + }) + } + Device (ETH3) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF0}}, + Package () {"port-idx-in-ae", 3}, + } + }) + } + + Device (ROCE) { + Name(_HID, "HISI00D1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"eth-handle", Package () {_SB.ETH0, _SB.ETH1, 0, 0, _SB.ETH4, _SB.ETH5}}, + Package () {"dsaf-handle", Package (){_SB.DSF0}}, + Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes + Package () {"interrupt-parent", Package() {_SB.MBI9}}, + Package () {"interrupt-names", Package() {"hns-roce-comp-0", + "hns-roce-comp-1", + "hns-roce-comp-2", + "hns-roce-comp-3", + "hns-roce-comp-4", + "hns-roce-comp-5", + "hns-roce-comp-6", + "hns-roce-comp-7", + "hns-roce-comp-8", + "hns-roce-comp-9", + "hns-roce-comp-10", + "hns-roce-comp-11", + "hns-roce-comp-12", + "hns-roce-comp-13", + "hns-roce-comp-14", + "hns-roce-comp-15", + "hns-roce-comp-16", + "hns-roce-comp-17", + "hns-roce-comp-18", + "hns-roce-comp-19", + "hns-roce-comp-20", + "hns-roce-comp-21", + "hns-roce-comp-22", + "hns-roce-comp-23", + "hns-roce-comp-24", + "hns-roce-comp-25", + "hns-roce-comp-26", + "hns-roce-comp-27", + "hns-roce-comp-28", + "hns-roce-comp-29", + "hns-roce-comp-30", + "hns-roce-comp-31", + "hns-roce-async", + "hns-roce-common"}}, + } + }) + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI9") + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + } + + /* for p1 */ + Device (DSF1) + { + + OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4) + Field(H3SR, DWordAcc, NoLock, Preserve) { + H3ST, 1, + , 31, //RESERVED + } + OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4) + Field(H4SR, DWordAcc, NoLock, Preserve) { + H4ST, 1, + , 31, //RESERVED + } + // DSAF RESET + OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8) + Field(DRER, DWordAcc, NoLock, Preserve) { + DRTE, 1, + , 31, //RESERVED + DRTD, 1, + , 31, //RESERVED + } + // NT RESET + OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8) + Field(NRER, DWordAcc, NoLock, Preserve) { + NRTE, 1, + , 31, //RESERVED + NRTD, 1, + , 31, //RESERVED + } + // XGE RESET + OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8) + Field(XRER, DWordAcc, NoLock, Preserve) { + XRTE, 31, + , 1, //RESERVED + XRTD, 31, + , 1, //RESERVED + } + + // GE RESET + OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16) + Field(GRTR, DWordAcc, NoLock, Preserve) { + GR0E, 30, + , 2, //RESERVED + GR0D, 30, + , 2, //RESERVED + GR1E, 18, + , 14, //RESERVED + GR1D, 18, + , 14, //RESERVED + } + // PPE RESET + OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8) + Field(PRTR, DWordAcc, NoLock, Preserve) { + PRTE, 10, + , 22, //RESERVED + PRTD, 10, + , 22, //RESERVED + } + + // RCB PPE COM RESET + OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8) + Field(RRTR, DWordAcc, NoLock, Preserve) { + RRTE, 1, + , 31, //RESERVED + RRTD, 1, + , 31, //RESERVED + } + + // RCB_2X COM RESET + OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8) + Field(RBTR, DWordAcc, NoLock, Preserve) { + RBTE, 1, + , 31, //RESERVED + RBTD, 1, + , 31, //RESERVED + } + + // Hilink access sel cfg reg + OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4) + Field(HSER, DWordAcc, NoLock, Preserve) { + HSEL, 2, // hilink_access_sel & hilink_access_wr_pul + , 30, // RESERVED + } + + // Serdes + OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000) + Field(H4LR, DWordAcc, NoLock, Preserve) { + H4L0, 16, // port0 + , 16, //RESERVED + Offset (0x400), + H4L1, 16, // port1 + , 16, //RESERVED + Offset (0x800), + H4L2, 16, // port2 + , 16, //RESERVED + Offset (0xc00), + H4L3, 16, // port3 + , 16, //RESERVED + } + OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800) + Field(H3LR, DWordAcc, NoLock, Preserve) { + H3L2, 16, // port4 + , 16, //RESERVED + Offset (0x400), + H3L3, 16, // port5 + , 16, //RESERVED + } + + Name (_HID, "HISI00B2") + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x400c5000000, // Min Base Address + 0x400c588ffff, // Max Base Address + 0x0, // Translate + 0x890000 // Length + ) + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x400c7000000, // Min Base Address + 0x400c705ffff, // Max Base Address + 0x0, // Translate + 0x60000 // Length + ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI8") + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI8") + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI8") + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"mode", "6port-16rss"}, + Package () {"buf-size", 4096}, + Package () {"desc-num", 1024}, + Package () {"interrupt-parent", Package() {_SB.MBI8}}, + } + }) + + //reset XGE port + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XRST, 2, Serialized) { + ShiftLeft (0x2082082, Arg0, Local0) + Or (Local0, 0x1, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset XGE core + //Arg0 : XGE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(XCRT, 2, Serialized) { + ShiftLeft (0x2080, Arg0, Local0) + + If (LEqual (Arg1, 0)) { + Store(Local0, XRTE) + } Else { + Store(Local0, XRTD) + } + } + + //reset GE port + //Arg0 : GE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(GRST, 2, Serialized) { + If (LLessEqual (Arg0, 5)) { + //Service port + ShiftLeft (0x2082082, Arg0, Local0) + ShiftLeft (0x1, Arg0, Local1) + + If (LEqual (Arg1, 0)) { + Store(Local1, GR1E) + Store(Local0, GR0E) + } Else { + Store(Local0, GR0D) + Store(Local1, GR1D) + } + } + } + + //reset PPE port + //Arg0 : PPE port index in dsaf + //Arg1 : 0 reset, 1 cancle reset + Method(PRST, 2, Serialized) { + ShiftLeft (0x1, Arg0, Local0) + If (LEqual (Arg1, 0)) { + Store(Local0, PRTE) + } Else { + Store(Local0, PRTD) + } + } + + // Set Serdes Loopback + //Arg0 : port + //Arg1 : 0 disable, 1 enable + Method(SRLP, 2, Serialized) { + ShiftLeft (Arg1, 10, Local0) + Switch (ToInteger(Arg0)) + { + case (0x0){ + Store (0, HSEL) + Store (H4L0, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L0) + } + case (0x1){ + Store (0, HSEL) + Store (H4L1, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L1) + } + case (0x2){ + Store (0, HSEL) + Store (H4L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L2) + } + case (0x3){ + Store (0, HSEL) + Store (H4L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H4L3) + } + case (0x4){ + Store (3, HSEL) + Store (H3L2, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L2) + } + case (0x5){ + Store (3, HSEL) + Store (H3L3, Local1) + And (Local1, 0xfffffbff, Local1) + Or (Local0, Local1, Local0) + Store (Local0, H3L3) + } + } + } + + //Reset + //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) + //Arg1 : port + //Arg2 : 0 disable, 1 enable + Method(DRST, 3, Serialized) + { + Switch (ToInteger(Arg0)) + { + //DSAF reset + case (0x1) + { + Store (Arg2, Local0) + If (LEqual (Local0, 0)) + { + Store (0x1, DRTE) + Store (0x1, NRTE) + Sleep (10) + Store (0x1, RRTE) + Store (0x1, RBTE) + } + Else + { + Store (0x1, DRTD) + Store (0x1, NRTD) + Sleep (10) + Store (0x1, RRTD) + Store (0x1, RBTD) + } + } + //Reset PPE port + case (0x2) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + PRST (Local0, Local1) + } + + //Reset XGE core + case (0x3) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XCRT (Local0, Local1) + } + //Reset XGE port + case (0x4) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + XRST (Local0, Local1) + } + + //Reset GE port + case (0x5) + { + Store (Arg1, Local0) + Store (Arg2, Local1) + GRST (Local0, Local1) + } + } + } + + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // 0 : Return Supported Functions bit mask + // 1 : Reset Sequence + // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) + // Arg3[1] : port index in dsaf + // Arg3[2] : 0 reset, 1 cancle reset + // 2 : Set Serdes Loopback + // Arg3[0] : port + // Arg3[1] : 0 disable, 1 enable + // 3 : LED op set + // Arg3[0] : op type + // Arg3[1] : port + // Arg3[2] : para + // 4 : Get port type (GE or XGE) + // Arg3[0] : port index in dsaf + // Return : 0 GE, 1 XGE + // 5 : Get sfp status + // Arg3[0] : port index in dsaf + // Return : 0 no sfp, 1 have sfp + // Arg3: Package Parameters + Method (_DSM, 4, Serialized) + { + If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) + { + If (LEqual (Arg1, 0x00)) + { + Switch (ToInteger(Arg2)) + { + case (0x0) + { + Return (Buffer () {0x3F}) + } + + //Reset Sequence + case (0x1) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + Store (DeRefOf (Index (Arg3, 2)), Local2) + DRST (Local0, Local1, Local2) + } + + //Set Serdes Loopback + case (0x2) + { + Store (DeRefOf (Index (Arg3, 0)), Local0) + Store (DeRefOf (Index (Arg3, 1)), Local1) + SRLP (Local0, Local1) + } + + //LED op set + case (0x3) + { + + } + + // Get port type (GE or XGE) + case (0x4) + { + Store (0, Local1) + Store (DeRefOf (Index (Arg3, 0)), Local0) + If (LLessEqual (Local0, 3)) + { + // mac0: Hilink4 Lane0 + // mac1: Hilink4 Lane1 + // mac2: Hilink4 Lane2 + // mac3: Hilink4 Lane3 + Store (H4ST, Local1) + } + ElseIf (LLessEqual (Local0, 5)) + { + // mac4: Hilink3 Lane2 + // mac5: Hilink3 Lane3 + Store (H3ST, Local1) + } + + Return (Local1) + } + + //Get sfp status + case (0x5) + { + + } + } + } + } + Return (Buffer() {0x00}) + } + + Device (PRT6) + { + Name (_ADR, 0x6) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 0}, + Package () {"media-type", "fiber"}, + } + }) + } + Device (PRT7) + { + Name (_ADR, 0x7) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"reg", 1}, + Package () {"media-type", "fiber"}, + } + }) + } + } + + Device (ETH6) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF1}}, + Package () {"port-idx-in-ae", 0}, + } + }) + } + Device (ETH7) { + Name(_HID, "HISI00C2") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes + Package () {"ae-handle", Package (){_SB.DSF1}}, + Package () {"port-idx-in-ae", 1}, + } + }) + } + +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl new file mode 100644 index 0000000..e2d3ed1 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -0,0 +1,58 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) +{ + Device(I2C0) { + Name(_HID, "APMC0D0F") + Name(_CID, "APMC0D0F") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI6") { 705 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-frequency", 100000}, + Package () {"i2c-sda-falling-time-ns", 913}, + Package () {"i2c-scl-falling-time-ns", 303}, + Package () {"i2c-sda-hold-time-ns", 0x9c2}, + Package () {"interrut-parent",Package() {_SB.MBI6}}, + } + }) + } + + Device(I2C2) { + Name(_HID, "APMC0D0F") + Name(_CID, "APMC0D0F") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xd0100000, 0x10000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI7") { 707 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"clock-frequency", 100000}, + Package () {"i2c-sda-falling-time-ns", 913}, + Package () {"i2c-scl-falling-time-ns", 303}, + Package () {"i2c-sda-hold-time-ns", 0x9c2}, + Package () {"interrut-parent",Package() {_SB.MBI6}}, + } + }) + } +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl new file mode 100644 index 0000000..528f8a3 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -0,0 +1,438 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + // Mbi-gen peri b intc + Device(MBI0) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x60080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 1} + } + }) + } + + Device(MBI1) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 409} + } + }) + } + + // Mbi-gen sas0 + Device(MBI2) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + + Device(MBI3) { // Mbi-gen sas1 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, + } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + Device(MBI4) { // Mbi-gen sas2 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } + + Device(MBI5) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) {640,641,} + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 2} + } + }) + } + + Device(MBI6) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xd0080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 705 } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 1} + } + }) + } + + Device(MBI7) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xd0080000, 0x10000) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 707 } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 1} + } + }) + } + + Device(MBI8) { + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x400c0080000, // Min Base Address + 0x400c008ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name(_PRS, ResourceTemplate() { + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } + }) + + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 409} + } + }) + } +/* + Device(MBI4) { // Mbi-gen dsa1 dbg0 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 9} + } + }) + } + + Device(MBI5) { // Mbi-gen dsa2 dbg1 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 9} + } + }) + } + + Device(MBI6) { // Mbi-gen dsa sas0 intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 128} + } + }) + } +*/ + Device(MBI9) { // Mbi-gen roce intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name (_PRS, ResourceTemplate (){ + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + } +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl new file mode 100644 index 0000000..b822c61 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -0,0 +1,584 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +//#include "ArmPlatform.h" +Scope(_SB) +{ + // 1P NA PCIe2 + Device (PCI2) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 2) // Segment of this Root complex + Name(_BBN, 0x80) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x80, // AddressMinimum - Minimum Bus Number + 0x87, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x8 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xa8800000, // Min Base Address + 0xaffeffff, // Max Base Address + 0x0, // Translate + 0x77f0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0xafff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) + }) + } + } + + } // Device(PCI2) + // 1p NB PCIe0 + Device (PCI4) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 4) // Segment of this Root complex + Name(_BBN, 0x88) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x88, // AddressMinimum - Minimum Bus Number + 0x8f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x8 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xa9000000, // Min Base Address + 0xabfeffff, // Max Base Address + 0x800000000, // Translate + 0x2ff0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0x8abff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0) + Device (RES4) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0090000, // Min Base Address + 0x8a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + } + + } // Device(PCI4) + + // 1P NB PCI1 + Device (PCI5) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 5) // Segment of this Root complex + Name(_BBN, 0x0) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x0, // AddressMinimum - Minimum Bus Number + 0x7, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x8 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xb0800000, // Min Base Address + 0xb7feffff, // Max Base Address + 0x800000000, // Translate + 0x77f0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0x8b7ff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0) + Device (RES5) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0200000, // Min Base Address + 0x8a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + } + } // Device(PCI5) + + // 1P NB PCIe2 + Device (PCI6) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 0x6) // Segment of this Root complex + Name(_BBN, 0xc0) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0xc0, // AddressMinimum - Minimum Bus Number + 0xc7, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x8 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xac900000, // Min Base Address + 0xaffeffff, // Max Base Address + 0x800000000, // Translate + 0x36f0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0x8afff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0) + Device (RES6) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00a0000, // Min Base Address + 0x8a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + } + } // Device(PCI6) + // 1P NB PCIe3 + Device (PCI7) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 0x7) // Segment of this Root complex + Name(_BBN, 0x90) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x90, // AddressMinimum - Minimum Bus Number + 0x97, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x8 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0xb9800000, // Min Base Address + 0xbffeffff, // Max Base Address + 0x800000000, // Translate + 0x67f0000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0x8bfff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0) + Device (RES7) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00b0000, // Min Base Address + 0x8a00bffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + } + } // Device(PCI7) + // 2P NA PCIe2 + Device (PCIa) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 0xa) // Segment of this Root complex + Name(_BBN, 0x10) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x10, // AddressMinimum - Minimum Bus Number + 0x1f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x10 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x20000000, // Min Base Address + 0xefffffff, // Max Base Address + 0x65000000000, // Translate + 0xd0000000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0x67fffff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + Device (RESa) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x600a00a0000, // Min Base Address + 0x600a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + } + } // Device(PCIa) + // 2P NB PCIe0 + Device (PCIc) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 0xc) // Segment of this Root complex + Name(_BBN, 0x20) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x20, // AddressMinimum - Minimum Bus Number + 0x2f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x10 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x30000000, // Min Base Address + 0xefffffff, // Max Base Address + 0x75000000000, // Translate + 0xc0000000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0x77fffff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0) + Device (RESc) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0090000, // Min Base Address + 0x700a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + } + } // Device(PCIc) + + //2P NB PCIe1 + Device (PCId) + { + Name (_HID, "PNP0A08") // PCI Express Root Bridge + Name (_CID, "PNP0A03") // Compatible PCI Root Bridge + Name(_SEG, 0xd) // Segment of this Root complex + Name(_BBN, 0x30) // Base Bus Number + Name(_CCA, 1) + Method (_CRS, 0, Serialized) { // Root complex resources + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0x30, // AddressMinimum - Minimum Bus Number + 0x3f, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 0x10 // RangeLength - Number of Busses + ) + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40000000, // Min Base Address + 0xefffffff, // Max Base Address + 0x79000000000, // Translate + 0xB0000000 // Length + ) + QWordIO ( + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0, // Granularity + 0x0, // Min Base Address + 0xffff, // Max Base Address + 0x7bfffff0000, // Translate + 0x10000 // Length + ) + }) // Name(RBUF) + Return (RBUF) + } // Method(_CRS) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0) + Device (RESd) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0200000, // Min Base Address + 0x700a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + } + } // Device(PCId) +} + diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl new file mode 100644 index 0000000..96df0a8 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -0,0 +1,247 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(_SB) +{ + Device(SAS0) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xC3000000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI2") + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI2") + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI2}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x338), + CLK, 32, + CLKD, 32, + Offset (0xa60), + RST, 32, + DRST, 32, + Offset (0x5a30), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + Device(SAS1) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA2000000, 0x10000) + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI3") + { + 64,65,66,67,68, + 69,70,71,72,73, + 75,76,77,78,79, + 80,81,82,83,84, + 85,86,87,88,89, + 90,91,92,93,94, + 95,96,97,98,99, + 100,101,102,103,104, + 105,106,107,108,109, + 110,111,112,113,114, + 115,116,117,118,119, + 120,121,122,123,124, + 125,126,127,128,129, + 130,131,132,133,134, + 135,136,137,138,139, + 140,141,142,143,144, + 145,146,147,148,149, + 150,151,152,153,154, + 155,156,157,158,159, + 160, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI3") + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI3}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + Package () {"hip06-sas-v2-quirk-amt", 1}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x318), + CLK, 32, + CLKD, 32, + Offset (0xa18), + RST, 32, + DRST, 32, + Offset (0x5a0c), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + + Device(SAS2) { + Name(_HID, "HISI0162") + Name(_CCA, 1) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xA3000000, 0x10000) + + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI4") + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, + } + + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI4") + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"interrupt-parent",Package() {_SB.MBI4}}, + Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, + Package () {"queue-count", 16}, + Package () {"phy-count", 8}, + } + }) + + OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000) + Field (CTL, AnyAcc, NoLock, Preserve) + { + Offset (0x3a8), + CLK, 32, + CLKD, 32, + Offset (0xae0), + RST, 32, + DRST, 32, + Offset (0x5a70), + STS, 32, + } + + Method (_RST, 0x0, Serialized) + { + Store(0x7ffff, RST) + Store(0x7ffff, CLKD) + Sleep(1) + Store(0x7ffff, DRST) + Store(0x7ffff, CLK) + Sleep(1) + } + } + +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl new file mode 100644 index 0000000..51d7d2a --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl @@ -0,0 +1,135 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +//#include "ArmPlatform.h" +Scope(_SB) +{ + Device (USB0) + { + Name (_HID, "PNP0D20") // _HID: Hardware ID + Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xa7020000, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\_SB.MBI5") + { + 641, + } + }) + Return (RBUF) /* _SB_.USB0._CRS.RBUF */ + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"interrupt-parent",Package() {_SB.MBI5}} + } + }) + + Device (RHUB) + { + Name (_ADR, Zero) // _ADR: Address + Device (PRT1) + { + Name (_ADR, One) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, + Zero, + Zero, + Zero + }) + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x1, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "UNKNOWN", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0x0, + PLD_HorizontalOffset = 0x0) + }) + } + + Device (PRT2) + { + Name (_ADR, 0x02) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT3) + { + Name (_ADR, 0x03) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + + Device (PRT4) + { + Name (_ADR, 0x04) // _ADR: Address + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + Zero, + 0xFF, + Zero, + Zero + }) + } + } + } +} + diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl new file mode 100644 index 0000000..b4fc538 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl @@ -0,0 +1,31 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include "Hi1616Platform.h" + +DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP07 ", EFI_ACPI_ARM_OEM_REVISION) { + include ("Lpc.asl") + include ("D05Mbig.asl") + include ("Com.asl") + include ("CPU.asl") + include ("D05I2c.asl") + include ("D05Usb.asl") + include ("D05Hns.asl") + include ("D05Sas.asl") + include ("D05Pci.asl") +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000..0965afc --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2016 Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +// +// LPC +// + +Device (LPC0) +{ + Name(_HID, "HISI0191") // HiSi LPC + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000) + }) +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc new file mode 100644 index 0000000..2908b24 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length + 0xA152, // UINT32 HardwareSignature + 0, // UINT32 FirmwareWakingVector + 0, // UINT32 GlobalLock + 0, // UINT32 Flags + 0, // UINT64 XFirmwareWakingVector + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] + 0, // UINT32 OspmFlags "Platform firmware must + // initialize this field to zero." + { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21] + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22] + EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23] +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs; + diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc new file mode 100644 index 0000000..152410b --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc @@ -0,0 +1,91 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include "Hi1616Platform.h" + +#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h> + +EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..b472828 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc @@ -0,0 +1,95 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include "Hi1616Platform.h" + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT]; +} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ARM_ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress +#ifdef notyet + PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), + 0, 0, 0, 0), + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + 0, 0, 0, 0) + } +#else /* !notyet */ + 0, 0 + } +#endif + }; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; + diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h new file mode 100644 index 0000000..808219a --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + + +#ifndef _HI1610_PLATFORM_H_ +#define _HI1610_PLATFORM_H_ + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124 + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define HI1616_WATCHDOG_COUNT 2 + +#endif diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc new file mode 100644 index 0000000..b83c221 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc @@ -0,0 +1,282 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/ + + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include "Hi1616Platform.h" + +// Differs from Juno, we have another affinity level beyond cluster and core +// 0x20000 is only for socket 0 +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId) << 8) | (CoreId)) + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[64]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[8]; +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_1_0_APIC_SIGNATURE, + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // GsivId, GicRBase, Mpidr) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of + // ACPI v5.1). + // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses + // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( + 63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */), + }, + + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4), + { + EFI_ACPI_6_0_GIC_ITS_INIT(0,0x4C000000), //peri a + EFI_ACPI_6_0_GIC_ITS_INIT(1,0x6C000000), //peri b + EFI_ACPI_6_0_GIC_ITS_INIT(2,0xC6000000), //dsa a + EFI_ACPI_6_0_GIC_ITS_INIT(3,0x8C6000000), //dsa b + EFI_ACPI_6_0_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a + EFI_ACPI_6_0_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b + EFI_ACPI_6_0_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a + EFI_ACPI_6_0_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt;
I have a few style comments inline.
Graeme, Mark, do you have any comments on content? Specifically, there are a lot of _DSD entries in here.
On Thu, Nov 10, 2016 at 09:52:18PM +0800, Heyi Guo wrote:
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 58 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 651 +++++++++++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 127 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 64 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 129 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 280 +++++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 36 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 1236 ++++++++++++++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 58 + .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 438 +++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 584 +++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 247 ++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl | 135 +++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 31 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 91 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 95 ++ .../Hi1616/D05AcpiTables/Hi1616Platform.h | 48 + .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 282 +++++ 20 files changed, 4682 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf new file mode 100644 index 0000000..68379c5 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf @@ -0,0 +1,58 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
Not true, since shose files no longer exist. I guess these are really based on the D03 tables? Please address throughout.
+# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = Hi1616AcpiTables
- FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
+[Sources]
- Dsdt/DsdtHi1616.asl
- Facs.aslc
- Fadt.aslc
- Gtdt.aslc
- MadtHi1616.aslc
- D05Mcfg.aslc
- D05Iort.asl
- D05Slit.aslc
- D05Srat.aslc
+[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl new file mode 100644 index 0000000..61a3c33 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -0,0 +1,651 @@ +/*
- Intel ACPI Component Architecture
- iASL Compiler/Disassembler version 20151124-64
- Copyright (c) 2000 - 2015 Intel Corporation
- Template for [IORT] ACPI Table (static data table)
- Format: [ByteLength] FieldName : HexFieldValue
- */
+[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 000002e4 +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP07 " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124
+[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00
+/* ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 +//4c +/* ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000001 +//64 +/* ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000002 +//7c +/* ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000003 +//94 +/*Sec CPU ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000004 +//ac +/* SEC CPU ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000005 +//c4 +/* SEC CPU ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000006 +//dc +/* SEC CPU ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000007
+/* mbi-gen peri b, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI0" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 000120c7 //device id +[0004] Output Reference : 0000004C +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI1" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI9" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen dsa a - usb named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI5" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI2" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI3" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI4" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 alg a, i2c 0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI6" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B0E //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 alg a, i2c 2 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI7" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B10 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/*1P NA PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002
+[0004] Input base : 00008000 +[0004] ID Count : 00000800 +[0004] Output Base : 00008000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000004
+[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000005
+[0004] Input base : 00000000 +[0004] ID Count : 00000800 +[0004] Output Base : 00000000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000006
+[0004] Input base : 0000c000 +[0004] ID Count : 00000800 +[0004] Output Base : 0000c000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe3 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000007
+[0004] Input base : 00009000 +[0004] ID Count : 00000800 +[0004] Output Base : 00009000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 2P NA PCIe2*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000a
+[0004] Input base : 00001000 +[0004] ID Count : 00001000 +[0004] Output Base : 00001000 +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 2P NB PCIe0*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000c
+[0004] Input base : 00002000 +[0004] ID Count : 00001000 +[0004] Output Base : 00002000 +[0004] Output Reference : 000000dc +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
- /* 2P NB PCIe1*/
+[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000d
+[0004] Input base : 00003000 +[0004] ID Count : 00001000 +[0004] Output Base : 00003000 +[0004] Output Reference : 000000dc +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* mbi-gen1 P1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI8" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00044800 //device id +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc new file mode 100644 index 0000000..9255037 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -0,0 +1,127 @@ +/*
- Copyright (c) 2016 Hisilicon Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- */
+#include <IndustryStandard/Acpi.h> +#include "Hi1616Platform.h"
+#define ACPI_5_0_MCFG_VERSION 0x1
Everything else here seems to be ACPI6 based, so why these ACPI5 defines?
+#pragma pack(1) +typedef struct +{
- UINT64 ullBaseAddress;
- UINT16 usSegGroupNum;
- UINT8 ucStartBusNum;
- UINT8 ucEndBusNum;
- UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+typedef struct +{
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+typedef struct +{
- EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
- EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[8];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack()
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{
- {
{
EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
ACPI_5_0_MCFG_VERSION,
0x00, // Checksum will be updated at runtime
{EFI_ACPI_ARM_OEM_ID},
EFI_ACPI_ARM_OEM_TABLE_ID,
EFI_ACPI_ARM_OEM_REVISION,
EFI_ACPI_ARM_CREATOR_ID,
EFI_ACPI_ARM_CREATOR_REVISION
},
0x0000000000000000, //Reserved
- },
- {
- //1p NA PCIe2
- {
0xa0000000, //Base Address
0x2, //Segment Group Number
0x80, //Start Bus Number
0x87, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe0
- {
0x8a0000000, //Base Address
Comment alignment (and several more instances below).
0x4, //Segment Group Number
0x88, //Start Bus Number
0x8f, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe1
- {
0x8b0000000, //Base Address
0x5, //Segment Group Number
0x0, //Start Bus Number
0x7, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe2
- {
0x8a0000000, //Base Address
0x6, //Segment Group Number
0xc0, //Start Bus Number
0xc7, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe3
- {
0x8b0000000, //Base Address
0x7, //Segment Group Number
0x90, //Start Bus Number
0x97, //End Bus Number
0x00000000, //Reserved
- },
- //2P NA PCIe2
- {
0x64000000000, //Base Address
0xa, //Segment Group Number
0x10, //Start Bus Number
0x1f, //End Bus Number
0x00000000, //Reserved
- },
- //2P NB PCIe0
- {
0x74000000000, //Base Address
0xc, //Segment Group Number
0x20, //Start Bus Number
0x2f, //End Bus Number
0x00000000, //Reserved
- },
- //2P NB PCIe1
- {
0x78000000000, //Base Address
0xd, //Segment Group Number
0x30, //Start Bus Number
0x3f, //End Bus Number
0x00000000, //Reserved
- },
- }
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc new file mode 100644 index 0000000..2276240 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc @@ -0,0 +1,64 @@ +/*
- Copyright (c) 2013 Linaro Limited
And Hisilicon.
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org
+*/
+#include <IndustryStandard/Acpi.h> +#include "Hi1616Platform.h"
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004
+#pragma pack(1) +typedef struct {
- UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+typedef struct {
- EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header;
- EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +#pragma pack()
+// +// System Locality Information Table +// Please modify all values in Slit.h only. +// +EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
- {
- {
EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE),
EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
0x00, // Checksum will be updated at runtime
{EFI_ACPI_ARM_OEM_ID},
EFI_ACPI_ARM_OEM_TABLE_ID,
EFI_ACPI_ARM_OEM_REVISION,
EFI_ACPI_ARM_CREATOR_ID,
EFI_ACPI_ARM_CREATOR_REVISION,
- },
- //
- // Beginning of SLIT specific fields
- //
- EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
- },
- {
- {{0x0A, 0x10, 0x20, 0x21}}, //Locality 0
- {{0x10, 0x0A, 0x19, 0x20}}, //Locality 1
- {{0x20, 0x19, 0x0A, 0x10}}, //Locality 2
- {{0x21, 0x20, 0x10, 0x0A}}, //Locality 3
- },
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Slit; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc new file mode 100644 index 0000000..f7ea15e --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc @@ -0,0 +1,129 @@ +/*
- Copyright (c) 2013 Linaro Limited
And Hisilicon?
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> +#include "Hi1616Platform.h"
+// +// Static Resource Affinity Table definition +// +EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
- {
- {EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE),
- EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
- 0x00, // Checksum will be updated at runtime
- {EFI_ACPI_ARM_OEM_ID},
- EFI_ACPI_ARM_OEM_TABLE_ID,
- EFI_ACPI_ARM_OEM_REVISION,
- EFI_ACPI_ARM_CREATOR_ID,
- EFI_ACPI_ARM_CREATOR_REVISION},
- /*Reserved*/
- 0x00000001, // Reserved to be 1 for backward compatibility
- EFI_ACPI_RESERVED_QWORD
- },
- //
- //
- // Memory Affinity
- //
- {
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- },
- {
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63
- },
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Srat; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..5ecbf50 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,280 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- //
- // A57x16 Processor declaration
- //
- Device(CPU0) {
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- }
- Device(CPU1) {
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- }
- Device(CPU2) {
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- }
- Device(CPU3) {
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- }
- Device(CPU4) {
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- }
- Device(CPU5) {
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- }
- Device(CPU6) {
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- }
- Device(CPU7) {
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- }
- Device(CPU8) {
- Name(_HID, "ACPI0007")
- Name(_UID, 8)
- }
- Device(CPU9) {
- Name(_HID, "ACPI0007")
- Name(_UID, 9)
- }
- Device(CP10) {
- Name(_HID, "ACPI0007")
- Name(_UID, 10)
- }
- Device(CP11) {
- Name(_HID, "ACPI0007")
- Name(_UID, 11)
- }
- Device(CP12) {
- Name(_HID, "ACPI0007")
- Name(_UID, 12)
- }
- Device(CP13) {
- Name(_HID, "ACPI0007")
- Name(_UID, 13)
- }
- Device(CP14) {
- Name(_HID, "ACPI0007")
- Name(_UID, 14)
- }
- Device(CP15) {
- Name(_HID, "ACPI0007")
- Name(_UID, 15)
- }
- Device(CP16) {
- Name(_HID, "ACPI0007")
- Name(_UID, 16)
- }
- Device(CP17) {
- Name(_HID, "ACPI0007")
- Name(_UID, 17)
- }
- Device(CP18) {
- Name(_HID, "ACPI0007")
- Name(_UID, 18)
- }
- Device(CP19) {
- Name(_HID, "ACPI0007")
- Name(_UID, 19)
- }
- Device(CP20) {
- Name(_HID, "ACPI0007")
- Name(_UID, 20)
- }
- Device(CP21) {
- Name(_HID, "ACPI0007")
- Name(_UID, 21)
- }
- Device(CP22) {
- Name(_HID, "ACPI0007")
- Name(_UID, 22)
- }
- Device(CP23) {
- Name(_HID, "ACPI0007")
- Name(_UID, 23)
- }
- Device(CP24) {
- Name(_HID, "ACPI0007")
- Name(_UID, 24)
- }
- Device(CP25) {
- Name(_HID, "ACPI0007")
- Name(_UID, 25)
- }
- Device(CP26) {
- Name(_HID, "ACPI0007")
- Name(_UID, 26)
- }
- Device(CP27) {
- Name(_HID, "ACPI0007")
- Name(_UID, 27)
- }
- Device(CP28) {
- Name(_HID, "ACPI0007")
- Name(_UID, 28)
- }
- Device(CP29) {
- Name(_HID, "ACPI0007")
- Name(_UID, 29)
- }
- Device(CP30) {
- Name(_HID, "ACPI0007")
- Name(_UID, 30)
- }
- Device(CP31) {
- Name(_HID, "ACPI0007")
- Name(_UID, 31)
- }
- Device(CP32) {
- Name(_HID, "ACPI0007")
- Name(_UID, 32)
- }
- Device(CP33) {
- Name(_HID, "ACPI0007")
- Name(_UID, 33)
- }
- Device(CP34) {
- Name(_HID, "ACPI0007")
- Name(_UID, 34)
- }
- Device(CP35) {
- Name(_HID, "ACPI0007")
- Name(_UID, 35)
- }
- Device(CP36) {
- Name(_HID, "ACPI0007")
- Name(_UID, 36)
- }
- Device(CP37) {
- Name(_HID, "ACPI0007")
- Name(_UID, 37)
- }
- Device(CP38) {
- Name(_HID, "ACPI0007")
- Name(_UID, 38)
- }
- Device(CP39) {
- Name(_HID, "ACPI0007")
- Name(_UID, 39)
- }
- Device(CP40) {
- Name(_HID, "ACPI0007")
- Name(_UID, 40)
- }
- Device(CP41) {
- Name(_HID, "ACPI0007")
- Name(_UID, 41)
- }
- Device(CP42) {
- Name(_HID, "ACPI0007")
- Name(_UID, 42)
- }
- Device(CP43) {
- Name(_HID, "ACPI0007")
- Name(_UID, 43)
- }
- Device(CP44) {
- Name(_HID, "ACPI0007")
- Name(_UID, 44)
- }
- Device(CP45) {
- Name(_HID, "ACPI0007")
- Name(_UID, 45)
- }
- Device(CP46) {
- Name(_HID, "ACPI0007")
- Name(_UID, 46)
- }
- Device(CP47) {
- Name(_HID, "ACPI0007")
- Name(_UID, 47)
- }
- Device(CP48) {
- Name(_HID, "ACPI0007")
- Name(_UID, 48)
- }
- Device(CP49) {
- Name(_HID, "ACPI0007")
- Name(_UID, 49)
- }
- Device(CP50) {
- Name(_HID, "ACPI0007")
- Name(_UID, 50)
- }
- Device(CP51) {
- Name(_HID, "ACPI0007")
- Name(_UID, 51)
- }
- Device(CP52) {
- Name(_HID, "ACPI0007")
- Name(_UID, 52)
- }
- Device(CP53) {
- Name(_HID, "ACPI0007")
- Name(_UID, 53)
- }
- Device(CP54) {
- Name(_HID, "ACPI0007")
- Name(_UID, 54)
- }
- Device(CP55) {
- Name(_HID, "ACPI0007")
- Name(_UID, 55)
- }
- Device(CP56) {
- Name(_HID, "ACPI0007")
- Name(_UID, 56)
- }
- Device(CP57) {
- Name(_HID, "ACPI0007")
- Name(_UID, 57)
- }
- Device(CP58) {
- Name(_HID, "ACPI0007")
- Name(_UID, 58)
- }
- Device(CP59) {
- Name(_HID, "ACPI0007")
- Name(_UID, 59)
- }
- Device(CP60) {
- Name(_HID, "ACPI0007")
- Name(_UID, 60)
- }
- Device(CP61) {
- Name(_HID, "ACPI0007")
- Name(_UID, 61)
- }
- Device(CP62) {
- Name(_HID, "ACPI0007")
- Name(_UID, 62)
- }
- Device(CP63) {
- Name(_HID, "ACPI0007")
- Name(_UID, 63)
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000..b7c4905 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl @@ -0,0 +1,36 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- Device(COM0) {
- Name(_HID, "ARMH0011")
- Name(_CID, "PL011")
- Name(_UID, Zero)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x602B0000, 0x1000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 807 }
- })
- Name(_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package() {
Package() {"interrupt-parent",Package() {\_SB.MBI0}},
Is this putting interrupt topology information into _DSD?
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl new file mode 100644 index 0000000..e855e5d --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -0,0 +1,1236 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- Device (MDIO)
- {
- OperationRegion(CLKR, SystemMemory, 0x60000550, 8)
- Field(CLKR, DWordAcc, NoLock, Preserve) {
CLKE, 1, // clock enable
, 31,
CLKD, 1, // clode disable
, 31,
- }
- OperationRegion(RSTR, SystemMemory, 0x60000c40, 8)
- Field(RSTR, DWordAcc, NoLock, Preserve) {
RSTE, 1, // reset
, 31,
RSTD, 1, // de-reset
, 31,
- }
- Name(_HID, "HISI0141")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)
- })
- Method(_RST, 0, Serialized) {
Store (0x1, RSTE)
Sleep (10)
Store (0x1, CLKD)
Sleep (10)
Store (0x1, RSTD)
Sleep (10)
Store (0x1, CLKE)
Sleep (10)
- }
- }
- Device (DSF0)
- {
- OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
H3ST, 1,
, 31, //RESERVED
- }
- OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
- Field(H4SR, DWordAcc, NoLock, Preserve) {
H4ST, 1,
, 31, //RESERVED
- }
- // DSAF RESET
- OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
- Field(DRER, DWordAcc, NoLock, Preserve) {
DRTE, 1,
, 31, //RESERVED
DRTD, 1,
, 31, //RESERVED
- }
- // NT RESET
- OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
- Field(NRER, DWordAcc, NoLock, Preserve) {
NRTE, 1,
, 31, //RESERVED
NRTD, 1,
, 31, //RESERVED
- }
- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
XRTE, 31,
, 1, //RESERVED
XRTD, 31,
, 1, //RESERVED
- }
- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
GR0E, 30,
, 2, //RESERVED
GR0D, 30,
, 2, //RESERVED
GR1E, 18,
, 14, //RESERVED
GR1D, 18,
, 14, //RESERVED
- }
- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
PRTE, 10,
, 22, //RESERVED
PRTD, 10,
, 22, //RESERVED
- }
- // RCB PPE COM RESET
- OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
- Field(RRTR, DWordAcc, NoLock, Preserve) {
RRTE, 1,
, 31, //RESERVED
RRTD, 1,
, 31, //RESERVED
- }
- // DSAF Channel RESET
- OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8)
- Field(DCRR, DWordAcc, NoLock, Preserve) {
DCRE, 1,
, 31, //RESERVED
DCRD, 1,
, 31, //RESERVED
- }
- // RoCE RESET
- OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8)
- Field(RKRR, DWordAcc, NoLock, Preserve) {
RKRE, 1,
, 31, //RESERVED
RKRD, 1,
, 31, //RESERVED
- }
- // RoCE Clock enable/disable
- OperationRegion(RKCR, SystemMemory, 0xC0000328, 8)
- Field(RKCR, DWordAcc, NoLock, Preserve) {
RCLE, 1,
, 31, //RESERVED
RCLD, 1,
, 31, //RESERVED
- }
- // Hilink access sel cfg reg
- OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
- Field(HSER, DWordAcc, NoLock, Preserve) {
HSEL, 2, // hilink_access_sel & hilink_access_wr_pul
, 30, // RESERVED
- }
- // Serdes
- OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
- Field(H4LR, DWordAcc, NoLock, Preserve) {
H4L0, 16, // port0
, 16, //RESERVED
Offset (0x400),
H4L1, 16, // port1
, 16, //RESERVED
Offset (0x800),
H4L2, 16, // port2
, 16, //RESERVED
Offset (0xc00),
H4L3, 16, // port3
, 16, //RESERVED
- }
- OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
H3L2, 16, // port4
, 16, //RESERVED
Offset (0x400),
H3L3, 16, // port5
, 16, //RESERVED
- }
- Name (_HID, "HISI00B2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"mode", "6port-16rss"},
Package () {"buf-size", 4096},
Package () {"desc-num", 1024},
Package () {"interrupt-parent", Package() {\_SB.MBI1}},
}
- })
- //reset XGE port
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XRST, 2, Serialized) {
ShiftLeft (0x2082082, Arg0, Local0)
Or (Local0, 0x1, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset XGE core
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XCRT, 2, Serialized) {
ShiftLeft (0x2080, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset GE port
- //Arg0 : GE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(GRST, 2, Serialized) {
If (LLessEqual (Arg0, 5)) {
//Service port
ShiftLeft (0x2082082, Arg0, Local0)
ShiftLeft (0x1, Arg0, Local1)
If (LEqual (Arg1, 0)) {
Store(Local1, GR1E)
Store(Local0, GR0E)
} Else {
Store(Local0, GR0D)
Store(Local1, GR1D)
}
}
- }
- //reset PPE port
- //Arg0 : PPE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(PRST, 2, Serialized) {
ShiftLeft (0x1, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, PRTE)
} Else {
Store(Local0, PRTD)
}
- }
- //reset DSAF channels
- //Arg0 : mask
- //Arg1 : 0 reset, 1 de-reset
- Method(DCRT, 2, Serialized) {
If (LEqual (Arg1, 0)) {
Store(Arg0, DCRE)
} Else {
Store(Arg0, DCRD)
}
- }
- //reset RoCE
- //Arg0 : 0 reset, 1 de-reset
- Method(RRST, 1, Serialized) {
If (LEqual (Arg0, 0)) {
Store(0x1, RKRE)
} Else {
Store(0x1, RCLD)
Store(0x1, RKRD)
sleep(20)
Store(0x1, RCLE)
}
- }
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 2, Serialized) {
ShiftLeft (Arg1, 10, Local0)
Switch (ToInteger(Arg0))
{
case (0x0){
Store (0, HSEL)
Store (H4L0, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L0)
}
case (0x1){
Store (0, HSEL)
Store (H4L1, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L1)
}
case (0x2){
Store (0, HSEL)
Store (H4L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L2)
}
case (0x3){
Store (0, HSEL)
Store (H4L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L3)
}
case (0x4){
Store (3, HSEL)
Store (H3L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L2)
}
case (0x5){
Store (3, HSEL)
Store (H3L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L3)
}
}
- }
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:ge; 6:dchan; 7:RoCE)
- //Arg1 : port
- //Arg2 : 0 disable, 1 enable
- Method(DRST, 3, Serialized)
- {
Switch (ToInteger(Arg0))
{
//DSAF reset
case (0x1)
{
Store (Arg2, Local0)
If (LEqual (Local0, 0))
{
Store (0x1, DRTE)
Store (0x1, NRTE)
Sleep (10)
Store (0x1, RRTE)
}
Else
{
Store (0x1, DRTD)
Store (0x1, NRTD)
Sleep (10)
Store (0x1, RRTD)
}
}
//Reset PPE port
case (0x2)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
PRST (Local0, Local1)
}
//Reset XGE core
case (0x3)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XCRT (Local0, Local1)
}
//Reset XGE port
case (0x4)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XRST (Local0, Local1)
}
//Reset GE port
case (0x5)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
GRST (Local0, Local1)
}
//Reset DSAF Channels
case (0x6)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
DCRT (Local0, Local1)
}
//Reset RoCE
case (0x7)
{
// Discarding Arg1 as it is always 0
Store (Arg2, Local0)
RRST (Local0)
}
}
- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge; 6:dchan; 7:RoCE)
- // Arg3[1] : port index in dsaf
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : port
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : port
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : port index in dsaf
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : port index in dsaf
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
{
If (LEqual (Arg1, 0x00))
{
Switch (ToInteger(Arg2))
{
case (0x0)
{
Return (Buffer () {0x3F})
}
//Reset Sequence
case (0x1)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
Store (DeRefOf (Index (Arg3, 2)), Local2)
DRST (Local0, Local1, Local2)
}
//Set Serdes Loopback
case (0x2)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
SRLP (Local0, Local1)
}
//LED op set
case (0x3)
{
}
// Get port type (GE or XGE)
case (0x4)
{
Store (0, Local1)
Store (DeRefOf (Index (Arg3, 0)), Local0)
If (LLessEqual (Local0, 3))
{
// mac0: Hilink4 Lane0
// mac1: Hilink4 Lane1
// mac2: Hilink4 Lane2
// mac3: Hilink4 Lane3
Store (H4ST, Local1)
}
ElseIf (LLessEqual (Local0, 5))
{
// mac4: Hilink3 Lane2
// mac5: Hilink3 Lane3
Store (H3ST, Local1)
}
Return (Local1)
}
//Get sfp status
case (0x5)
{
}
}
}
}
Return (Buffer() {0x00})
- }
- Device (PRT0)
- {
Name (_ADR, 0x0)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 0},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT1)
- {
Name (_ADR, 0x1)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 1},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT2)
- {
Name (_ADR, 0x2)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 2},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT3)
- {
Name (_ADR, 0x3)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 3},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT4)
- {
Name (_ADR, 0x4)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 4},
Package () {"phy-mode", "sgmii"},
Package () {"phy-addr", 0},
Package () {"mdio-node", Package (){\_SB.MDIO}},
Package () {"media-type", "copper"},
}
})
- }
- Device (PRT5)
- {
Name (_ADR, 0x5)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 5},
Package () {"phy-mode", "sgmii"},
Package () {"phy-addr", 1},
Package () {"mdio-node", Package (){\_SB.MDIO}},
Package () {"media-type", "copper"},
}
})
- }
- }
- Device (ETH4) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 4},
}
- })
- }
- Device (ETH5) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 5},
}
- })
- }
- Device (ETH0) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 0},
}
- })
- }
- Device (ETH1) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 1},
}
- })
- }
- Device (ETH2) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 2},
}
- })
- }
- Device (ETH3) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 3},
}
- })
- }
- Device (ROCE) {
- Name(_HID, "HISI00D1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},
Package () {"dsaf-handle", Package (){\_SB.DSF0}},
Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes
Package () {"interrupt-parent", Package() {\_SB.MBI9}},
Package () {"interrupt-names", Package() {"hns-roce-comp-0",
"hns-roce-comp-1",
"hns-roce-comp-2",
"hns-roce-comp-3",
"hns-roce-comp-4",
"hns-roce-comp-5",
"hns-roce-comp-6",
"hns-roce-comp-7",
"hns-roce-comp-8",
"hns-roce-comp-9",
"hns-roce-comp-10",
"hns-roce-comp-11",
"hns-roce-comp-12",
"hns-roce-comp-13",
"hns-roce-comp-14",
"hns-roce-comp-15",
"hns-roce-comp-16",
"hns-roce-comp-17",
"hns-roce-comp-18",
"hns-roce-comp-19",
"hns-roce-comp-20",
"hns-roce-comp-21",
"hns-roce-comp-22",
"hns-roce-comp-23",
"hns-roce-comp-24",
"hns-roce-comp-25",
"hns-roce-comp-26",
"hns-roce-comp-27",
"hns-roce-comp-28",
"hns-roce-comp-29",
"hns-roce-comp-30",
"hns-roce-comp-31",
"hns-roce-async",
"hns-roce-common"}},
}
- })
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI9")
{
722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
}
- })
- }
- /* for p1 */
- Device (DSF1)
- {
- OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
H3ST, 1,
, 31, //RESERVED
- }
- OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4)
- Field(H4SR, DWordAcc, NoLock, Preserve) {
H4ST, 1,
, 31, //RESERVED
- }
- // DSAF RESET
- OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8)
- Field(DRER, DWordAcc, NoLock, Preserve) {
DRTE, 1,
, 31, //RESERVED
DRTD, 1,
, 31, //RESERVED
- }
- // NT RESET
- OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8)
- Field(NRER, DWordAcc, NoLock, Preserve) {
NRTE, 1,
, 31, //RESERVED
NRTD, 1,
, 31, //RESERVED
- }
- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
XRTE, 31,
, 1, //RESERVED
XRTD, 31,
, 1, //RESERVED
- }
- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
GR0E, 30,
, 2, //RESERVED
GR0D, 30,
, 2, //RESERVED
GR1E, 18,
, 14, //RESERVED
GR1D, 18,
, 14, //RESERVED
- }
- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
PRTE, 10,
, 22, //RESERVED
PRTD, 10,
, 22, //RESERVED
- }
- // RCB PPE COM RESET
- OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8)
- Field(RRTR, DWordAcc, NoLock, Preserve) {
RRTE, 1,
, 31, //RESERVED
RRTD, 1,
, 31, //RESERVED
- }
- // RCB_2X COM RESET
- OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8)
- Field(RBTR, DWordAcc, NoLock, Preserve) {
RBTE, 1,
, 31, //RESERVED
RBTD, 1,
, 31, //RESERVED
- }
- // Hilink access sel cfg reg
- OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4)
- Field(HSER, DWordAcc, NoLock, Preserve) {
HSEL, 2, // hilink_access_sel & hilink_access_wr_pul
, 30, // RESERVED
- }
- // Serdes
- OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000)
- Field(H4LR, DWordAcc, NoLock, Preserve) {
H4L0, 16, // port0
, 16, //RESERVED
Offset (0x400),
H4L1, 16, // port1
, 16, //RESERVED
Offset (0x800),
H4L2, 16, // port2
, 16, //RESERVED
Offset (0xc00),
H4L3, 16, // port3
, 16, //RESERVED
- }
- OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
H3L2, 16, // port4
, 16, //RESERVED
Offset (0x400),
H3L3, 16, // port5
, 16, //RESERVED
- }
- Name (_HID, "HISI00B2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x400c5000000, // Min Base Address
0x400c588ffff, // Max Base Address
0x0, // Translate
0x890000 // Length
)
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x400c7000000, // Min Base Address
0x400c705ffff, // Max Base Address
0x0, // Translate
0x60000 // Length
)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"mode", "6port-16rss"},
Package () {"buf-size", 4096},
Package () {"desc-num", 1024},
Package () {"interrupt-parent", Package() {\_SB.MBI8}},
}
- })
- //reset XGE port
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XRST, 2, Serialized) {
ShiftLeft (0x2082082, Arg0, Local0)
Or (Local0, 0x1, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset XGE core
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XCRT, 2, Serialized) {
ShiftLeft (0x2080, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset GE port
- //Arg0 : GE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(GRST, 2, Serialized) {
If (LLessEqual (Arg0, 5)) {
//Service port
ShiftLeft (0x2082082, Arg0, Local0)
ShiftLeft (0x1, Arg0, Local1)
If (LEqual (Arg1, 0)) {
Store(Local1, GR1E)
Store(Local0, GR0E)
} Else {
Store(Local0, GR0D)
Store(Local1, GR1D)
}
}
- }
- //reset PPE port
- //Arg0 : PPE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(PRST, 2, Serialized) {
ShiftLeft (0x1, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, PRTE)
} Else {
Store(Local0, PRTD)
}
- }
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 2, Serialized) {
ShiftLeft (Arg1, 10, Local0)
Switch (ToInteger(Arg0))
{
case (0x0){
Store (0, HSEL)
Store (H4L0, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L0)
}
case (0x1){
Store (0, HSEL)
Store (H4L1, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L1)
}
case (0x2){
Store (0, HSEL)
Store (H4L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L2)
}
case (0x3){
Store (0, HSEL)
Store (H4L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L3)
}
case (0x4){
Store (3, HSEL)
Store (H3L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L2)
}
case (0x5){
Store (3, HSEL)
Store (H3L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L3)
}
}
- }
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
- //Arg1 : port
- //Arg2 : 0 disable, 1 enable
- Method(DRST, 3, Serialized)
- {
Switch (ToInteger(Arg0))
{
//DSAF reset
case (0x1)
{
Store (Arg2, Local0)
If (LEqual (Local0, 0))
{
Store (0x1, DRTE)
Store (0x1, NRTE)
Sleep (10)
Store (0x1, RRTE)
Store (0x1, RBTE)
}
Else
{
Store (0x1, DRTD)
Store (0x1, NRTD)
Sleep (10)
Store (0x1, RRTD)
Store (0x1, RBTD)
}
}
//Reset PPE port
case (0x2)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
PRST (Local0, Local1)
}
//Reset XGE core
case (0x3)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XCRT (Local0, Local1)
}
//Reset XGE port
case (0x4)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XRST (Local0, Local1)
}
//Reset GE port
case (0x5)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
GRST (Local0, Local1)
}
}
- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
- // Arg3[1] : port index in dsaf
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : port
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : port
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : port index in dsaf
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : port index in dsaf
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
{
If (LEqual (Arg1, 0x00))
{
Switch (ToInteger(Arg2))
{
case (0x0)
{
Return (Buffer () {0x3F})
}
//Reset Sequence
case (0x1)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
Store (DeRefOf (Index (Arg3, 2)), Local2)
DRST (Local0, Local1, Local2)
}
//Set Serdes Loopback
case (0x2)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
SRLP (Local0, Local1)
}
//LED op set
case (0x3)
{
}
// Get port type (GE or XGE)
case (0x4)
{
Store (0, Local1)
Store (DeRefOf (Index (Arg3, 0)), Local0)
If (LLessEqual (Local0, 3))
{
// mac0: Hilink4 Lane0
// mac1: Hilink4 Lane1
// mac2: Hilink4 Lane2
// mac3: Hilink4 Lane3
Store (H4ST, Local1)
}
ElseIf (LLessEqual (Local0, 5))
{
// mac4: Hilink3 Lane2
// mac5: Hilink3 Lane3
Store (H3ST, Local1)
}
Return (Local1)
}
//Get sfp status
case (0x5)
{
}
}
}
}
Return (Buffer() {0x00})
- }
- Device (PRT6)
- {
Name (_ADR, 0x6)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 0},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT7)
- {
Name (_ADR, 0x7)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 1},
Package () {"media-type", "fiber"},
}
})
- }
- }
- Device (ETH6) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF1}},
Package () {"port-idx-in-ae", 0},
}
- })
- }
- Device (ETH7) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF1}},
Package () {"port-idx-in-ae", 1},
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl new file mode 100644 index 0000000..e2d3ed1 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -0,0 +1,58 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- Device(I2C0) {
- Name(_HID, "APMC0D0F")
- Name(_CID, "APMC0D0F")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 }
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"clock-frequency", 100000},
Package () {"i2c-sda-falling-time-ns", 913},
Package () {"i2c-scl-falling-time-ns", 303},
Package () {"i2c-sda-hold-time-ns", 0x9c2},
Package () {"interrut-parent",Package() {\_SB.MBI6}},
}
- })
- }
- Device(I2C2) {
- Name(_HID, "APMC0D0F")
- Name(_CID, "APMC0D0F")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd0100000, 0x10000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") { 707 }
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"clock-frequency", 100000},
Package () {"i2c-sda-falling-time-ns", 913},
Package () {"i2c-scl-falling-time-ns", 303},
Package () {"i2c-sda-hold-time-ns", 0x9c2},
Package () {"interrut-parent",Package() {\_SB.MBI6}},
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl new file mode 100644 index 0000000..528f8a3 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -0,0 +1,438 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- // Mbi-gen peri b intc
- Device(MBI0) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x60080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 }
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 1}
}
- })
- }
- Device(MBI1) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 409}
}
- })
- }
- // Mbi-gen sas0
- Device(MBI2) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,)
{
601,602,603,604,
605,606,607,608,609,
610,611,612,613,614,
615,616,617,618,619,
620,621,622,623,624,
625,626,627,628,629,
630,631,632,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
- Device(MBI3) { // Mbi-gen sas1 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
576,577,578,579,580,
581,582,583,584,585,
586,587,588,589,590,
591,592,593,594,595,
596,597,598,599,600,
601,602,603,604,605,
606,607,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
- Device(MBI4) { // Mbi-gen sas2 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
{
192,193,194,195,196,
197,198,199,200,201,
202,203,204,205,206,
207,208,209,210,211,
212,213,214,215,216,
217,218,219,220,221,
222,223,224,225,226,
227,228,229,230,231,
232,233,234,235,236,
237,238,239,240,241,
242,243,244,245,246,
247,248,249,250,251,
252,253,254,255,256,
257,258,259,260,261,
262,263,264,265,266,
267,268,269,270,271,
272,273,274,275,276,
277,278,279,280,281,
282,283,284,285,286,
287,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
608,609,610,611,
612,613,614,615,616,
617,618,619,620,621,
622,623,624,625,626,
627,628,629,630,631,
632,633,634,635,636,
637,638,639,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
- Device(MBI5) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) {640,641,}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 2}
}
- })
- }
- Device(MBI6) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 705 }
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 1}
}
- })
- }
- Device(MBI7) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 707 }
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 1}
}
- })
- }
- Device(MBI8) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x400c0080000, // Min Base Address
0x400c008ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 409}
}
- })
- }
+/*
- Device(MBI4) { // Mbi-gen dsa1 dbg0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 9}
}
- })
- }
- Device(MBI5) { // Mbi-gen dsa2 dbg1 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 9}
}
- })
- }
- Device(MBI6) { // Mbi-gen dsa sas0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
+*/
- Device(MBI9) { // Mbi-gen roce intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name (_PRS, ResourceTemplate (){
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
{
722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl new file mode 100644 index 0000000..b822c61 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -0,0 +1,584 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+//#include "ArmPlatform.h" +Scope(_SB) +{
- // 1P NA PCIe2
- Device (PCI2)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 2) // Segment of this Root complex
- Name(_BBN, 0x80) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x80, // AddressMinimum - Minimum Bus Number
0x87, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xa8800000, // Min Base Address
0xaffeffff, // Max Base Address
0x0, // Translate
0x77f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0xafff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)
- Device (RES2)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000)
})
- }
- }
- } // Device(PCI2)
- // 1p NB PCIe0
- Device (PCI4)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 4) // Segment of this Root complex
- Name(_BBN, 0x88) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x88, // AddressMinimum - Minimum Bus Number
0x8f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xa9000000, // Min Base Address
0xabfeffff, // Max Base Address
0x800000000, // Translate
0x2ff0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8abff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES4)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a0090000, // Min Base Address
0x8a009ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCI4)
- // 1P NB PCI1
- Device (PCI5)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 5) // Segment of this Root complex
- Name(_BBN, 0x0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x0, // AddressMinimum - Minimum Bus Number
0x7, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xb0800000, // Min Base Address
0xb7feffff, // Max Base Address
0x800000000, // Translate
0x77f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8b7ff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES5)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a0200000, // Min Base Address
0x8a020ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCI5)
- // 1P NB PCIe2
- Device (PCI6)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0x6) // Segment of this Root complex
- Name(_BBN, 0xc0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0xc0, // AddressMinimum - Minimum Bus Number
0xc7, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xac900000, // Min Base Address
0xaffeffff, // Max Base Address
0x800000000, // Translate
0x36f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8afff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES6)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a00a0000, // Min Base Address
0x8a00affff, // Max Base Address
0x0, // Translate
0x10000 // Length
- )
})
- }
- }
- } // Device(PCI6)
- // 1P NB PCIe3
- Device (PCI7)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0x7) // Segment of this Root complex
- Name(_BBN, 0x90) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x90, // AddressMinimum - Minimum Bus Number
0x97, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xb9800000, // Min Base Address
0xbffeffff, // Max Base Address
0x800000000, // Translate
0x67f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8bfff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES7)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a00b0000, // Min Base Address
0x8a00bffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCI7)
- // 2P NA PCIe2
- Device (PCIa)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0xa) // Segment of this Root complex
- Name(_BBN, 0x10) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x10, // AddressMinimum - Minimum Bus Number
0x1f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x10 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0x20000000, // Min Base Address
0xefffffff, // Max Base Address
0x65000000000, // Translate
0xd0000000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x67fffff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)
- Device (RESa)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x600a00a0000, // Min Base Address
0x600a00affff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCIa)
- // 2P NB PCIe0
- Device (PCIc)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0xc) // Segment of this Root complex
- Name(_BBN, 0x20) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x20, // AddressMinimum - Minimum Bus Number
0x2f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x10 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0x30000000, // Min Base Address
0xefffffff, // Max Base Address
0x75000000000, // Translate
0xc0000000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x77fffff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RESc)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x700a0090000, // Min Base Address
0x700a009ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCIc)
- //2P NB PCIe1
- Device (PCId)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0xd) // Segment of this Root complex
- Name(_BBN, 0x30) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x30, // AddressMinimum - Minimum Bus Number
0x3f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x10 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0x40000000, // Min Base Address
0xefffffff, // Max Base Address
0x79000000000, // Translate
0xB0000000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x7bfffff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RESd)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x700a0200000, // Min Base Address
0x700a020ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCId)
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl new file mode 100644 index 0000000..96df0a8 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -0,0 +1,247 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- Device(SAS0) {
- Name(_HID, "HISI0162")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
{
601,602,603,604,
605,606,607,608,609,
610,611,612,613,614,
615,616,617,618,619,
620,621,622,623,624,
625,626,627,628,629,
630,631,632,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"interrupt-parent",Package() {\_SB.MBI2}},
Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},
Package () {"queue-count", 16},
Package () {"phy-count", 8},
}
- })
- OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x338),
CLK, 32,
CLKD, 32,
Offset (0xa60),
RST, 32,
DRST, 32,
Offset (0x5a30),
STS, 32,
- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)
Store(0x7ffff, CLKD)
Sleep(1)
Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
- }
- }
- Device(SAS1) {
- Name(_HID, "HISI0162")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
{
576,577,578,579,580,
581,582,583,584,585,
586,587,588,589,590,
591,592,593,594,595,
596,597,598,599,600,
601,602,603,604,605,
606,607,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"interrupt-parent",Package() {\_SB.MBI3}},
Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
Package () {"queue-count", 16},
Package () {"phy-count", 8},
Package () {"hip06-sas-v2-quirk-amt", 1},
}
- })
- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x318),
CLK, 32,
CLKD, 32,
Offset (0xa18),
RST, 32,
DRST, 32,
Offset (0x5a0c),
STS, 32,
- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)
Store(0x7ffff, CLKD)
Sleep(1)
Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
- }
- }
- Device(SAS2) {
- Name(_HID, "HISI0162")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
{
192,193,194,195,196,
197,198,199,200,201,
202,203,204,205,206,
207,208,209,210,211,
212,213,214,215,216,
217,218,219,220,221,
222,223,224,225,226,
227,228,229,230,231,
232,233,234,235,236,
237,238,239,240,241,
242,243,244,245,246,
247,248,249,250,251,
252,253,254,255,256,
257,258,259,260,261,
262,263,264,265,266,
267,268,269,270,271,
272,273,274,275,276,
277,278,279,280,281,
282,283,284,285,286,
287,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
{
608,609,610,611,
612,613,614,615,616,
617,618,619,620,621,
622,623,624,625,626,
627,628,629,630,631,
632,633,634,635,636,
637,638,639,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"interrupt-parent",Package() {\_SB.MBI4}},
Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
Package () {"queue-count", 16},
Package () {"phy-count", 8},
}
- })
- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x3a8),
CLK, 32,
CLKD, 32,
Offset (0xae0),
RST, 32,
DRST, 32,
Offset (0x5a70),
STS, 32,
- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)
Store(0x7ffff, CLKD)
Sleep(1)
Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
- }
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl new file mode 100644 index 0000000..51d7d2a --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl @@ -0,0 +1,135 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+//#include "ArmPlatform.h" +Scope(_SB) +{
- Device (USB0)
- {
- Name (_HID, "PNP0D20") // _HID: Hardware ID
- Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID
- Name (_CCA, One) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
- {
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0xa7020000, // Address Base
0x00010000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI5")
{
641,
}
})
Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
- }
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"interrupt-parent",Package() {\_SB.MBI5}}
}
- })
- Device (RHUB)
- {
Name (_ADR, Zero) // _ADR: Address
Device (PRT1)
{
Name (_ADR, One) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
Zero,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
})
}
Device (PRT2)
{
Name (_ADR, 0x02) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
Zero,
0xFF,
Zero,
Zero
})
}
Device (PRT3)
{
Name (_ADR, 0x03) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
Zero,
0xFF,
Zero,
Zero
})
}
Device (PRT4)
{
Name (_ADR, 0x04) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
Zero,
0xFF,
Zero,
Zero
})
}
- }
- }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl new file mode 100644 index 0000000..b4fc538 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl @@ -0,0 +1,31 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+#include "Hi1616Platform.h"
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP07 ", EFI_ACPI_ARM_OEM_REVISION) {
- include ("Lpc.asl")
- include ("D05Mbig.asl")
- include ("Com.asl")
- include ("CPU.asl")
- include ("D05I2c.asl")
- include ("D05Usb.asl")
- include ("D05Hns.asl")
- include ("D05Sas.asl")
- include ("D05Pci.asl")
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000..0965afc --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2016 Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+// +// LPC +//
+Device (LPC0) +{
- Name(_HID, "HISI0191") // HiSi LPC
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
- })
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc new file mode 100644 index 0000000..2908b24 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include <IndustryStandard/Acpi.h>
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
- sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
- 0xA152, // UINT32 HardwareSignature
- 0, // UINT32 FirmwareWakingVector
- 0, // UINT32 GlobalLock
- 0, // UINT32 Flags
- 0, // UINT64 XFirmwareWakingVector
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]
EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
- 0, // UINT32 OspmFlags "Platform firmware must
// initialize this field to zero."
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]
EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc new file mode 100644 index 0000000..152410b --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc @@ -0,0 +1,91 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include "Hi1616Platform.h"
+#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h>
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
- ARM_ACPI_HEADER (
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
- ),
- 0, // UINT32 FirmwareCtrl
- 0, // UINT32 Dsdt
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
- EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
- 0, // UINT16 SciInt
- 0, // UINT32 SmiCmd
- 0, // UINT8 AcpiEnable
- 0, // UINT8 AcpiDisable
- 0, // UINT8 S4BiosReq
- 0, // UINT8 PstateCnt
- 0, // UINT32 Pm1aEvtBlk
- 0, // UINT32 Pm1bEvtBlk
- 0, // UINT32 Pm1aCntBlk
- 0, // UINT32 Pm1bCntBlk
- 0, // UINT32 Pm2CntBlk
- 0, // UINT32 PmTmrBlk
- 0, // UINT32 Gpe0Blk
- 0, // UINT32 Gpe1Blk
- 0, // UINT8 Pm1EvtLen
- 0, // UINT8 Pm1CntLen
- 0, // UINT8 Pm2CntLen
- 0, // UINT8 PmTmrLen
- 0, // UINT8 Gpe0BlkLen
- 0, // UINT8 Gpe1BlkLen
- 0, // UINT8 Gpe1Base
- 0, // UINT8 CstCnt
- 0, // UINT16 PLvl2Lat
- 0, // UINT16 PLvl3Lat
- 0, // UINT16 FlushSize
- 0, // UINT16 FlushStride
- 0, // UINT8 DutyOffset
- 0, // UINT8 DutyWidth
- 0, // UINT8 DayAlrm
- 0, // UINT8 MonAlrm
- 0, // UINT8 Century
- 0, // UINT16 IaPcBootArch
- 0, // UINT8 Reserved1
- EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
- 0, // UINT8 ResetValue
- EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
- 0, // UINT64 XFirmwareCtrl
- 0, // UINT64 XDsdt
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
- NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..b472828 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc @@ -0,0 +1,95 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include "Hi1616Platform.h"
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
- #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+#pragma pack (1)
+typedef struct {
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+#pragma pack ()
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
- {
- ARM_ACPI_HEADER(
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES,
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
- ),
- SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
- 0, // UINT32 Reserved
- FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
- FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
- 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+#ifdef notyet
- PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
- sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
- },
- {
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
0, 0, 0, 0),
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
0, 0, 0, 0)
- }
+#else /* !notyet */
- 0, 0
- }
+#endif
- };
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h new file mode 100644 index 0000000..808219a --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#ifndef _HI1610_PLATFORM_H_ +#define _HI1610_PLATFORM_H_
+// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
- Signature, /* UINT32 Signature */ \
- sizeof (Type), /* UINT32 Length */ \
- Revision, /* UINT8 Revision */ \
- 0, /* UINT8 Checksum */ \
- { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
- EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
- EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
- EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
- EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
- }
+#define HI1616_WATCHDOG_COUNT 2
+#endif diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc new file mode 100644 index 0000000..b83c221 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc @@ -0,0 +1,282 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include "Hi1616Platform.h"
+// Differs from Juno, we have another affinity level beyond cluster and core +// 0x20000 is only for socket 0 +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId) << 8) | (CoreId))
+// +// Multiple APIC Description Table +// +#pragma pack (1)
+typedef struct {
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[64];
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[8];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+#pragma pack ()
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
- {
- ARM_ACPI_HEADER (
EFI_ACPI_1_0_APIC_SIGNATURE,
EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
- ),
- //
- // MADT specific fields
- //
- 0, // LocalApicAddress
- 0, // Flags
- },
- {
- // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
- // GsivId, GicRBase, Mpidr)
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
- // ACPI v5.1).
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */),
- },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4),
- {
- EFI_ACPI_6_0_GIC_ITS_INIT(0,0x4C000000), //peri a
- EFI_ACPI_6_0_GIC_ITS_INIT(1,0x6C000000), //peri b
- EFI_ACPI_6_0_GIC_ITS_INIT(2,0xC6000000), //dsa a
- EFI_ACPI_6_0_GIC_ITS_INIT(3,0x8C6000000), //dsa b
- EFI_ACPI_6_0_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a
- EFI_ACPI_6_0_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b
- EFI_ACPI_6_0_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a
- EFI_ACPI_6_0_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b
- }
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +//
+VOID* CONST ReferenceAcpiTable = &Madt;
1.9.1
On Thu, Nov 10, 2016 at 09:52:18PM +0800, Heyi Guo wrote:
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 58 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 651 +++++++++++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 127 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 64 + Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 129 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 280 +++++ Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 36 + .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 1236 ++++++++++++++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 58 + .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 438 +++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 584 +++++++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 247 ++++ .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl | 135 +++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 31 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl | 25 + Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 67 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 91 ++ Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 95 ++ .../Hi1616/D05AcpiTables/Hi1616Platform.h | 48 + .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 282 +++++ 20 files changed, 4682 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf new file mode 100644 index 0000000..68379c5 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf @@ -0,0 +1,58 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = Hi1616AcpiTables
- FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
+[Sources]
- Dsdt/DsdtHi1616.asl
- Facs.aslc
- Fadt.aslc
- Gtdt.aslc
- MadtHi1616.aslc
- D05Mcfg.aslc
- D05Iort.asl
- D05Slit.aslc
- D05Srat.aslc
+[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl new file mode 100644 index 0000000..61a3c33 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -0,0 +1,651 @@ +/*
- Intel ACPI Component Architecture
- iASL Compiler/Disassembler version 20151124-64
- Copyright (c) 2000 - 2015 Intel Corporation
- Template for [IORT] ACPI Table (static data table)
- Format: [ByteLength] FieldName : HexFieldValue
- */
+[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 000002e4 +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP07 " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124
+[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00
+/* ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 +//4c +/* ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000001 +//64 +/* ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000002 +//7c +/* ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000003 +//94 +/*Sec CPU ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000004 +//ac +/* SEC CPU ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000005 +//c4 +/* SEC CPU ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000006 +//dc +/* SEC CPU ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000
+[0004] ItsCount : 00000001 +[0004] Identifiers : 00000007
+/* mbi-gen peri b, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI0" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 000120c7 //device id +[0004] Output Reference : 0000004C +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI1" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI9" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen dsa a - usb named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI5" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI2" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI3" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI4" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 alg a, i2c 0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI6" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B0E //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/* mbi-gen1 alg a, i2c 2 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI7" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B10 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
+/*1P NA PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002
+[0004] Input base : 00008000 +[0004] ID Count : 00000800 +[0004] Output Base : 00008000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000004
+[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000005
+[0004] Input base : 00000000 +[0004] ID Count : 00000800 +[0004] Output Base : 00000000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000006
+[0004] Input base : 0000c000 +[0004] ID Count : 00000800 +[0004] Output Base : 0000c000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 1P NB PCIe3 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000007
+[0004] Input base : 00009000 +[0004] ID Count : 00000800 +[0004] Output Base : 00009000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 2P NA PCIe2*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000a
+[0004] Input base : 00001000 +[0004] ID Count : 00001000 +[0004] Output Base : 00001000 +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* 2P NB PCIe0*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000c
+[0004] Input base : 00002000 +[0004] ID Count : 00001000 +[0004] Output Base : 00002000 +[0004] Output Reference : 000000dc +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
- /* 2P NB PCIe1*/
+[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020
+[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000d
+[0004] Input base : 00003000 +[0004] ID Count : 00001000 +[0004] Output Base : 00003000 +[0004] Output Reference : 000000dc +[0004] Flags (decoded below) : 00000000
Single Mapping : 0
+/* mbi-gen1 P1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032
+[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
+[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00
Coherency : 0
Device Attribute : 0
+[0001] Memory Size Limit : 00 +[0016] Device Name : "_SB_.MBI8" +[0004] Padding : 00 00 00 00
+[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00044800 //device id +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000001
Single Mapping : 1
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc new file mode 100644 index 0000000..9255037 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -0,0 +1,127 @@ +/*
- Copyright (c) 2016 Hisilicon Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- */
+#include <IndustryStandard/Acpi.h> +#include "Hi1616Platform.h"
+#define ACPI_5_0_MCFG_VERSION 0x1
+#pragma pack(1) +typedef struct +{
- UINT64 ullBaseAddress;
- UINT16 usSegGroupNum;
- UINT8 ucStartBusNum;
- UINT8 ucEndBusNum;
- UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+typedef struct +{
- EFI_ACPI_DESCRIPTION_HEADER Header;
- UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+typedef struct +{
- EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
- EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[8];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; +#pragma pack()
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +{
- {
{
EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
ACPI_5_0_MCFG_VERSION,
0x00, // Checksum will be updated at runtime
{EFI_ACPI_ARM_OEM_ID},
EFI_ACPI_ARM_OEM_TABLE_ID,
EFI_ACPI_ARM_OEM_REVISION,
EFI_ACPI_ARM_CREATOR_ID,
EFI_ACPI_ARM_CREATOR_REVISION
},
0x0000000000000000, //Reserved
- },
- {
- //1p NA PCIe2
- {
0xa0000000, //Base Address
0x2, //Segment Group Number
0x80, //Start Bus Number
0x87, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe0
- {
0x8a0000000, //Base Address
0x4, //Segment Group Number
0x88, //Start Bus Number
0x8f, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe1
- {
0x8b0000000, //Base Address
0x5, //Segment Group Number
0x0, //Start Bus Number
0x7, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe2
- {
0x8a0000000, //Base Address
0x6, //Segment Group Number
0xc0, //Start Bus Number
0xc7, //End Bus Number
0x00000000, //Reserved
- },
- //1p NB PCIe3
- {
0x8b0000000, //Base Address
0x7, //Segment Group Number
0x90, //Start Bus Number
0x97, //End Bus Number
0x00000000, //Reserved
- },
- //2P NA PCIe2
- {
0x64000000000, //Base Address
0xa, //Segment Group Number
0x10, //Start Bus Number
0x1f, //End Bus Number
0x00000000, //Reserved
- },
- //2P NB PCIe0
- {
0x74000000000, //Base Address
0xc, //Segment Group Number
0x20, //Start Bus Number
0x2f, //End Bus Number
0x00000000, //Reserved
- },
- //2P NB PCIe1
- {
0x78000000000, //Base Address
0xd, //Segment Group Number
0x30, //Start Bus Number
0x3f, //End Bus Number
0x00000000, //Reserved
- },
- }
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc new file mode 100644 index 0000000..2276240 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc @@ -0,0 +1,64 @@ +/*
- Copyright (c) 2013 Linaro Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org
+*/
+#include <IndustryStandard/Acpi.h> +#include "Hi1616Platform.h"
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004
+#pragma pack(1) +typedef struct {
- UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+typedef struct {
- EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header;
- EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +#pragma pack()
+// +// System Locality Information Table +// Please modify all values in Slit.h only. +// +EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
- {
- {
EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE),
EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
0x00, // Checksum will be updated at runtime
{EFI_ACPI_ARM_OEM_ID},
EFI_ACPI_ARM_OEM_TABLE_ID,
EFI_ACPI_ARM_OEM_REVISION,
EFI_ACPI_ARM_CREATOR_ID,
EFI_ACPI_ARM_CREATOR_REVISION,
- },
- //
- // Beginning of SLIT specific fields
- //
- EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
- },
- {
- {{0x0A, 0x10, 0x20, 0x21}}, //Locality 0
- {{0x10, 0x0A, 0x19, 0x20}}, //Locality 1
- {{0x20, 0x19, 0x0A, 0x10}}, //Locality 2
- {{0x21, 0x20, 0x10, 0x0A}}, //Locality 3
- },
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Slit; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc new file mode 100644 index 0000000..f7ea15e --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc @@ -0,0 +1,129 @@ +/*
- Copyright (c) 2013 Linaro Limited
- All rights reserved. This program and the accompanying materials
- are made available under the terms of the BSD License which accompanies
- this distribution, and is available at
- Contributors:
Yi Li - yi.li@linaro.org
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> +#include "Hi1616Platform.h"
+// +// Static Resource Affinity Table definition +// +EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
- {
- {EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE),
- EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
- 0x00, // Checksum will be updated at runtime
- {EFI_ACPI_ARM_OEM_ID},
- EFI_ACPI_ARM_OEM_TABLE_ID,
- EFI_ACPI_ARM_OEM_REVISION,
- EFI_ACPI_ARM_CREATOR_ID,
- EFI_ACPI_ARM_CREATOR_REVISION},
- /*Reserved*/
- 0x00000001, // Reserved to be 1 for backward compatibility
- EFI_ACPI_RESERVED_QWORD
- },
- //
- //
- // Memory Affinity
- //
- {
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
- },
- {
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62
- EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63
- },
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Srat; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..5ecbf50 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,280 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- //
- // A57x16 Processor declaration
- //
- Device(CPU0) {
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- }
- Device(CPU1) {
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- }
- Device(CPU2) {
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- }
- Device(CPU3) {
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- }
- Device(CPU4) {
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- }
- Device(CPU5) {
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- }
- Device(CPU6) {
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- }
- Device(CPU7) {
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- }
- Device(CPU8) {
- Name(_HID, "ACPI0007")
- Name(_UID, 8)
- }
- Device(CPU9) {
- Name(_HID, "ACPI0007")
- Name(_UID, 9)
- }
- Device(CP10) {
- Name(_HID, "ACPI0007")
- Name(_UID, 10)
- }
- Device(CP11) {
- Name(_HID, "ACPI0007")
- Name(_UID, 11)
- }
- Device(CP12) {
- Name(_HID, "ACPI0007")
- Name(_UID, 12)
- }
- Device(CP13) {
- Name(_HID, "ACPI0007")
- Name(_UID, 13)
- }
- Device(CP14) {
- Name(_HID, "ACPI0007")
- Name(_UID, 14)
- }
- Device(CP15) {
- Name(_HID, "ACPI0007")
- Name(_UID, 15)
- }
- Device(CP16) {
- Name(_HID, "ACPI0007")
- Name(_UID, 16)
- }
- Device(CP17) {
- Name(_HID, "ACPI0007")
- Name(_UID, 17)
- }
- Device(CP18) {
- Name(_HID, "ACPI0007")
- Name(_UID, 18)
- }
- Device(CP19) {
- Name(_HID, "ACPI0007")
- Name(_UID, 19)
- }
- Device(CP20) {
- Name(_HID, "ACPI0007")
- Name(_UID, 20)
- }
- Device(CP21) {
- Name(_HID, "ACPI0007")
- Name(_UID, 21)
- }
- Device(CP22) {
- Name(_HID, "ACPI0007")
- Name(_UID, 22)
- }
- Device(CP23) {
- Name(_HID, "ACPI0007")
- Name(_UID, 23)
- }
- Device(CP24) {
- Name(_HID, "ACPI0007")
- Name(_UID, 24)
- }
- Device(CP25) {
- Name(_HID, "ACPI0007")
- Name(_UID, 25)
- }
- Device(CP26) {
- Name(_HID, "ACPI0007")
- Name(_UID, 26)
- }
- Device(CP27) {
- Name(_HID, "ACPI0007")
- Name(_UID, 27)
- }
- Device(CP28) {
- Name(_HID, "ACPI0007")
- Name(_UID, 28)
- }
- Device(CP29) {
- Name(_HID, "ACPI0007")
- Name(_UID, 29)
- }
- Device(CP30) {
- Name(_HID, "ACPI0007")
- Name(_UID, 30)
- }
- Device(CP31) {
- Name(_HID, "ACPI0007")
- Name(_UID, 31)
- }
- Device(CP32) {
- Name(_HID, "ACPI0007")
- Name(_UID, 32)
- }
- Device(CP33) {
- Name(_HID, "ACPI0007")
- Name(_UID, 33)
- }
- Device(CP34) {
- Name(_HID, "ACPI0007")
- Name(_UID, 34)
- }
- Device(CP35) {
- Name(_HID, "ACPI0007")
- Name(_UID, 35)
- }
- Device(CP36) {
- Name(_HID, "ACPI0007")
- Name(_UID, 36)
- }
- Device(CP37) {
- Name(_HID, "ACPI0007")
- Name(_UID, 37)
- }
- Device(CP38) {
- Name(_HID, "ACPI0007")
- Name(_UID, 38)
- }
- Device(CP39) {
- Name(_HID, "ACPI0007")
- Name(_UID, 39)
- }
- Device(CP40) {
- Name(_HID, "ACPI0007")
- Name(_UID, 40)
- }
- Device(CP41) {
- Name(_HID, "ACPI0007")
- Name(_UID, 41)
- }
- Device(CP42) {
- Name(_HID, "ACPI0007")
- Name(_UID, 42)
- }
- Device(CP43) {
- Name(_HID, "ACPI0007")
- Name(_UID, 43)
- }
- Device(CP44) {
- Name(_HID, "ACPI0007")
- Name(_UID, 44)
- }
- Device(CP45) {
- Name(_HID, "ACPI0007")
- Name(_UID, 45)
- }
- Device(CP46) {
- Name(_HID, "ACPI0007")
- Name(_UID, 46)
- }
- Device(CP47) {
- Name(_HID, "ACPI0007")
- Name(_UID, 47)
- }
- Device(CP48) {
- Name(_HID, "ACPI0007")
- Name(_UID, 48)
- }
- Device(CP49) {
- Name(_HID, "ACPI0007")
- Name(_UID, 49)
- }
- Device(CP50) {
- Name(_HID, "ACPI0007")
- Name(_UID, 50)
- }
- Device(CP51) {
- Name(_HID, "ACPI0007")
- Name(_UID, 51)
- }
- Device(CP52) {
- Name(_HID, "ACPI0007")
- Name(_UID, 52)
- }
- Device(CP53) {
- Name(_HID, "ACPI0007")
- Name(_UID, 53)
- }
- Device(CP54) {
- Name(_HID, "ACPI0007")
- Name(_UID, 54)
- }
- Device(CP55) {
- Name(_HID, "ACPI0007")
- Name(_UID, 55)
- }
- Device(CP56) {
- Name(_HID, "ACPI0007")
- Name(_UID, 56)
- }
- Device(CP57) {
- Name(_HID, "ACPI0007")
- Name(_UID, 57)
- }
- Device(CP58) {
- Name(_HID, "ACPI0007")
- Name(_UID, 58)
- }
- Device(CP59) {
- Name(_HID, "ACPI0007")
- Name(_UID, 59)
- }
- Device(CP60) {
- Name(_HID, "ACPI0007")
- Name(_UID, 60)
- }
- Device(CP61) {
- Name(_HID, "ACPI0007")
- Name(_UID, 61)
- }
- Device(CP62) {
- Name(_HID, "ACPI0007")
- Name(_UID, 62)
- }
- Device(CP63) {
- Name(_HID, "ACPI0007")
- Name(_UID, 63)
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000..b7c4905 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl @@ -0,0 +1,36 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- Device(COM0) {
- Name(_HID, "ARMH0011")
- Name(_CID, "PL011")
- Name(_UID, Zero)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x602B0000, 0x1000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 807 }
- })
- Name(_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package() {
Package() {"interrupt-parent",Package() {\_SB.MBI0}},
Don't think this is correct as the interrupt parent is already given as part of the _CRS. The discussion around _DSD is that _DSD values should not repeat or replicate parameters already 1st class in ACPI. This may mean a driver update is required.
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl new file mode 100644 index 0000000..e855e5d --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -0,0 +1,1236 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- Device (MDIO)
- {
- OperationRegion(CLKR, SystemMemory, 0x60000550, 8)
- Field(CLKR, DWordAcc, NoLock, Preserve) {
CLKE, 1, // clock enable
, 31,
CLKD, 1, // clode disable
, 31,
- }
- OperationRegion(RSTR, SystemMemory, 0x60000c40, 8)
- Field(RSTR, DWordAcc, NoLock, Preserve) {
RSTE, 1, // reset
, 31,
RSTD, 1, // de-reset
, 31,
- }
- Name(_HID, "HISI0141")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)
- })
- Method(_RST, 0, Serialized) {
Store (0x1, RSTE)
Sleep (10)
Store (0x1, CLKD)
Sleep (10)
Store (0x1, RSTD)
Sleep (10)
Store (0x1, CLKE)
Sleep (10)
- }
- }
- Device (DSF0)
- {
- OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
H3ST, 1,
, 31, //RESERVED
- }
- OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
- Field(H4SR, DWordAcc, NoLock, Preserve) {
H4ST, 1,
, 31, //RESERVED
- }
- // DSAF RESET
- OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
- Field(DRER, DWordAcc, NoLock, Preserve) {
DRTE, 1,
, 31, //RESERVED
DRTD, 1,
, 31, //RESERVED
- }
- // NT RESET
- OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
- Field(NRER, DWordAcc, NoLock, Preserve) {
NRTE, 1,
, 31, //RESERVED
NRTD, 1,
, 31, //RESERVED
- }
- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
XRTE, 31,
, 1, //RESERVED
XRTD, 31,
, 1, //RESERVED
- }
- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
GR0E, 30,
, 2, //RESERVED
GR0D, 30,
, 2, //RESERVED
GR1E, 18,
, 14, //RESERVED
GR1D, 18,
, 14, //RESERVED
- }
- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
PRTE, 10,
, 22, //RESERVED
PRTD, 10,
, 22, //RESERVED
- }
- // RCB PPE COM RESET
- OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
- Field(RRTR, DWordAcc, NoLock, Preserve) {
RRTE, 1,
, 31, //RESERVED
RRTD, 1,
, 31, //RESERVED
- }
- // DSAF Channel RESET
- OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8)
- Field(DCRR, DWordAcc, NoLock, Preserve) {
DCRE, 1,
, 31, //RESERVED
DCRD, 1,
, 31, //RESERVED
- }
- // RoCE RESET
- OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8)
- Field(RKRR, DWordAcc, NoLock, Preserve) {
RKRE, 1,
, 31, //RESERVED
RKRD, 1,
, 31, //RESERVED
- }
- // RoCE Clock enable/disable
- OperationRegion(RKCR, SystemMemory, 0xC0000328, 8)
- Field(RKCR, DWordAcc, NoLock, Preserve) {
RCLE, 1,
, 31, //RESERVED
RCLD, 1,
, 31, //RESERVED
- }
- // Hilink access sel cfg reg
- OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
- Field(HSER, DWordAcc, NoLock, Preserve) {
HSEL, 2, // hilink_access_sel & hilink_access_wr_pul
, 30, // RESERVED
- }
- // Serdes
- OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
- Field(H4LR, DWordAcc, NoLock, Preserve) {
H4L0, 16, // port0
, 16, //RESERVED
Offset (0x400),
H4L1, 16, // port1
, 16, //RESERVED
Offset (0x800),
H4L2, 16, // port2
, 16, //RESERVED
Offset (0xc00),
H4L3, 16, // port3
, 16, //RESERVED
- }
- OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
H3L2, 16, // port4
, 16, //RESERVED
Offset (0x400),
H3L3, 16, // port5
, 16, //RESERVED
- }
- Name (_HID, "HISI00B2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"mode", "6port-16rss"},
Package () {"buf-size", 4096},
Package () {"desc-num", 1024},
Package () {"interrupt-parent", Package() {\_SB.MBI1}},
And again.
}
- })
- //reset XGE port
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XRST, 2, Serialized) {
ShiftLeft (0x2082082, Arg0, Local0)
Or (Local0, 0x1, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset XGE core
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XCRT, 2, Serialized) {
ShiftLeft (0x2080, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset GE port
- //Arg0 : GE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(GRST, 2, Serialized) {
If (LLessEqual (Arg0, 5)) {
//Service port
ShiftLeft (0x2082082, Arg0, Local0)
ShiftLeft (0x1, Arg0, Local1)
If (LEqual (Arg1, 0)) {
Store(Local1, GR1E)
Store(Local0, GR0E)
} Else {
Store(Local0, GR0D)
Store(Local1, GR1D)
}
}
- }
- //reset PPE port
- //Arg0 : PPE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(PRST, 2, Serialized) {
ShiftLeft (0x1, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, PRTE)
} Else {
Store(Local0, PRTD)
}
- }
- //reset DSAF channels
- //Arg0 : mask
- //Arg1 : 0 reset, 1 de-reset
- Method(DCRT, 2, Serialized) {
If (LEqual (Arg1, 0)) {
Store(Arg0, DCRE)
} Else {
Store(Arg0, DCRD)
}
- }
- //reset RoCE
- //Arg0 : 0 reset, 1 de-reset
- Method(RRST, 1, Serialized) {
If (LEqual (Arg0, 0)) {
Store(0x1, RKRE)
} Else {
Store(0x1, RCLD)
Store(0x1, RKRD)
sleep(20)
Store(0x1, RCLE)
}
- }
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 2, Serialized) {
ShiftLeft (Arg1, 10, Local0)
Switch (ToInteger(Arg0))
{
case (0x0){
Store (0, HSEL)
Store (H4L0, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L0)
}
case (0x1){
Store (0, HSEL)
Store (H4L1, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L1)
}
case (0x2){
Store (0, HSEL)
Store (H4L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L2)
}
case (0x3){
Store (0, HSEL)
Store (H4L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L3)
}
case (0x4){
Store (3, HSEL)
Store (H3L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L2)
}
case (0x5){
Store (3, HSEL)
Store (H3L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L3)
}
}
- }
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:ge; 6:dchan; 7:RoCE)
- //Arg1 : port
- //Arg2 : 0 disable, 1 enable
- Method(DRST, 3, Serialized)
- {
Switch (ToInteger(Arg0))
{
//DSAF reset
case (0x1)
{
Store (Arg2, Local0)
If (LEqual (Local0, 0))
{
Store (0x1, DRTE)
Store (0x1, NRTE)
Sleep (10)
Store (0x1, RRTE)
}
Else
{
Store (0x1, DRTD)
Store (0x1, NRTD)
Sleep (10)
Store (0x1, RRTD)
}
}
//Reset PPE port
case (0x2)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
PRST (Local0, Local1)
}
//Reset XGE core
case (0x3)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XCRT (Local0, Local1)
}
//Reset XGE port
case (0x4)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XRST (Local0, Local1)
}
//Reset GE port
case (0x5)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
GRST (Local0, Local1)
}
//Reset DSAF Channels
case (0x6)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
DCRT (Local0, Local1)
}
//Reset RoCE
case (0x7)
{
// Discarding Arg1 as it is always 0
Store (Arg2, Local0)
RRST (Local0)
}
}
- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge; 6:dchan; 7:RoCE)
- // Arg3[1] : port index in dsaf
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : port
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : port
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : port index in dsaf
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : port index in dsaf
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
{
If (LEqual (Arg1, 0x00))
{
Switch (ToInteger(Arg2))
{
case (0x0)
{
Return (Buffer () {0x3F})
}
//Reset Sequence
case (0x1)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
Store (DeRefOf (Index (Arg3, 2)), Local2)
DRST (Local0, Local1, Local2)
}
//Set Serdes Loopback
case (0x2)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
SRLP (Local0, Local1)
}
//LED op set
case (0x3)
{
}
// Get port type (GE or XGE)
case (0x4)
{
Store (0, Local1)
Store (DeRefOf (Index (Arg3, 0)), Local0)
If (LLessEqual (Local0, 3))
{
// mac0: Hilink4 Lane0
// mac1: Hilink4 Lane1
// mac2: Hilink4 Lane2
// mac3: Hilink4 Lane3
Store (H4ST, Local1)
}
ElseIf (LLessEqual (Local0, 5))
{
// mac4: Hilink3 Lane2
// mac5: Hilink3 Lane3
Store (H3ST, Local1)
}
Return (Local1)
}
//Get sfp status
case (0x5)
{
}
}
}
}
Return (Buffer() {0x00})
- }
- Device (PRT0)
- {
Name (_ADR, 0x0)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 0},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT1)
- {
Name (_ADR, 0x1)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 1},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT2)
- {
Name (_ADR, 0x2)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 2},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT3)
- {
Name (_ADR, 0x3)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 3},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT4)
- {
Name (_ADR, 0x4)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 4},
Package () {"phy-mode", "sgmii"},
Package () {"phy-addr", 0},
Package () {"mdio-node", Package (){\_SB.MDIO}},
Package () {"media-type", "copper"},
}
})
- }
- Device (PRT5)
- {
Name (_ADR, 0x5)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 5},
Package () {"phy-mode", "sgmii"},
Package () {"phy-addr", 1},
Package () {"mdio-node", Package (){\_SB.MDIO}},
Package () {"media-type", "copper"},
}
})
- }
- }
- Device (ETH4) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 4},
}
- })
- }
- Device (ETH5) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 5},
}
- })
- }
- Device (ETH0) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 0},
}
- })
- }
- Device (ETH1) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 1},
}
- })
- }
- Device (ETH2) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 2},
}
- })
- }
- Device (ETH3) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF0}},
Package () {"port-idx-in-ae", 3},
}
- })
- }
- Device (ROCE) {
- Name(_HID, "HISI00D1")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},
Package () {"dsaf-handle", Package (){\_SB.DSF0}},
Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes
Package () {"interrupt-parent", Package() {\_SB.MBI9}},
Package () {"interrupt-names", Package() {"hns-roce-comp-0",
"hns-roce-comp-1",
"hns-roce-comp-2",
"hns-roce-comp-3",
"hns-roce-comp-4",
"hns-roce-comp-5",
"hns-roce-comp-6",
"hns-roce-comp-7",
"hns-roce-comp-8",
"hns-roce-comp-9",
"hns-roce-comp-10",
"hns-roce-comp-11",
"hns-roce-comp-12",
"hns-roce-comp-13",
"hns-roce-comp-14",
"hns-roce-comp-15",
"hns-roce-comp-16",
"hns-roce-comp-17",
"hns-roce-comp-18",
"hns-roce-comp-19",
"hns-roce-comp-20",
"hns-roce-comp-21",
"hns-roce-comp-22",
"hns-roce-comp-23",
"hns-roce-comp-24",
"hns-roce-comp-25",
"hns-roce-comp-26",
"hns-roce-comp-27",
"hns-roce-comp-28",
"hns-roce-comp-29",
"hns-roce-comp-30",
"hns-roce-comp-31",
"hns-roce-async",
"hns-roce-common"}},
and again, also interupt names should not be required!
}
- })
- Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI9")
{
722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
}
- })
- }
- /* for p1 */
- Device (DSF1)
- {
- OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4)
- Field(H3SR, DWordAcc, NoLock, Preserve) {
H3ST, 1,
, 31, //RESERVED
- }
- OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4)
- Field(H4SR, DWordAcc, NoLock, Preserve) {
H4ST, 1,
, 31, //RESERVED
- }
- // DSAF RESET
- OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8)
- Field(DRER, DWordAcc, NoLock, Preserve) {
DRTE, 1,
, 31, //RESERVED
DRTD, 1,
, 31, //RESERVED
- }
- // NT RESET
- OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8)
- Field(NRER, DWordAcc, NoLock, Preserve) {
NRTE, 1,
, 31, //RESERVED
NRTD, 1,
, 31, //RESERVED
- }
- // XGE RESET
- OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8)
- Field(XRER, DWordAcc, NoLock, Preserve) {
XRTE, 31,
, 1, //RESERVED
XRTD, 31,
, 1, //RESERVED
- }
- // GE RESET
- OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16)
- Field(GRTR, DWordAcc, NoLock, Preserve) {
GR0E, 30,
, 2, //RESERVED
GR0D, 30,
, 2, //RESERVED
GR1E, 18,
, 14, //RESERVED
GR1D, 18,
, 14, //RESERVED
- }
- // PPE RESET
- OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8)
- Field(PRTR, DWordAcc, NoLock, Preserve) {
PRTE, 10,
, 22, //RESERVED
PRTD, 10,
, 22, //RESERVED
- }
- // RCB PPE COM RESET
- OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8)
- Field(RRTR, DWordAcc, NoLock, Preserve) {
RRTE, 1,
, 31, //RESERVED
RRTD, 1,
, 31, //RESERVED
- }
- // RCB_2X COM RESET
- OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8)
- Field(RBTR, DWordAcc, NoLock, Preserve) {
RBTE, 1,
, 31, //RESERVED
RBTD, 1,
, 31, //RESERVED
- }
- // Hilink access sel cfg reg
- OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4)
- Field(HSER, DWordAcc, NoLock, Preserve) {
HSEL, 2, // hilink_access_sel & hilink_access_wr_pul
, 30, // RESERVED
- }
- // Serdes
- OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000)
- Field(H4LR, DWordAcc, NoLock, Preserve) {
H4L0, 16, // port0
, 16, //RESERVED
Offset (0x400),
H4L1, 16, // port1
, 16, //RESERVED
Offset (0x800),
H4L2, 16, // port2
, 16, //RESERVED
Offset (0xc00),
H4L3, 16, // port3
, 16, //RESERVED
- }
- OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800)
- Field(H3LR, DWordAcc, NoLock, Preserve) {
H3L2, 16, // port4
, 16, //RESERVED
Offset (0x400),
H3L3, 16, // port5
, 16, //RESERVED
- }
- Name (_HID, "HISI00B2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x400c5000000, // Min Base Address
0x400c588ffff, // Max Base Address
0x0, // Translate
0x890000 // Length
)
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x400c7000000, // Min Base Address
0x400c705ffff, // Max Base Address
0x0, // Translate
0x60000 // Length
)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"mode", "6port-16rss"},
Package () {"buf-size", 4096},
Package () {"desc-num", 1024},
Package () {"interrupt-parent", Package() {\_SB.MBI8}},
and again..
Ill stop here as the patch generally looks ok apart from the interupt parent issue. If this is fixed then I am happy to add my reviewed by.
Graeme
}
- })
- //reset XGE port
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XRST, 2, Serialized) {
ShiftLeft (0x2082082, Arg0, Local0)
Or (Local0, 0x1, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset XGE core
- //Arg0 : XGE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(XCRT, 2, Serialized) {
ShiftLeft (0x2080, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, XRTE)
} Else {
Store(Local0, XRTD)
}
- }
- //reset GE port
- //Arg0 : GE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(GRST, 2, Serialized) {
If (LLessEqual (Arg0, 5)) {
//Service port
ShiftLeft (0x2082082, Arg0, Local0)
ShiftLeft (0x1, Arg0, Local1)
If (LEqual (Arg1, 0)) {
Store(Local1, GR1E)
Store(Local0, GR0E)
} Else {
Store(Local0, GR0D)
Store(Local1, GR1D)
}
}
- }
- //reset PPE port
- //Arg0 : PPE port index in dsaf
- //Arg1 : 0 reset, 1 cancle reset
- Method(PRST, 2, Serialized) {
ShiftLeft (0x1, Arg0, Local0)
If (LEqual (Arg1, 0)) {
Store(Local0, PRTE)
} Else {
Store(Local0, PRTD)
}
- }
- // Set Serdes Loopback
- //Arg0 : port
- //Arg1 : 0 disable, 1 enable
- Method(SRLP, 2, Serialized) {
ShiftLeft (Arg1, 10, Local0)
Switch (ToInteger(Arg0))
{
case (0x0){
Store (0, HSEL)
Store (H4L0, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L0)
}
case (0x1){
Store (0, HSEL)
Store (H4L1, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L1)
}
case (0x2){
Store (0, HSEL)
Store (H4L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L2)
}
case (0x3){
Store (0, HSEL)
Store (H4L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H4L3)
}
case (0x4){
Store (3, HSEL)
Store (H3L2, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L2)
}
case (0x5){
Store (3, HSEL)
Store (H3L3, Local1)
And (Local1, 0xfffffbff, Local1)
Or (Local0, Local1, Local0)
Store (Local0, H3L3)
}
}
- }
- //Reset
- //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
- //Arg1 : port
- //Arg2 : 0 disable, 1 enable
- Method(DRST, 3, Serialized)
- {
Switch (ToInteger(Arg0))
{
//DSAF reset
case (0x1)
{
Store (Arg2, Local0)
If (LEqual (Local0, 0))
{
Store (0x1, DRTE)
Store (0x1, NRTE)
Sleep (10)
Store (0x1, RRTE)
Store (0x1, RBTE)
}
Else
{
Store (0x1, DRTD)
Store (0x1, NRTD)
Sleep (10)
Store (0x1, RRTD)
Store (0x1, RBTD)
}
}
//Reset PPE port
case (0x2)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
PRST (Local0, Local1)
}
//Reset XGE core
case (0x3)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XCRT (Local0, Local1)
}
//Reset XGE port
case (0x4)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
XRST (Local0, Local1)
}
//Reset GE port
case (0x5)
{
Store (Arg1, Local0)
Store (Arg2, Local1)
GRST (Local0, Local1)
}
}
- }
- // _DSM Device Specific Method
- //
- // Arg0: UUID Unique function identifier
- // Arg1: Integer Revision Level
- // Arg2: Integer Function Index
- // 0 : Return Supported Functions bit mask
- // 1 : Reset Sequence
- // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
- // Arg3[1] : port index in dsaf
- // Arg3[2] : 0 reset, 1 cancle reset
- // 2 : Set Serdes Loopback
- // Arg3[0] : port
- // Arg3[1] : 0 disable, 1 enable
- // 3 : LED op set
- // Arg3[0] : op type
- // Arg3[1] : port
- // Arg3[2] : para
- // 4 : Get port type (GE or XGE)
- // Arg3[0] : port index in dsaf
- // Return : 0 GE, 1 XGE
- // 5 : Get sfp status
- // Arg3[0] : port index in dsaf
- // Return : 0 no sfp, 1 have sfp
- // Arg3: Package Parameters
- Method (_DSM, 4, Serialized)
- {
If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
{
If (LEqual (Arg1, 0x00))
{
Switch (ToInteger(Arg2))
{
case (0x0)
{
Return (Buffer () {0x3F})
}
//Reset Sequence
case (0x1)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
Store (DeRefOf (Index (Arg3, 2)), Local2)
DRST (Local0, Local1, Local2)
}
//Set Serdes Loopback
case (0x2)
{
Store (DeRefOf (Index (Arg3, 0)), Local0)
Store (DeRefOf (Index (Arg3, 1)), Local1)
SRLP (Local0, Local1)
}
//LED op set
case (0x3)
{
}
// Get port type (GE or XGE)
case (0x4)
{
Store (0, Local1)
Store (DeRefOf (Index (Arg3, 0)), Local0)
If (LLessEqual (Local0, 3))
{
// mac0: Hilink4 Lane0
// mac1: Hilink4 Lane1
// mac2: Hilink4 Lane2
// mac3: Hilink4 Lane3
Store (H4ST, Local1)
}
ElseIf (LLessEqual (Local0, 5))
{
// mac4: Hilink3 Lane2
// mac5: Hilink3 Lane3
Store (H3ST, Local1)
}
Return (Local1)
}
//Get sfp status
case (0x5)
{
}
}
}
}
Return (Buffer() {0x00})
- }
- Device (PRT6)
- {
Name (_ADR, 0x6)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 0},
Package () {"media-type", "fiber"},
}
})
- }
- Device (PRT7)
- {
Name (_ADR, 0x7)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"reg", 1},
Package () {"media-type", "fiber"},
}
})
- }
- }
- Device (ETH6) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF1}},
Package () {"port-idx-in-ae", 0},
}
- })
- }
- Device (ETH7) {
- Name(_HID, "HISI00C2")
- Name (_CCA, 1) // Cache-coherent controller
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
Package () {"ae-handle", Package (){\_SB.DSF1}},
Package () {"port-idx-in-ae", 1},
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl new file mode 100644 index 0000000..e2d3ed1 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -0,0 +1,58 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+Scope(_SB) +{
- Device(I2C0) {
- Name(_HID, "APMC0D0F")
- Name(_CID, "APMC0D0F")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 }
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"clock-frequency", 100000},
Package () {"i2c-sda-falling-time-ns", 913},
Package () {"i2c-scl-falling-time-ns", 303},
Package () {"i2c-sda-hold-time-ns", 0x9c2},
Package () {"interrut-parent",Package() {\_SB.MBI6}},
}
- })
- }
- Device(I2C2) {
- Name(_HID, "APMC0D0F")
- Name(_CID, "APMC0D0F")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd0100000, 0x10000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") { 707 }
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"clock-frequency", 100000},
Package () {"i2c-sda-falling-time-ns", 913},
Package () {"i2c-scl-falling-time-ns", 303},
Package () {"i2c-sda-hold-time-ns", 0x9c2},
Package () {"interrut-parent",Package() {\_SB.MBI6}},
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl new file mode 100644 index 0000000..528f8a3 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -0,0 +1,438 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- // Mbi-gen peri b intc
- Device(MBI0) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x60080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 }
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 1}
}
- })
- }
- Device(MBI1) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 409}
}
- })
- }
- // Mbi-gen sas0
- Device(MBI2) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,)
{
601,602,603,604,
605,606,607,608,609,
610,611,612,613,614,
615,616,617,618,619,
620,621,622,623,624,
625,626,627,628,629,
630,631,632,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
- Device(MBI3) { // Mbi-gen sas1 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
576,577,578,579,580,
581,582,583,584,585,
586,587,588,589,590,
591,592,593,594,595,
596,597,598,599,600,
601,602,603,604,605,
606,607,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
- Device(MBI4) { // Mbi-gen sas2 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
{
192,193,194,195,196,
197,198,199,200,201,
202,203,204,205,206,
207,208,209,210,211,
212,213,214,215,216,
217,218,219,220,221,
222,223,224,225,226,
227,228,229,230,231,
232,233,234,235,236,
237,238,239,240,241,
242,243,244,245,246,
247,248,249,250,251,
252,253,254,255,256,
257,258,259,260,261,
262,263,264,265,266,
267,268,269,270,271,
272,273,274,275,276,
277,278,279,280,281,
282,283,284,285,286,
287,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
608,609,610,611,
612,613,614,615,616,
617,618,619,620,621,
622,623,624,625,626,
627,628,629,630,631,
632,633,634,635,636,
637,638,639,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
- Device(MBI5) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) {640,641,}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 2}
}
- })
- }
- Device(MBI6) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 705 }
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 1}
}
- })
- }
- Device(MBI7) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 707 }
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 1}
}
- })
- }
- Device(MBI8) {
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x400c0080000, // Min Base Address
0x400c008ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
- })
- Name(_PRS, ResourceTemplate() {
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
}
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
{
1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
}
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 409}
}
- })
- }
+/*
- Device(MBI4) { // Mbi-gen dsa1 dbg0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 9}
}
- })
- }
- Device(MBI5) { // Mbi-gen dsa2 dbg1 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 9}
}
- })
- }
- Device(MBI6) { // Mbi-gen dsa sas0 intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"num-pins", 128}
}
- })
- }
+*/
- Device(MBI9) { // Mbi-gen roce intc
- Name(_HID, "HISI0152")
- Name(_CID, "MBIGen")
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
- })
- Name (_PRS, ResourceTemplate (){
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
{
722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
}
- })
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl new file mode 100644 index 0000000..b822c61 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -0,0 +1,584 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+//#include "ArmPlatform.h" +Scope(_SB) +{
- // 1P NA PCIe2
- Device (PCI2)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 2) // Segment of this Root complex
- Name(_BBN, 0x80) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x80, // AddressMinimum - Minimum Bus Number
0x87, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xa8800000, // Min Base Address
0xaffeffff, // Max Base Address
0x0, // Translate
0x77f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0xafff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)
- Device (RES2)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000)
})
- }
- }
- } // Device(PCI2)
- // 1p NB PCIe0
- Device (PCI4)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 4) // Segment of this Root complex
- Name(_BBN, 0x88) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x88, // AddressMinimum - Minimum Bus Number
0x8f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xa9000000, // Min Base Address
0xabfeffff, // Max Base Address
0x800000000, // Translate
0x2ff0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8abff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES4)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a0090000, // Min Base Address
0x8a009ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCI4)
- // 1P NB PCI1
- Device (PCI5)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 5) // Segment of this Root complex
- Name(_BBN, 0x0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x0, // AddressMinimum - Minimum Bus Number
0x7, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xb0800000, // Min Base Address
0xb7feffff, // Max Base Address
0x800000000, // Translate
0x77f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8b7ff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES5)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a0200000, // Min Base Address
0x8a020ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCI5)
- // 1P NB PCIe2
- Device (PCI6)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0x6) // Segment of this Root complex
- Name(_BBN, 0xc0) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0xc0, // AddressMinimum - Minimum Bus Number
0xc7, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xac900000, // Min Base Address
0xaffeffff, // Max Base Address
0x800000000, // Translate
0x36f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8afff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES6)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a00a0000, // Min Base Address
0x8a00affff, // Max Base Address
0x0, // Translate
0x10000 // Length
- )
})
- }
- }
- } // Device(PCI6)
- // 1P NB PCIe3
- Device (PCI7)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0x7) // Segment of this Root complex
- Name(_BBN, 0x90) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x90, // AddressMinimum - Minimum Bus Number
0x97, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x8 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0xb9800000, // Min Base Address
0xbffeffff, // Max Base Address
0x800000000, // Translate
0x67f0000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x8bfff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RES7)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x8a00b0000, // Min Base Address
0x8a00bffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCI7)
- // 2P NA PCIe2
- Device (PCIa)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0xa) // Segment of this Root complex
- Name(_BBN, 0x10) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x10, // AddressMinimum - Minimum Bus Number
0x1f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x10 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0x20000000, // Min Base Address
0xefffffff, // Max Base Address
0x65000000000, // Translate
0xd0000000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x67fffff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0xf)
- Device (RESa)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x600a00a0000, // Min Base Address
0x600a00affff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCIa)
- // 2P NB PCIe0
- Device (PCIc)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0xc) // Segment of this Root complex
- Name(_BBN, 0x20) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x20, // AddressMinimum - Minimum Bus Number
0x2f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x10 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0x30000000, // Min Base Address
0xefffffff, // Max Base Address
0x75000000000, // Translate
0xc0000000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x77fffff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RESc)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x700a0090000, // Min Base Address
0x700a009ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCIc)
- //2P NB PCIe1
- Device (PCId)
- {
- Name (_HID, "PNP0A08") // PCI Express Root Bridge
- Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
- Name(_SEG, 0xd) // Segment of this Root complex
- Name(_BBN, 0x30) // Base Bus Number
- Name(_CCA, 1)
- Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer, MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0x30, // AddressMinimum - Minimum Bus Number
0x3f, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
0x10 // RangeLength - Number of Busses
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
Cacheable,
ReadWrite,
0x0, // Granularity
0x40000000, // Min Base Address
0xefffffff, // Max Base Address
0x79000000000, // Translate
0xB0000000 // Length
)
QWordIO (
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x0, // Granularity
0x0, // Min Base Address
0xffff, // Max Base Address
0x7bfffff0000, // Translate
0x10000 // Length
)
}) // Name(RBUF)
Return (RBUF)
- } // Method(_CRS)
- Method (_STA, 0x0, NotSerialized)
- {
Return (0x0)
- Device (RESd)
- {
Name (_HID, "HISI0081") // HiSi PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_CRS, ResourceTemplate (){
QwordMemory (
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0, // Granularity
0x700a0200000, // Min Base Address
0x700a020ffff, // Max Base Address
0x0, // Translate
0x10000 // Length
)
})
- }
- }
- } // Device(PCId)
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl new file mode 100644 index 0000000..96df0a8 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -0,0 +1,247 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+Scope(_SB) +{
- Device(SAS0) {
- Name(_HID, "HISI0162")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
{
601,602,603,604,
605,606,607,608,609,
610,611,612,613,614,
615,616,617,618,619,
620,621,622,623,624,
625,626,627,628,629,
630,631,632,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"interrupt-parent",Package() {\_SB.MBI2}},
Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},
Package () {"queue-count", 16},
Package () {"phy-count", 8},
}
- })
- OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x338),
CLK, 32,
CLKD, 32,
Offset (0xa60),
RST, 32,
DRST, 32,
Offset (0x5a30),
STS, 32,
- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)
Store(0x7ffff, CLKD)
Sleep(1)
Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
- }
- }
- Device(SAS1) {
- Name(_HID, "HISI0162")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
{
64,65,66,67,68,
69,70,71,72,73,
75,76,77,78,79,
80,81,82,83,84,
85,86,87,88,89,
90,91,92,93,94,
95,96,97,98,99,
100,101,102,103,104,
105,106,107,108,109,
110,111,112,113,114,
115,116,117,118,119,
120,121,122,123,124,
125,126,127,128,129,
130,131,132,133,134,
135,136,137,138,139,
140,141,142,143,144,
145,146,147,148,149,
150,151,152,153,154,
155,156,157,158,159,
160,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
{
576,577,578,579,580,
581,582,583,584,585,
586,587,588,589,590,
591,592,593,594,595,
596,597,598,599,600,
601,602,603,604,605,
606,607,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"interrupt-parent",Package() {\_SB.MBI3}},
Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
Package () {"queue-count", 16},
Package () {"phy-count", 8},
Package () {"hip06-sas-v2-quirk-amt", 1},
}
- })
- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x318),
CLK, 32,
CLKD, 32,
Offset (0xa18),
RST, 32,
DRST, 32,
Offset (0x5a0c),
STS, 32,
- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)
Store(0x7ffff, CLKD)
Sleep(1)
Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
- }
- }
- Device(SAS2) {
- Name(_HID, "HISI0162")
- Name(_CCA, 1)
- Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
{
192,193,194,195,196,
197,198,199,200,201,
202,203,204,205,206,
207,208,209,210,211,
212,213,214,215,216,
217,218,219,220,221,
222,223,224,225,226,
227,228,229,230,231,
232,233,234,235,236,
237,238,239,240,241,
242,243,244,245,246,
247,248,249,250,251,
252,253,254,255,256,
257,258,259,260,261,
262,263,264,265,266,
267,268,269,270,271,
272,273,274,275,276,
277,278,279,280,281,
282,283,284,285,286,
287,
}
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
{
608,609,610,611,
612,613,614,615,616,
617,618,619,620,621,
622,623,624,625,626,
627,628,629,630,631,
632,633,634,635,636,
637,638,639,
}
- })
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"interrupt-parent",Package() {\_SB.MBI4}},
Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
Package () {"queue-count", 16},
Package () {"phy-count", 8},
}
- })
- OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
- Field (CTL, AnyAcc, NoLock, Preserve)
- {
Offset (0x3a8),
CLK, 32,
CLKD, 32,
Offset (0xae0),
RST, 32,
DRST, 32,
Offset (0x5a70),
STS, 32,
- }
- Method (_RST, 0x0, Serialized)
- {
Store(0x7ffff, RST)
Store(0x7ffff, CLKD)
Sleep(1)
Store(0x7ffff, DRST)
Store(0x7ffff, CLK)
Sleep(1)
- }
- }
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl new file mode 100644 index 0000000..51d7d2a --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl @@ -0,0 +1,135 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+//#include "ArmPlatform.h" +Scope(_SB) +{
- Device (USB0)
- {
- Name (_HID, "PNP0D20") // _HID: Hardware ID
- Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID
- Name (_CCA, One) // _CCA: Cache Coherency Attribute
- Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
- {
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0xa7020000, // Address Base
0x00010000, // Address Length
)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI5")
{
641,
}
})
Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
- }
- Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
Package () {"interrupt-parent",Package() {\_SB.MBI5}}
}
- })
- Device (RHUB)
- {
Name (_ADR, Zero) // _ADR: Address
Device (PRT1)
{
Name (_ADR, One) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
Zero,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
})
}
Device (PRT2)
{
Name (_ADR, 0x02) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
Zero,
0xFF,
Zero,
Zero
})
}
Device (PRT3)
{
Name (_ADR, 0x03) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
Zero,
0xFF,
Zero,
Zero
})
}
Device (PRT4)
{
Name (_ADR, 0x04) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
Zero,
0xFF,
Zero,
Zero
})
}
- }
- }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl new file mode 100644 index 0000000..b4fc538 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl @@ -0,0 +1,31 @@ +/** @file
- Differentiated System Description Table Fields (DSDT)
- Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2015-2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
- Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+**/
+#include "Hi1616Platform.h"
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP07 ", EFI_ACPI_ARM_OEM_REVISION) {
- include ("Lpc.asl")
- include ("D05Mbig.asl")
- include ("Com.asl")
- include ("CPU.asl")
- include ("D05I2c.asl")
- include ("D05Usb.asl")
- include ("D05Hns.asl")
- include ("D05Sas.asl")
- include ("D05Pci.asl")
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl new file mode 100644 index 0000000..0965afc --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2016 Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+// +// LPC +//
+Device (LPC0) +{
- Name(_HID, "HISI0191") // HiSi LPC
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
- })
+} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc new file mode 100644 index 0000000..2908b24 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc @@ -0,0 +1,67 @@ +/** @file +* Firmware ACPI Control Structure (FACS) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include <IndustryStandard/Acpi.h>
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
- sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
- 0xA152, // UINT32 HardwareSignature
- 0, // UINT32 FirmwareWakingVector
- 0, // UINT32 GlobalLock
- 0, // UINT32 Flags
- 0, // UINT64 XFirmwareWakingVector
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]
EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
- 0, // UINT32 OspmFlags "Platform firmware must
// initialize this field to zero."
- { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]
EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Facs;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc new file mode 100644 index 0000000..152410b --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc @@ -0,0 +1,91 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include "Hi1616Platform.h"
+#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h>
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
- ARM_ACPI_HEADER (
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
- ),
- 0, // UINT32 FirmwareCtrl
- 0, // UINT32 Dsdt
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
- EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
- 0, // UINT16 SciInt
- 0, // UINT32 SmiCmd
- 0, // UINT8 AcpiEnable
- 0, // UINT8 AcpiDisable
- 0, // UINT8 S4BiosReq
- 0, // UINT8 PstateCnt
- 0, // UINT32 Pm1aEvtBlk
- 0, // UINT32 Pm1bEvtBlk
- 0, // UINT32 Pm1aCntBlk
- 0, // UINT32 Pm1bCntBlk
- 0, // UINT32 Pm2CntBlk
- 0, // UINT32 PmTmrBlk
- 0, // UINT32 Gpe0Blk
- 0, // UINT32 Gpe1Blk
- 0, // UINT8 Pm1EvtLen
- 0, // UINT8 Pm1CntLen
- 0, // UINT8 Pm2CntLen
- 0, // UINT8 PmTmrLen
- 0, // UINT8 Gpe0BlkLen
- 0, // UINT8 Gpe1BlkLen
- 0, // UINT8 Gpe1Base
- 0, // UINT8 CstCnt
- 0, // UINT16 PLvl2Lat
- 0, // UINT16 PLvl3Lat
- 0, // UINT16 FlushSize
- 0, // UINT16 FlushStride
- 0, // UINT8 DutyOffset
- 0, // UINT8 DutyWidth
- 0, // UINT8 DayAlrm
- 0, // UINT8 MonAlrm
- 0, // UINT8 Century
- 0, // UINT16 IaPcBootArch
- 0, // UINT8 Reserved1
- EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
- 0, // UINT8 ResetValue
- EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
- 0, // UINT64 XFirmwareCtrl
- 0, // UINT64 XDsdt
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
- NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..b472828 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc @@ -0,0 +1,95 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include "Hi1616Platform.h"
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
- #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
- #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+#pragma pack (1)
+typedef struct {
- EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+#pragma pack ()
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
- {
- ARM_ACPI_HEADER(
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES,
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
- ),
- SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
- 0, // UINT32 Reserved
- FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
- FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
- FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
- GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
- 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+#ifdef notyet
- PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
- sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
- },
- {
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
0, 0, 0, 0),
- EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
//FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
0, 0, 0, 0)
- }
+#else /* !notyet */
- 0, 0
- }
+#endif
- };
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h new file mode 100644 index 0000000..808219a --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#ifndef _HI1610_PLATFORM_H_ +#define _HI1610_PLATFORM_H_
+// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6 bytes long +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000 +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('I','N','T','L') +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
- Signature, /* UINT32 Signature */ \
- sizeof (Type), /* UINT32 Length */ \
- Revision, /* UINT8 Revision */ \
- 0, /* UINT8 Checksum */ \
- { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
- EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
- EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
- EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
- EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
- }
+#define HI1616_WATCHDOG_COUNT 2
+#endif diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc new file mode 100644 index 0000000..b83c221 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc @@ -0,0 +1,282 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ +* +**/
+#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/AcpiNextLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include "Hi1616Platform.h"
+// Differs from Juno, we have another affinity level beyond cluster and core +// 0x20000 is only for socket 0 +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId) << 8) | (CoreId))
+// +// Multiple APIC Description Table +// +#pragma pack (1)
+typedef struct {
- EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[64];
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[8];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+#pragma pack ()
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
- {
- ARM_ACPI_HEADER (
EFI_ACPI_1_0_APIC_SIGNATURE,
EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
- ),
- //
- // MADT specific fields
- //
- 0, // LocalApicAddress
- 0, // Flags
- },
- {
- // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
- // GsivId, GicRBase, Mpidr)
- // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
- // ACPI v5.1).
- // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
- // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */),
- EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */),
- },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4),
- {
- EFI_ACPI_6_0_GIC_ITS_INIT(0,0x4C000000), //peri a
- EFI_ACPI_6_0_GIC_ITS_INIT(1,0x6C000000), //peri b
- EFI_ACPI_6_0_GIC_ITS_INIT(2,0xC6000000), //dsa a
- EFI_ACPI_6_0_GIC_ITS_INIT(3,0x8C6000000), //dsa b
- EFI_ACPI_6_0_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a
- EFI_ACPI_6_0_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b
- EFI_ACPI_6_0_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a
- EFI_ACPI_6_0_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b
- }
+};
+// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +//
+VOID* CONST ReferenceAcpiTable = &Madt;
1.9.1
We'd like to update ACPI tables during post, so we first copy the AcpiPlatformDxe driver from MdeModulePkg, and then we will add the feature of updating Acpi tables by another commit.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 260 +++++++++++++++++++++ .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni | 22 ++ .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 56 +++++ .../HisiAcpiPlatformDxe/AcpiPlatformExtra.uni | 20 ++ 4 files changed, 358 insertions(+) create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c new file mode 100644 index 0000000..5b679fa --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,260 @@ +/** @file + Sample ACPI Platform Driver + + Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiDxe.h> + +#include <Protocol/AcpiTable.h> +#include <Protocol/FirmwareVolume2.h> + +#include <Library/BaseLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> + +#include <IndustryStandard/Acpi.h> + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param Instance Return pointer to the first instance of the protocol + + @return EFI_SUCCESS The function completed successfully. + @return EFI_NOT_FOUND The protocol could not be located. + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateFvInstanceWithTables ( + OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance; + + FvStatus = 0; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + + + // + // Looking for FV with ACPI storage file + // + + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID**) &FvInstance + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Status = FvInstance->ReadFile ( + FvInstance, + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile), + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + *Instance = FvInstance; + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + + +/** + This function calculates and updates an UINT8 checksum. + + @param Buffer Pointer to buffer to checksum + @param Size Number of bytes to checksum + +**/ +VOID +AcpiPlatformChecksum ( + IN UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // + // Set checksum to 0 first + // + Buffer[ChecksumOffset] = 0; + + // + // Update checksum value + // + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size); +} + + +/** + Entrypoint of Acpi Platform driver. + + @param ImageHandle + @param SystemTable + + @return EFI_SUCCESS + @return EFI_LOAD_ERROR + @return EFI_OUT_OF_RESOURCES + +**/ +EFI_STATUS +EFIAPI +AcpiPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINTN TableSize; + UINTN Size; + + Instance = 0; + CurrentTable = NULL; + TableHandle = 0; + + // + // Find the AcpiTable protocol + // + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + + // + // Locate the firmware volume protocol + // + Status = LocateFvInstanceWithTables (&FwVol); + if (EFI_ERROR (Status)) { + return EFI_ABORTED; + } + // + // Read tables from the storage file. + // + while (Status == EFI_SUCCESS) { + + Status = FwVol->ReadSection ( + FwVol, + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile), + EFI_SECTION_RAW, + Instance, + (VOID**) &CurrentTable, + &Size, + &FvStatus + ); + if (!EFI_ERROR(Status)) { + // + // Add the table + // + TableHandle = 0; + + TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length; + ASSERT (Size >= TableSize); + + // + // Checksum ACPI table + // + AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize); + + // + // Install ACPI table + // + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + TableSize, + &TableHandle + ); + + // + // Free memory allocated by ReadSection + // + gBS->FreePool (CurrentTable); + + if (EFI_ERROR(Status)) { + return EFI_ABORTED; + } + + // + // Increment the instance + // + Instance++; + CurrentTable = NULL; + } + } + + return EFI_SUCCESS; +} + diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni new file mode 100644 index 0000000..1275549 --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni @@ -0,0 +1,22 @@ +// /** @file +// Sample ACPI Platform Driver +// +// Sample ACPI Platform Driver +// +// Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Sample ACPI Platform Driver" + +#string STR_MODULE_DESCRIPTION #language en-US "Sample ACPI Platform Driver" + diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 0000000..80ff49b --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,56 @@ +## @file +# Sample ACPI Platform Driver +# +# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiPlatform + MODULE_UNI_FILE = AcpiPlatform.uni + FILE_GUID = cb933912-df8f-4305-b1f9-7b44fa11395c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AcpiPlatformEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + AcpiPlatform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + UefiLib + DxeServicesLib + PcdLib + BaseMemoryLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES + +[Depex] + gEfiAcpiTableProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + AcpiPlatformExtra.uni diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni new file mode 100644 index 0000000..4c21968 --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni @@ -0,0 +1,20 @@ +// /** @file +// AcpiPlatform Localized Strings and Content +// +// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"ACPI Platform Sample DXE Driver" + +
On Thu, Nov 10, 2016 at 09:52:19PM +0800, Heyi Guo wrote:
We'd like to update ACPI tables during post, so we first copy the AcpiPlatformDxe driver from MdeModulePkg, and then we will add the feature of updating Acpi tables by another commit.
So, I think this is a pretty clunky mechanism and something we should look into improving in the future - but I agree it is the established method of doing this so:
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
However, the patch that modifies this code should come immediately after this one. I don't mind which of them you move, as long as they are sequential.
/ Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 260 +++++++++++++++++++++ .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni | 22 ++ .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 56 +++++ .../HisiAcpiPlatformDxe/AcpiPlatformExtra.uni | 20 ++ 4 files changed, 358 insertions(+) create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c new file mode 100644 index 0000000..5b679fa --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,260 @@ +/** @file
- Sample ACPI Platform Driver
- Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <PiDxe.h>
+#include <Protocol/AcpiTable.h> +#include <Protocol/FirmwareVolume2.h>
+#include <Library/BaseLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+/**
- Locate the first instance of a protocol. If the protocol requested is an
- FV protocol, then it will return the first FV that contains the ACPI table
- storage file.
- @param Instance Return pointer to the first instance of the protocol
- @return EFI_SUCCESS The function completed successfully.
- @return EFI_NOT_FOUND The protocol could not be located.
- @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/ +EFI_STATUS +LocateFvInstanceWithTables (
- OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance
- )
+{
- EFI_STATUS Status;
- EFI_HANDLE *HandleBuffer;
- UINTN NumberOfHandles;
- EFI_FV_FILETYPE FileType;
- UINT32 FvStatus;
- EFI_FV_FILE_ATTRIBUTES Attributes;
- UINTN Size;
- UINTN Index;
- EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
- FvStatus = 0;
- //
- // Locate protocol.
- //
- Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiFirmwareVolume2ProtocolGuid,
NULL,
&NumberOfHandles,
&HandleBuffer
);
- if (EFI_ERROR (Status)) {
- //
- // Defined errors at this time are not found and out of resources.
- //
- return Status;
- }
- //
- // Looking for FV with ACPI storage file
- //
- for (Index = 0; Index < NumberOfHandles; Index++) {
- //
- // Get the protocol on this handle
- // This should not fail because of LocateHandleBuffer
- //
- Status = gBS->HandleProtocol (
HandleBuffer[Index],
&gEfiFirmwareVolume2ProtocolGuid,
(VOID**) &FvInstance
);
- ASSERT_EFI_ERROR (Status);
- //
- // See if it has the ACPI storage file
- //
- Status = FvInstance->ReadFile (
FvInstance,
(EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
NULL,
&Size,
&FileType,
&Attributes,
&FvStatus
);
- //
- // If we found it, then we are done
- //
- if (Status == EFI_SUCCESS) {
*Instance = FvInstance;
break;
- }
- }
- //
- // Our exit status is determined by the success of the previous operations
- // If the protocol was found, Instance already points to it.
- //
- //
- // Free any allocated buffers
- //
- gBS->FreePool (HandleBuffer);
- return Status;
+}
+/**
- This function calculates and updates an UINT8 checksum.
- @param Buffer Pointer to buffer to checksum
- @param Size Number of bytes to checksum
+**/ +VOID +AcpiPlatformChecksum (
- IN UINT8 *Buffer,
- IN UINTN Size
- )
+{
- UINTN ChecksumOffset;
- ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
- //
- // Set checksum to 0 first
- //
- Buffer[ChecksumOffset] = 0;
- //
- // Update checksum value
- //
- Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
+}
+/**
- Entrypoint of Acpi Platform driver.
- @param ImageHandle
- @param SystemTable
- @return EFI_SUCCESS
- @return EFI_LOAD_ERROR
- @return EFI_OUT_OF_RESOURCES
+**/ +EFI_STATUS +EFIAPI +AcpiPlatformEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
+{
- EFI_STATUS Status;
- EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
- EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
- INTN Instance;
- EFI_ACPI_COMMON_HEADER *CurrentTable;
- UINTN TableHandle;
- UINT32 FvStatus;
- UINTN TableSize;
- UINTN Size;
- Instance = 0;
- CurrentTable = NULL;
- TableHandle = 0;
- //
- // Find the AcpiTable protocol
- //
- Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
- if (EFI_ERROR (Status)) {
- return EFI_ABORTED;
- }
- //
- // Locate the firmware volume protocol
- //
- Status = LocateFvInstanceWithTables (&FwVol);
- if (EFI_ERROR (Status)) {
- return EFI_ABORTED;
- }
- //
- // Read tables from the storage file.
- //
- while (Status == EFI_SUCCESS) {
- Status = FwVol->ReadSection (
FwVol,
(EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
EFI_SECTION_RAW,
Instance,
(VOID**) &CurrentTable,
&Size,
&FvStatus
);
- if (!EFI_ERROR(Status)) {
//
// Add the table
//
TableHandle = 0;
TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
ASSERT (Size >= TableSize);
//
// Checksum ACPI table
//
AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
//
// Install ACPI table
//
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
TableSize,
&TableHandle
);
//
// Free memory allocated by ReadSection
//
gBS->FreePool (CurrentTable);
if (EFI_ERROR(Status)) {
return EFI_ABORTED;
}
//
// Increment the instance
//
Instance++;
CurrentTable = NULL;
- }
- }
- return EFI_SUCCESS;
+}
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni new file mode 100644 index 0000000..1275549 --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni @@ -0,0 +1,22 @@ +// /** @file +// Sample ACPI Platform Driver +// +// Sample ACPI Platform Driver +// +// Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/
+#string STR_MODULE_ABSTRACT #language en-US "Sample ACPI Platform Driver"
+#string STR_MODULE_DESCRIPTION #language en-US "Sample ACPI Platform Driver"
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 0000000..80ff49b --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,56 @@ +## @file +# Sample ACPI Platform Driver +# +# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +##
+[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = AcpiPlatform
- MODULE_UNI_FILE = AcpiPlatform.uni
- FILE_GUID = cb933912-df8f-4305-b1f9-7b44fa11395c
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = AcpiPlatformEntryPoint
+# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +#
+[Sources]
- AcpiPlatform.c
+[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
+[LibraryClasses]
- UefiLib
- DxeServicesLib
- PcdLib
- BaseMemoryLib
- DebugLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
+[Protocols]
- gEfiAcpiTableProtocolGuid ## CONSUMES
+[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES
+[Depex]
- gEfiAcpiTableProtocolGuid
+[UserExtensions.TianoCore."ExtraFiles"]
- AcpiPlatformExtra.uni
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni new file mode 100644 index 0000000..4c21968 --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni @@ -0,0 +1,20 @@ +// /** @file +// AcpiPlatform Localized Strings and Content +// +// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/
+#string STR_PROPERTIES_MODULE_NAME +#language en-US +"ACPI Platform Sample DXE Driver"
-- 1.9.1
Add OemIsNeedDisableExpanderBuffer() interface for SAS driver. Only add declaration at header file, the actual implementation code at OemMiscLib. D02 uses another SAS driver which doesn't need this interface.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com --- Chips/Hisilicon/Include/Library/OemMiscLib.h | 1 + Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 +++++ 2 files changed, 6 insertions(+)
diff --git a/Chips/Hisilicon/Include/Library/OemMiscLib.h b/Chips/Hisilicon/Include/Library/OemMiscLib.h index 19d92e0..6f18c0f 100644 --- a/Chips/Hisilicon/Include/Library/OemMiscLib.h +++ b/Chips/Hisilicon/Include/Library/OemMiscLib.h @@ -44,6 +44,7 @@ BOOLEAN OemIsMpBoot(); UINT32 OemIsWarmBoot();
VOID OemBiosSwitch(UINT32 Master); +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID);
extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index c709f8b..fa1039b 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -134,3 +134,8 @@ VOID OemBiosSwitch(UINT32 Master) (VOID)Master; return; } + +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{ + return TRUE; +}
On Thu, Nov 10, 2016 at 09:52:20PM +0800, Heyi Guo wrote:
Add OemIsNeedDisableExpanderBuffer() interface for SAS driver. Only add declaration at header file, the actual implementation code at OemMiscLib. D02 uses another SAS driver which doesn't need this interface.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo guoheyi@huawei.com
This should be moved to the patch that adds the updated binary SAS driver.
Chips/Hisilicon/Include/Library/OemMiscLib.h | 1 + Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 5 +++++ 2 files changed, 6 insertions(+)
diff --git a/Chips/Hisilicon/Include/Library/OemMiscLib.h b/Chips/Hisilicon/Include/Library/OemMiscLib.h index 19d92e0..6f18c0f 100644 --- a/Chips/Hisilicon/Include/Library/OemMiscLib.h +++ b/Chips/Hisilicon/Include/Library/OemMiscLib.h @@ -44,6 +44,7 @@ BOOLEAN OemIsMpBoot(); UINT32 OemIsWarmBoot(); VOID OemBiosSwitch(UINT32 Master); +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID); extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index c709f8b..fa1039b 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -134,3 +134,8 @@ VOID OemBiosSwitch(UINT32 Master) (VOID)Master; return; }
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+}
1.9.1
D03 OemNicConfig driver is using CpldIoLib, so CpldIoLib needs to be added to the INF file to avoid potential build error.
The reason why it didn't cause D03 build failure is that CpldIoLib is invoked by this module implicitly via below chain: I2CLib->PlatformSysCtrlLib of Hi1610->OemAddressMapLib of D03->CpldIoLib
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf | 1 + 1 file changed, 1 insertion(+)
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf index 4327406..cc544f7 100644 --- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -39,6 +39,7 @@ DebugLib IoLib TimerLib + CpldIoLib I2CLib PcdLib
On Thu, Nov 10, 2016 at 09:52:21PM +0800, Heyi Guo wrote:
D03 OemNicConfig driver is using CpldIoLib, so CpldIoLib needs to be added to the INF file to avoid potential build error.
The reason why it didn't cause D03 build failure is that CpldIoLib is invoked by this module implicitly via below chain: I2CLib->PlatformSysCtrlLib of Hi1610->OemAddressMapLib of D03->CpldIoLib
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf | 1 + 1 file changed, 1 insertion(+)
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf index 4327406..cc544f7 100644 --- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -39,6 +39,7 @@ DebugLib IoLib TimerLib
- CpldIoLib
Please move before DebugLib, so it at least does not make sorting worse.
I2CLib PcdLib -- 1.9.1
1. Rename Pv660.dsc.inc and Pv660.fdf.inc to Hisilicon and move it to Hisilicon root path. 2. Modify D02/D03 dsc and fdf accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hisilicon.dsc.inc | 371 +++++++++++++++++++++++++++++++++++ Chips/Hisilicon/Hisilicon.fdf.inc | 139 +++++++++++++ Chips/Hisilicon/Pv660/Pv660.dsc.inc | 371 ----------------------------------- Chips/Hisilicon/Pv660/Pv660.fdf.inc | 139 ------------- Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 8 files changed, 514 insertions(+), 514 deletions(-) create mode 100644 Chips/Hisilicon/Hisilicon.dsc.inc create mode 100644 Chips/Hisilicon/Hisilicon.fdf.inc delete mode 100644 Chips/Hisilicon/Pv660/Pv660.dsc.inc delete mode 100644 Chips/Hisilicon/Pv660/Pv660.fdf.inc
diff --git a/Chips/Hisilicon/Hisilicon.dsc.inc b/Chips/Hisilicon/Hisilicon.dsc.inc new file mode 100644 index 0000000..510ee1d --- /dev/null +++ b/Chips/Hisilicon/Hisilicon.dsc.inc @@ -0,0 +1,371 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +[LibraryClasses.common] +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + # + # Allow dynamic PCDs + # + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + + # Versatile Express Specific Libraries + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf + # ARM PL111 Lcd Driver + LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + + # ARM PL354 SMC Driver + PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf + # ARM PL011 UART Driver + PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf + + SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # EBL Related Libraries + EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf + EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf + EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf + EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf + + UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scripts accessing system memory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf + + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf + + # BDS Libraries + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + + # Use ArmCortexA5xLib to get A57 specific functions + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf + + # + # It is not possible to prevent the ARM compiler for generic intrinsic functions. + # This library provides the instrinsic functions generate by a given compiler. + # And NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +[LibraryClasses.common.SEC] + ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf + + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf + + # Trustzone Support + ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf + + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + + ## Fixed compile error after upgrade to 14.10 + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf + DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf + +[LibraryClasses.AARCH64] + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + +[BuildOptions] + RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # + # Control what commands are supported from the UI + # Turn these on and off to add features or save size + # + ## Set PcdEmbeddedMacBoot to FALSE, or console mode will be changed when + ## entering EBL and not restored when exiting. + gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|FALSE + gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE + gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE + + gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" + + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"VExpress" + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Verbose + # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // UNDI Driver + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_ERROR 0x80000000 // Error + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06 + gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" + gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000 + + # + # ARM PrimeCell + # + + # + # ARM OS Loader + # + # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/MemoryMapped(0x0,0xED000000,0xED400000)" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()" + + # Set timer interrupt to be triggerred in 1ms to avoid missing + # serial terminal input characters. + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 + gArmTokenSpaceGuid.PcdVFPEnabled|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 # Variable: L"Timeout" + diff --git a/Chips/Hisilicon/Hisilicon.fdf.inc b/Chips/Hisilicon/Hisilicon.fdf.inc new file mode 100644 index 0000000..ee87cd1 --- /dev/null +++ b/Chips/Hisilicon/Hisilicon.fdf.inc @@ -0,0 +1,139 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.BINARY] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } + diff --git a/Chips/Hisilicon/Pv660/Pv660.dsc.inc b/Chips/Hisilicon/Pv660/Pv660.dsc.inc deleted file mode 100644 index d9ef115..0000000 --- a/Chips/Hisilicon/Pv660/Pv660.dsc.inc +++ /dev/null @@ -1,371 +0,0 @@ -# -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# - -[LibraryClasses.common] -!if $(TARGET) == RELEASE - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf -!else - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf -!endif - DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf - - BaseLib|MdePkg/Library/BaseLib/BaseLib.inf - SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf - PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf - IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf - CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf - - UefiLib|MdePkg/Library/UefiLib/UefiLib.inf - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf - DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf - UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf - UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf - - UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - # - # Allow dynamic PCDs - # - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - - BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf - - # ARM Architectural Libraries - CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf - DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf - CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf - ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf - DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf - ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf - ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf - ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf - ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf - ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf - - # Versatile Express Specific Libraries - ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf - NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf - EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf - # ARM PL111 Lcd Driver - LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf - - # ARM PL354 SMC Driver - PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf - # ARM PL011 UART Driver - PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf - - SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf - TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf - - # EBL Related Libraries - EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf - EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf - EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf - EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf - - UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - # - # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window - # in the debugger will show load and unload commands for symbols. You can cut and paste this - # into the command window to load symbols. We should be able to use a script to do this, but - # the version of RVD I have does not support scripts accessing system memory. - # - #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf - #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf - PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf - - DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf - DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf - - SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf - - TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf - AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf - - # BDS Libraries - BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf - UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - - VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf - - ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf - - # Use ArmCortexA5xLib to get A57 specific functions - ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf - - # - # It is not possible to prevent the ARM compiler for generic intrinsic functions. - # This library provides the instrinsic functions generate by a given compiler. - # And NULL mean link this library into all ARM images. - # - NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf - - # Add support for GCC stack protector - NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf - -[LibraryClasses.common.SEC] - ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf - - DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf - - # Trustzone Support - ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf - - ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - -[LibraryClasses.common.PEI_CORE] - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf - PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf - ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf - - PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - -[LibraryClasses.common.PEIM] - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf - PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf - PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf - PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf - PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf - ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf - - PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf - - ## Fixed compile error after upgrade to 14.10 - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - -[LibraryClasses.common.DXE_CORE] - HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf - MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf - DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf - ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf - ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf - -[LibraryClasses.common.DXE_DRIVER] - ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - -[LibraryClasses.common.UEFI_APPLICATION] - UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf - FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - -[LibraryClasses.common.UEFI_DRIVER] - ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf - UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf - ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf - PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf - DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - -[LibraryClasses.common.DXE_RUNTIME_DRIVER] - HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf - ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf - DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf - -[LibraryClasses.AARCH64] - ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf - -[BuildOptions] - RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG - GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG - -[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] - GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000 - GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 - -################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################ - -[PcdsFeatureFlag.common] - gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE - - # - # Control what commands are supported from the UI - # Turn these on and off to add features or save size - # - ## Set PcdEmbeddedMacBoot to FALSE, or console mode will be changed when - ## entering EBL and not restored when exiting. - gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|FALSE - gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE - gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE - - gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE - - # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress - gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE - - gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE - - gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE - - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE - - gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE - -[PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" - - gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"VExpress" - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44 - gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 - gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 - gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 - gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 - gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 - gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 - gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 - - # DEBUG_ASSERT_ENABLED 0x01 - # DEBUG_PRINT_ENABLED 0x02 - # DEBUG_CODE_ENABLED 0x04 - # CLEAR_MEMORY_ENABLED 0x08 - # ASSERT_BREAKPOINT_ENABLED 0x10 - # ASSERT_DEADLOOP_ENABLED 0x20 -!if $(TARGET) == RELEASE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f -!endif - - # DEBUG_INIT 0x00000001 // Initialization - # DEBUG_WARN 0x00000002 // Warnings - # DEBUG_LOAD 0x00000004 // Load events - # DEBUG_FS 0x00000008 // EFI File system - # DEBUG_POOL 0x00000010 // Alloc & Free's - # DEBUG_PAGE 0x00000020 // Alloc & Free's - # DEBUG_INFO 0x00000040 // Verbose - # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers - # DEBUG_VARIABLE 0x00000100 // Variable - # DEBUG_BM 0x00000400 // Boot Manager - # DEBUG_BLKIO 0x00001000 // BlkIo Driver - # DEBUG_NET 0x00004000 // SNI Driver - # DEBUG_UNDI 0x00010000 // UNDI Driver - # DEBUG_LOADFILE 0x00020000 // UNDI Driver - # DEBUG_EVENT 0x00080000 // Event messages - # DEBUG_ERROR 0x80000000 // Error - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004 - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06 - gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" - gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 - gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 - - # - # Optional feature to help prevent EFI memory map fragments - # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob - # Values are in EFI Pages (4K). DXE Core will make sure that - # at least this much of each type of memory can be allocated - # from a single memory range. This way you only end up with - # maximum of two fragements for each type in the memory map - # (the memory used, and the free memory that was prereserved - # but not used). - # - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 - - # - # ARM Pcds - # - gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000 - - # - # ARM PrimeCell - # - - # - # ARM OS Loader - # - # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: - gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash" - gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/MemoryMapped(0x0,0xED000000,0xED400000)" - gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"" - - # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) - gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)" - gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()" - - # Set timer interrupt to be triggerred in 1ms to avoid missing - # serial terminal input characters. - gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 - gArmTokenSpaceGuid.PcdVFPEnabled|1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32 - -[PcdsDynamicHii.common.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 # Variable: L"Timeout" - diff --git a/Chips/Hisilicon/Pv660/Pv660.fdf.inc b/Chips/Hisilicon/Pv660/Pv660.fdf.inc deleted file mode 100644 index c5f0e8b..0000000 --- a/Chips/Hisilicon/Pv660/Pv660.fdf.inc +++ /dev/null @@ -1,139 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/ - - -################################################################################ -# -# Rules are use with the [FV] section's module INF type to define -# how an FFS file is created for a given INF file. The following Rule are the default -# rules for the different module type. User can add the customized rules to define the -# content of the FFS file. -# -################################################################################ - - -############################################################################ -# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # -############################################################################ -# -#[Rule.Common.DXE_DRIVER] -# FILE DRIVER = $(NAMED_GUID) { -# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex -# COMPRESS PI_STD { -# GUIDED { -# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi -# UI STRING="$(MODULE_NAME)" Optional -# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) -# } -# } -# } -# -############################################################################ - -[Rule.Common.SEC] - FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi - } - -[Rule.Common.PEI_CORE] - FILE PEI_CORE = $(NAMED_GUID) { - TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING ="$(MODULE_NAME)" Optional - } - -[Rule.Common.PEIM] - FILE PEIM = $(NAMED_GUID) { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.PEIM.BINARY] - FILE PEIM = $(NAMED_GUID) { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - TE TE Align = Auto |.efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.PEIM.TIANOCOMPRESSED] - FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - } - -[Rule.Common.DXE_CORE] - FILE DXE_CORE = $(NAMED_GUID) { - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.UEFI_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_DRIVER.BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.DXE_RUNTIME_DRIVER] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - UI STRING="$(MODULE_NAME)" Optional - } - -[Rule.Common.UEFI_APPLICATION] - FILE APPLICATION = $(NAMED_GUID) { - UI STRING ="$(MODULE_NAME)" Optional - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi - } - -[Rule.Common.UEFI_DRIVER.BINARY] - FILE DRIVER = $(NAMED_GUID) { - DXE_DEPEX DXE_DEPEX Optional |.depex - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.UEFI_APPLICATION.BINARY] - FILE APPLICATION = $(NAMED_GUID) { - PE32 PE32 |.efi - UI STRING="$(MODULE_NAME)" Optional - VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) - } - -[Rule.Common.USER_DEFINED.ACPITABLE] - FILE FREEFORM = $(NAMED_GUID) { - RAW ACPI |.acpi - RAW ASL |.aml - } - diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 2228e51..c000b26 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -30,7 +30,7 @@ FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/D02/$(PLATFORM_NAME).fdf DEFINE INCLUDE_TFTP_COMMAND=1
-!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.dsc.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
[LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf index fa0dc2d..34f2368 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.fdf +++ b/Platforms/Hisilicon/D02/Pv660D02.fdf @@ -320,5 +320,5 @@ READ_LOCK_STATUS = TRUE }
-!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.fdf.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 7c72c84..9c96952 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -30,7 +30,7 @@ FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf DEFINE INCLUDE_TFTP_COMMAND=1
-!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.dsc.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
[LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 8ba3bd0..d4a0049 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -338,5 +338,5 @@ READ_LOCK_STATUS = TRUE }
-!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.fdf.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
On Thu, Nov 10, 2016 at 09:52:22PM +0800, Heyi Guo wrote:
- Rename Pv660.dsc.inc and Pv660.fdf.inc to Hisilicon and move it to Hisilicon root path.
- Modify D02/D03 dsc and fdf accordingly.
Useful cleanup, thanks.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.com
Chips/Hisilicon/Hisilicon.dsc.inc | 371 +++++++++++++++++++++++++++++++++++ Chips/Hisilicon/Hisilicon.fdf.inc | 139 +++++++++++++ Chips/Hisilicon/Pv660/Pv660.dsc.inc | 371 ----------------------------------- Chips/Hisilicon/Pv660/Pv660.fdf.inc | 139 ------------- Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- 8 files changed, 514 insertions(+), 514 deletions(-) create mode 100644 Chips/Hisilicon/Hisilicon.dsc.inc create mode 100644 Chips/Hisilicon/Hisilicon.fdf.inc delete mode 100644 Chips/Hisilicon/Pv660/Pv660.dsc.inc delete mode 100644 Chips/Hisilicon/Pv660/Pv660.fdf.inc
diff --git a/Chips/Hisilicon/Hisilicon.dsc.inc b/Chips/Hisilicon/Hisilicon.dsc.inc new file mode 100644 index 0000000..510ee1d --- /dev/null +++ b/Chips/Hisilicon/Hisilicon.dsc.inc @@ -0,0 +1,371 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#
+[LibraryClasses.common] +!if $(TARGET) == RELEASE
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
- DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
- BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
- SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
- PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
- UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
- DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
- DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
- UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
- UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- #
- # Allow dynamic PCDs
- #
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
- # ARM Architectural Libraries
- CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
- DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
- CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
- ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
- DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
- ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
- ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
- ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
- ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
- ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
- # Versatile Express Specific Libraries
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
- # ARM PL111 Lcd Driver
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- # ARM PL354 SMC Driver
- PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
- # ARM PL011 UART Driver
- PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
- SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- # EBL Related Libraries
- EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
- EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
- EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
- EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
- UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- #
- # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
- # in the debugger will show load and unload commands for symbols. You can cut and paste this
- # into the command window to load symbols. We should be able to use a script to do this, but
- # the version of RVD I have does not support scripts accessing system memory.
- #
- #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
- #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
- PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
- DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
- DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
- SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
- TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
- AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
- # BDS Libraries
- BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
- FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
- UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- # Use ArmCortexA5xLib to get A57 specific functions
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
- #
- # It is not possible to prevent the ARM compiler for generic intrinsic functions.
- # This library provides the instrinsic functions generate by a given compiler.
- # And NULL mean link this library into all ARM images.
- #
- NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
- # Add support for GCC stack protector
- NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+[LibraryClasses.common.SEC]
- ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
- DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
- # Trustzone Support
- ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
- ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+[LibraryClasses.common.PEI_CORE]
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
- PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+[LibraryClasses.common.PEIM]
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
- PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
- ## Fixed compile error after upgrade to 14.10
- PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
- ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+[LibraryClasses.common.DXE_CORE]
- HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
- MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
- DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+[LibraryClasses.common.DXE_DRIVER]
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+[LibraryClasses.common.UEFI_APPLICATION]
- UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
- FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+[LibraryClasses.common.UEFI_DRIVER]
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
- UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
- DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+[LibraryClasses.AARCH64]
- ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+[BuildOptions]
- RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
- GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
- GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
- GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################
+[PcdsFeatureFlag.common]
- gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
- gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
- gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
- gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
- #
- # Control what commands are supported from the UI
- # Turn these on and off to add features or save size
- #
- ## Set PcdEmbeddedMacBoot to FALSE, or console mode will be changed when
- ## entering EBL and not restored when exiting.
- gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|FALSE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
- gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
- # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
- gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
- gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE
+[PcdsFixedAtBuild.common]
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"VExpress"
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
- gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
- gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
- gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
- gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
- gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
- gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
- gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
- gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
- # DEBUG_ASSERT_ENABLED 0x01
- # DEBUG_PRINT_ENABLED 0x02
- # DEBUG_CODE_ENABLED 0x04
- # CLEAR_MEMORY_ENABLED 0x08
- # ASSERT_BREAKPOINT_ENABLED 0x10
- # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
+!else
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
+!endif
- # DEBUG_INIT 0x00000001 // Initialization
- # DEBUG_WARN 0x00000002 // Warnings
- # DEBUG_LOAD 0x00000004 // Load events
- # DEBUG_FS 0x00000008 // EFI File system
- # DEBUG_POOL 0x00000010 // Alloc & Free's
- # DEBUG_PAGE 0x00000020 // Alloc & Free's
- # DEBUG_INFO 0x00000040 // Verbose
- # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
- # DEBUG_VARIABLE 0x00000100 // Variable
- # DEBUG_BM 0x00000400 // Boot Manager
- # DEBUG_BLKIO 0x00001000 // BlkIo Driver
- # DEBUG_NET 0x00004000 // SNI Driver
- # DEBUG_UNDI 0x00010000 // UNDI Driver
- # DEBUG_LOADFILE 0x00020000 // UNDI Driver
- # DEBUG_EVENT 0x00080000 // Event messages
- # DEBUG_ERROR 0x80000000 // Error
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06
- gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
- gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
- gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
- #
- # Optional feature to help prevent EFI memory map fragments
- # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
- # Values are in EFI Pages (4K). DXE Core will make sure that
- # at least this much of each type of memory can be allocated
- # from a single memory range. This way you only end up with
- # maximum of two fragements for each type in the memory map
- # (the memory used, and the free memory that was prereserved
- # but not used).
- #
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
- #
- # ARM PrimeCell
- #
- #
- # ARM OS Loader
- #
- # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/MemoryMapped(0x0,0xED000000,0xED400000)"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
- # Set timer interrupt to be triggerred in 1ms to avoid missing
- # serial terminal input characters.
- gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
- gArmTokenSpaceGuid.PcdVFPEnabled|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32
+[PcdsDynamicHii.common.DEFAULT]
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 # Variable: L"Timeout"
diff --git a/Chips/Hisilicon/Hisilicon.fdf.inc b/Chips/Hisilicon/Hisilicon.fdf.inc new file mode 100644 index 0000000..ee87cd1 --- /dev/null +++ b/Chips/Hisilicon/Hisilicon.fdf.inc @@ -0,0 +1,139 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################
+############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################
+[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
- }
+[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING ="$(MODULE_NAME)" Optional
- }
+[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
- }
+[Rule.Common.PEIM.BINARY]
- FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE Align = Auto |.efi
UI STRING="$(MODULE_NAME)" Optional
- }
+[Rule.Common.PEIM.TIANOCOMPRESSED]
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
- }
- }
+[Rule.Common.DXE_CORE]
- FILE DXE_CORE = $(NAMED_GUID) {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
+[Rule.Common.UEFI_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
+[Rule.Common.DXE_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
+[Rule.Common.DXE_DRIVER.BINARY]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- }
+[Rule.Common.DXE_RUNTIME_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
+[Rule.Common.UEFI_APPLICATION]
- FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- }
+[Rule.Common.UEFI_DRIVER.BINARY]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
+[Rule.Common.UEFI_APPLICATION.BINARY]
- FILE APPLICATION = $(NAMED_GUID) {
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
+[Rule.Common.USER_DEFINED.ACPITABLE]
- FILE FREEFORM = $(NAMED_GUID) {
- RAW ACPI |.acpi
- RAW ASL |.aml
- }
diff --git a/Chips/Hisilicon/Pv660/Pv660.dsc.inc b/Chips/Hisilicon/Pv660/Pv660.dsc.inc deleted file mode 100644 index d9ef115..0000000 --- a/Chips/Hisilicon/Pv660/Pv660.dsc.inc +++ /dev/null @@ -1,371 +0,0 @@ -# -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#
-[LibraryClasses.common] -!if $(TARGET) == RELEASE
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
-!else
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
-!endif
- DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
- BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
- SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
- PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
- UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
- DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
- DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
- UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
- UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- #
- # Allow dynamic PCDs
- #
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
- # ARM Architectural Libraries
- CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
- DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
- CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
- ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
- DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
- ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
- ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
- ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
- ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
- ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
- # Versatile Express Specific Libraries
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
- # ARM PL111 Lcd Driver
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- # ARM PL354 SMC Driver
- PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
- # ARM PL011 UART Driver
- PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
- SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- # EBL Related Libraries
- EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
- EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
- EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
- EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
- UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- #
- # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
- # in the debugger will show load and unload commands for symbols. You can cut and paste this
- # into the command window to load symbols. We should be able to use a script to do this, but
- # the version of RVD I have does not support scripts accessing system memory.
- #
- #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
- #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
- PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
- DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
- DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
- SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
- TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
- AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
- # BDS Libraries
- BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
- FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
- UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- # Use ArmCortexA5xLib to get A57 specific functions
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
- #
- # It is not possible to prevent the ARM compiler for generic intrinsic functions.
- # This library provides the instrinsic functions generate by a given compiler.
- # And NULL mean link this library into all ARM images.
- #
- NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
- # Add support for GCC stack protector
- NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
-[LibraryClasses.common.SEC]
- ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
- DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
- # Trustzone Support
- ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
- ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-[LibraryClasses.common.PEI_CORE]
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
- PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-[LibraryClasses.common.PEIM]
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
- PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
- ## Fixed compile error after upgrade to 14.10
- PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
- ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-[LibraryClasses.common.DXE_CORE]
- HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
- MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
- DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
-[LibraryClasses.common.DXE_DRIVER]
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-[LibraryClasses.common.UEFI_APPLICATION]
- UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
- FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
-[LibraryClasses.common.UEFI_DRIVER]
- ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
- UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw8250SerialPortRuntimeLib.inf
- DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
-[LibraryClasses.AARCH64]
- ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
-[BuildOptions]
- RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
- GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
-[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
- GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
- GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
-################################################################################ -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################
-[PcdsFeatureFlag.common]
- gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
- gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
- gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
- gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
- #
- # Control what commands are supported from the UI
- # Turn these on and off to add features or save size
- #
- ## Set PcdEmbeddedMacBoot to FALSE, or console mode will be changed when
- ## entering EBL and not restored when exiting.
- gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|FALSE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
- gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
- gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
- # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
- gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
- gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE
-[PcdsFixedAtBuild.common]
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"VExpress"
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
- gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
- gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
- gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
- gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
- gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
- gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
- gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
- gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
- # DEBUG_ASSERT_ENABLED 0x01
- # DEBUG_PRINT_ENABLED 0x02
- # DEBUG_CODE_ENABLED 0x04
- # CLEAR_MEMORY_ENABLED 0x08
- # ASSERT_BREAKPOINT_ENABLED 0x10
- # ASSERT_DEADLOOP_ENABLED 0x20
-!if $(TARGET) == RELEASE
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0e
-!else
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
-!endif
- # DEBUG_INIT 0x00000001 // Initialization
- # DEBUG_WARN 0x00000002 // Warnings
- # DEBUG_LOAD 0x00000004 // Load events
- # DEBUG_FS 0x00000008 // EFI File system
- # DEBUG_POOL 0x00000010 // Alloc & Free's
- # DEBUG_PAGE 0x00000020 // Alloc & Free's
- # DEBUG_INFO 0x00000040 // Verbose
- # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
- # DEBUG_VARIABLE 0x00000100 // Variable
- # DEBUG_BM 0x00000400 // Boot Manager
- # DEBUG_BLKIO 0x00001000 // BlkIo Driver
- # DEBUG_NET 0x00004000 // SNI Driver
- # DEBUG_UNDI 0x00010000 // UNDI Driver
- # DEBUG_LOADFILE 0x00020000 // UNDI Driver
- # DEBUG_EVENT 0x00080000 // Event messages
- # DEBUG_ERROR 0x80000000 // Error
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06
- gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
- gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
- gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
- #
- # Optional feature to help prevent EFI memory map fragments
- # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
- # Values are in EFI Pages (4K). DXE Core will make sure that
- # at least this much of each type of memory can be allocated
- # from a single memory range. This way you only end up with
- # maximum of two fragements for each type in the memory map
- # (the memory used, and the free memory that was prereserved
- # but not used).
- #
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
- #
- # ARM PrimeCell
- #
- #
- # ARM OS Loader
- #
- # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/MemoryMapped(0x0,0xED000000,0xED400000)"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
- # Set timer interrupt to be triggerred in 1ms to avoid missing
- # serial terminal input characters.
- gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
- gArmTokenSpaceGuid.PcdVFPEnabled|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32
-[PcdsDynamicHii.common.DEFAULT]
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 # Variable: L"Timeout"
diff --git a/Chips/Hisilicon/Pv660/Pv660.fdf.inc b/Chips/Hisilicon/Pv660/Pv660.fdf.inc deleted file mode 100644 index c5f0e8b..0000000 --- a/Chips/Hisilicon/Pv660/Pv660.fdf.inc +++ /dev/null @@ -1,139 +0,0 @@ -#/** @file -# -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/
-################################################################################ -# -# Rules are use with the [FV] section's module INF type to define -# how an FFS file is created for a given INF file. The following Rule are the default -# rules for the different module type. User can add the customized rules to define the -# content of the FFS file. -# -################################################################################
-############################################################################ -# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # -############################################################################ -# -#[Rule.Common.DXE_DRIVER] -# FILE DRIVER = $(NAMED_GUID) { -# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex -# COMPRESS PI_STD { -# GUIDED { -# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi -# UI STRING="$(MODULE_NAME)" Optional -# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) -# } -# } -# } -# -############################################################################
-[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
- }
-[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING ="$(MODULE_NAME)" Optional
- }
-[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.PEIM.BINARY]
- FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE Align = Auto |.efi
UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.PEIM.TIANOCOMPRESSED]
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
- }
- }
-[Rule.Common.DXE_CORE]
- FILE DXE_CORE = $(NAMED_GUID) {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.UEFI_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.DXE_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.DXE_DRIVER.BINARY]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.DXE_RUNTIME_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
-[Rule.Common.UEFI_APPLICATION]
- FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- }
-[Rule.Common.UEFI_DRIVER.BINARY]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-[Rule.Common.UEFI_APPLICATION.BINARY]
- FILE APPLICATION = $(NAMED_GUID) {
- PE32 PE32 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-[Rule.Common.USER_DEFINED.ACPITABLE]
- FILE FREEFORM = $(NAMED_GUID) {
- RAW ACPI |.acpi
- RAW ASL |.aml
- }
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 2228e51..c000b26 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -30,7 +30,7 @@ FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/D02/$(PLATFORM_NAME).fdf DEFINE INCLUDE_TFTP_COMMAND=1 -!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.dsc.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf index fa0dc2d..34f2368 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.fdf +++ b/Platforms/Hisilicon/D02/Pv660D02.fdf @@ -320,5 +320,5 @@ READ_LOCK_STATUS = TRUE } -!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.fdf.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 7c72c84..9c96952 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -30,7 +30,7 @@ FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf DEFINE INCLUDE_TFTP_COMMAND=1 -!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.dsc.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 8ba3bd0..d4a0049 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -338,5 +338,5 @@ READ_LOCK_STATUS = TRUE } -!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.fdf.inc +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc -- 1.9.1
1. Rename ArmPlatformLibPv660 folder to ArmPlatformLibHisilicon. 2. Modify D02/D03 dsc file accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../ArmPlatformLibHisilicon/AArch64/Helper.S | 61 ++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLib.c | 108 +++++++++++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLib.inf | 69 +++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLibMem.c | 98 +++++++++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLibSec.inf | 56 +++++++++++ .../Library/ArmPlatformLibPv660/AArch64/Helper.S | 61 ------------ .../Library/ArmPlatformLibPv660/ArmPlatformLib.c | 108 --------------------- .../Library/ArmPlatformLibPv660/ArmPlatformLib.inf | 69 ------------- .../ArmPlatformLibPv660/ArmPlatformLibMem.c | 98 ------------------- .../ArmPlatformLibPv660/ArmPlatformLibSec.inf | 56 ----------- Platforms/Hisilicon/D02/Pv660D02.dsc | 6 +- Platforms/Hisilicon/D03/D03.dsc | 6 +- 12 files changed, 398 insertions(+), 398 deletions(-) create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S new file mode 100644 index 0000000..3422df2 --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S @@ -0,0 +1,61 @@ +// +// Copyright (c) 2011-2013, ARM Limited. All rights reserved. +// Copyright (c) 2015, Hisilicon Limited. All rights reserved. +// Copyright (c) 2015, Linaro Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +// +// + +#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h> + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +# IN None +# OUT x0 = number of cores present in the system +ASM_FUNC(ArmGetCpuCountPerCluster) + MOV32 (w0, FixedPcdGet32(PcdCoreCount)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c new file mode 100644 index 0000000..6c85958 --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c @@ -0,0 +1,108 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> + +#include <Ppi/ArmMpCoreInfo.h> + +#include <ArmPlatform.h> +UINTN +ArmGetCpuCountPerCluster ( + VOID + ); + +extern EFI_STATUS MemInitEntry (VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + // Nothing to do here +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + return EFI_UNSUPPORTED; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf new file mode 100644 index 0000000..e86e53e --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf @@ -0,0 +1,69 @@ +#/* @file +# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmPlatformLibPv660 + FILE_GUID = 6887500D-32AD-41cd-855E-F8A5D5B0D4D2 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + IoLib + ArmLib + MemoryAllocationLib + SerialPortLib + +[Sources.common] + ArmPlatformLib.c + ArmPlatformLibMem.c + +[Sources.AARCH64] + AArch64/Helper.S + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gHisiTokenSpaceGuid.PcdNORFlashBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gHisiTokenSpaceGuid.PcdSysControlBaseAddress + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase + diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c new file mode 100644 index 0000000..5bbcab3 --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c @@ -0,0 +1,98 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <ArmPlatform.h> + +#include <Library/OemSetVirtualMapDesc.h> + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_PEI_HOB_POINTERS NextHob; + + ASSERT (VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + Index = OemSetVirtualMapDesc(VirtualMemoryTable, CacheAttributes); + + // Search for System Memory Hob that contains the EFI resource system memory + NextHob.Raw = GetHobList (); + while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) + { + if (NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) + { + if (NextHob.ResourceDescriptor->PhysicalStart > BASE_4GB) + { + VirtualMemoryTable[++Index].PhysicalBase = NextHob.ResourceDescriptor->PhysicalStart; + VirtualMemoryTable[Index].VirtualBase = NextHob.ResourceDescriptor->PhysicalStart; + VirtualMemoryTable[Index].Length =NextHob.ResourceDescriptor->ResourceLength; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + } + } + + NextHob.Raw = GET_NEXT_HOB (NextHob); + } + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG((EFI_D_INFO, "[%a]:[%dL] discriptor count=%d\n", __FUNCTION__, __LINE__, Index+1)); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf new file mode 100644 index 0000000..fa308bd --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf @@ -0,0 +1,56 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmPlatformLibPv660Sec + FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + IoLib + ArmLib + SerialPortLib + +[Sources.common] + ArmPlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S b/Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S deleted file mode 100644 index 3422df2..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S +++ /dev/null @@ -1,61 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// Copyright (c) 2015, Hisilicon Limited. All rights reserved. -// Copyright (c) 2015, Linaro Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -// -// - -#include <AsmMacroIoLibV8.h> -#include <Library/ArmLib.h> - -ASM_FUNC(ArmPlatformPeiBootAction) - ret - -//UINTN -//ArmPlatformGetPrimaryCoreMpId ( -// VOID -// ); -ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) - MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) - ret - -# IN None -# OUT x0 = number of cores present in the system -ASM_FUNC(ArmGetCpuCountPerCluster) - MOV32 (w0, FixedPcdGet32(PcdCoreCount)) - ret - -//UINTN -//ArmPlatformIsPrimaryCore ( -// IN UINTN MpId -// ); -ASM_FUNC(ArmPlatformIsPrimaryCore) - MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) - and x0, x0, x1 - MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) - cmp w0, w1 - cset x0, eq - ret - -//UINTN -//ArmPlatformGetCorePosition ( -// IN UINTN MpId -// ); -// With this function: CorePos = (ClusterId * 4) + CoreId -ASM_FUNC(ArmPlatformGetCorePosition) - and x1, x0, #ARM_CORE_MASK - and x0, x0, #ARM_CLUSTER_MASK - add x0, x1, x0, LSR #6 - ret - -ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c deleted file mode 100644 index 6c85958..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c +++ /dev/null @@ -1,108 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -* -**/ - -#include <Library/IoLib.h> -#include <Library/ArmPlatformLib.h> -#include <Library/DebugLib.h> -#include <Library/PcdLib.h> - -#include <Ppi/ArmMpCoreInfo.h> - -#include <ArmPlatform.h> -UINTN -ArmGetCpuCountPerCluster ( - VOID - ); - -extern EFI_STATUS MemInitEntry (VOID); - -/** - Return the current Boot Mode - - This function returns the boot reason on the platform - - @return Return the current Boot Mode of the platform - -**/ -EFI_BOOT_MODE -ArmPlatformGetBootMode ( - VOID - ) -{ - return BOOT_WITH_FULL_CONFIGURATION; -} - -/** - Initialize controllers that must setup in the normal world - - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim - in the PEI phase. - -**/ -RETURN_STATUS -ArmPlatformInitialize ( - IN UINTN MpId - ) -{ - return RETURN_SUCCESS; -} - -/** - Initialize the system (or sometimes called permanent) memory - - This memory is generally represented by the DRAM. - -**/ -VOID -ArmPlatformInitializeSystemMemory ( - VOID - ) -{ - // Nothing to do here -} - -EFI_STATUS -PrePeiCoreGetMpCoreInfo ( - OUT UINTN *CoreCount, - OUT ARM_CORE_INFO **ArmCoreTable - ) -{ - return EFI_UNSUPPORTED; -} - -// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore -EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; -ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; - -EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &mArmMpCoreInfoPpiGuid, - &mMpCoreInfoPpi - } -}; - -VOID -ArmPlatformGetPlatformPpiList ( - OUT UINTN *PpiListSize, - OUT EFI_PEI_PPI_DESCRIPTOR **PpiList - ) -{ - *PpiListSize = sizeof(gPlatformPpiTable); - *PpiList = gPlatformPpiTable; -} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf deleted file mode 100644 index e86e53e..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf +++ /dev/null @@ -1,69 +0,0 @@ -#/* @file -# Copyright (c) 2011-2014, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -# -#*/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = ArmPlatformLibPv660 - FILE_GUID = 6887500D-32AD-41cd-855E-F8A5D5B0D4D2 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmPlatformLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - - OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec - -[LibraryClasses] - IoLib - ArmLib - MemoryAllocationLib - SerialPortLib - -[Sources.common] - ArmPlatformLib.c - ArmPlatformLibMem.c - -[Sources.AARCH64] - AArch64/Helper.S - -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping - -[FixedPcd] - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdFvBaseAddress - - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdArmPrimaryCore - - gArmPlatformTokenSpaceGuid.PcdCoreCount - - gHisiTokenSpaceGuid.PcdNORFlashBase - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase - gArmTokenSpaceGuid.PcdGicDistributorBase - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase - gHisiTokenSpaceGuid.PcdSysControlBaseAddress - gHisiTokenSpaceGuid.PcdPeriSubctrlAddress - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase - diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c deleted file mode 100644 index 5bbcab3..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c +++ /dev/null @@ -1,98 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -* -**/ - -#include <Library/ArmPlatformLib.h> -#include <Library/DebugLib.h> -#include <Library/HobLib.h> -#include <Library/PcdLib.h> -#include <Library/IoLib.h> -#include <Library/MemoryAllocationLib.h> -#include <ArmPlatform.h> - -#include <Library/OemSetVirtualMapDesc.h> - -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32 - -// DDR attributes -#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK -#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED - -/** - Return the Virtual Memory Map of your platform - - This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. - - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- - Virtual Memory mapping. This array must be ended by a zero-filled - entry - -**/ -VOID -ArmPlatformGetVirtualMemoryMap ( - IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap - ) -{ - ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; - UINTN Index; - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - EFI_PEI_HOB_POINTERS NextHob; - - ASSERT (VirtualMemoryMap != NULL); - - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); - if (VirtualMemoryTable == NULL) { - return; - } - - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = DDR_ATTRIBUTES_CACHED; - } else { - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; - } - - Index = OemSetVirtualMapDesc(VirtualMemoryTable, CacheAttributes); - - // Search for System Memory Hob that contains the EFI resource system memory - NextHob.Raw = GetHobList (); - while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) - { - if (NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) - { - if (NextHob.ResourceDescriptor->PhysicalStart > BASE_4GB) - { - VirtualMemoryTable[++Index].PhysicalBase = NextHob.ResourceDescriptor->PhysicalStart; - VirtualMemoryTable[Index].VirtualBase = NextHob.ResourceDescriptor->PhysicalStart; - VirtualMemoryTable[Index].Length =NextHob.ResourceDescriptor->ResourceLength; - VirtualMemoryTable[Index].Attributes = CacheAttributes; - } - } - - NextHob.Raw = GET_NEXT_HOB (NextHob); - } - - // End of Table - VirtualMemoryTable[++Index].PhysicalBase = 0; - VirtualMemoryTable[Index].VirtualBase = 0; - VirtualMemoryTable[Index].Length = 0; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; - - ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - DEBUG((EFI_D_INFO, "[%a]:[%dL] discriptor count=%d\n", __FUNCTION__, __LINE__, Index+1)); - - *VirtualMemoryMap = VirtualMemoryTable; -} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf deleted file mode 100644 index fa308bd..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf +++ /dev/null @@ -1,56 +0,0 @@ -#/* @file -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -# -#*/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = ArmPlatformLibPv660Sec - FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmPlatformLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - EmbeddedPkg/EmbeddedPkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - -[LibraryClasses] - IoLib - ArmLib - SerialPortLib - -[Sources.common] - ArmPlatformLib.c - -[Sources.AARCH64] - AArch64/Helper.S - -[FeaturePcd] - gEmbeddedTokenSpaceGuid.PcdCacheEnable - gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping - -[FixedPcd] - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - gArmTokenSpaceGuid.PcdFvBaseAddress - - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask - gArmTokenSpaceGuid.PcdArmPrimaryCore - - gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index c000b26..8f840a1 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -34,7 +34,7 @@
[LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf @@ -75,12 +75,12 @@ ## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when ## input signal is de-asserted, except for virtual timer interrupt IRQ #27. ## So we choose to use virtual timer instead of physical one as a workaround. -## This library instance is to override the original define in LibraryClasses.AARCH64 in Pv660.dsc.inc. +## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc. [LibraryClasses.AARCH64] ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf
[LibraryClasses.common.SEC] - ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER] I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 9c96952..c8ee43b 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -34,7 +34,7 @@
[LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf @@ -85,12 +85,12 @@ ## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when ## input signal is de-asserted, except for virtual timer interrupt IRQ #27. ## So we choose to use virtual timer instead of physical one as a workaround. -## This library instance is to override the original define in LibraryClasses.AARCH64 in Pv660.dsc.inc. +## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc. [LibraryClasses.AARCH64] ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf
[LibraryClasses.common.SEC] - ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
On Thu, Nov 10, 2016 at 09:52:23PM +0800, Heyi Guo wrote:
- Rename ArmPlatformLibPv660 folder to ArmPlatformLibHisilicon.
- Modify D02/D03 dsc file accordingly.
Again, useful cleanup.
Comment only: it can be useful to generate patches with --find-copies or --find-copies-harder to make such operations even more clear in the diff.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
.../ArmPlatformLibHisilicon/AArch64/Helper.S | 61 ++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLib.c | 108 +++++++++++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLib.inf | 69 +++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLibMem.c | 98 +++++++++++++++++++ .../ArmPlatformLibHisilicon/ArmPlatformLibSec.inf | 56 +++++++++++ .../Library/ArmPlatformLibPv660/AArch64/Helper.S | 61 ------------ .../Library/ArmPlatformLibPv660/ArmPlatformLib.c | 108 --------------------- .../Library/ArmPlatformLibPv660/ArmPlatformLib.inf | 69 ------------- .../ArmPlatformLibPv660/ArmPlatformLibMem.c | 98 ------------------- .../ArmPlatformLibPv660/ArmPlatformLibSec.inf | 56 ----------- Platforms/Hisilicon/D02/Pv660D02.dsc | 6 +- Platforms/Hisilicon/D03/D03.dsc | 6 +- 12 files changed, 398 insertions(+), 398 deletions(-) create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c create mode 100644 Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c delete mode 100644 Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S new file mode 100644 index 0000000..3422df2 --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/AArch64/Helper.S @@ -0,0 +1,61 @@ +// +// Copyright (c) 2011-2013, ARM Limited. All rights reserved. +// Copyright (c) 2015, Hisilicon Limited. All rights reserved. +// Copyright (c) 2015, Linaro Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +// +//
+#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h>
+ASM_FUNC(ArmPlatformPeiBootAction)
- ret
+//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
- MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
- ret
+# IN None +# OUT x0 = number of cores present in the system +ASM_FUNC(ArmGetCpuCountPerCluster)
- MOV32 (w0, FixedPcdGet32(PcdCoreCount))
- ret
+//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore)
- MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
- and x0, x0, x1
- MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
- cmp w0, w1
- cset x0, eq
- ret
+//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition)
- and x1, x0, #ARM_CORE_MASK
- and x0, x0, #ARM_CLUSTER_MASK
- add x0, x1, x0, LSR #6
- ret
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c new file mode 100644 index 0000000..6c85958 --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c @@ -0,0 +1,108 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +* +**/
+#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+#include <ArmPlatform.h> +UINTN +ArmGetCpuCountPerCluster (
- VOID
- );
+extern EFI_STATUS MemInitEntry (VOID);
+/**
- Return the current Boot Mode
- This function returns the boot reason on the platform
- @return Return the current Boot Mode of the platform
+**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode (
- VOID
- )
+{
- return BOOT_WITH_FULL_CONFIGURATION;
+}
+/**
- Initialize controllers that must setup in the normal world
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
- in the PEI phase.
+**/ +RETURN_STATUS +ArmPlatformInitialize (
- IN UINTN MpId
- )
+{
- return RETURN_SUCCESS;
+}
+/**
- Initialize the system (or sometimes called permanent) memory
- This memory is generally represented by the DRAM.
+**/ +VOID +ArmPlatformInitializeSystemMemory (
- VOID
- )
+{
- // Nothing to do here
+}
+EFI_STATUS +PrePeiCoreGetMpCoreInfo (
- OUT UINTN *CoreCount,
- OUT ARM_CORE_INFO **ArmCoreTable
- )
+{
- return EFI_UNSUPPORTED;
+}
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &mArmMpCoreInfoPpiGuid,
- &mMpCoreInfoPpi
- }
+};
+VOID +ArmPlatformGetPlatformPpiList (
- OUT UINTN *PpiListSize,
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
- )
+{
- *PpiListSize = sizeof(gPlatformPpiTable);
- *PpiList = gPlatformPpiTable;
+} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf new file mode 100644 index 0000000..e86e53e --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf @@ -0,0 +1,69 @@ +#/* @file +# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +# +#*/
+[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformLibPv660
- FILE_GUID = 6887500D-32AD-41cd-855E-F8A5D5B0D4D2
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmPlatformLib
+[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- IoLib
- ArmLib
- MemoryAllocationLib
- SerialPortLib
+[Sources.common]
- ArmPlatformLib.c
- ArmPlatformLibMem.c
+[Sources.AARCH64]
- AArch64/Helper.S
+[FeaturePcd]
- gEmbeddedTokenSpaceGuid.PcdCacheEnable
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+[FixedPcd]
- gArmTokenSpaceGuid.PcdSystemMemoryBase
- gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmTokenSpaceGuid.PcdFvBaseAddress
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gHisiTokenSpaceGuid.PcdNORFlashBase
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c new file mode 100644 index 0000000..5bbcab3 --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c @@ -0,0 +1,98 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +* +**/
+#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <ArmPlatform.h>
+#include <Library/OemSetVirtualMapDesc.h>
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32
+// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+/**
- Return the Virtual Memory Map of your platform
- This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
+**/ +VOID +ArmPlatformGetVirtualMemoryMap (
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
- )
+{
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
- UINTN Index;
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- EFI_PEI_HOB_POINTERS NextHob;
- ASSERT (VirtualMemoryMap != NULL);
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
- if (VirtualMemoryTable == NULL) {
return;
- }
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
CacheAttributes = DDR_ATTRIBUTES_CACHED;
- } else {
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
- }
- Index = OemSetVirtualMapDesc(VirtualMemoryTable, CacheAttributes);
- // Search for System Memory Hob that contains the EFI resource system memory
- NextHob.Raw = GetHobList ();
- while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL)
- {
- if (NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)
- {
if (NextHob.ResourceDescriptor->PhysicalStart > BASE_4GB)
{
VirtualMemoryTable[++Index].PhysicalBase = NextHob.ResourceDescriptor->PhysicalStart;
VirtualMemoryTable[Index].VirtualBase = NextHob.ResourceDescriptor->PhysicalStart;
VirtualMemoryTable[Index].Length =NextHob.ResourceDescriptor->ResourceLength;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
- }
- NextHob.Raw = GET_NEXT_HOB (NextHob);
- }
- // End of Table
- VirtualMemoryTable[++Index].PhysicalBase = 0;
- VirtualMemoryTable[Index].VirtualBase = 0;
- VirtualMemoryTable[Index].Length = 0;
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
- ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
- DEBUG((EFI_D_INFO, "[%a]:[%dL] discriptor count=%d\n", __FUNCTION__, __LINE__, Index+1));
- *VirtualMemoryMap = VirtualMemoryTable;
+} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf new file mode 100644 index 0000000..fa308bd --- /dev/null +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf @@ -0,0 +1,56 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ +# +#*/
+[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformLibPv660Sec
- FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmPlatformLib
+[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
+[LibraryClasses]
- IoLib
- ArmLib
- SerialPortLib
+[Sources.common]
- ArmPlatformLib.c
+[Sources.AARCH64]
- AArch64/Helper.S
+[FeaturePcd]
- gEmbeddedTokenSpaceGuid.PcdCacheEnable
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+[FixedPcd]
- gArmTokenSpaceGuid.PcdSystemMemoryBase
- gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmTokenSpaceGuid.PcdFvBaseAddress
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S b/Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S deleted file mode 100644 index 3422df2..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/AArch64/Helper.S +++ /dev/null @@ -1,61 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// Copyright (c) 2015, Hisilicon Limited. All rights reserved. -// Copyright (c) 2015, Linaro Limited. All rights reserved. -// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -// -//
-#include <AsmMacroIoLibV8.h> -#include <Library/ArmLib.h>
-ASM_FUNC(ArmPlatformPeiBootAction)
- ret
-//UINTN -//ArmPlatformGetPrimaryCoreMpId ( -// VOID -// ); -ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
- MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
- ret
-# IN None -# OUT x0 = number of cores present in the system -ASM_FUNC(ArmGetCpuCountPerCluster)
- MOV32 (w0, FixedPcdGet32(PcdCoreCount))
- ret
-//UINTN -//ArmPlatformIsPrimaryCore ( -// IN UINTN MpId -// ); -ASM_FUNC(ArmPlatformIsPrimaryCore)
- MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
- and x0, x0, x1
- MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
- cmp w0, w1
- cset x0, eq
- ret
-//UINTN -//ArmPlatformGetCorePosition ( -// IN UINTN MpId -// ); -// With this function: CorePos = (ClusterId * 4) + CoreId -ASM_FUNC(ArmPlatformGetCorePosition)
- and x1, x0, #ARM_CORE_MASK
- and x0, x0, #ARM_CLUSTER_MASK
- add x0, x1, x0, LSR #6
- ret
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c deleted file mode 100644 index 6c85958..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.c +++ /dev/null @@ -1,108 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -* -**/
-#include <Library/IoLib.h> -#include <Library/ArmPlatformLib.h> -#include <Library/DebugLib.h> -#include <Library/PcdLib.h>
-#include <Ppi/ArmMpCoreInfo.h>
-#include <ArmPlatform.h> -UINTN -ArmGetCpuCountPerCluster (
- VOID
- );
-extern EFI_STATUS MemInitEntry (VOID);
-/**
- Return the current Boot Mode
- This function returns the boot reason on the platform
- @return Return the current Boot Mode of the platform
-**/ -EFI_BOOT_MODE -ArmPlatformGetBootMode (
- VOID
- )
-{
- return BOOT_WITH_FULL_CONFIGURATION;
-}
-/**
- Initialize controllers that must setup in the normal world
- This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
- in the PEI phase.
-**/ -RETURN_STATUS -ArmPlatformInitialize (
- IN UINTN MpId
- )
-{
- return RETURN_SUCCESS;
-}
-/**
- Initialize the system (or sometimes called permanent) memory
- This memory is generally represented by the DRAM.
-**/ -VOID -ArmPlatformInitializeSystemMemory (
- VOID
- )
-{
- // Nothing to do here
-}
-EFI_STATUS -PrePeiCoreGetMpCoreInfo (
- OUT UINTN *CoreCount,
- OUT ARM_CORE_INFO **ArmCoreTable
- )
-{
- return EFI_UNSUPPORTED;
-}
-// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore -EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; -ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &mArmMpCoreInfoPpiGuid,
- &mMpCoreInfoPpi
- }
-};
-VOID -ArmPlatformGetPlatformPpiList (
- OUT UINTN *PpiListSize,
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
- )
-{
- *PpiListSize = sizeof(gPlatformPpiTable);
- *PpiList = gPlatformPpiTable;
-} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf deleted file mode 100644 index e86e53e..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf +++ /dev/null @@ -1,69 +0,0 @@ -#/* @file -# Copyright (c) 2011-2014, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -# -#*/
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformLibPv660
- FILE_GUID = 6887500D-32AD-41cd-855E-F8A5D5B0D4D2
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmPlatformLib
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
-[LibraryClasses]
- IoLib
- ArmLib
- MemoryAllocationLib
- SerialPortLib
-[Sources.common]
- ArmPlatformLib.c
- ArmPlatformLibMem.c
-[Sources.AARCH64]
- AArch64/Helper.S
-[FeaturePcd]
- gEmbeddedTokenSpaceGuid.PcdCacheEnable
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
-[FixedPcd]
- gArmTokenSpaceGuid.PcdSystemMemoryBase
- gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmTokenSpaceGuid.PcdFvBaseAddress
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gHisiTokenSpaceGuid.PcdNORFlashBase
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c deleted file mode 100644 index 5bbcab3..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibMem.c +++ /dev/null @@ -1,98 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2014, ARM Limited. All rights reserved. -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -* Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -* -**/
-#include <Library/ArmPlatformLib.h> -#include <Library/DebugLib.h> -#include <Library/HobLib.h> -#include <Library/PcdLib.h> -#include <Library/IoLib.h> -#include <Library/MemoryAllocationLib.h> -#include <ArmPlatform.h>
-#include <Library/OemSetVirtualMapDesc.h>
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32
-// DDR attributes -#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK -#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
-/**
- Return the Virtual Memory Map of your platform
- This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
-**/ -VOID -ArmPlatformGetVirtualMemoryMap (
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
- )
-{
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
- UINTN Index;
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- EFI_PEI_HOB_POINTERS NextHob;
- ASSERT (VirtualMemoryMap != NULL);
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
- if (VirtualMemoryTable == NULL) {
return;
- }
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
CacheAttributes = DDR_ATTRIBUTES_CACHED;
- } else {
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
- }
- Index = OemSetVirtualMapDesc(VirtualMemoryTable, CacheAttributes);
- // Search for System Memory Hob that contains the EFI resource system memory
- NextHob.Raw = GetHobList ();
- while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL)
- {
- if (NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)
- {
if (NextHob.ResourceDescriptor->PhysicalStart > BASE_4GB)
{
VirtualMemoryTable[++Index].PhysicalBase = NextHob.ResourceDescriptor->PhysicalStart;
VirtualMemoryTable[Index].VirtualBase = NextHob.ResourceDescriptor->PhysicalStart;
VirtualMemoryTable[Index].Length =NextHob.ResourceDescriptor->ResourceLength;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
- }
- NextHob.Raw = GET_NEXT_HOB (NextHob);
- }
- // End of Table
- VirtualMemoryTable[++Index].PhysicalBase = 0;
- VirtualMemoryTable[Index].VirtualBase = 0;
- VirtualMemoryTable[Index].Length = 0;
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
- ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
- DEBUG((EFI_D_INFO, "[%a]:[%dL] discriptor count=%d\n", __FUNCTION__, __LINE__, Index+1));
- *VirtualMemoryMap = VirtualMemoryTable;
-} diff --git a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf b/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf deleted file mode 100644 index fa308bd..0000000 --- a/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf +++ /dev/null @@ -1,56 +0,0 @@ -#/* @file -# Copyright (c) 2011-2012, ARM Limited. All rights reserved. -# Copyright (c) 2015, Hisilicon Limited. All rights reserved. -# Copyright (c) 2015, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Based on the files under ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ -# -#*/
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformLibPv660Sec
- FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ArmPlatformLib
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-[LibraryClasses]
- IoLib
- ArmLib
- SerialPortLib
-[Sources.common]
- ArmPlatformLib.c
-[Sources.AARCH64]
- AArch64/Helper.S
-[FeaturePcd]
- gEmbeddedTokenSpaceGuid.PcdCacheEnable
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
-[FixedPcd]
- gArmTokenSpaceGuid.PcdSystemMemoryBase
- gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmTokenSpaceGuid.PcdFvBaseAddress
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index c000b26..8f840a1 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -34,7 +34,7 @@ [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf @@ -75,12 +75,12 @@ ## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when ## input signal is de-asserted, except for virtual timer interrupt IRQ #27. ## So we choose to use virtual timer instead of physical one as a workaround. -## This library instance is to override the original define in LibraryClasses.AARCH64 in Pv660.dsc.inc. +## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc. [LibraryClasses.AARCH64] ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf [LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER] I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 9c96952..c8ee43b 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -34,7 +34,7 @@ [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf @@ -85,12 +85,12 @@ ## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when ## input signal is de-asserted, except for virtual timer interrupt IRQ #27. ## So we choose to use virtual timer instead of physical one as a workaround. -## This library instance is to override the original define in LibraryClasses.AARCH64 in Pv660.dsc.inc. +## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc. [LibraryClasses.AARCH64] ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf [LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER] -- 1.9.1
1. D02/D03: Remove ARMVExpressPkg platform include path from build option. 2. Delete ArmPlatform.h header which is not used by Hisilicon platforms.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c | 1 - Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c | 1 - Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c index 6c85958..07ab0d1 100644 --- a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c @@ -23,7 +23,6 @@
#include <Ppi/ArmMpCoreInfo.h>
-#include <ArmPlatform.h> UINTN ArmGetCpuCountPerCluster ( VOID diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c index 5bbcab3..b7bc75d 100644 --- a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c @@ -22,7 +22,6 @@ #include <Library/PcdLib.h> #include <Library/IoLib.h> #include <Library/MemoryAllocationLib.h> -#include <ArmPlatform.h>
#include <Library/OemSetVirtualMapDesc.h>
diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 8f840a1..9c23fa7 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -86,7 +86,7 @@ I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
[BuildOptions] - GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Pv660/Include + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Pv660/Include
################################################################################ diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index c8ee43b..b853c69 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -98,7 +98,7 @@ SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf
[BuildOptions] - GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Include + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Include
################################################################################ #
On Thu, Nov 10, 2016 at 09:52:24PM +0800, Heyi Guo wrote:
- D02/D03: Remove ARMVExpressPkg platform include path from build option.
- Delete ArmPlatform.h header which is not used by Hisilicon platforms.
Splendid!
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Reviewed-by: Leif Lindholm leif.lindholm@linaro.org
Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c | 1 - Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c | 1 - Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c index 6c85958..07ab0d1 100644 --- a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.c @@ -23,7 +23,6 @@ #include <Ppi/ArmMpCoreInfo.h> -#include <ArmPlatform.h> UINTN ArmGetCpuCountPerCluster ( VOID diff --git a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c index 5bbcab3..b7bc75d 100644 --- a/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c +++ b/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibMem.c @@ -22,7 +22,6 @@ #include <Library/PcdLib.h> #include <Library/IoLib.h> #include <Library/MemoryAllocationLib.h> -#include <ArmPlatform.h> #include <Library/OemSetVirtualMapDesc.h> diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 8f840a1..9c23fa7 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -86,7 +86,7 @@ I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf [BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Pv660/Include
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Pv660/Include
################################################################################ diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index c8ee43b..b853c69 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -98,7 +98,7 @@ SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf [BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Include
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Include
################################################################################
#
1.9.1
The Hisilicon platforms only have 1GB memroy tested before BDS phase, and our platforms require uefi not using memory above 4GB. In order to promote the memory above 4GB,we need to perform MemoryTest.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Hisilicon/Drivers/PlatformBoot/PlatformBoot.c | 58 ++++++++++++++++++++++ .../Drivers/PlatformBoot/PlatformBoot.inf | 42 ++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c create mode 100644 Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf
diff --git a/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c new file mode 100644 index 0000000..9f977e6 --- /dev/null +++ b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c @@ -0,0 +1,58 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Uefi.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/GenericMemoryTest.h> + +EFI_STATUS +EFIAPI PlatformBootInit( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_GENERIC_MEMORY_TEST_PROTOCOL* MemoryTest = NULL; + BOOLEAN RequireSoftECCInit = FALSE; + UINT64 TestedMemorySize; + UINT64 TotalMemorySize; + BOOLEAN TestAbort = FALSE; + BOOLEAN ErrorOut; + + //The Hisilicon platforms only have 1GB memroy tested before BDS phase, and our platforms require + //uefi not using memory above 4GB. + //In order to promote the memory above 4GB,we need to perform MemoryTest. + Status = gBS->LocateProtocol(&gEfiGenericMemTestProtocolGuid, NULL, (VOID**)&MemoryTest); + if (!EFI_ERROR(Status)) { + (VOID)MemoryTest->MemoryTestInit (MemoryTest, IGNORE, &RequireSoftECCInit); + DEBUG ((DEBUG_INFO,"MemoryTestInit done.\n")); + } + Status = MemoryTest->PerformMemoryTest ( + MemoryTest, + &TestedMemorySize, + &TotalMemorySize, + &ErrorOut, + TestAbort + ); + if (ErrorOut && (Status == EFI_DEVICE_ERROR)) { + DEBUG((DEBUG_INFO, "PerformMemoryTest error occur!\n")); + return Status; + } else { + DEBUG ((DEBUG_INFO, "%d bytes of system memory tested OK\r\n", TotalMemorySize)); + } + Status = MemoryTest->Finished (MemoryTest); + return Status; +} diff --git a/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf new file mode 100644 index 0000000..4763cc4 --- /dev/null +++ b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf @@ -0,0 +1,42 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = PlatformBoot + FILE_GUID = 9A6C7020-12E8-4198-9BE2-1785ABC8CA8B + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformBootInit + +[Sources] + PlatformBoot.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiGenericMemTestProtocolGuid + +[Guids] + +[Depex] + gEfiGenericMemTestProtocolGuid
On Thu, Nov 10, 2016 at 09:52:25PM +0800, Heyi Guo wrote:
The Hisilicon platforms only have 1GB memroy tested before BDS phase, and our platforms require uefi not using memory above 4GB. In order to promote the memory above 4GB,we need to perform MemoryTest.
Sorry, but this message is slightly confusing. Platforms require not using memory above 4GB?
Regards,
Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Hisilicon/Drivers/PlatformBoot/PlatformBoot.c | 58 ++++++++++++++++++++++ .../Drivers/PlatformBoot/PlatformBoot.inf | 42 ++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c create mode 100644 Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf
diff --git a/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c new file mode 100644 index 0000000..9f977e6 --- /dev/null +++ b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.c @@ -0,0 +1,58 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <Uefi.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/GenericMemoryTest.h>
+EFI_STATUS +EFIAPI PlatformBootInit(
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
+{
- EFI_STATUS Status = EFI_SUCCESS;
- EFI_GENERIC_MEMORY_TEST_PROTOCOL* MemoryTest = NULL;
- BOOLEAN RequireSoftECCInit = FALSE;
- UINT64 TestedMemorySize;
- UINT64 TotalMemorySize;
- BOOLEAN TestAbort = FALSE;
- BOOLEAN ErrorOut;
- //The Hisilicon platforms only have 1GB memroy tested before BDS phase, and our platforms require
- //uefi not using memory above 4GB.
- //In order to promote the memory above 4GB,we need to perform MemoryTest.
- Status = gBS->LocateProtocol(&gEfiGenericMemTestProtocolGuid, NULL, (VOID**)&MemoryTest);
- if (!EFI_ERROR(Status)) {
- (VOID)MemoryTest->MemoryTestInit (MemoryTest, IGNORE, &RequireSoftECCInit);
- DEBUG ((DEBUG_INFO,"MemoryTestInit done.\n"));
- }
- Status = MemoryTest->PerformMemoryTest (
MemoryTest,
&TestedMemorySize,
&TotalMemorySize,
&ErrorOut,
TestAbort
);
- if (ErrorOut && (Status == EFI_DEVICE_ERROR)) {
- DEBUG((DEBUG_INFO, "PerformMemoryTest error occur!\n"));
- return Status;
- } else {
- DEBUG ((DEBUG_INFO, "%d bytes of system memory tested OK\r\n", TotalMemorySize));
- }
- Status = MemoryTest->Finished (MemoryTest);
- return Status;
+} diff --git a/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf new file mode 100644 index 0000000..4763cc4 --- /dev/null +++ b/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf @@ -0,0 +1,42 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformBoot
- FILE_GUID = 9A6C7020-12E8-4198-9BE2-1785ABC8CA8B
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = PlatformBootInit
+[Sources]
- PlatformBoot.c
+[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
+[LibraryClasses]
- DebugLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
+[Protocols]
- gEfiGenericMemTestProtocolGuid
+[Guids]
+[Depex]
- gEfiGenericMemTestProtocolGuid
-- 1.9.1
D05 is a new Hisilicon reference hardware platform, which is a dual socket SMP system and has 32 cores on each socket.
Binary modules will be uploaded in following separate patches.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 78 +++ Chips/Hisilicon/HisiPkg.dec | 3 + Platforms/Hisilicon/D05/D05.dsc | 684 +++++++++++++++++++++ Platforms/Hisilicon/D05/D05.fdf | 369 +++++++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 61 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 ++ .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 218 +++++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 ++ .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 ++++++ 12 files changed, 2146 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h new file mode 100644 index 0000000..4bc1c91 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -0,0 +1,78 @@ +#ifndef _SERDES_LIB_H_ +#define _SERDES_LIB_H_ + +typedef enum hilink0_mode_type +{ + EM_HILINK0_HCCS1_8LANE = 0, + EM_HILINK0_PCIE1_8LANE = 2, + EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3, + EM_HILINK0_SAS2_8LANE = 4, + EM_HILINK0_HCCS1_8LANE_16, + EM_HILINK0_HCCS1_8LANE_32, + EM_HILINK0_HCCS1_8LANE_5000, +}hilink0_mode_type_e; + +typedef enum hilink1_mode_type +{ + EM_HILINK1_SAS2_1LANE = 0, + EM_HILINK1_HCCS0_8LANE = 1, + EM_HILINK1_PCIE0_8LANE = 2, + EM_HILINK1_HCCS0_8LANE_16, + EM_HILINK1_HCCS0_8LANE_32, + EM_HILINK1_HCCS0_8LANE_5000, +}hilink1_mode_type_e; + +typedef enum hilink2_mode_type +{ + EM_HILINK2_PCIE2_8LANE = 0, + EM_HILINK2_HCCS2_8LANE = 1, + EM_HILINK2_SAS0_8LANE = 2, + EM_HILINK2_HCCS2_8LANE_16, + EM_HILINK2_HCCS2_8LANE_32, + EM_HILINK2_HCCS2_8LANE_5000, +}hilink2_mode_type_e; + +typedef enum hilink5_mode_type +{ + EM_HILINK5_PCIE3_4LANE = 0, + EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1, + EM_HILINK5_SAS1_4LANE = 2, + +}hilink5_mode_type_e; + + +typedef struct serdes_param +{ + hilink0_mode_type_e hilink0_mode; + hilink1_mode_type_e hilink1_mode; + hilink2_mode_type_e hilink2_mode; + UINT32 hilink3_mode; + UINT32 hilink4_mode; + hilink5_mode_type_e hilink5_mode; + UINT32 hilink6_mode; + UINT32 use_ssc; + //board_type_e board_type; +}serdes_param_t; + +#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF + +typedef struct { + UINT32 MacroId; + UINT32 DsNum; + UINT32 DsCfg; +} SERDES_POLARITY_INVERT; + +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +void serdes_enable_ctle_dfe(UINT32 nimbus_id, UINT32 macro, UINT32 lane, UINT32 lane_mode); + +EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro); + +#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 39dd75a..4bf44cc 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a + gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b + gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
+ gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d
gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038 diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..148e617 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,684 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = D05 + PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf + DEFINE EDK2_SKIP_PEICORE=0 + DEFINE INCLUDE_TFTP_COMMAND=1 + DEFINE NETWORK_IP6_ENABLE = FALSE + DEFINE HTTP_BOOT_ENABLE = FALSE + +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + + + I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf + + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + BootMaintenanceManagerUiLib|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + +!if $(NETWORK_IP6_ENABLE) == TRUE + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf +!endif + +!if $(HTTP_BOOT_ENABLE) == TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + +!ifdef $(FDT_ENABLE) + #FDTUpdateLib + FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf +!endif #$(FDT_ENABLE) + + CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf + + SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf + + EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf + #D05 RTC hardware is same as D03 + RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf + + OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf + OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf + PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + +[LibraryClasses.common.SEC] + ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf + + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + +[BuildOptions] + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + +!if $(EDK2_SKIP_PEICORE) == 1 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05" + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 + + + gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 + + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 + + gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1 + + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 + + + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 + + ## Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + # use the TTY terminal type (which has a working backspace) + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + + gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 + gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 + gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 + gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 + + + gHisiTokenSpaceGuid.PcdIsMPBoot|1 + gHisiTokenSpaceGuid.PcdSocketMask|0x3 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1" + + gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" + + gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12" + + gHisiTokenSpaceGuid.PcdSystemProductName|L"D05" + gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" + gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05" + gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" + + gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616" + + + gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000 + + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM Architectual Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + + gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 + gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 + + gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000 + + gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000 + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000 + + + gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128 + + + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000 + + + gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000 + + ## DTB address at spi flash + gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000 + + gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1 + + gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000 + + gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000 + + gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000 + + gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000 + gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000 + + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 + gHisiTokenSpaceGuid.PcdNumaEnable|1 + gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000 + + gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000 + + + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000 + gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000 + gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000 + gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000 + gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000 + gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000 + gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000 + gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000 + gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000 + gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000 + gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000 + gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000 + gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000 + gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000 + gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000 + gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K + + gHisiTokenSpaceGuid.Pcdsoctype|0x1610 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf + + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug. + #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + <LibraryClasses> + CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf + } + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + # + #ACPI + # + OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + # Usb Support + # + OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf + + # + #network + # + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf + + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + NetworkPkg/Ip6Dxe/Ip6Dxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf +!endif + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) == TRUE + NetworkPkg/DnsDxe/DnsDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/HttpDxe/HttpDxe.inf + NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif + + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + + OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + +!ifdef $(FDT_ENABLE) + OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +!endif #$(FDT_ENABLE) + + #PCIe Support + OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf { + <LibraryClasses> + NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + <LibraryClasses> + NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + + OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + # Memory test + # + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + <LibraryClasses> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf +!endif + +!ifdef $(INCLUDE_DP) + NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf +!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND) + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..5f48936 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,369 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[DEFINES] + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05] + +BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. + +Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv + +0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin + +0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 + 0xB8, 0xdF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, + 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + + # + # Usb Support + # + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + #ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf + + INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + #Network + # + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf + + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf +!endif + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) == TRUE + INF NetworkPkg/DnsDxe/DnsDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif + +!ifdef $(FDT_ENABLE) + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +!endif #$(FDT_ENABLE) + + # + # PCI Support + # + INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + # VGA Driver + # + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf + # + # UEFI application (Shell Embedded Boot Loader) + # + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf + + # + # Build Shell from latest source code instead of prebuilt binary + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + } + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc + diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..55aacc8 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,61 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + + +#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h> + +VOID QResetAp(VOID) +{ + MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0); + (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); + + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { + StartupAp(); + } +} + + +EFI_STATUS +EFIAPI +EarlyConfigEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG((DEBUG_INFO,"SMMU CONFIG.........")); + (VOID)SmmuConfigForBios(); + DEBUG((DEBUG_INFO,"Done\n")); + + DEBUG((DEBUG_INFO,"AP CONFIG.........")); + (VOID)QResetAp(); + DEBUG((DEBUG_INFO,"Done\n")); + + DEBUG((DEBUG_INFO,"MN CONFIG.........")); + (VOID)MN_CONFIG(); + DEBUG((DEBUG_INFO,"Done\n")); + + return EFI_SUCCESS; +} + diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = EarlyConfigPeimD05 + FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = EarlyConfigEntry + +[Sources.common] + EarlyConfigPeimD05.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + ArmLib + CacheMaintenanceLib + DebugLib + IoLib + PcdLib + PeimEntryPoint + PlatformSysCtrlLib + +[Pcd] + gHisiTokenSpaceGuid.PcdMailBoxAddress + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + +[Depex] +## As we will clean mailbox in this module, need to wait memory init complete + gEfiPeiMemoryDiscoveredPpiGuid + +[BuildOptions] + diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..f49b2bc --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,218 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h> + + +I2C_DEVICE gDS3231RtcDevice = { + .Socket = 0, + .Port = 4, + .DeviceType = DEVICE_TYPE_SPD, + .SlaveDeviceAddress = 0x68 +}; + +SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = { + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = { + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +serdes_param_t gSerdesParamNA = { + .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16, + .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16, + .hilink2_mode = EM_HILINK2_PCIE2_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_SAS1_4LANE, + .hilink6_mode = 0x0, + .use_ssc = 0, + }; + +serdes_param_t gSerdesParamNB = { + .hilink0_mode = EM_HILINK0_PCIE1_8LANE, + .hilink1_mode = EM_HILINK1_PCIE0_8LANE, + .hilink2_mode = EM_HILINK2_SAS0_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE, + .hilink6_mode = 0xF, + .use_ssc = 0, + }; + +serdes_param_t gSerdesParamS1NA = { + .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16, + .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16, + .hilink2_mode = EM_HILINK2_PCIE2_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_SAS1_4LANE, + .hilink6_mode = 0x0, + .use_ssc = 0, + }; + +serdes_param_t gSerdesParamS1NB = { + .hilink0_mode = EM_HILINK0_PCIE1_8LANE, + .hilink1_mode = EM_HILINK1_PCIE0_8LANE, + .hilink2_mode = EM_HILINK2_SAS0_8LANE, + .hilink3_mode = 0x0, + .hilink4_mode = 0xF, + .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE, + .hilink6_mode = 0xF, + .use_ssc = 0, + }; + + +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) +{ + if ( ParamA == NULL) { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + if (ParamB == NULL) { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + if(SocketId == 0) { + (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA)); + (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB)); + } else { + (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA)); + (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB)); + } + + return EFI_SUCCESS; +} + +VOID OemPcieResetAndOffReset(VOID) +{ + return; +} + +SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { + // PCIe0 Slot 1 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0001, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + + // PCIe0 Slot 4 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0004, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + } +}; + + +UINT8 OemGetPcieSlotNumber () +{ + return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); +} + +EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { + {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}}, + + {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}} +}; + +EFI_HII_HANDLE +EFIAPI +OemGetPackages ( + ) +{ + return HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + OemMiscLibHi1616EvbStrings, + NULL, + NULL + ); +} + + diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/ + +/=# + +#langdef en-US "English" + +// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" + +// +// DIMM Device Locator strings + +#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28" + +// +// End English Language Strings +// + diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..149bb7d --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <PlatformArch.h> +#include <Uefi.h> + +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h> + +#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2 + +REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { + {67,0,0,0}, + {225,0,0,3}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF} +}; + + +BOOLEAN OemIsSocketPresent (UINTN Socket) +{ + if (PcdGet32(PcdSocketMask) & (1 << Socket)) { + return TRUE; + } else { + return FALSE; + } +} + + +UINTN OemGetSocketNumber (VOID) +{ + + if(!OemIsMpBoot()) { + return OEM_SINGLE_SOCKET; + } + + return OEM_DUAL_SOCKET; +} + + +UINTN OemGetDdrChannel (VOID) +{ + return 4; +} + + +UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{ + return 2; +} + +VOID CoreSelectBoot(VOID) +{ + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { + StartupAp (); + } + + return; +} + +BOOLEAN OemIsMpBoot() +{ + return PcdGet32(PcdIsMPBoot); +} + +VOID OemLpcInit(VOID) +{ + LpcInit(); + return; +} + +UINT32 OemIsWarmBoot(VOID) +{ + return 0; +} + +VOID OemBiosSwitch(UINT32 Master) +{ + (VOID)Master; + return; +} + +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{ + return TRUE; +} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = OemMiscLibHi1616Evb + FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OemMiscLib + +[Sources.common] + BoardFeatureD05.c + BoardFeatureD05Strings.uni + OemMiscLibD05.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + TimerLib + +[BuildOptions] + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES + +[Pcd] + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz + gHisiTokenSpaceGuid.PcdIsMPBoot + gHisiTokenSpaceGuid.PcdSocketMask + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + +[FixedPcd.common] + +[Guids] + +[Protocols] + diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file + + Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> + Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> + +UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000}, + {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}}; +UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000}, + {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}}; +UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000}, + {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}}; +UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040}, + {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}}; + +PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { + {// HostBridge 0 + /* Port 0 */ + { + PCI_HB0RB0_ECAM_BASE, //ecam + 0x80, //BusBase + 0x87, //BusLimit + PCI_HB0RB0_PCIREGION_BASE, //Membase + PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit + PCI_HB0RB0_IO_BASE, //IoBase + (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB0_PCI_BASE),//RbPciBar + PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 1 */ + { + PCI_HB0RB1_ECAM_BASE,//ecam + 0x90, //BusBase + 0x97, //BusLimit + PCI_HB0RB1_PCIREGION_BASE, //Membase + PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB1_IO_BASE), //IoBase + (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit + PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 2 */ + { + PCI_HB0RB2_ECAM_BASE, + 0x80, //BusBase + 0x87, //BusLimit + PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase + PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB2_IO_BASE), //IOBase + (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit + PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 3 */ + { + PCI_HB0RB3_ECAM_BASE, + 0xb0, //BusBase + 0xb7, //BusLimit + (PCI_HB0RB3_ECAM_BASE), //MemBase + (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit + (PCI_HB0RB3_IO_BASE), //IoBase + (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit + PCI_HB0RB3_CPUMEMREGIONBASE, + PCI_HB0RB3_CPUIOREGIONBASE, + (PCI_HB0RB3_PCI_BASE), //RbPciBar + PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 4 */ + { + PCI_HB0RB4_ECAM_BASE, //ecam + 0x88, //BusBase + 0x8f, //BusLimit + PCI_HB0RB4_CPUMEMREGIONBASE, //Membase + PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit + PCI_HB0RB4_IO_BASE, //IoBase + (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit + PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB4_PCI_BASE), //RbPciBar + PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 5 */ + { + PCI_HB0RB5_ECAM_BASE,//ecam + 0x0, //BusBase + 0x7, //BusLimit + PCI_HB0RB5_CPUMEMREGIONBASE, //Membase + PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB5_IO_BASE), //IoBase + (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit + PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB5_PCI_BASE), //RbPciBar + PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 6 */ + { + PCI_HB0RB6_ECAM_BASE, + 0xC0, //BusBase + 0xC7, //BusLimit + PCI_HB0RB6_PCIREGION_BASE ,//MemBase + PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB6_IO_BASE), //IOBase + (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit + PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB6_PCI_BASE), //RbPciBar + PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 7 */ + { + PCI_HB0RB7_ECAM_BASE, + 0x90, //BusBase + 0x97, //BusLimit + PCI_HB0RB7_CPUMEMREGIONBASE, //MemBase + PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB7_IO_BASE), //IoBase + (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit + PCI_HB0RB7_CPUMEMREGIONBASE, + PCI_HB0RB7_CPUIOREGIONBASE, + (PCI_HB0RB7_PCI_BASE), //RbPciBar + PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit + } + }, +{// HostBridge 1 + /* Port 0 */ + { + PCI_HB1RB0_ECAM_BASE, + 0x80, //BusBase + 0x87, //BusLimit + (PCI_HB1RB0_ECAM_BASE), //MemBase + (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB0_IO_BASE, //IoBase + (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB0_PCI_BASE), //RbPciBar + PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 1 */ + { + PCI_HB1RB1_ECAM_BASE, + 0x90, //BusBase + 0x97, //BusLimit + (PCI_HB1RB1_ECAM_BASE), //MemBase + (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB1_IO_BASE, //IoBase + (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB1_PCI_BASE), //RbPciBar + PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 2 */ + { + PCI_HB1RB2_ECAM_BASE, + 0x10, //BusBase + 0x1f, //BusLimit + PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB2_IO_BASE, //IoBase + (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB2_PCI_BASE), //RbPciBar + PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 3 */ + { + PCI_HB1RB3_ECAM_BASE, + 0xb0, //BusBase + 0xb7, //BusLimit + (PCI_HB1RB3_ECAM_BASE), //MemBase + (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB3_IO_BASE, //IoBase + (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB3_PCI_BASE), //RbPciBar + PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 4 */ + { + PCI_HB1RB4_ECAM_BASE, + 0x20, //BusBase + 0x2f, //BusLimit + PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB4_IO_BASE, //IoBase + (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB4_PCI_BASE), //RbPciBar + PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 5 */ + { + PCI_HB1RB5_ECAM_BASE, + 0x30, //BusBase + 0x3f, //BusLimit + PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB5_IO_BASE, //IoBase + (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB5_PCI_BASE), //RbPciBar + PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 6 */ + { + PCI_HB1RB6_ECAM_BASE, + 0xa8, //BusBase + 0xaf, //BusLimit + (PCI_HB1RB6_ECAM_BASE), //MemBase + PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB6_IO_BASE, //IoBase + (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB6_PCI_BASE), //RbPciBar + PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 7 */ + { + PCI_HB1RB7_ECAM_BASE, + 0xb8, //BusBase + 0xbf, //BusLimit + (PCI_HB1RB7_ECAM_BASE), //MemBase + PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB7_IO_BASE, //IoBase + (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB7_PCI_BASE), //RbPciBar + PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit + } + + } +}; + diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = PlatformPciLib + FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + +[Sources] + PlatformPciLib.c + +[Packages] + MdePkg/MdePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + +[FixedPcd] + gHisiTokenSpaceGuid.PcdHb1BaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PciHb0Rb0Base + gHisiTokenSpaceGuid.PciHb0Rb1Base + gHisiTokenSpaceGuid.PciHb0Rb2Base + gHisiTokenSpaceGuid.PciHb0Rb3Base + gHisiTokenSpaceGuid.PciHb0Rb4Base + gHisiTokenSpaceGuid.PciHb0Rb5Base + gHisiTokenSpaceGuid.PciHb0Rb6Base + gHisiTokenSpaceGuid.PciHb0Rb7Base + gHisiTokenSpaceGuid.PciHb1Rb0Base + gHisiTokenSpaceGuid.PciHb1Rb1Base + gHisiTokenSpaceGuid.PciHb1Rb2Base + gHisiTokenSpaceGuid.PciHb1Rb3Base + gHisiTokenSpaceGuid.PciHb1Rb4Base + gHisiTokenSpaceGuid.PciHb1Rb5Base + gHisiTokenSpaceGuid.PciHb1Rb6Base + gHisiTokenSpaceGuid.PciHb1Rb7Base + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize +
On Thu, Nov 10, 2016 at 09:52:26PM +0800, Heyi Guo wrote:
D05 is a new Hisilicon reference hardware platform, which is a dual socket SMP system and has 32 cores on each socket.
Binary modules will be uploaded in following separate patches.
No, they need to come before. This commit breaks bisect.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 78 +++ Chips/Hisilicon/HisiPkg.dec | 3 + Platforms/Hisilicon/D05/D05.dsc | 684 +++++++++++++++++++++ Platforms/Hisilicon/D05/D05.fdf | 369 +++++++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 61 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 ++ .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 218 +++++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 ++ .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 ++++++ 12 files changed, 2146 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h create mode 100644 Platforms/Hisilicon/D05/D05.dsc create mode 100644 Platforms/Hisilicon/D05/D05.fdf create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h new file mode 100644 index 0000000..4bc1c91 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -0,0 +1,78 @@ +#ifndef _SERDES_LIB_H_ +#define _SERDES_LIB_H_
+typedef enum hilink0_mode_type +{
- EM_HILINK0_HCCS1_8LANE = 0,
- EM_HILINK0_PCIE1_8LANE = 2,
- EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3,
- EM_HILINK0_SAS2_8LANE = 4,
- EM_HILINK0_HCCS1_8LANE_16,
- EM_HILINK0_HCCS1_8LANE_32,
- EM_HILINK0_HCCS1_8LANE_5000,
+}hilink0_mode_type_e;
+typedef enum hilink1_mode_type +{
- EM_HILINK1_SAS2_1LANE = 0,
- EM_HILINK1_HCCS0_8LANE = 1,
- EM_HILINK1_PCIE0_8LANE = 2,
- EM_HILINK1_HCCS0_8LANE_16,
- EM_HILINK1_HCCS0_8LANE_32,
- EM_HILINK1_HCCS0_8LANE_5000,
+}hilink1_mode_type_e;
+typedef enum hilink2_mode_type +{
- EM_HILINK2_PCIE2_8LANE = 0,
- EM_HILINK2_HCCS2_8LANE = 1,
- EM_HILINK2_SAS0_8LANE = 2,
- EM_HILINK2_HCCS2_8LANE_16,
- EM_HILINK2_HCCS2_8LANE_32,
- EM_HILINK2_HCCS2_8LANE_5000,
+}hilink2_mode_type_e;
+typedef enum hilink5_mode_type +{
- EM_HILINK5_PCIE3_4LANE = 0,
- EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1,
- EM_HILINK5_SAS1_4LANE = 2,
+}hilink5_mode_type_e;
+typedef struct serdes_param +{
- hilink0_mode_type_e hilink0_mode;
- hilink1_mode_type_e hilink1_mode;
- hilink2_mode_type_e hilink2_mode;
- UINT32 hilink3_mode;
- UINT32 hilink4_mode;
- hilink5_mode_type_e hilink5_mode;
- UINT32 hilink6_mode;
- UINT32 use_ssc;
- //board_type_e board_type;
+}serdes_param_t;
+#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
+typedef struct {
- UINT32 MacroId;
- UINT32 DsNum;
- UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; +UINT32 GetEthType(UINT8 EthChannel); +void serdes_enable_ctle_dfe(UINT32 nimbus_id, UINT32 macro, UINT32 lane, UINT32 lane_mode);
+EFI_STATUS +EfiSerdesInitWrap (VOID); +INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); +VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+#endif diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 39dd75a..4bf44cc 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -104,7 +104,10 @@ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008 gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009 gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
- gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
- gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
- gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d
gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038 diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000..148e617 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -0,0 +1,684 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#
+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]
- PLATFORM_NAME = D05
- PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x00010019
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64
- BUILD_TARGETS = DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
- DEFINE EDK2_SKIP_PEICORE=0
- DEFINE INCLUDE_TFTP_COMMAND=1
- DEFINE NETWORK_IP6_ENABLE = FALSE
- DEFINE HTTP_BOOT_ENABLE = FALSE
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.dsc.inc
+[LibraryClasses.common]
- ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
- FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
- BootMaintenanceManagerUiLib|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
- BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
- PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+!endif
+!if $(HTTP_BOOT_ENABLE) == TRUE
- HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+!ifdef $(FDT_ENABLE)
- #FDTUpdateLib
- FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
- CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
- SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
- EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
- #D05 RTC hardware is same as D03
- RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
- OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
- OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
- PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
- # USB Requirements
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[LibraryClasses.common.SEC]
- ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
- SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+[BuildOptions]
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################
+[PcdsFeatureFlag.common]
+!if $(EDK2_SKIP_PEICORE) == 1
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
- # It could be set FALSE to save size.
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+[PcdsFixedAtBuild.common]
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
- gArmPlatformTokenSpaceGuid.PcdCoreCount|8
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- # Stacks for MPCores in Secure World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
- # Stacks for MPCores in Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
- # Stacks for MPCores in Normal World
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
- gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
- #
- # ARM Pcds
- #
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
- gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
- gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
# bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
- ## SP805 Watchdog - Motherboard Watchdog
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
- ## Serial Terminal
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
- # use the TTY terminal type (which has a working backspace)
- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gHisiTokenSpaceGuid.PcdIsMPBoot|1
- gHisiTokenSpaceGuid.PcdSocketMask|0x3
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"
- gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
- gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
- gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
- gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
- gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
- gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
- #
- # ARM Architectual Timer Frequency
- #
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
- gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
- gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
- gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
- gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
- gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
- gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
- gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
- ## DTB address at spi flash
- gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
- gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
- gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
- gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
- gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
- gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
- gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
- gHisiTokenSpaceGuid.PcdNumaEnable|1
- gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
- gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
- gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
- gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
- gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
- gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
- gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
- gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
- gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
- gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
- gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
- gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
- gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
- gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
- gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
- gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
- gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common]
- #
- # SEC
- #
- #
- # PEI Phase modules
- #
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- MdeModulePkg/Core/Pei/PeiMain.inf
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- ArmPkg/Drivers/CpuPei/CpuPei.inf
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- }
- #
- # DXE
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
- }
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # Architectural Protocols
- #
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug.
- #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
- }
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
- }
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- #ACPI
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- # Usb Support
- #
- OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- NetworkPkg/TcpDxe/TcpDxe.inf
- NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- NetworkPkg/DnsDxe/DnsDxe.inf
- NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- NetworkPkg/HttpDxe/HttpDxe.inf
- NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Bds
- #
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+!ifdef $(FDT_ENABLE)
- OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #PCIe Support
- OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
- }
- OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
- }
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- # Memory test
- #
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- OpenPlatformPkg/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
- MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
- MdeModulePkg/Application/UiApp/UiApp.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
- }
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+!endif
+!ifdef $(INCLUDE_DP)
NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND)
NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
- }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000..5f48936 --- /dev/null +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -0,0 +1,369 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#
+[DEFINES]
+################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05]
+BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1
+# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30
+################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################
+0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT
+0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin +0x002A0000|0x00020000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = {
- ## This is the EFI_FIRMWARE_VOLUME_HEADER
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- # FileSystemGuid: gEfiSystemNvDataFvGuid =
- 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
- 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
- # FvLength: 0x20000
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- #Signature "_FVH" #Attributes
- 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
- #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
- 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
- #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
- 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
- #Blockmap[1]: End
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
- 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
- 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
- #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
- 0xB8, 0xdF, 0x00, 0x00,
- #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
- 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = {
- # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
- 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
- 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
- # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
- 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
- # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
- 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+0x002F0000|0x00010000 +FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################
+[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI DXE {
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- }
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
- #
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
- #
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- #
- # Multiple Console IO support
- #
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
- # Simple TextIn/TextOut for UEFI Terminal
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
- #
- # FAT filesystem + GPT/MBR partitioning
- #
- INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- INF FatBinPkg/EnhancedFatDxe/Fat.inf
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- #
- # Usb Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
- INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
- INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
- #
- #ACPI
- #
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
- #
- #Network
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
- INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- INF NetworkPkg/TcpDxe/TcpDxe.inf
- INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!endif
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(HTTP_BOOT_ENABLE) == TRUE
- INF NetworkPkg/DnsDxe/DnsDxe.inf
- INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
- INF NetworkPkg/HttpDxe/HttpDxe.inf
- INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+!endif
+!ifdef $(FDT_ENABLE)
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
- #
- # PCI Support
- #
- INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
- # VGA Driver
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
- INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
- #
- # UEFI application (Shell Embedded Boot Loader)
- #
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
- #
- # Build Shell from latest source code instead of prebuilt binary
- #
- INF ShellPkg/Application/Shell/Shell.inf
- #
- # Bds
- #
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PlatformBoot/PlatformBoot.inf
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
- INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
- INF MdeModulePkg/Application/UiApp/UiApp.inf
+[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE
- APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- }
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
- INF MdeModulePkg/Core/Pei/PeiMain.inf
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
- INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
- }
- }
+!include OpenPlatformPkg/Chips/Hisilicon/Hisilicon.fdf.inc
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000..55aacc8 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,61 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PiPei.h> +#include <PlatformArch.h> +#include <Uefi.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformSysCtrlLib.h>
Please sort include files.
+VOID QResetAp(VOID)
Coding style.
+{
- MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
Indentation is 2 spaces.
- (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
StartupAp();
- }
+}
+EFI_STATUS +EFIAPI +EarlyConfigEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
+{
- DEBUG((DEBUG_INFO,"SMMU CONFIG........."));
- (VOID)SmmuConfigForBios();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"AP CONFIG........."));
- (VOID)QResetAp();
- DEBUG((DEBUG_INFO,"Done\n"));
- DEBUG((DEBUG_INFO,"MN CONFIG........."));
- (VOID)MN_CONFIG();
- DEBUG((DEBUG_INFO,"Done\n"));
- return EFI_SUCCESS;
+}
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000..5fdf555 --- /dev/null +++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = EarlyConfigPeimD05
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = EarlyConfigEntry
+[Sources.common]
- EarlyConfigPeimD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- ArmLib
- CacheMaintenanceLib
- DebugLib
- IoLib
- PcdLib
- PeimEntryPoint
- PlatformSysCtrlLib
+[Pcd]
- gHisiTokenSpaceGuid.PcdMailBoxAddress
- gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[Depex] +## As we will clean mailbox in this module, need to wait memory init complete
- gEfiPeiMemoryDiscoveredPpiGuid
+[BuildOptions]
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000..f49b2bc --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,218 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h> +#include <IndustryStandard/SmBios.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HiiLib.h> +#include <Library/I2CLib.h> +#include <Library/IoLib.h> +#include <Library/OemMiscLib.h> +#include <Library/SerdesLib.h> +#include <Protocol/Smbios.h>
+I2C_DEVICE gDS3231RtcDevice = {
- .Socket = 0,
- .Port = 4,
- .DeviceType = DEVICE_TYPE_SPD,
- .SlaveDeviceAddress = 0x68
+};
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = {
- {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+serdes_param_t gSerdesParamNA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
- };
+serdes_param_t gSerdesParamNB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
- };
+serdes_param_t gSerdesParamS1NA = {
- .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
- .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
- .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_SAS1_4LANE,
- .hilink6_mode = 0x0,
- .use_ssc = 0,
- };
+serdes_param_t gSerdesParamS1NB = {
- .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
- .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
- .hilink2_mode = EM_HILINK2_SAS0_8LANE,
- .hilink3_mode = 0x0,
- .hilink4_mode = 0xF,
- .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
- .hilink6_mode = 0xF,
- .use_ssc = 0,
- };
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId)
Coding style. (Apply throughout.)
+{
- if ( ParamA == NULL) {
- DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
- if (ParamB == NULL) {
- DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
- return EFI_INVALID_PARAMETER;
- }
- if(SocketId == 0) {
- (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
- } else {
- (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
- (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
- }
- return EFI_SUCCESS;
+}
+VOID OemPcieResetAndOffReset(VOID) +{
- return;
+}
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
- // PCIe0 Slot 1
- {
{ // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
0, // Length,
0 // Handle
},
1, // SlotDesignation
SlotTypePciExpressX8, // SlotType
SlotDataBusWidth8X, // SlotDataBusWidth
SlotUsageAvailable, // SlotUsage
SlotLengthOther, // SlotLength
0x0001, // SlotId
{ // SlotCharacteristics1
0, // CharacteristicsUnknown :1;
0, // Provides50Volts :1;
0, // Provides33Volts :1;
0, // SharedSlot :1;
0, // PcCard16Supported :1;
0, // CardBusSupported :1;
0, // ZoomVideoSupported :1;
0 // ModemRingResumeSupported:1;
},
{ // SlotCharacteristics2
0, // PmeSignalSupported :1;
0, // HotPlugDevicesSupported :1;
0, // SmbusSignalSupported :1;
0 // Reserved :5;
},
0x00, // SegmentGroupNum
0x00, // BusNum
0 // DevFuncNum
- },
- // PCIe0 Slot 4
- {
{ // Hdr
EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
0, // Length,
0 // Handle
},
1, // SlotDesignation
SlotTypePciExpressX8, // SlotType
SlotDataBusWidth8X, // SlotDataBusWidth
SlotUsageAvailable, // SlotUsage
SlotLengthOther, // SlotLength
0x0004, // SlotId
{ // SlotCharacteristics1
0, // CharacteristicsUnknown :1;
0, // Provides50Volts :1;
0, // Provides33Volts :1;
0, // SharedSlot :1;
0, // PcCard16Supported :1;
0, // CardBusSupported :1;
0, // ZoomVideoSupported :1;
0 // ModemRingResumeSupported:1;
},
{ // SlotCharacteristics2
0, // PmeSignalSupported :1;
0, // HotPlugDevicesSupported :1;
0, // SmbusSignalSupported :1;
0 // Reserved :5;
},
0x00, // SegmentGroupNum
0x00, // BusNum
0 // DevFuncNum
- }
+};
+UINT8 OemGetPcieSlotNumber () +{
- return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
- {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
- {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+EFI_HII_HANDLE +EFIAPI +OemGetPackages (
- )
+{
- return HiiAddPackages (
&gEfiCallerIdGuid,
NULL,
OemMiscLibHi1616EvbStrings,
NULL,
NULL
);
+}
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000..9f5be02 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> +// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/
+/=#
+#langdef en-US "English"
+// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"
+// +// DIMM Device Locator strings
+#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28"
+// +// End English Language Strings +//
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000..149bb7d --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#include <PlatformArch.h> +#include <Uefi.h>
+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LpcLib.h> +#include <Library/OemAddressMapLib.h> +#include <Library/OemMiscLib.h> +#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h> +#include <Library/PlatformSysCtrlLib.h> +#include <Library/SerialPortLib.h> +#include <Library/TimerLib.h>
+#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
{67,0,0,0},
{225,0,0,3},
{0xFFFF,0xFFFF,0xFFFF,0xFFFF},
{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+BOOLEAN OemIsSocketPresent (UINTN Socket) +{
- if (PcdGet32(PcdSocketMask) & (1 << Socket)) {
- return TRUE;
- } else {
- return FALSE;
- }
+}
+UINTN OemGetSocketNumber (VOID) +{
- if(!OemIsMpBoot()) {
- return OEM_SINGLE_SOCKET;
- }
- return OEM_DUAL_SOCKET;
+}
+UINTN OemGetDdrChannel (VOID) +{
- return 4;
+}
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{
- return 2;
+}
+VOID CoreSelectBoot(VOID) +{
- if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
StartupAp ();
- }
- return;
+}
+BOOLEAN OemIsMpBoot() +{
- return PcdGet32(PcdIsMPBoot);
+}
+VOID OemLpcInit(VOID) +{
- LpcInit();
- return;
+}
+UINT32 OemIsWarmBoot(VOID) +{
- return 0;
+}
+VOID OemBiosSwitch(UINT32 Master) +{
- (VOID)Master;
- return;
+}
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{
- return TRUE;
+} diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000..b2f41b8 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = OemMiscLibHi1616Evb
- FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = OemMiscLib
+[Sources.common]
- BoardFeatureD05.c
- BoardFeatureD05Strings.uni
- OemMiscLibD05.c
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
- TimerLib
+[BuildOptions]
+[Ppis]
- gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES
+[Pcd]
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
- gHisiTokenSpaceGuid.PcdIsMPBoot
- gHisiTokenSpaceGuid.PcdSocketMask
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+[FixedPcd.common]
+[Guids]
+[Protocols]
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..57283a1 --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
- Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <Library/PcdLib.h> +#include <Library/PlatformPciLib.h>
+UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
{0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};
+UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
{0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};
+UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
{0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};
+UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
{0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
- {// HostBridge 0
- /* Port 0 */
- {
PCI_HB0RB0_ECAM_BASE, //ecam
0x80, //BusBase
0x87, //BusLimit
PCI_HB0RB0_PCIREGION_BASE, //Membase
PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
PCI_HB0RB0_IO_BASE, //IoBase
(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB0RB0_PCI_BASE),//RbPciBar
PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 1 */
- {
PCI_HB0RB1_ECAM_BASE,//ecam
0x90, //BusBase
0x97, //BusLimit
PCI_HB0RB1_PCIREGION_BASE, //Membase
PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
(PCI_HB0RB1_IO_BASE), //IoBase
(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB0RB1_PCI_BASE), //RbPciBar
PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 2 */
- {
PCI_HB0RB2_ECAM_BASE,
0x80, //BusBase
0x87, //BusLimit
PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
(PCI_HB0RB2_IO_BASE), //IOBase
(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB0RB2_PCI_BASE), //RbPciBar
PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 3 */
- {
PCI_HB0RB3_ECAM_BASE,
0xb0, //BusBase
0xb7, //BusLimit
(PCI_HB0RB3_ECAM_BASE), //MemBase
(PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit
(PCI_HB0RB3_IO_BASE), //IoBase
(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit
PCI_HB0RB3_CPUMEMREGIONBASE,
PCI_HB0RB3_CPUIOREGIONBASE,
(PCI_HB0RB3_PCI_BASE), //RbPciBar
PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 4 */
- {
PCI_HB0RB4_ECAM_BASE, //ecam
0x88, //BusBase
0x8f, //BusLimit
PCI_HB0RB4_CPUMEMREGIONBASE, //Membase
PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit
PCI_HB0RB4_IO_BASE, //IoBase
(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB0RB4_PCI_BASE), //RbPciBar
PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 5 */
- {
PCI_HB0RB5_ECAM_BASE,//ecam
0x0, //BusBase
0x7, //BusLimit
PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
(PCI_HB0RB5_IO_BASE), //IoBase
(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB0RB5_PCI_BASE), //RbPciBar
PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 6 */
- {
PCI_HB0RB6_ECAM_BASE,
0xC0, //BusBase
0xC7, //BusLimit
PCI_HB0RB6_PCIREGION_BASE ,//MemBase
PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit
(PCI_HB0RB6_IO_BASE), //IOBase
(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB0RB6_PCI_BASE), //RbPciBar
PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 7 */
- {
PCI_HB0RB7_ECAM_BASE,
0x90, //BusBase
0x97, //BusLimit
PCI_HB0RB7_CPUMEMREGIONBASE, //MemBase
PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit
(PCI_HB0RB7_IO_BASE), //IoBase
(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit
PCI_HB0RB7_CPUMEMREGIONBASE,
PCI_HB0RB7_CPUIOREGIONBASE,
(PCI_HB0RB7_PCI_BASE), //RbPciBar
PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase
PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit
- }
- },
+{// HostBridge 1
- /* Port 0 */
- {
PCI_HB1RB0_ECAM_BASE,
0x80, //BusBase
0x87, //BusLimit
(PCI_HB1RB0_ECAM_BASE), //MemBase
(PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit
PCI_HB1RB0_IO_BASE, //IoBase
(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB0_PCI_BASE), //RbPciBar
PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 1 */
- {
PCI_HB1RB1_ECAM_BASE,
0x90, //BusBase
0x97, //BusLimit
(PCI_HB1RB1_ECAM_BASE), //MemBase
(PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit
PCI_HB1RB1_IO_BASE, //IoBase
(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB1_PCI_BASE), //RbPciBar
PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 2 */
- {
PCI_HB1RB2_ECAM_BASE,
0x10, //BusBase
0x1f, //BusLimit
PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase
PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit
PCI_HB1RB2_IO_BASE, //IoBase
(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB2_PCI_BASE), //RbPciBar
PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 3 */
- {
PCI_HB1RB3_ECAM_BASE,
0xb0, //BusBase
0xb7, //BusLimit
(PCI_HB1RB3_ECAM_BASE), //MemBase
(PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit
PCI_HB1RB3_IO_BASE, //IoBase
(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB3_PCI_BASE), //RbPciBar
PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 4 */
- {
PCI_HB1RB4_ECAM_BASE,
0x20, //BusBase
0x2f, //BusLimit
PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase
PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit
PCI_HB1RB4_IO_BASE, //IoBase
(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB4_PCI_BASE), //RbPciBar
PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 5 */
- {
PCI_HB1RB5_ECAM_BASE,
0x30, //BusBase
0x3f, //BusLimit
PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase
PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit
PCI_HB1RB5_IO_BASE, //IoBase
(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB5_PCI_BASE), //RbPciBar
PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 6 */
- {
PCI_HB1RB6_ECAM_BASE,
0xa8, //BusBase
0xaf, //BusLimit
(PCI_HB1RB6_ECAM_BASE), //MemBase
PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit
PCI_HB1RB6_IO_BASE, //IoBase
(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB6_PCI_BASE), //RbPciBar
PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
- },
- /* Port 7 */
- {
PCI_HB1RB7_ECAM_BASE,
0xb8, //BusBase
0xbf, //BusLimit
(PCI_HB1RB7_ECAM_BASE), //MemBase
PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit
PCI_HB1RB7_IO_BASE, //IoBase
(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase
(PCI_HB1RB7_PCI_BASE), //RbPciBar
PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase
PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit
- }
- }
+};
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..8e013ca --- /dev/null +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +##
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
+[Sources]
- PlatformPciLib.c
+[Packages]
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- PcdLib
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdHb1BaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
- gHisiTokenSpaceGuid.PciHb0Rb0Base
- gHisiTokenSpaceGuid.PciHb0Rb1Base
- gHisiTokenSpaceGuid.PciHb0Rb2Base
- gHisiTokenSpaceGuid.PciHb0Rb3Base
- gHisiTokenSpaceGuid.PciHb0Rb4Base
- gHisiTokenSpaceGuid.PciHb0Rb5Base
- gHisiTokenSpaceGuid.PciHb0Rb6Base
- gHisiTokenSpaceGuid.PciHb0Rb7Base
- gHisiTokenSpaceGuid.PciHb1Rb0Base
- gHisiTokenSpaceGuid.PciHb1Rb1Base
- gHisiTokenSpaceGuid.PciHb1Rb2Base
- gHisiTokenSpaceGuid.PciHb1Rb3Base
- gHisiTokenSpaceGuid.PciHb1Rb4Base
- gHisiTokenSpaceGuid.PciHb1Rb5Base
- gHisiTokenSpaceGuid.PciHb1Rb6Base
- gHisiTokenSpaceGuid.PciHb1Rb7Base
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
- gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
-- 1.9.1
The dependency should be added to FdtUpdateLib, but it could not be added to UpdateFdtDxe when FdtUpdateLib becomes binary.
So this is a WA and can be removed after FdtUpdateLib open source.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun sunchenhui@huawei.com Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf index a0f0a9d..ccdcae7 100644 --- a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +++ b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf @@ -29,6 +29,7 @@ [Packages] ArmPlatformPkg/ArmPlatformPkg.dec MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec EmbeddedPkg/EmbeddedPkg.dec @@ -58,5 +59,4 @@
[Depex] -TRUE - + gEfiGenericMemTestProtocolGuid
Add binary module INF files separately so that it can be easier to be reviewed.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Library/Hi1616Serdes/Hi1616SerdesLib.inf | 48 +++++++++++++++++++ .../PlatformSysCtrlLibHi1616.inf | 54 ++++++++++++++++++++++ .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf | 26 +++++++++++ .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf | 28 +++++++++++ .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf | 32 +++++++++++++ .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf | 27 +++++++++++ .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf | 27 +++++++++++ .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf | 29 ++++++++++++ .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf | 28 +++++++++++ .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf | 27 +++++++++++ .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf | 27 +++++++++++ .../Binary/D05/Drivers/OhciDxe/OhciDxe.inf | 26 +++++++++++ .../ReportPciePlugDidVidToBmc.inf | 25 ++++++++++ .../Binary/D05/Drivers/SFC/SfcDxeDriver.inf | 29 ++++++++++++ .../Binary/D05/Drivers/Sas/SasDxeDriver.inf | 28 +++++++++++ .../Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf | 32 +++++++++++++ .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf | 26 +++++++++++ Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf | 32 +++++++++++++ .../D05/Library/FdtUpdateLib/FdtUpdateLib.inf | 51 ++++++++++++++++++++ .../Library/OemAddressMapD05/OemAddressMapD05.inf | 44 ++++++++++++++++++ .../Binary/D05/MemoryInitPei/MemoryInitPeim.inf | 33 +++++++++++++ 21 files changed, 679 insertions(+) create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf new file mode 100644 index 0000000..1fee6ea --- /dev/null +++ b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Hi1616SerdesLib + FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SerdesLib + +[Binaries.common] + LIB|Hi1616SerdesLib.lib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + TimerLib + IoLib + + OemMiscLib + +[BuildOptions] + +[FixedPcd] + gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag + +[Pcd] diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf new file mode 100644 index 0000000..50c63a1 --- /dev/null +++ b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf @@ -0,0 +1,54 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = PlatformSysCtrlLibHi1616 + FILE_GUID = EBF63479-8F72-4ada-8B2A-960322F7F61A + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformSysCtrlLib + +[Sources.common] + + +[Sources.AARCH64] + +[Binaries.AARCH64] + LIB|PlatformSysCtrlLibHi1616.lib|* + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + ArmLib + IoLib + OemAddressMapLib + OemMiscLib + +[FixedPcd] + gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress + gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress + gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress + gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress + +[BuildOptions] + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf new file mode 100644 index 0000000..20e2f05 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = GetInfoFromBmc + FILE_GUID = 43B59C81-9C5F-4021-B0F2-947DB839B781 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = GetBmcInfoDriverEntry + +[Binaries] + PE32|GetInfoFromBmc.efi|* + DXE_DEPEX|GetInfoFromBmc.depex|* diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf new file mode 100644 index 0000000..a614b68 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = IpmiInterfaceDxe + FILE_GUID = EF5483F8-68AD-4D71-9A23-674D2E9C013E + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + +[Binaries.common] + PE32|IpmiInterfaceDxe.efi|* + DXE_DEPEX|IpmiInterfaceDxe.depex|* + + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf new file mode 100644 index 0000000..e55d3f7 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = IpmiInterfacePei + FILE_GUID = 269702AF-8004-4570-A08E-00762AE65D15 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = IpmiInterfacePeiEntry + +[Sources] + +[Binaries.AARCH64] + TE|IpmiInterfacePei.efi|* + +[Depex] + TRUE + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf new file mode 100644 index 0000000..8075f40 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = IpmiMiscOp + FILE_GUID = EC68451C-6D10-4ba2-9862-D27D4D6090DB + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = IpmiMiscOpEntry + +[Binaries] + PE32|IpmiMiscOp.efi|* + DXE_DEPEX|IpmiMiscOpDxe.depex|* diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf new file mode 100644 index 0000000..c173587 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = IpmiWatchdogDxe + FILE_GUID = 7C7ACA9F-DB25-43FB-A479-1B6E42F38792 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeWatchdogDxeEntry + +[Binaries] + PE32|IpmiWatchdogDxe.efi|* + DXE_DEPEX|IpmiWatchdogDxe.depex|* diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf new file mode 100644 index 0000000..6c69e5b --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf @@ -0,0 +1,29 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SnpPV600Dxe + FILE_GUID = 92D37768-571C-48d9-BEF5-9744AE2FDAF4 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeSnpPV600Driver + UNLOAD_IMAGE = SnpPV600Unload + +[Binaries] + PE32|SnpPV600DxeMac0.efi|* + + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf new file mode 100644 index 0000000..b2c801d --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SnpPV600Dxe + FILE_GUID = 3247F150-3612-4803-BD4E-4104D7EF944A + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeSnpPV600Driver + UNLOAD_IMAGE = SnpPV600Unload + +[Binaries] + PE32|SnpPV600DxeMac1.efi|* + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf new file mode 100644 index 0000000..c7794be --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SnpPV600Dxe + FILE_GUID = 3247F153-3612-4803-BD4E-4104D7EF944A + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeSnpPV600Driver + UNLOAD_IMAGE = SnpPV600Unload + +[Binaries] + PE32|SnpPV600DxeMac4.efi|* + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf new file mode 100644 index 0000000..b06a3db --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SnpPV600Dxe + FILE_GUID = 3246F154-3612-4803-BD4E-4104D7EF944A + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeSnpPV600Driver + UNLOAD_IMAGE = SnpPV600Unload + +[Binaries] + PE32|SnpPV600DxeMac5.efi|* + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf new file mode 100644 index 0000000..80d9c49 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[defines] + INF_VERSION = 0x00010019 + BASE_NAME = NativeOhci + FILE_GUID = 043D0B5E-DAC1-463a-85BA-2CEDC33A8C4F + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + +[Binaries] + PE32|NativeOhci.efi|* + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf new file mode 100644 index 0000000..ab2be5e --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf @@ -0,0 +1,25 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = ReportPciePlugDidVidToBmc + FILE_GUID = 9BC4A5D1-5A46-4A6C-AF11-4875268179D3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + +[Binaries] + PE32|ReportPciePlugDidVidToBmc.efi|* + DXE_DEPEX|ReportPciePlugDidVidToBmc.depex|* diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf new file mode 100644 index 0000000..909462f --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf @@ -0,0 +1,29 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SFCDriver + FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SFCInitialize + + + +[Binaries.common] + PE32|SFCDriver.efi|* + DXE_DEPEX|SFCDriver.depex|* + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf new file mode 100644 index 0000000..539d612 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SasDriverDxe + FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe234567 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = SasDriverInitialize + +[Binaries] + PE32|SasDriverDxe.efi|* + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf new file mode 100644 index 0000000..0590919 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SmiGraphicsOutput + FILE_GUID = BFB7B510-B09B-11DB-96E3-005056C00008 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + + PCI_VENDOR_ID = 0x126F + PCI_DEVICE_ID = 0x0750 + PCI_CLASS_CODE = 0x030000 + PCI_REVISION = 0xA1 + COMPRESS = TRUE + +[Binaries] + PE32|SmiGraphicsOutput.efi|* + diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf new file mode 100644 index 0000000..6b34037 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = TransSmbiosInfo + FILE_GUID = 13668C32-1977-436a-800C-F8644D11CB76 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = TransferSmbiosInfoToBMC + +[Binaries] + PE32|TransSmbiosInfo.efi|* + DXE_DEPEX|TransSmbiosInfo.depex|* diff --git a/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf new file mode 100644 index 0000000..9419fcb --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Ebl + FILE_GUID = 3CEF354A-3B7A-4519-AD70-72A134698311 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 1.0 + ENTRY_POINT = EdkBootLoaderEntry + +[Binaries.common] + PE32|Ebl.efi|* + diff --git a/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf new file mode 100644 index 0000000..cb4cda8 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -0,0 +1,51 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = FdtUpdateLib + FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = FdtUpdateLib + +[Sources.common] + +[Binaries.AARCH64] + LIB|FdtUpdateLib.lib|* + +[Sources.AARCH64.GCC] + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + FdtLib + OemMiscLib + PlatformSysCtrlLib + +[Protocols] + gEfiGenericMemTestProtocolGuid + + +[Pcd] + gHisiTokenSpaceGuid.PcdIsMPBoot + gHisiTokenSpaceGuid.PcdNumaEnable + gHisiTokenSpaceGuid.Pcdsoctype + diff --git a/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf new file mode 100644 index 0000000..6743eef --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf @@ -0,0 +1,44 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = OemAddressMapD05 + FILE_GUID = 32BC48E3-5428-4556-A383-25A23EA816A7 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OemAddressMapLib + +[Sources.common] + +[Binaries.AARCH64] + LIB|OemAddressMapD05.lib|* + +[Sources.AARCH64.GCC] + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + CpldIoLib +[BuildOptions] + +[FixedPcd] + gHisiTokenSpaceGuid.PcdNORFlashBase + diff --git a/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf new file mode 100644 index 0000000..da28c5a --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf @@ -0,0 +1,33 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR> +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/MemoryInitPei/ +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = MemoryInit + FILE_GUID = c61ef796-b50d-4f98-9f78-4f6f79d800d5 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeMemory + +[Sources] + +[Binaries.AARCH64] + TE|MemoryInit.efi|* + +[Depex] + TRUE
On Thu, Nov 10, 2016 at 09:52:28PM +0800, Heyi Guo wrote:
Add binary module INF files separately so that it can be easier to be reviewed.
Needs to be resolved by generating --no-binary patches.
Also, I would ideally like to see some sort of license, like Platforms/ARM/Juno/Binary/Copying.txt or Platforms/AMD/Styx/License.txt
Regards,
Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Library/Hi1616Serdes/Hi1616SerdesLib.inf | 48 +++++++++++++++++++ .../PlatformSysCtrlLibHi1616.inf | 54 ++++++++++++++++++++++ .../D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf | 26 +++++++++++ .../Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf | 28 +++++++++++ .../Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf | 32 +++++++++++++ .../D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf | 27 +++++++++++ .../Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf | 27 +++++++++++ .../Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf | 29 ++++++++++++ .../Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf | 28 +++++++++++ .../Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf | 27 +++++++++++ .../Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf | 27 +++++++++++ .../Binary/D05/Drivers/OhciDxe/OhciDxe.inf | 26 +++++++++++ .../ReportPciePlugDidVidToBmc.inf | 25 ++++++++++ .../Binary/D05/Drivers/SFC/SfcDxeDriver.inf | 29 ++++++++++++ .../Binary/D05/Drivers/Sas/SasDxeDriver.inf | 28 +++++++++++ .../Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf | 32 +++++++++++++ .../Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf | 26 +++++++++++ Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf | 32 +++++++++++++ .../D05/Library/FdtUpdateLib/FdtUpdateLib.inf | 51 ++++++++++++++++++++ .../Library/OemAddressMapD05/OemAddressMapD05.inf | 44 ++++++++++++++++++ .../Binary/D05/MemoryInitPei/MemoryInitPeim.inf | 33 +++++++++++++ 21 files changed, 679 insertions(+) create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf create mode 100644 Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf create mode 100644 Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf create mode 100644 Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf new file mode 100644 index 0000000..1fee6ea --- /dev/null +++ b/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = Hi1616SerdesLib
- FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SerdesLib
+[Binaries.common]
- LIB|Hi1616SerdesLib.lib
+[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- TimerLib
- IoLib
- OemMiscLib
+[BuildOptions]
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag
+[Pcd] diff --git a/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf new file mode 100644 index 0000000..50c63a1 --- /dev/null +++ b/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf @@ -0,0 +1,54 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = PlatformSysCtrlLibHi1616
- FILE_GUID = EBF63479-8F72-4ada-8B2A-960322F7F61A
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformSysCtrlLib
+[Sources.common]
+[Sources.AARCH64]
+[Binaries.AARCH64]
- LIB|PlatformSysCtrlLibHi1616.lib|*
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- ArmLib
- IoLib
- OemAddressMapLib
- OemMiscLib
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress
- gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress
- gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress
- gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType
- gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
- gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress
+[BuildOptions]
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf new file mode 100644 index 0000000..20e2f05 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = GetInfoFromBmc
- FILE_GUID = 43B59C81-9C5F-4021-B0F2-947DB839B781
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = GetBmcInfoDriverEntry
+[Binaries]
- PE32|GetInfoFromBmc.efi|*
- DXE_DEPEX|GetInfoFromBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf new file mode 100644 index 0000000..a614b68 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = IpmiInterfaceDxe
- FILE_GUID = EF5483F8-68AD-4D71-9A23-674D2E9C013E
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
+[Binaries.common]
- PE32|IpmiInterfaceDxe.efi|*
- DXE_DEPEX|IpmiInterfaceDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf new file mode 100644 index 0000000..e55d3f7 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = IpmiInterfacePei
- FILE_GUID = 269702AF-8004-4570-A08E-00762AE65D15
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = IpmiInterfacePeiEntry
+[Sources]
+[Binaries.AARCH64]
- TE|IpmiInterfacePei.efi|*
+[Depex]
- TRUE
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf new file mode 100644 index 0000000..8075f40 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = IpmiMiscOp
- FILE_GUID = EC68451C-6D10-4ba2-9862-D27D4D6090DB
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = IpmiMiscOpEntry
+[Binaries]
- PE32|IpmiMiscOp.efi|*
- DXE_DEPEX|IpmiMiscOpDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf new file mode 100644 index 0000000..c173587 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = IpmiWatchdogDxe
- FILE_GUID = 7C7ACA9F-DB25-43FB-A479-1B6E42F38792
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeWatchdogDxeEntry
+[Binaries]
- PE32|IpmiWatchdogDxe.efi|*
- DXE_DEPEX|IpmiWatchdogDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf new file mode 100644 index 0000000..6c69e5b --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf @@ -0,0 +1,29 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = SnpPV600Dxe
- FILE_GUID = 92D37768-571C-48d9-BEF5-9744AE2FDAF4
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeSnpPV600Driver
- UNLOAD_IMAGE = SnpPV600Unload
+[Binaries]
- PE32|SnpPV600DxeMac0.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf new file mode 100644 index 0000000..b2c801d --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = SnpPV600Dxe
- FILE_GUID = 3247F150-3612-4803-BD4E-4104D7EF944A
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeSnpPV600Driver
- UNLOAD_IMAGE = SnpPV600Unload
+[Binaries]
- PE32|SnpPV600DxeMac1.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf new file mode 100644 index 0000000..c7794be --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = SnpPV600Dxe
- FILE_GUID = 3247F153-3612-4803-BD4E-4104D7EF944A
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeSnpPV600Driver
- UNLOAD_IMAGE = SnpPV600Unload
+[Binaries]
- PE32|SnpPV600DxeMac4.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf new file mode 100644 index 0000000..b06a3db --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf @@ -0,0 +1,27 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = SnpPV600Dxe
- FILE_GUID = 3246F154-3612-4803-BD4E-4104D7EF944A
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeSnpPV600Driver
- UNLOAD_IMAGE = SnpPV600Unload
+[Binaries]
- PE32|SnpPV600DxeMac5.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf new file mode 100644 index 0000000..80d9c49 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[defines]
- INF_VERSION = 0x00010019
- BASE_NAME = NativeOhci
- FILE_GUID = 043D0B5E-DAC1-463a-85BA-2CEDC33A8C4F
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
+[Binaries]
- PE32|NativeOhci.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf new file mode 100644 index 0000000..ab2be5e --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf @@ -0,0 +1,25 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = ReportPciePlugDidVidToBmc
- FILE_GUID = 9BC4A5D1-5A46-4A6C-AF11-4875268179D3
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
+[Binaries]
- PE32|ReportPciePlugDidVidToBmc.efi|*
- DXE_DEPEX|ReportPciePlugDidVidToBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf new file mode 100644 index 0000000..909462f --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf @@ -0,0 +1,29 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = SFCDriver
- FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = SFCInitialize
+[Binaries.common]
- PE32|SFCDriver.efi|*
- DXE_DEPEX|SFCDriver.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf new file mode 100644 index 0000000..539d612 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = SasDriverDxe
- FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe234567
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = SasDriverInitialize
+[Binaries]
- PE32|SasDriverDxe.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf new file mode 100644 index 0000000..0590919 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = SmiGraphicsOutput
- FILE_GUID = BFB7B510-B09B-11DB-96E3-005056C00008
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- PCI_VENDOR_ID = 0x126F
- PCI_DEVICE_ID = 0x0750
- PCI_CLASS_CODE = 0x030000
- PCI_REVISION = 0xA1
- COMPRESS = TRUE
+[Binaries]
- PE32|SmiGraphicsOutput.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf new file mode 100644 index 0000000..6b34037 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = TransSmbiosInfo
- FILE_GUID = 13668C32-1977-436a-800C-F8644D11CB76
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = TransferSmbiosInfoToBMC
+[Binaries]
- PE32|TransSmbiosInfo.efi|*
- DXE_DEPEX|TransSmbiosInfo.depex|*
diff --git a/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf new file mode 100644 index 0000000..9419fcb --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf @@ -0,0 +1,32 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = Ebl
- FILE_GUID = 3CEF354A-3B7A-4519-AD70-72A134698311
- MODULE_TYPE = UEFI_APPLICATION
- VERSION_STRING = 1.0
- ENTRY_POINT = EdkBootLoaderEntry
+[Binaries.common]
- PE32|Ebl.efi|*
diff --git a/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf new file mode 100644 index 0000000..cb4cda8 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -0,0 +1,51 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = FdtUpdateLib
- FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = FdtUpdateLib
+[Sources.common]
+[Binaries.AARCH64]
- LIB|FdtUpdateLib.lib|*
+[Sources.AARCH64.GCC]
+[Packages]
- EmbeddedPkg/EmbeddedPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- FdtLib
- OemMiscLib
- PlatformSysCtrlLib
+[Protocols]
- gEfiGenericMemTestProtocolGuid
+[Pcd]
- gHisiTokenSpaceGuid.PcdIsMPBoot
- gHisiTokenSpaceGuid.PcdNumaEnable
- gHisiTokenSpaceGuid.Pcdsoctype
diff --git a/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf new file mode 100644 index 0000000..6743eef --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf @@ -0,0 +1,44 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = OemAddressMapD05
- FILE_GUID = 32BC48E3-5428-4556-A383-25A23EA816A7
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = OemAddressMapLib
+[Sources.common]
+[Binaries.AARCH64]
- LIB|OemAddressMapD05.lib|*
+[Sources.AARCH64.GCC]
+[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+[LibraryClasses]
- CpldIoLib
+[BuildOptions]
+[FixedPcd]
- gHisiTokenSpaceGuid.PcdNORFlashBase
diff --git a/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf new file mode 100644 index 0000000..da28c5a --- /dev/null +++ b/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf @@ -0,0 +1,33 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR> +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR> +# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# Based on the files under ArmPlatformPkg/MemoryInitPei/ +# +#**/
+[Defines]
- INF_VERSION = 0x00010019
- BASE_NAME = MemoryInit
- FILE_GUID = c61ef796-b50d-4f98-9f78-4f6f79d800d5
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializeMemory
+[Sources]
+[Binaries.AARCH64]
- TE|MemoryInit.efi|*
+[Depex]
- TRUE
-- 1.9.1
we add updating ACPI table feature to update SRAT and SLIT table for D05 platform.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 53 +++++--- .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 6 + .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 137 +++++++++++++++++++++ 3 files changed, 176 insertions(+), 20 deletions(-) create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c index 5b679fa..c1a31b5 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c @@ -24,6 +24,11 @@
#include <IndustryStandard/Acpi.h>
+EFI_STATUS +UpdateAcpiTable ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader +); + /** Locate the first instance of a protocol. If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table @@ -180,6 +185,8 @@ AcpiPlatformEntryPoint ( UINT32 FvStatus; UINTN TableSize; UINTN Size; + EFI_STATUS TableStatus; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
Instance = 0; CurrentTable = NULL; @@ -218,26 +225,32 @@ AcpiPlatformEntryPoint ( // // Add the table // - TableHandle = 0; - - TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length; - ASSERT (Size >= TableSize); - - // - // Checksum ACPI table - // - AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize); - - // - // Install ACPI table - // - Status = AcpiTable->InstallAcpiTable ( - AcpiTable, - CurrentTable, - TableSize, - &TableHandle - ); - + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER*) (CurrentTable); + //Update specfic Acpi Table + //If the Table is updated failed, doesn't install it, + //go to find next section. + TableStatus = UpdateAcpiTable(TableHeader); + if (TableStatus == EFI_SUCCESS) { + TableHandle = 0; + + TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length; + ASSERT (Size >= TableSize); + + // + // Checksum ACPI table + // + AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize); + + // + // Install ACPI table + // + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + TableSize, + &TableHandle + ); + } // // Free memory allocated by ReadSection // diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf index 80ff49b..35b4a0a 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf @@ -29,10 +29,12 @@
[Sources] AcpiPlatform.c + UpdateAcpiTable.c
[Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] UefiLib @@ -42,10 +44,14 @@ DebugLib UefiBootServicesTableLib UefiDriverEntryPoint + HobLib
[Protocols] gEfiAcpiTableProtocolGuid ## CONSUMES
+[Guids] + gHisiEfiMemoryMapGuid + [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c new file mode 100644 index 0000000..1d7797c --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -0,0 +1,137 @@ +/** @file + Copyright (c) 2016, Hisilicon Limited. All rights reserved. + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#include <PlatformArch.h> +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiNextLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/HwMemInitLib.h> +#include <Library/OemMiscLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> + +#define CORE_NUM_PER_SOCKET 32 +#define NODE_IN_SOCKET 2 + +STATIC +VOID +RemoveInvalidMemoryNode ( + IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table, + IN UINTN MemoryNodeNum +) +{ + UINT8 *CurrPtr, *NewPtr; + + if (MemoryNodeNum >= EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT) { + return; + } + + CurrPtr = (UINT8 *) &(Table->Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]); + NewPtr = (UINT8 *) &(Table->Memory[MemoryNodeNum]); + + CopyMem (NewPtr, CurrPtr, (UINT8 *)Table + Table->Header.Header.Length - CurrPtr); + + Table->Header.Header.Length -= CurrPtr - NewPtr; + + return; +} + +STATIC +EFI_STATUS +UpdateSrat ( + IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table + ) +{ + UINT8 Skt = 0; + UINTN Index = 0; + VOID *HobList; + GBL_DATA *Gbl_Data; + UINTN Base; + UINTN Size; + UINT8 NodeId; + UINT32 ScclInterleaveEn; + UINT8 i; + UINTN MemoryNode = 0; + + DEBUG((DEBUG_INFO, "SRAT: Updating SRAT memory information.\n")); + + HobList = GetHobList(); + if (HobList == NULL) { + return EFI_UNSUPPORTED; + } + Gbl_Data = (GBL_DATA*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList); + if (Gbl_Data == NULL) { + DEBUG((DEBUG_ERROR, "Get next Guid HOb fail.\n")); + return EFI_NOT_FOUND; + } + Gbl_Data = GET_GUID_HOB_DATA(Gbl_Data); + for(Skt = 0; Skt < MAX_SOCKET; Skt++) { + for(Index = 0; Index < MAX_NUM_PER_TYPE; Index++) { + NodeId = Gbl_Data->NumaInfo[Skt][Index].NodeId; + Base = Gbl_Data->NumaInfo[Skt][Index].Base; + Size = Gbl_Data->NumaInfo[Skt][Index].Length; + DEBUG((DEBUG_INFO, "Skt %d Index %d: NodeId = %d, Base = 0x%lx, Size = 0x%lx\n", Skt, Index, NodeId, Base, Size)); + if (Size > 0) { + Table->Memory[MemoryNode].ProximityDomain = NodeId; + Table->Memory[MemoryNode].AddressBaseLow = Base; + Table->Memory[MemoryNode].AddressBaseHigh = Base >> 32; + Table->Memory[MemoryNode].LengthLow = Size; + Table->Memory[MemoryNode].LengthHigh = Size >> 32; + MemoryNode = MemoryNode + 1; + } + } + ScclInterleaveEn = Gbl_Data->NumaInfo[Skt][0].ScclInterleaveEn; + DEBUG((DEBUG_INFO, "ScclInterleaveEn = %d\n", ScclInterleaveEn)); + //update gicc structure + if (ScclInterleaveEn != 0) { + DEBUG((DEBUG_INFO, "SRAT: Updating SRAT Gicc information.\n" )); + for (i = Skt * CORE_NUM_PER_SOCKET; i < (Skt + 1) * CORE_NUM_PER_SOCKET; i++) { + Table->Gicc[i].ProximityDomain = Skt * NODE_IN_SOCKET; + } + } + } + + //remove invalid memory node + RemoveInvalidMemoryNode (Table, MemoryNode); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +UpdateSlit ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *Table + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +UpdateAcpiTable ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader +) +{ + EFI_STATUS Status = EFI_SUCCESS; + + switch (TableHeader->Signature) { + + case EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE: + Status = UpdateSrat ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) TableHeader); + break; + + case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: + Status = UpdateSlit (TableHeader); + break; + } + return Status; +}
On Thu, Nov 10, 2016 at 09:52:29PM +0800, Heyi Guo wrote:
we add updating ACPI table feature to update SRAT and SLIT table for D05 platform.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 53 +++++--- .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 6 + .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 137 +++++++++++++++++++++ 3 files changed, 176 insertions(+), 20 deletions(-) create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c index 5b679fa..c1a31b5 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c @@ -24,6 +24,11 @@ #include <IndustryStandard/Acpi.h> +EFI_STATUS +UpdateAcpiTable (
- IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
+);
Function declarations go in header files. In this case, please create and include an UpdateAcpiTable.h.
/** Locate the first instance of a protocol. If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table @@ -180,6 +185,8 @@ AcpiPlatformEntryPoint ( UINT32 FvStatus; UINTN TableSize; UINTN Size;
- EFI_STATUS TableStatus;
- EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
Instance = 0; CurrentTable = NULL; @@ -218,26 +225,32 @@ AcpiPlatformEntryPoint ( // // Add the table //
TableHandle = 0;
TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
ASSERT (Size >= TableSize);
//
// Checksum ACPI table
//
AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
//
// Install ACPI table
//
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
TableSize,
&TableHandle
);
TableHeader = (EFI_ACPI_DESCRIPTION_HEADER*) (CurrentTable);
//Update specfic Acpi Table
//If the Table is updated failed, doesn't install it,
//go to find next section.
TableStatus = UpdateAcpiTable(TableHeader);
if (TableStatus == EFI_SUCCESS) {
TableHandle = 0;
TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
ASSERT (Size >= TableSize);
//
// Checksum ACPI table
//
AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
//
// Install ACPI table
//
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
TableSize,
&TableHandle
);
} // // Free memory allocated by ReadSection //
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf index 80ff49b..35b4a0a 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf @@ -29,10 +29,12 @@ [Sources] AcpiPlatform.c
- UpdateAcpiTable.c
[Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] UefiLib @@ -42,10 +44,14 @@ DebugLib UefiBootServicesTableLib UefiDriverEntryPoint
- HobLib
Insert after DebugLib, so improve sorting.
[Protocols] gEfiAcpiTableProtocolGuid ## CONSUMES +[Guids]
- gHisiEfiMemoryMapGuid
[Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c new file mode 100644 index 0000000..1d7797c --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -0,0 +1,137 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/ +#include <PlatformArch.h> +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiNextLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/HwMemInitLib.h> +#include <Library/OemMiscLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h>
+#define CORE_NUM_PER_SOCKET 32 +#define NODE_IN_SOCKET 2
+STATIC +VOID +RemoveInvalidMemoryNode (
This function appears to be named for how it is used rather than for what it does. Could it be renamed RemoveMemoryNode()?
Or is it that it removes any unused nodes in the table? If so, a better name would be RemoveUnusedMemoryNodes().
- IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table,
- IN UINTN MemoryNodeNum
+) +{
- UINT8 *CurrPtr, *NewPtr;
Don't use UINT8 * where you mean VOID * (or UINTN). (Applies throughout function.)
- if (MemoryNodeNum >= EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT) {
- return;
- }
- CurrPtr = (UINT8 *) &(Table->Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]);
I don't understand this bit. What is it taking the address of, to copy data from?
- NewPtr = (UINT8 *) &(Table->Memory[MemoryNodeNum]);
- CopyMem (NewPtr, CurrPtr, (UINT8 *)Table + Table->Header.Header.Length - CurrPtr);
- Table->Header.Header.Length -= CurrPtr - NewPtr;
- return;
+}
+STATIC +EFI_STATUS +UpdateSrat (
- IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table
- )
+{
- UINT8 Skt = 0;
- UINTN Index = 0;
- VOID *HobList;
- GBL_DATA *Gbl_Data;
- UINTN Base;
- UINTN Size;
- UINT8 NodeId;
- UINT32 ScclInterleaveEn;
- UINT8 i;
There is no performance or other benefit to using UINT8 for a generic counter. UINT32 or UINTN.
- UINTN MemoryNode = 0;
- DEBUG((DEBUG_INFO, "SRAT: Updating SRAT memory information.\n"));
- HobList = GetHobList();
- if (HobList == NULL) {
- return EFI_UNSUPPORTED;
- }
- Gbl_Data = (GBL_DATA*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
- if (Gbl_Data == NULL) {
- DEBUG((DEBUG_ERROR, "Get next Guid HOb fail.\n"));
- return EFI_NOT_FOUND;
- }
- Gbl_Data = GET_GUID_HOB_DATA(Gbl_Data);
- for(Skt = 0; Skt < MAX_SOCKET; Skt++) {
- for(Index = 0; Index < MAX_NUM_PER_TYPE; Index++) {
NodeId = Gbl_Data->NumaInfo[Skt][Index].NodeId;
Base = Gbl_Data->NumaInfo[Skt][Index].Base;
Size = Gbl_Data->NumaInfo[Skt][Index].Length;
DEBUG((DEBUG_INFO, "Skt %d Index %d: NodeId = %d, Base = 0x%lx, Size = 0x%lx\n", Skt, Index, NodeId, Base, Size));
if (Size > 0) {
Table->Memory[MemoryNode].ProximityDomain = NodeId;
Table->Memory[MemoryNode].AddressBaseLow = Base;
Table->Memory[MemoryNode].AddressBaseHigh = Base >> 32;
Table->Memory[MemoryNode].LengthLow = Size;
Table->Memory[MemoryNode].LengthHigh = Size >> 32;
MemoryNode = MemoryNode + 1;
}
- }
- ScclInterleaveEn = Gbl_Data->NumaInfo[Skt][0].ScclInterleaveEn;
- DEBUG((DEBUG_INFO, "ScclInterleaveEn = %d\n", ScclInterleaveEn));
- //update gicc structure
- if (ScclInterleaveEn != 0) {
DEBUG((DEBUG_INFO, "SRAT: Updating SRAT Gicc information.\n" ));
Drop space before )).
for (i = Skt * CORE_NUM_PER_SOCKET; i < (Skt + 1) * CORE_NUM_PER_SOCKET; i++) {
Could benefit from a local macro such as #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)
Also, why is there even an 'i' here? Could we not just reuse Index?
Table->Gicc[i].ProximityDomain = Skt * NODE_IN_SOCKET;
}
- }
- }
- //remove invalid memory node
- RemoveInvalidMemoryNode (Table, MemoryNode);
Why is this invalid?
- return EFI_SUCCESS;
+}
+STATIC +EFI_STATUS +UpdateSlit (
- IN OUT EFI_ACPI_DESCRIPTION_HEADER *Table
- )
+{
- return EFI_SUCCESS;
+}
+EFI_STATUS +UpdateAcpiTable (
- IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
+) +{
- EFI_STATUS Status = EFI_SUCCESS;
- switch (TableHeader->Signature) {
- case EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE:
- Status = UpdateSrat ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) TableHeader);
- break;
- case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
- Status = UpdateSlit (TableHeader);
- break;
- }
- return Status;
+}
1.9.1
在 11/14/2016 10:45 PM, Leif Lindholm 写道:
On Thu, Nov 10, 2016 at 09:52:29PM +0800, Heyi Guo wrote:
we add updating ACPI table feature to update SRAT and SLIT table for D05 platform.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c | 53 +++++--- .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 6 + .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 137 +++++++++++++++++++++ 3 files changed, 176 insertions(+), 20 deletions(-) create mode 100644 Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c index 5b679fa..c1a31b5 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c @@ -24,6 +24,11 @@ #include <IndustryStandard/Acpi.h> +EFI_STATUS +UpdateAcpiTable (
- IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
+);
Function declarations go in header files. In this case, please create and include an UpdateAcpiTable.h.
/** Locate the first instance of a protocol. If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table @@ -180,6 +185,8 @@ AcpiPlatformEntryPoint ( UINT32 FvStatus; UINTN TableSize; UINTN Size;
- EFI_STATUS TableStatus;
- EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
Instance = 0; CurrentTable = NULL; @@ -218,26 +225,32 @@ AcpiPlatformEntryPoint ( // // Add the table //
TableHandle = 0;
TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
ASSERT (Size >= TableSize);
//
// Checksum ACPI table
//
AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
//
// Install ACPI table
//
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
TableSize,
&TableHandle
);
TableHeader = (EFI_ACPI_DESCRIPTION_HEADER*) (CurrentTable);
//Update specfic Acpi Table
//If the Table is updated failed, doesn't install it,
//go to find next section.
TableStatus = UpdateAcpiTable(TableHeader);
if (TableStatus == EFI_SUCCESS) {
TableHandle = 0;
TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
ASSERT (Size >= TableSize);
//
// Checksum ACPI table
//
AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
//
// Install ACPI table
//
Status = AcpiTable->InstallAcpiTable (
AcpiTable,
CurrentTable,
TableSize,
&TableHandle
);
} // // Free memory allocated by ReadSection //
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf index 80ff49b..35b4a0a 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf @@ -29,10 +29,12 @@ [Sources] AcpiPlatform.c
- UpdateAcpiTable.c
[Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec
- OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
[LibraryClasses] UefiLib @@ -42,10 +44,14 @@ DebugLib UefiBootServicesTableLib UefiDriverEntryPoint
- HobLib
Insert after DebugLib, so improve sorting.
[Protocols] gEfiAcpiTableProtocolGuid ## CONSUMES +[Guids]
- gHisiEfiMemoryMapGuid
- [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c new file mode 100644 index 0000000..1d7797c --- /dev/null +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -0,0 +1,137 @@ +/** @file
- Copyright (c) 2016, Hisilicon Limited. All rights reserved.
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/ +#include <PlatformArch.h> +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiNextLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/HwMemInitLib.h> +#include <Library/OemMiscLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h>
+#define CORE_NUM_PER_SOCKET 32 +#define NODE_IN_SOCKET 2
+STATIC +VOID +RemoveInvalidMemoryNode (
This function appears to be named for how it is used rather than for what it does. Could it be renamed RemoveMemoryNode()?
Or is it that it removes any unused nodes in the table? If so, a better name would be RemoveUnusedMemoryNodes().
Hi Leif, There have some static Memory Nodes at Srat table, the nodes will be initialized during boot, and different DIMM Slots inserting may have different notes number used, so the nodes useless will be removed here, and we also need to copy the data next block to the end of memory nodes.
- IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table,
- IN UINTN MemoryNodeNum
+) +{
- UINT8 *CurrPtr, *NewPtr;
Don't use UINT8 * where you mean VOID * (or UINTN). (Applies throughout function.)
- if (MemoryNodeNum >= EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT) {
- return;
- }
- CurrPtr = (UINT8 *) &(Table->Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]);
I don't understand this bit. What is it taking the address of, to copy data from?
- NewPtr = (UINT8 *) &(Table->Memory[MemoryNodeNum]);
- CopyMem (NewPtr, CurrPtr, (UINT8 *)Table + Table->Header.Header.Length - CurrPtr);
- Table->Header.Header.Length -= CurrPtr - NewPtr;
- return;
+}
+STATIC +EFI_STATUS +UpdateSrat (
- IN OUT EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *Table
- )
+{
- UINT8 Skt = 0;
- UINTN Index = 0;
- VOID *HobList;
- GBL_DATA *Gbl_Data;
- UINTN Base;
- UINTN Size;
- UINT8 NodeId;
- UINT32 ScclInterleaveEn;
- UINT8 i;
There is no performance or other benefit to using UINT8 for a generic counter. UINT32 or UINTN.
- UINTN MemoryNode = 0;
- DEBUG((DEBUG_INFO, "SRAT: Updating SRAT memory information.\n"));
- HobList = GetHobList();
- if (HobList == NULL) {
- return EFI_UNSUPPORTED;
- }
- Gbl_Data = (GBL_DATA*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
- if (Gbl_Data == NULL) {
- DEBUG((DEBUG_ERROR, "Get next Guid HOb fail.\n"));
- return EFI_NOT_FOUND;
- }
- Gbl_Data = GET_GUID_HOB_DATA(Gbl_Data);
- for(Skt = 0; Skt < MAX_SOCKET; Skt++) {
- for(Index = 0; Index < MAX_NUM_PER_TYPE; Index++) {
NodeId = Gbl_Data->NumaInfo[Skt][Index].NodeId;
Base = Gbl_Data->NumaInfo[Skt][Index].Base;
Size = Gbl_Data->NumaInfo[Skt][Index].Length;
DEBUG((DEBUG_INFO, "Skt %d Index %d: NodeId = %d, Base = 0x%lx, Size = 0x%lx\n", Skt, Index, NodeId, Base, Size));
if (Size > 0) {
Table->Memory[MemoryNode].ProximityDomain = NodeId;
Table->Memory[MemoryNode].AddressBaseLow = Base;
Table->Memory[MemoryNode].AddressBaseHigh = Base >> 32;
Table->Memory[MemoryNode].LengthLow = Size;
Table->Memory[MemoryNode].LengthHigh = Size >> 32;
MemoryNode = MemoryNode + 1;
}
- }
- ScclInterleaveEn = Gbl_Data->NumaInfo[Skt][0].ScclInterleaveEn;
- DEBUG((DEBUG_INFO, "ScclInterleaveEn = %d\n", ScclInterleaveEn));
- //update gicc structure
- if (ScclInterleaveEn != 0) {
DEBUG((DEBUG_INFO, "SRAT: Updating SRAT Gicc information.\n" ));
Drop space before )).
for (i = Skt * CORE_NUM_PER_SOCKET; i < (Skt + 1) * CORE_NUM_PER_SOCKET; i++) {
Could benefit from a local macro such as #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)
Also, why is there even an 'i' here? Could we not just reuse Index?
Table->Gicc[i].ProximityDomain = Skt * NODE_IN_SOCKET;
}
- }
- }
- //remove invalid memory node
- RemoveInvalidMemoryNode (Table, MemoryNode);
Why is this invalid?
the memory nodes which are not be initialized will be invalid, we have to remove them and copy the next block data to the end of memory nodes block.
- return EFI_SUCCESS;
+}
+STATIC +EFI_STATUS +UpdateSlit (
- IN OUT EFI_ACPI_DESCRIPTION_HEADER *Table
- )
+{
- return EFI_SUCCESS;
+}
+EFI_STATUS +UpdateAcpiTable (
- IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader
+) +{
- EFI_STATUS Status = EFI_SUCCESS;
- switch (TableHeader->Signature) {
- case EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE:
- Status = UpdateSrat ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) TableHeader);
- break;
- case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
- Status = UpdateSlit (TableHeader);
- break;
- }
- return Status;
+}
1.9.1
We would get incorrect data when accessing multiple bytes at one time and going across EEPROM page boundary, so we split data when the length greater than page boundary.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org --- .../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 35 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c index 994ed6a..eaabb1d 100644 --- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -26,6 +26,7 @@ #include <Library/I2CLib.h>
#define EEPROM_I2C_PORT 6 +#define EEPROM_PAGE_SIZE 0x40
EFI_STATUS EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port); @@ -110,6 +111,8 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) UINT16 I2cOffset; UINT16 crc16; NIC_MAC_ADDRESS stMacDesc = {0}; + UINT16 RemainderMacOffset; + UINT16 LessSizeOfPage;
Status = I2CInit(0, EEPROM_I2C_PORT, Normal); if (EFI_ERROR(Status)) @@ -124,7 +127,20 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; + LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; + //The length of NIC_MAC_ADDRESS is 10 bytes long, + //It surly less than EEPROM page size, so we could + //code as bellow, check the address whether across the page boundary, + //and split the data when across page boundary. + if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { + Status |= I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + } else { + Status |= I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); + if (!(EFI_ERROR(Status))) { + Status |= I2CRead(&stI2cDev, I2cOffset + LessSizeOfPage, sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, (UINT8 *)&stMacDesc + LessSizeOfPage); + } + } if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); @@ -153,6 +169,8 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr)
stMacDesc.MacLen = MAC_ADDR_LEN; + UINT16 RemainderMacOffset; + UINT16 LessSizeOfPage; gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN);
stMacDesc.Crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN); @@ -170,7 +188,20 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0; - Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; + LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; + //The length of NIC_MAC_ADDRESS is 10 bytes long, + //It surly less than EEPROM page size, so we could + //code as bellow, check the address whether across the page boundary, + //and split the data when across page boundary. + if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { + Status |= I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + } else { + Status |= I2CWrite(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); + if (!(EFI_ERROR(Status))) { + Status |= I2CWrite(&stI2cDev, I2cOffset + LessSizeOfPage, sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, (UINT8 *)&stMacDesc + LessSizeOfPage); + } + } if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
On Thu, Nov 10, 2016 at 09:52:30PM +0800, Heyi Guo wrote:
We would get incorrect data when accessing multiple bytes at one time and going across EEPROM page boundary, so we split data when the length greater than page boundary.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li lipeicong@huawei.com Signed-off-by: Heyi Guo heyi.guo@linaro.org
.../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 35 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c index 994ed6a..eaabb1d 100644 --- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -26,6 +26,7 @@ #include <Library/I2CLib.h> #define EEPROM_I2C_PORT 6 +#define EEPROM_PAGE_SIZE 0x40 EFI_STATUS EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port); @@ -110,6 +111,8 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) UINT16 I2cOffset; UINT16 crc16; NIC_MAC_ADDRESS stMacDesc = {0};
- UINT16 RemainderMacOffset;
- UINT16 LessSizeOfPage;
Status = I2CInit(0, EEPROM_I2C_PORT, Normal); if (EFI_ERROR(Status)) @@ -124,7 +127,20 @@ EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0;
- Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
- RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
- LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
- //The length of NIC_MAC_ADDRESS is 10 bytes long,
- //It surly less than EEPROM page size, so we could
- //code as bellow, check the address whether across the page boundary,
- //and split the data when across page boundary.
- if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) {
Status |= I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
- } else {
Status |= I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc);
No need for |=. Status is always clear if we get here.
if (!(EFI_ERROR(Status))) {
Status |= I2CRead(&stI2cDev, I2cOffset + LessSizeOfPage, sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, (UINT8 *)&stMacDesc + LessSizeOfPage);
}
Indentation. Also, would make sense to wrap this long line.
Could write as
if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); } else { Status = I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); Status |= I2CRead( &stI2cDev, I2cOffset + LessSizeOfPage, sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, (UINT8 *)&stMacDesc + LessSizeOfPage ); }
Could also keep the "if (!EFI_ERROR" bit, if there is a problem with performing a second access if the first failed. But there is no point with the |= then, since we know Status is 0 if the code is executed.
- } if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
@@ -153,6 +169,8 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) stMacDesc.MacLen = MAC_ADDR_LEN;
- UINT16 RemainderMacOffset;
- UINT16 LessSizeOfPage; gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN);
stMacDesc.Crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN); @@ -170,7 +188,20 @@ EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) stI2cDev.Port = EEPROM_I2C_PORT; stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; stI2cDev.Socket = 0;
- Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
- RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
- LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
- //The length of NIC_MAC_ADDRESS is 10 bytes long,
- //It surly less than EEPROM page size, so we could
- //code as bellow, check the address whether across the page boundary,
- //and split the data when across page boundary.
- if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) {
Status |= I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
- } else {
Status |= I2CWrite(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc);
if (!(EFI_ERROR(Status))) {
Status |= I2CWrite(&stI2cDev, I2cOffset + LessSizeOfPage, sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, (UINT8 *)&stMacDesc + LessSizeOfPage);
Identical comments as for the Get function.
}
- } if (EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
-- 1.9.1