Hi Ard,
Please see my replies inline.
From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: Tuesday, October 18, 2016 2:56 PM
On 17 October 2016 at 21:04, Bhupesh Sharma bhupesh.sharma@freescale.com wrote:
From: Sakar Arora sakar.arora@nxp.com
NXP/FSL's LS1043A-RDB board houses a CPLD (FPGA) which can be used to control various pin-multiplexing options, which allows certain combinations of peripherals to be enabled on the board.
In addition this CPLD provides a mechanism to divide the NOR/NAND flash memory into primary and alternate regions. While golden images can be flashed on the primary bank, experimental images can be
flashed
on the alternate bank.
CPLD provides a way to switch from primary to alternate region (and vice-versa), thus protecting the board from damage if primary region is flashed with incorrect set of images.
Signed-off-by: Sakar Arora sakar.arora@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com
Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h | 75 +++ Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h | 721 +++++++++++++++++++++
Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c | 157 +++++
.../Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf | 33 + 4 files changed, 986 insertions(+) create mode 100644
Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h
create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h create mode 100644
Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c
create mode 100644 Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf
diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h b/Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h
Please add this library class to the package .dec file
Ok.
new file mode 100644 index 0000000..56f47da --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h @@ -0,0 +1,75 @@ +/** CpldLib.h +* Header defining the LS1043a Cpld specific constants (Base +addresses, sizes, flags) +* +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights
reserved.
+* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of +the BSD License +* which accompanies this distribution. The full text of the
license
+may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
OR IMPLIED.
+* +**/
+#ifndef __LS1043A_CPLD_H__ +#define __LS1043A_CPLD_H__
+#include <Library/Common.h>
+/*
- CPLD register set of LS1043ARDB board-specific.
- */
+struct CpldRegSet {
UINT8 CpldVersionMajor; /* 0x0 - CPLD Major Revision Register*/
UINT8 CpldVersionMinor; /* 0x1 - CPLD Minor Revision Register*/
UINT8 PcbaVersion; /* 0x2 - PCBA Revision Register */UINT8 SystemReset; /* 0x3 - system reset register */UINT8 SoftMuxOn; /* 0x4 - Switch Control EnableRegister */
UINT8 RcwSource1; /* 0x5 - Reset config word 1 */UINT8 RcwSource2; /* 0x6 - Reset config word 1 */UINT8 Vbank; /* 0x7 - Flash bank selection Control*/
UINT8 SysclkSelect; /* 0x8 - */UINT8 UartSel; /* 0x9 - */UINT8 Sd1RefClkSel; /* 0xA - */UINT8 TdmClkMuxSel; /* 0xB - */UINT8 SdhcSpiCsSel; /* 0xC - */UINT8 StatusLed; /* 0xD - */UINT8 GlobalReset; /* 0xE - */+};
+/*
- Reset the board, Reset to alternate bank or Dump registers:
- RESET - reset to default bank
- RESET_ALTBANK - reset to alternate bank
- DUMP_REGISTERS - display the CPLD registers */ typedef enum {
RESET = 0,RESET_ALTBANK,DUMP_REGISTERS+} CpldCmd;
+UINT8 CpldRead(UINTN Reg); +VOID CpldWrite(UINTN Reg, UINT8 Value); VOID CpldRevBit(UINT8 +*Value); VOID DoCpld (CpldCmd Cmd); VOID CpldInit (VOID);
+#define CPLD_READ(Reg) CpldRead(offsetof(struct CpldRegSet, Reg)) +#define CPLD_WRITE(Reg, Value) \
CpldWrite(offsetof(struct CpldRegSet, Reg), Value)+/* CPLD on IFC */ +#define CPLD_SW_MUX_BANK_SEL 0x40 +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_ALTBANK 0x04
+/* SDXC/DSPI CPLD Settings */ +#define ENABLE_SDXC_SOFT_MUX 0x30 +#define ENABLE_RCW_SOFT_MUX 0x01 +#define SELECT_SW4_SDXC 0x40 +#define SELECT_SW5_SDXC 0x01
+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h b/Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h
If this is an internal header, keep it with the .c files. Include/Library should only contain header files that define APIs that are exposed via LibraryClasses
Ok, will keep this with the .c files as this is an internal header.
new file mode 100644 index 0000000..27c8295 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h @@ -0,0 +1,721 @@ +/** @FslIfc.h
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2016, Freescale Semiconductor, Inc. All rights
reserved.
- This program and the accompanying materials are licensed and made
- available under the terms and conditions of the BSD License which
- accompanies this distribution. The full text of the license may be
- found at http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
- BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
+**/
+#ifndef __FLASH_H__ +#define __FLASH_H__
+#include <Uefi.h>
+#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> #include +<Library/DebugLib.h> #include <Library/IoLib.h> #include +<Library/PcdLib.h> #include <Library/UefiBootServicesTableLib.h> +#include <Library/IoLib.h> +#include <Library/PlatformLib.h>
+#include <Protocol/BlockIo.h> +#include <Protocol/Cpu.h>
+#define NOIBR
+#define FSL_IFC_BANK_COUNT 4
+#define NAND_PAGE_SIZE_2K (2048) +#define NAND_SPARE_AREA_SIZE_64B (64) +#define NAND_BLOCK_SIZE_128K (128*1024) +#define NAND_BLOCK_COUNT (2048) +#define NAND_LAST_BLOCK (NAND_BLOCK_COUNT - 1)
+//List of commands. +#define IFC_NAND_CMD_RESET 0xFF +#define IFC_NAND_CMD_READID 0x90
+#define IFC_NAND_CMD_STATUS 0x70
+#define IFC_NAND_CMD_READ0 0x00 +#define IFC_NAND_CMD_READSTART 0x30
+#define IFC_NAND_CMD_ERASE1 0x60 +#define IFC_NAND_CMD_ERASE2 0xD0
+#define IFC_NAND_CMD_SEQIN 0x80 +#define IFC_NAND_CMD_PAGEPROG 0x10
+#define MAX_RETRY_COUNT 150000
+#define FSL_IFC_REG_BASE 0x1530000 +#define FSL_IFC_NAND_BUF_BASE 0x70000000 +#define FSL_IFC_NOR_BUF_BASE 0x60000000
+#define FSL_IFC_NOR_RESERVED_REGION_BASE 0x60700000
+#define FSL_IFC_CSPR_REG_LEN 148 +#define FSL_IFC_AMASK_REG_LEN 144 +#define FSL_IFC_CSOR_REG_LEN 144 +#define FSL_IFC_FTIM_REG_LEN 576
+#define FSL_IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
+#define FSL_IFC_CSPR_USED_LEN sizeof(FSL_IFC_CSPR) * \
FSL_IFC_BANK_COUNT #define+FSL_IFC_AMASK_USED_LEN sizeof(FSL_IFC_AMASK) * \
FSL_IFC_BANK_COUNT #define+FSL_IFC_CSOR_USED_LEN sizeof(FSL_IFC_CSOR) * \
FSL_IFC_BANK_COUNT #define+FSL_IFC_FTIM_USED_LEN sizeof(FSL_IFC_FTIM) * \
FSL_IFC_BANK_COUNT+/*
- NAND Event and Error Status Register (NAND_EVTER_STAT) */
+/* Operation Complete */ +#define FSL_IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define FSL_IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define FSL_IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define FSL_IFC_NAND_EVTER_STAT_ECCER 0x02000000
+/*
- NAND Flash Byte Count Register (NAND_BC) */
+/* Byte Count for read/Write */ +#define FSL_IFC_NAND_BC 0x000001FF
+/*
- NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+*/ +/* NAND Machine specific opcodes OP0-OP14*/ +#define FSL_IFC_NAND_FIR0_OP0 0xFC000000 +#define FSL_IFC_NAND_FIR0_OP0_SHIFT 26 +#define FSL_IFC_NAND_FIR0_OP1 0x03F00000 +#define FSL_IFC_NAND_FIR0_OP1_SHIFT 20 +#define FSL_IFC_NAND_FIR0_OP2 0x000FC000 +#define FSL_IFC_NAND_FIR0_OP2_SHIFT 14 +#define FSL_IFC_NAND_FIR0_OP3 0x00003F00 +#define FSL_IFC_NAND_FIR0_OP3_SHIFT 8 +#define FSL_IFC_NAND_FIR0_OP4 0x000000FC +#define FSL_IFC_NAND_FIR0_OP4_SHIFT 2 +#define FSL_IFC_NAND_FIR1_OP5 0xFC000000 +#define FSL_IFC_NAND_FIR1_OP5_SHIFT 26 +#define FSL_IFC_NAND_FIR1_OP6 0x03F00000 +#define FSL_IFC_NAND_FIR1_OP6_SHIFT 20 +#define FSL_IFC_NAND_FIR1_OP7 0x000FC000 +#define FSL_IFC_NAND_FIR1_OP7_SHIFT 14 +#define FSL_IFC_NAND_FIR1_OP8 0x00003F00 +#define FSL_IFC_NAND_FIR1_OP8_SHIFT 8 +#define FSL_IFC_NAND_FIR1_OP9 0x000000FC +#define FSL_IFC_NAND_FIR1_OP9_SHIFT 2 +#define FSL_IFC_NAND_FIR2_OP10 0xFC000000 +#define FSL_IFC_NAND_FIR2_OP10_SHIFT 26 +#define FSL_IFC_NAND_FIR2_OP11 0x03F00000 +#define FSL_IFC_NAND_FIR2_OP11_SHIFT 20 +#define FSL_IFC_NAND_FIR2_OP12 0x000FC000 +#define FSL_IFC_NAND_FIR2_OP12_SHIFT 14 +#define FSL_IFC_NAND_FIR2_OP13 0x00003F00 +#define FSL_IFC_NAND_FIR2_OP13_SHIFT 8 +#define FSL_IFC_NAND_FIR2_OP14 0x000000FC +#define FSL_IFC_NAND_FIR2_OP14_SHIFT 2
+/*
- NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) */
+/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define FSL_IFC_NAND_FCR0_CMD0 0xFF000000 +#define FSL_IFC_NAND_FCR0_CMD0_SHIFT 24 +#define FSL_IFC_NAND_FCR0_CMD1 0x00FF0000 +#define FSL_IFC_NAND_FCR0_CMD1_SHIFT 16 +#define FSL_IFC_NAND_FCR0_CMD2 0x0000FF00 +#define FSL_IFC_NAND_FCR0_CMD2_SHIFT 8 +#define FSL_IFC_NAND_FCR0_CMD3 0x000000FF +#define FSL_IFC_NAND_FCR0_CMD3_SHIFT 0 +#define FSL_IFC_NAND_FCR1_CMD4 0xFF000000 +#define FSL_IFC_NAND_FCR1_CMD4_SHIFT 24 +#define FSL_IFC_NAND_FCR1_CMD5 0x00FF0000 +#define FSL_IFC_NAND_FCR1_CMD5_SHIFT 16 +#define FSL_IFC_NAND_FCR1_CMD6 0x0000FF00 +#define FSL_IFC_NAND_FCR1_CMD6_SHIFT 8 +#define FSL_IFC_NAND_FCR1_CMD7 0x000000FF +#define FSL_IFC_NAND_FCR1_CMD7_SHIFT 0
+/* Timing registers for NAND Flash */
+#define FSL_IFC_FTIM0_NAND_TCCST_SHIFT 25 +#define FSL_IFC_FTIM0_NAND_TCCST(n) ((n) <<
FSL_IFC_FTIM0_NAND_TCCST_SHIFT)
+#define FSL_IFC_FTIM0_NAND_TWP_SHIFT 16 +#define FSL_IFC_FTIM0_NAND_TWP(n) ((n) <<
FSL_IFC_FTIM0_NAND_TWP_SHIFT)
+#define FSL_IFC_FTIM0_NAND_TWCHT_SHIFT 8 +#define FSL_IFC_FTIM0_NAND_TWCHT(n) ((n) <<
FSL_IFC_FTIM0_NAND_TWCHT_SHIFT)
+#define FSL_IFC_FTIM0_NAND_TWH_SHIFT 0 +#define FSL_IFC_FTIM0_NAND_TWH(n) ((n) <<
FSL_IFC_FTIM0_NAND_TWH_SHIFT)
+#define FSL_IFC_FTIM1_NAND_TADLE_SHIFT 24 +#define FSL_IFC_FTIM1_NAND_TADLE(n) ((n) <<
FSL_IFC_FTIM1_NAND_TADLE_SHIFT)
+#define FSL_IFC_FTIM1_NAND_TWBE_SHIFT 16 +#define FSL_IFC_FTIM1_NAND_TWBE(n) ((n) <<
FSL_IFC_FTIM1_NAND_TWBE_SHIFT)
+#define FSL_IFC_FTIM1_NAND_TRR_SHIFT 8 +#define FSL_IFC_FTIM1_NAND_TRR(n) ((n) <<
FSL_IFC_FTIM1_NAND_TRR_SHIFT)
+#define FSL_IFC_FTIM1_NAND_TRP_SHIFT 0 +#define FSL_IFC_FTIM1_NAND_TRP(n) ((n) <<
FSL_IFC_FTIM1_NAND_TRP_SHIFT)
+#define FSL_IFC_FTIM2_NAND_TRAD_SHIFT 21 +#define FSL_IFC_FTIM2_NAND_TRAD(n) ((n) <<
FSL_IFC_FTIM2_NAND_TRAD_SHIFT)
+#define FSL_IFC_FTIM2_NAND_TREH_SHIFT 11 +#define FSL_IFC_FTIM2_NAND_TREH(n) ((n) <<
FSL_IFC_FTIM2_NAND_TREH_SHIFT)
+#define FSL_IFC_FTIM2_NAND_TWHRE_SHIFT 0 +#define FSL_IFC_FTIM2_NAND_TWHRE(n) ((n) <<
FSL_IFC_FTIM2_NAND_TWHRE_SHIFT)
+#define FSL_IFC_FTIM3_NAND_TWW_SHIFT 24 +#define FSL_IFC_FTIM3_NAND_TWW(n) ((n) <<
FSL_IFC_FTIM3_NAND_TWW_SHIFT)
+/*
- Flash ROW and COL Address Register (ROWn, COLn) */
+/* Main/spare region locator */ +#define FSL_IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define FSL_IFC_NAND_COL_CA_MASK 0x00000FFF
+#define NAND_STATUS_WP 0x80
+/*
- NAND Event and Error Enable Register (NAND_EVTER_EN) */
+/* Operation complete event enable */ +#define FSL_IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define FSL_IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define FSL_IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define FSL_IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define FSL_IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
+/*
- CSPR - Chip Select Property Register */
+#define IFC_CSPR_BA 0xFFFF0000 +#define IFC_CSPR_BA_SHIFT 16 +#define IFC_CSPR_PORT_SIZE 0x00000180 +#define IFC_CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define IFC_CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define IFC_CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define IFC_CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define IFC_CSPR_WP 0x00000040 +#define IFC_CSPR_WP_SHIFT 6 +/* Machine Select */ +#define IFC_CSPR_MSEL 0x00000006 +#define IFC_CSPR_MSEL_SHIFT 1 +/* NOR */ +#define IFC_CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define IFC_CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define IFC_CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define IFC_CSPR_V 0x00000001 +#define IFC_CSPR_V_SHIFT 0
+/*
- Chip Select Option Register - NOR Flash Mode */
+/* Enable Address shift Mode */ +#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define IFC_CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define IFC_CSOR_NOR_ADM_MASK 0x0003E000 +#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) <<
IFC_CSOR_NOR_ADM_SHIFT_SHIFT)
+/* Type of the NOR device hooked */ +#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C +#define IFC_CSOR_NOR_TRHZ_SHIFT 2 +#define IFC_CSOR_NOR_TRHZ_20 0x00000000 +#define IFC_CSOR_NOR_TRHZ_40 0x00000004 +#define IFC_CSOR_NOR_TRHZ_60 0x00000008 +#define IFC_CSOR_NOR_TRHZ_80 0x0000000C +#define IFC_CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define IFC_CSOR_NOR_BCTLD 0x00000001
+/*
- Chip Select Option Register FSL_IFC_NAND Machine */
+/* Enable ECC Encoder */ +#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000 +#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000 +/* 4 bit correction per 520 Byte sector */ +#define IFC_CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define IFC_CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define IFC_CSOR_NAND_RAL_MASK 0x01800000 +#define IFC_CSOR_NAND_RAL_SHIFT 20 +#define IFC_CSOR_NAND_RAL_1 0x00000000 +#define IFC_CSOR_NAND_RAL_2 0x00800000 +#define IFC_CSOR_NAND_RAL_3 0x01000000 +#define IFC_CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define IFC_CSOR_NAND_PGS_MASK 0x00180000 +#define IFC_CSOR_NAND_PGS_SHIFT 16 +#define IFC_CSOR_NAND_PGS_512 0x00000000 +#define IFC_CSOR_NAND_PGS_2K 0x00080000 +#define IFC_CSOR_NAND_PGS_4K 0x00100000 +#define IFC_CSOR_NAND_PGS_8K 0x00180000 +/* Spare region Size */ +#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000 +#define IFC_CSOR_NAND_SPRZ_SHIFT 13 +#define IFC_CSOR_NAND_SPRZ_16 0x00000000 +#define IFC_CSOR_NAND_SPRZ_64 0x00002000 +#define IFC_CSOR_NAND_SPRZ_128 0x00004000 +#define IFC_CSOR_NAND_SPRZ_210 0x00006000 +#define IFC_CSOR_NAND_SPRZ_218 0x00008000 +#define IFC_CSOR_NAND_SPRZ_224 0x0000A000 +#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 +/* Pages Per Block */ +#define IFC_CSOR_NAND_PB_MASK 0x00000700 +#define IFC_CSOR_NAND_PB_SHIFT 8 +#define IFC_CSOR_NAND_PB(n) (n-5) <<
IFC_CSOR_NAND_PB_SHIFT
+/* Time for Read Enable High to Output High Impedance */ +#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C +#define IFC_CSOR_NAND_TRHZ_SHIFT 2 +#define IFC_CSOR_NAND_TRHZ_20 0x00000000 +#define IFC_CSOR_NAND_TRHZ_40 0x00000004 +#define IFC_CSOR_NAND_TRHZ_60 0x00000008 +#define IFC_CSOR_NAND_TRHZ_80 0x0000000C +#define IFC_CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define IFC_CSOR_NAND_BCTLD 0x00000001
+#define FSL_IFC_NAND_BUF_MASK 0xffff0000 +#define FSL_IFC_NOR_BUF_MASK 0xffff0000
+#define FSL_IFC_NAND_CSPR ((FSL_IFC_NAND_BUF_BASE &
FSL_IFC_NAND_BUF_MASK)\
| IFC_CSPR_PORT_SIZE_8 \| IFC_CSPR_MSEL_NAND \| IFC_CSPR_V) #define+FSL_IFC_NAND_CSPR_EXT 0x0 +#define FSL_IFC_NAND_AMASK 0xFFFF0000 +#define FSL_IFC_NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on
encode */ \
| IFC_CSOR_NAND_ECC_DEC_EN /* ECC ondecode */ \
| IFC_CSOR_NAND_ECC_MODE_4 /* 4-bitECC */ \
| IFC_CSOR_NAND_RAL_3 /* RAL =3 Bytes */ \
| IFC_CSOR_NAND_PGS_2K /* PageSize = 2K */ \
| IFC_CSOR_NAND_SPRZ_64 /* Sparesize = 64 */ \
| IFC_CSOR_NAND_PB(6)) /* 2^6Pages Per Block */
+/*
- FTIM0 - NOR Flash Mode
- */
+#define FSL_IFC_FTIM0_NOR 0xF03F3F3F +#define FSL_IFC_FTIM0_NOR_TACSE_SHIFT 28 +#define FSL_IFC_FTIM0_NOR_TACSE(n) ((n) <<
FSL_IFC_FTIM0_NOR_TACSE_SHIFT)
+#define FSL_IFC_FTIM0_NOR_TEADC_SHIFT 16 +#define FSL_IFC_FTIM0_NOR_TEADC(n) ((n) <<
FSL_IFC_FTIM0_NOR_TEADC_SHIFT)
+#define FSL_IFC_FTIM0_NOR_TAVDS_SHIFT 8 +#define FSL_IFC_FTIM0_NOR_TAVDS(n) ((n) <<
FSL_IFC_FTIM0_NOR_TAVDS_SHIFT)
+#define FSL_IFC_FTIM0_NOR_TEAHC_SHIFT 0 +#define FSL_IFC_FTIM0_NOR_TEAHC(n) ((n) <<
FSL_IFC_FTIM0_NOR_TEAHC_SHIFT)
+/*
- FTIM1 - NOR Flash Mode
- */
+#define FSL_IFC_FTIM1_NOR 0xFF003F3F +#define FSL_IFC_FTIM1_NOR_TACO_SHIFT 24 +#define FSL_IFC_FTIM1_NOR_TACO(n) ((n) <<
FSL_IFC_FTIM1_NOR_TACO_SHIFT)
+#define FSL_IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FSL_IFC_FTIM1_NOR_TRAD_NOR(n) ((n) <<
FSL_IFC_FTIM1_NOR_TRAD_NOR_SHIFT)
+#define FSL_IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FSL_IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) <<
FSL_IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT)
+/*
- FTIM2 - NOR Flash Mode
- */
+#define FSL_IFC_FTIM2_NOR 0x0F3CFCFF +#define FSL_IFC_FTIM2_NOR_TCS_SHIFT 24 +#define FSL_IFC_FTIM2_NOR_TCS(n) ((n) <<
FSL_IFC_FTIM2_NOR_TCS_SHIFT)
+#define FSL_IFC_FTIM2_NOR_TCH_SHIFT 18 +#define FSL_IFC_FTIM2_NOR_TCH(n) ((n) <<
FSL_IFC_FTIM2_NOR_TCH_SHIFT)
+#define FSL_IFC_FTIM2_NOR_TWPH_SHIFT 10 +#define FSL_IFC_FTIM2_NOR_TWPH(n) ((n) <<
FSL_IFC_FTIM2_NOR_TWPH_SHIFT)
+#define FSL_IFC_FTIM2_NOR_TWP_SHIFT 0 +#define FSL_IFC_FTIM2_NOR_TWP(n) ((n) <<
FSL_IFC_FTIM2_NOR_TWP_SHIFT)
+/*
- FTIM0 - Normal GPCM Mode
- */
+#define FSL_IFC_FTIM0_GPCM 0xF03F3F3F +#define FSL_IFC_FTIM0_GPCM_TACSE_SHIFT 28 +#define FSL_IFC_FTIM0_GPCM_TACSE(n) ((n) <<
FSL_IFC_FTIM0_GPCM_TACSE_SHIFT)
+#define FSL_IFC_FTIM0_GPCM_TEADC_SHIFT 16 +#define FSL_IFC_FTIM0_GPCM_TEADC(n) ((n) <<
FSL_IFC_FTIM0_GPCM_TEADC_SHIFT)
+#define FSL_IFC_FTIM0_GPCM_TAVDS_SHIFT 8 +#define FSL_IFC_FTIM0_GPCM_TAVDS(n) ((n) <<
FSL_IFC_FTIM0_GPCM_TAVDS_SHIFT)
+#define FSL_IFC_FTIM0_GPCM_TEAHC_SHIFT 0 +#define FSL_IFC_FTIM0_GPCM_TEAHC(n) ((n) <<
FSL_IFC_FTIM0_GPCM_TEAHC_SHIFT)
+/*
- FTIM1 - Normal GPCM Mode
- */
+#define FSL_IFC_FTIM1_GPCM 0xFF003F00 +#define FSL_IFC_FTIM1_GPCM_TACO_SHIFT 24 +#define FSL_IFC_FTIM1_GPCM_TACO(n) ((n) <<
FSL_IFC_FTIM1_GPCM_TACO_SHIFT)
+#define FSL_IFC_FTIM1_GPCM_TRAD_SHIFT 8 +#define FSL_IFC_FTIM1_GPCM_TRAD(n) ((n) <<
FSL_IFC_FTIM1_GPCM_TRAD_SHIFT)
+/*
- FTIM2 - Normal GPCM Mode
- */
+#define FSL_IFC_FTIM2_GPCM 0x0F3C00FF +#define FSL_IFC_FTIM2_GPCM_TCS_SHIFT 24 +#define FSL_IFC_FTIM2_GPCM_TCS(n) ((n) <<
FSL_IFC_FTIM2_GPCM_TCS_SHIFT)
+#define FSL_IFC_FTIM2_GPCM_TCH_SHIFT 18 +#define FSL_IFC_FTIM2_GPCM_TCH(n) ((n) <<
FSL_IFC_FTIM2_GPCM_TCH_SHIFT)
+#define FSL_IFC_FTIM2_GPCM_TWP_SHIFT 0 +#define FSL_IFC_FTIM2_GPCM_TWP(n) ((n) <<
FSL_IFC_FTIM2_GPCM_TWP_SHIFT)
+/**
- fls - find last (most-significant) bit set
- @x: the word to search
- This is defined the same way as ffs.
- Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
+static inline int generic_fls(int x) +{
int r = 32;if (!x)return 0;if (!(x & 0xffff0000u)) {x <<= 16;r -= 16;}if (!(x & 0xff000000u)) {x <<= 8;r -= 8;}if (!(x & 0xf0000000u)) {x <<= 4;r -= 4;}if (!(x & 0xc0000000u)) {x <<= 2;r -= 2;}if (!(x & 0x80000000u)) {x <<= 1;r -= 1;}return r;+}
+static inline int __ilog2(unsigned int x) {
return generic_fls(x) - 1;+}
+/*
- Address Mask Register
- */
+#define FSL_IFC_AMASK_MASK 0xFFFF0000 +#define FSL_IFC_AMASK_SHIFT 16 +#define FSL_IFC_AMASK(n) (FSL_IFC_AMASK_MASK
<< \
(__ilog2(n) -FSL_IFC_AMASK_SHIFT))
+#define FSL_IFC_NOR_AMASK FSL_IFC_AMASK(128*1024*1024)
+#define FSL_IFC_NOR_CSPR ((FSL_IFC_NOR_BUF_BASE &
FSL_IFC_NOR_BUF_MASK)\
| IFC_CSPR_PORT_SIZE_16 \| IFC_CSPR_MSEL_NOR \| IFC_CSPR_V)+#define FSL_IFC_NOR_CSPR_EXT 0x0 +#define FSL_IFC_NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) |
\
IFC_CSOR_NOR_TRHZ_80)+#define FSL_IFC_NOR_FTIM0 (FSL_IFC_FTIM0_NOR_TACSE(0x1)
| \
FSL_IFC_FTIM0_NOR_TEADC(0x1) | \FSL_IFC_FTIM0_NOR_TAVDS(0x0) | \FSL_IFC_FTIM0_NOR_TEAHC(0xc))+#define FSL_IFC_NOR_FTIM1 (FSL_IFC_FTIM1_NOR_TACO(0x1c)
| \
FSL_IFC_FTIM1_NOR_TRAD_NOR(0xb) |\FSL_IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))+#define FSL_IFC_NOR_FTIM2 (FSL_IFC_FTIM2_NOR_TCS(0x1) |
\
FSL_IFC_FTIM2_NOR_TCH(0x4) | \FSL_IFC_FTIM2_NOR_TWPH(0x8) | \FSL_IFC_FTIM2_NOR_TWP(0x10))+#define FSL_IFC_NOR_FTIM3 0x0
+#define FSL_IFC_NOR_CSPR0 FSL_IFC_NOR_CSPR +#define FSL_IFC_NOR_AMASK0 FSL_IFC_NOR_AMASK +#define FSL_IFC_NOR_CSOR0 FSL_IFC_NOR_CSOR
+#define FSL_IFC_SRAM_BUF_SIZE 0x4000
+/* CPLD */
+/* Convert an address into the right format for the CSPR Registers
*/
+#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000)
+#define CPLD_BASE_PHYS LS1043A_CPLD_BASE
+#define FSL_IFC_CPLD_CSPR_EXT (0x0) +#define FSL_IFC_CPLD_CSPR
(IFC_CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
IFC_CSPR_PORT_SIZE_8 | \IFC_CSPR_MSEL_GPCM | \IFC_CSPR_V)+#define FSL_IFC_CPLD_AMASK FSL_IFC_AMASK(64 * 1024) +#define FSL_IFC_CPLD_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) |
\
IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \IFC_CSOR_NOR_TRHZ_80)+/* CPLD Timing parameters for IFC GPCM */ +#define FSL_IFC_CPLD_FTIM0
(FSL_IFC_FTIM0_GPCM_TACSE(0xf) | \
FSL_IFC_FTIM0_GPCM_TEADC(0xf) | \FSL_IFC_FTIM0_GPCM_TEAHC(0xf))+#define FSL_IFC_CPLD_FTIM1
(FSL_IFC_FTIM1_GPCM_TACO(0xff) | \
FSL_IFC_FTIM1_GPCM_TRAD(0x3f))+#define FSL_IFC_CPLD_FTIM2 (FSL_IFC_FTIM2_GPCM_TCS(0xf)
| \
FSL_IFC_FTIM2_GPCM_TCH(0xf) | \FSL_IFC_FTIM2_GPCM_TWP(0xff))+#define FSL_IFC_CPLD_FTIM3 0x0
+typedef enum {
FSL_IFC_CS0 = 0,FSL_IFC_CS1,FSL_IFC_CS2,FSL_IFC_CS3,FSL_IFC_CS4,FSL_IFC_CS5,FSL_IFC_CS6,FSL_IFC_CS7,+} FSL_IFC_CHIP_SEL;
+typedef enum {
FSL_IFC_FTIM0 = 0,FSL_IFC_FTIM1,FSL_IFC_FTIM2,FSL_IFC_FTIM3,+} FSL_IFC_FTIMS;
+/*
- Instruction opcodes to be programmed
- in FIR registers- 6bits
- */
+enum ifc_nand_fir_opcodes {
FSL_IFC_FIR_OP_NOP,FSL_IFC_FIR_OP_CA0,FSL_IFC_FIR_OP_CA1,FSL_IFC_FIR_OP_CA2,FSL_IFC_FIR_OP_CA3,FSL_IFC_FIR_OP_RA0,FSL_IFC_FIR_OP_RA1,FSL_IFC_FIR_OP_RA2,FSL_IFC_FIR_OP_RA3,FSL_IFC_FIR_OP_CMD0,FSL_IFC_FIR_OP_CMD1,FSL_IFC_FIR_OP_CMD2,FSL_IFC_FIR_OP_CMD3,FSL_IFC_FIR_OP_CMD4,FSL_IFC_FIR_OP_CMD5,FSL_IFC_FIR_OP_CMD6,FSL_IFC_FIR_OP_CMD7,FSL_IFC_FIR_OP_CW0,FSL_IFC_FIR_OP_CW1,FSL_IFC_FIR_OP_CW2,FSL_IFC_FIR_OP_CW3,FSL_IFC_FIR_OP_CW4,FSL_IFC_FIR_OP_CW5,FSL_IFC_FIR_OP_CW6,FSL_IFC_FIR_OP_CW7,FSL_IFC_FIR_OP_WBCD,FSL_IFC_FIR_OP_RBCD,FSL_IFC_FIR_OP_BTRD,FSL_IFC_FIR_OP_RDSTAT,FSL_IFC_FIR_OP_NWAIT,FSL_IFC_FIR_OP_WFR,FSL_IFC_FIR_OP_SBRD,FSL_IFC_FIR_OP_UA,FSL_IFC_FIR_OP_RB,+};
+typedef struct {
UINT32 cspr_ext;UINT32 cspr;UINT32 res;+} FSL_IFC_CSPR;
+typedef struct {
UINT32 amask;UINT32 res[0x2];+} FSL_IFC_AMASK;
+typedef struct {
UINT32 csor;UINT32 csor_ext;UINT32 res;+} FSL_IFC_CSOR;
+typedef struct {
UINT32 ftim[4];UINT32 res[0x8];+}FSL_IFC_FTIM ;
+typedef struct {
UINT32 ncfgr;UINT32 res1[0x4];UINT32 nand_fcr0;UINT32 nand_fcr1;UINT32 res2[0x8];UINT32 row0;UINT32 res3;UINT32 col0;UINT32 res4;UINT32 row1;UINT32 res5;UINT32 col1;UINT32 res6;UINT32 row2;UINT32 res7;UINT32 col2;UINT32 res8;UINT32 row3;UINT32 res9;UINT32 col3;UINT32 res10[0x24];UINT32 nand_fbcr;UINT32 res11;UINT32 nand_fir0;UINT32 nand_fir1;UINT32 nand_fir2;UINT32 res12[0x10];UINT32 nand_csel;UINT32 res13;UINT32 nandseq_strt;UINT32 res14;UINT32 nand_evter_stat;UINT32 res15;UINT32 pgrdcmpl_evt_stat;UINT32 res16[0x2];UINT32 nand_evter_en;UINT32 res17[0x2];UINT32 nand_evter_intr_en;UINT32 res18[0x2];UINT32 nand_erattr0;UINT32 nand_erattr1;UINT32 res19[0x10];UINT32 nand_fsr;UINT32 res20;UINT32 nand_eccstat[4];UINT32 res21[0x20];UINT32 nanndcr;UINT32 res22[0x2];UINT32 nand_autoboot_trgr;UINT32 res23;UINT32 nand_mdr;UINT32 res24[0x5C];+} FSL_IFC_NAND;
+/*
- IFC controller NOR Machine registers */ typedef struct {
UINT32 nor_evter_stat;UINT32 res1[0x2];UINT32 nor_evter_en;UINT32 res2[0x2];UINT32 nor_evter_intr_en;UINT32 res3[0x2];UINT32 nor_erattr0;UINT32 nor_erattr1;UINT32 nor_erattr2;UINT32 res4[0x4];UINT32 norcr;UINT32 res5[0xEF];+} FSL_IFC_NOR;
+/*
- IFC controller GPCM Machine registers
- */
+typedef struct {
UINT32 gpcm_evter_stat;UINT32 res1[0x2];UINT32 gpcm_evter_en;UINT32 res2[0x2];UINT32 gpcm_evter_intr_en;UINT32 res3[0x2];UINT32 gpcm_erattr0;UINT32 gpcm_erattr1;UINT32 gpcm_erattr2;UINT32 gpcm_stat;+} FSL_IFC_GPCM;
+/*
- IFC Controller Registers
- */
+typedef struct {
UINT32 ifc_rev;UINT32 res1[0x2];FSL_IFC_CSPR cspr_cs[FSL_IFC_BANK_COUNT];UINT8 res2[FSL_IFC_CSPR_REG_LEN - FSL_IFC_CSPR_USED_LEN];FSL_IFC_AMASK amask_cs[FSL_IFC_BANK_COUNT];UINT8 res3[FSL_IFC_AMASK_REG_LEN - FSL_IFC_AMASK_USED_LEN];FSL_IFC_CSOR csor_cs[FSL_IFC_BANK_COUNT];UINT8 res4[FSL_IFC_CSOR_REG_LEN - FSL_IFC_CSOR_USED_LEN];FSL_IFC_FTIM ftim_cs[FSL_IFC_BANK_COUNT];UINT8 res5[FSL_IFC_FTIM_REG_LEN - FSL_IFC_FTIM_USED_LEN];UINT32 rb_stat;UINT32 rb_map;UINT32 wp_map;UINT32 ifc_gcr;UINT32 res7[0x2];UINT32 cm_evter_stat;UINT32 res8[0x2];UINT32 cm_evter_en;UINT32 res9[0x2];UINT32 cm_evter_intr_en;UINT32 res10[0x2];UINT32 cm_erattr0;UINT32 cm_erattr1;UINT32 res11[0x2];UINT32 ifc_ccr;UINT32 ifc_csr;UINT32 ddr_ccr_low;UINT32 res12[0x2EA];FSL_IFC_NAND ifc_nand;FSL_IFC_NOR ifc_nor;FSL_IFC_GPCM ifc_gpcm;+} FSL_IFC_REGS;
+VOID IfcNorInit(VOID);
+VOID IfcNandInit(VOID);
+#define FSL_IFC_REGS_BASE \
((FSL_IFC_REGS *)FSL_IFC_REG_BASE)+#endif //__FLASH_H__ diff --git a/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c
b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c
new file mode 100644 index 0000000..fe115c8 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c @@ -0,0 +1,157 @@ +/** @CpldLib.c
- Cpld specific Library for LS1043A-RDB board, containing functions
to
- program and read the Cpld registers.
- Copyright (c) 2016, Freescale Semiconductor, Inc. All rights
reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of
the BSD License
- which accompanies this distribution. The full text of the license
may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
OR IMPLIED.
+**/
+#include <Base.h> +#include <PiPei.h> +#include <Uefi.h>
+#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PrintLib.h> +#include <Library/SerialPortLib.h>
+#include <Library/PlatformLib.h> +#include <Library/CpldLib.h> +#include <Library/FslIfc.h>
+UINT8 +CpldRead (
- OUT UINTN Reg
- )
+{
VOID *Base = (VOID *)LS1043A_CPLD_BASE;return MmioRead8((UINTN)(Base + Reg));+}
+VOID +CpldWrite (
- IN UINTN Reg,
- IN UINT8 Value
- )
+{
VOID *Base = (VOID *)LS1043A_CPLD_BASE;MmioWrite8((UINTN)(Base + Reg), Value);+}
+/* Set the boot bank to the alternate bank */ +VOID +CpldSetAlternatebank (
- VOID
- )
+{
UINT8 Reg4 = CPLD_READ(SoftMuxOn);UINT8 Reg7 = CPLD_READ(Vbank);CPLD_WRITE(SoftMuxOn, Reg4 | CPLD_SW_MUX_BANK_SEL);Reg7 = (Reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;CPLD_WRITE(Vbank, Reg7);CPLD_WRITE(SystemReset, 1);+}
+/* Set the boot bank to the default bank */ +VOID +CpldSetDefaultBank (
- VOID
- )
+{
CPLD_WRITE(GlobalReset, 1);+}
+VOID +CpldDumpRegs (
- VOID
- )
+{
DEBUG((EFI_D_INFO, "CpldVersionMajor = %x\n",CPLD_READ(CpldVersionMajor)));
DEBUG((EFI_D_INFO, "CpldVersionMinor = %x\n",CPLD_READ(CpldVersionMinor)));
DEBUG((EFI_D_INFO, "PcbaVersion = %x\n",CPLD_READ(PcbaVersion)));
DEBUG((EFI_D_INFO, "SoftMuxOn = %x\n",CPLD_READ(SoftMuxOn)));
DEBUG((EFI_D_INFO, "RcwSource1 = %x\n",CPLD_READ(RcwSource1)));
DEBUG((EFI_D_INFO, "RcwSource2 = %x\n",CPLD_READ(RcwSource2)));
DEBUG((EFI_D_INFO, "Vbank = %x\n",CPLD_READ(Vbank)));
DEBUG((EFI_D_INFO, "SysclkSelect = %x\n",CPLD_READ(SysclkSelect)));
DEBUG((EFI_D_INFO, "UartSel = %x\n",CPLD_READ(UartSel)));
DEBUG((EFI_D_INFO, "Sd1RefClkSel = %x\n",CPLD_READ(Sd1RefClkSel)));
DEBUG((EFI_D_INFO, "TdmClkMuxSel = %x\n",CPLD_READ(TdmClkMuxSel)));
DEBUG((EFI_D_INFO, "SdhcSpiCsSel = %x\n",CPLD_READ(SdhcSpiCsSel)));
DEBUG((EFI_D_INFO, "StatusLed = %x\n",CPLD_READ(StatusLed)));
+}
+VOID +CpldRevBit (
- OUT UINT8 *Value
- )
+{
UINT8 Rev, Val;UINTN Index;Val = *Value;Rev = Val & 1;for (Index = 1; Index <= 7; Index++) {Val >>= 1;Rev <<= 1;Rev |= Val & 1;}*Value = Rev;+}
+VOID +DoCpld (
- IN CpldCmd Cmd
- )
+{
switch (Cmd) {case RESET:CpldSetDefaultBank();break;case RESET_ALTBANK:CpldSetAlternatebank();break;case DUMP_REGISTERS:CpldDumpRegs();break;default:DEBUG((EFI_D_ERROR, "Error: Unknown CpldCommand!\n"));
break;}+}
+VOID +CpldInit (
- VOID
- )
+{
MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-cspr_cs[FSL_IFC_CS2].cspr_ext, FSL_IFC_CPLD_CSPR_EXT);
MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM0],
FSL_IFC_CPLD_FTIM0);MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM1],
FSL_IFC_CPLD_FTIM1);MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM2],
FSL_IFC_CPLD_FTIM2);MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM3],
FSL_IFC_CPLD_FTIM3);MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-csor_cs[FSL_IFC_CS2].csor, FSL_IFC_CPLD_CSOR);
MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-amask_cs[FSL_IFC_CS2].amask, FSL_IFC_CPLD_AMASK);
MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)-cspr_cs[FSL_IFC_CS2].cspr, FSL_IFC_CPLD_CSPR); +} diff --git a/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf
b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf
new file mode 100644 index 0000000..f37d153 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf @@ -0,0 +1,33 @@ +#/* @CpldLib.inf +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights
reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of
the BSD License
+# which accompanies this distribution. The full text of the
license may be found at
+# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
OR IMPLIED.
+# +#*/
+[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = CpldLib
- FILE_GUID = 5962d040-8b8a-11df-9a71-
0002a5d5c51b
Please use a fresh GUID
Ok.
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = CpldLib
+[Sources.common]
- CpldLib.c
+[Packages]
- MdePkg/MdePkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec
+[LibraryClasses]
- BaseLib
- IoLib
-- 1.9.1
Regards, Bhupesh