On 17 October 2016 at 21:04, Bhupesh Sharma bhupesh.sharma@freescale.com wrote:
From: Sakar Arora sakar.arora@nxp.com
There are several early SoC/Board level initialization functions which need to be performed before the DXE phase can execute.
While some of these are more related to how the boot information looks on the console, others are related to setting up SoC/board components/mux'es in a way that a particular component can be used.
This patch adds the support for the same.
Signed-off-by: Sakar Arora sakar.arora@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com
Platforms/Nxp/LS1043aRdb/Include/Library/SocLib.h | 308 +++++++++++++++++++++ .../Library/LS1043aSocLib/LS1043aSocLib.c | 140 ++++++++++ .../Library/LS1043aSocLib/LS1043aSocLib.inf | 40 +++ 3 files changed, 488 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/SocLib.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.inf
diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/SocLib.h b/Platforms/Nxp/LS1043aRdb/Include/Library/SocLib.h new file mode 100644 index 0000000..d1655d5 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/SocLib.h
If this header defines the public API of the SocLib library class, please add this library to the [LibraryClasses] section of the package .dec file. If it is an internal header for the SocLib implementation, please keep it with the .c file. If it is both, please split it up.
@@ -0,0 +1,308 @@ +/** SoCLib.h +* Header defining the LS1043a SoC specific constants (Base addresses, sizes, flags) +* +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/
+#ifndef __LS1043A_SOC_H__ +#define __LS1043A_SOC_H__
+#define LS1043A_NUM_CC_PLLS 2 +#define HWA_CGA_M1_CLK_SEL 0xe0000000 +#define HWA_CGA_M1_CLK_SHIFT 29 +#define HWA_CGA_M2_CLK_SEL 0x00000007 +#define HWA_CGA_M2_CLK_SHIFT 0
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define LS1043A_CLK_FREQ 100000000 +#define LS1043A_DDR_CLK_FREQ 100000000
+#define LS1043A_MAX_CPUS 4 +#define LS1043A_NUM_FMAN 1
+struct SysInfo {
UINTN FreqProcessor[LS1043A_MAX_CPUS];UINTN FreqSystemBus;UINTN FreqDdrBus;UINTN FreqLocalBus;UINTN FreqSdhc;UINTN FreqFman[LS1043A_NUM_FMAN];UINTN FreqQman;+};
+/* Device Configuration and Pin Control */ +struct CcsrGur {
UINT32 porsr1; /* POR status 1 */UINT32 porsr2; /* POR status 2 */UINT8 res_008[0x20-0x8];UINT32 gpporcr1; /* General-purpose POR configuration */UINT32 gpporcr2;UINT32 dcfg_fusesr; /* Fuse status register */UINT8 res_02c[0x70-0x2c];UINT32 devdisr; /* Device disable control */UINT32 devdisr2; /* Device disable control 2 */UINT32 devdisr3; /* Device disable control 3 */UINT32 devdisr4; /* Device disable control 4 */UINT32 devdisr5; /* Device disable control 5 */UINT32 devdisr6; /* Device disable control 6 */UINT32 devdisr7; /* Device disable control 7 */UINT8 res_08c[0x94-0x8c];UINT32 coredisru; /* uppper portion for support of 64 cores */UINT32 coredisrl; /* lower portion for support of 64 cores */UINT8 res_09c[0xa0-0x9c];UINT32 pvr; /* Processor version */UINT32 svr; /* System version */UINT32 mvr; /* Manufacturing version */UINT8 res_0ac[0xb0-0xac];UINT32 rstcr; /* Reset control */UINT32 rstrqpblsr; /* Reset request preboot loader status */UINT8 res_0b8[0xc0-0xb8];UINT32 rstrqmr1; /* Reset request mask */UINT8 res_0c4[0xc8-0xc4];UINT32 rstrqsr1; /* Reset request status */UINT8 res_0cc[0xd4-0xcc];UINT32 rstrqwdtmrl; /* Reset request WDT mask */UINT8 res_0d8[0xdc-0xd8];UINT32 rstrqwdtsrl; /* Reset request WDT status */UINT8 res_0e0[0xe4-0xe0];UINT32 brrl; /* Boot release */UINT8 res_0e8[0x100-0xe8];UINT32 rcwsr[16]; /* Reset control word status */+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
UINT8 res_140[0x200-0x140];UINT32 scratchrw[4]; /* Scratch Read/Write */UINT8 res_210[0x300-0x210];UINT32 scratchw1r[4]; /* Scratch Read (Write once) */UINT8 res_310[0x400-0x310];UINT32 crstsr[12];UINT8 res_430[0x500-0x430];/* PCI Express n Logical I/O Device Number register */UINT32 dcfg_ccsr_pex1liodnr;UINT32 dcfg_ccsr_pex2liodnr;UINT32 dcfg_ccsr_pex3liodnr;UINT32 dcfg_ccsr_pex4liodnr;/* RIO n Logical I/O Device Number register */UINT32 dcfg_ccsr_rio1liodnr;UINT32 dcfg_ccsr_rio2liodnr;UINT32 dcfg_ccsr_rio3liodnr;UINT32 dcfg_ccsr_rio4liodnr;/* USB Logical I/O Device Number register */UINT32 dcfg_ccsr_usb1liodnr;UINT32 dcfg_ccsr_usb2liodnr;UINT32 dcfg_ccsr_usb3liodnr;UINT32 dcfg_ccsr_usb4liodnr;/* SD/MMC Logical I/O Device Number register */UINT32 dcfg_ccsr_sdmmc1liodnr;UINT32 dcfg_ccsr_sdmmc2liodnr;UINT32 dcfg_ccsr_sdmmc3liodnr;UINT32 dcfg_ccsr_sdmmc4liodnr;/* RIO Message Unit Logical I/O Device Number register */UINT32 dcfg_ccsr_riomaintliodnr;UINT8 res_544[0x550-0x544];UINT32 sataliodnr[4];UINT8 res_560[0x570-0x560];UINT32 dcfg_ccsr_misc1liodnr;UINT32 dcfg_ccsr_misc2liodnr;UINT32 dcfg_ccsr_misc3liodnr;UINT32 dcfg_ccsr_misc4liodnr;UINT32 dcfg_ccsr_dma1liodnr;UINT32 dcfg_ccsr_dma2liodnr;UINT32 dcfg_ccsr_dma3liodnr;UINT32 dcfg_ccsr_dma4liodnr;UINT32 dcfg_ccsr_spare1liodnr;UINT32 dcfg_ccsr_spare2liodnr;UINT32 dcfg_ccsr_spare3liodnr;UINT32 dcfg_ccsr_spare4liodnr;UINT8 res_5a0[0x600-0x5a0];UINT32 dcfg_ccsr_pblsr;UINT32 pamubypenr;UINT32 dmacr1;UINT8 res_60c[0x610-0x60c];UINT32 dcfg_ccsr_gensr1;UINT32 dcfg_ccsr_gensr2;UINT32 dcfg_ccsr_gensr3;UINT32 dcfg_ccsr_gensr4;UINT32 dcfg_ccsr_gencr1;UINT32 dcfg_ccsr_gencr2;UINT32 dcfg_ccsr_gencr3;UINT32 dcfg_ccsr_gencr4;UINT32 dcfg_ccsr_gencr5;UINT32 dcfg_ccsr_gencr6;UINT32 dcfg_ccsr_gencr7;UINT8 res_63c[0x658-0x63c];UINT32 dcfg_ccsr_cgensr1;UINT32 dcfg_ccsr_cgensr0;UINT8 res_660[0x678-0x660];UINT32 dcfg_ccsr_cgencr1;UINT32 dcfg_ccsr_cgencr0;UINT8 res_680[0x700-0x680];UINT32 dcfg_ccsr_sriopstecr;UINT32 dcfg_ccsr_dcsrcr;UINT8 res_708[0x740-0x708]; /* add more registers when needed */UINT32 tp_ityp[64]; /* Topology Initiator Type Register */struct {UINT32 upper;UINT32 lower;} tp_cluster[16];UINT8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */UINT32 dcfg_ccsr_qmbm_warmrst;UINT8 res_a04[0xa20-0xa04]; /* add more registers when needed */UINT32 dcfg_ccsr_reserved0;UINT32 dcfg_ccsr_reserved1;+};
+/* Supplemental Configuration Unit */ +struct CcsrScfg {
UINT8 res_000[0x100-0x000];UINT32 usb2_icid;UINT32 usb3_icid;UINT8 res_108[0x114-0x108];UINT32 dma_icid;UINT32 sata_icid;UINT32 usb1_icid;UINT32 qe_icid;UINT32 sdhc_icid;UINT32 edma_icid;UINT32 etr_icid;UINT32 core0_sft_rst;UINT32 core1_sft_rst;UINT32 core2_sft_rst;UINT32 core3_sft_rst;UINT8 res_140[0x158-0x140];UINT32 altcbar;UINT32 qspi_cfg;UINT8 res_160[0x180-0x160];UINT32 dmamcr;UINT8 res_184[0x18c-0x184];UINT32 debug_icid;UINT8 res_190[0x1a4-0x190];UINT32 snpcnfgcr;UINT8 res_1a8[0x1ac-0x1a8];UINT32 intpcr;UINT8 res_1b0[0x204-0x1b0];UINT32 coresrencr;UINT8 res_208[0x220-0x208];UINT32 rvbar0_0;UINT32 rvbar0_1;UINT32 rvbar1_0;UINT32 rvbar1_1;UINT32 rvbar2_0;UINT32 rvbar2_1;UINT32 rvbar3_0;UINT32 rvbar3_1;UINT32 lpmcsr;UINT8 res_244[0x400-0x244];UINT32 qspidqscr;UINT32 ecgtxcmcr;UINT32 sdhciovselcr;UINT32 rcwpmuxcr0;UINT32 usbdrvvbus_selcr;UINT32 usbpwrfault_selcr;UINT32 usb_refclk_selcr1;UINT32 usb_refclk_selcr2;UINT32 usb_refclk_selcr3;UINT8 res_424[0x600-0x424];UINT32 scratchrw[4];UINT8 res_610[0x680-0x610];UINT32 corebcr;UINT8 res_684[0x1000-0x684];UINT32 pex1msiir;UINT32 pex1msir;UINT8 res_1008[0x2000-0x1008];UINT32 pex2;UINT32 pex2msir;UINT8 res_2008[0x3000-0x2008];UINT32 pex3msiir;UINT32 pex3msir;+};
+/* Clocking */ +struct CcsrClk {
struct {UINT32 clkcncsr; /* core cluster n clock control status */UINT8 res_004[0x0c];UINT32 clkcghwacsr; /* Clock generator n hardware accelerator */UINT8 res_014[0x0c];} clkcsr[4];UINT8 res_040[0x780]; /* 0x100 */struct {UINT32 pllcngsr;UINT8 res_804[0x1c];} pllcgsr[2];UINT8 res_840[0x1c0];UINT32 clkpcsr; /* 0xa00 Platform clock domain control/status */UINT8 res_a04[0x1fc];UINT32 pllpgsr; /* 0xc00 Platform PLL General Status */UINT8 res_c04[0x1c];UINT32 plldgsr; /* 0xc20 DDR PLL General Status */UINT8 res_c24[0x3dc];+};
+/* CCI-400 registers */ +struct CcsrCci400 {
UINT32 ctrl_ord; /* Control Override */UINT32 spec_ctrl; /* Speculation Control */UINT32 secure_access; /* Secure Access */UINT32 status; /* Status */UINT32 impr_err; /* Imprecise Error */UINT8 res_14[0x100 - 0x14];UINT32 pmcr; /* Performance Monitor Control */UINT8 res_104[0xfd0 - 0x104];UINT32 pid[8]; /* Peripheral ID */UINT32 cid[4]; /* Component ID */struct {UINT32 snoop_ctrl; /* Snoop Control */UINT32 sha_ord; /* Shareable Override */UINT8 res_1008[0x1100 - 0x1008];UINT32 rc_qos_ord; /* read channel QoS Value Override */UINT32 wc_qos_ord; /* read channel QoS Value Override */UINT8 res_1108[0x110c - 0x1108];UINT32 qos_ctrl; /* QoS Control */UINT32 max_ot; /* Max OT */UINT8 res_1114[0x1130 - 0x1114];UINT32 target_lat; /* Target Latency */UINT32 latency_regu; /* Latency Regulation */UINT32 qos_range; /* QoS Range */UINT8 res_113c[0x2000 - 0x113c];} slave[5]; /* Slave Interface */UINT8 res_6000[0x9004 - 0x6000];UINT32 cycle_counter; /* Cycle counter */UINT32 count_ctrl; /* Count Control */UINT32 overflow_status; /* Overflow Flag Status */UINT8 res_9010[0xa000 - 0x9010];struct {UINT32 event_select; /* Event Select */UINT32 event_count; /* Event Count */UINT32 counter_ctrl; /* Counter Control */UINT32 overflow_status; /* Overflow Flag Status */UINT8 res_a010[0xb000 - 0xa010];} pcounter[4]; /* Performance Counter */UINT8 res_e004[0x10000 - 0xe004];+};
+UINT32 CalculateBaudDivisor(OUT UINT64 *BaudRate); +UINT32 CalculateI2cClockRate(VOID);
+#endif /* __LS1043A_SOC_H__ */ diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.c new file mode 100644 index 0000000..fdeae08 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.c @@ -0,0 +1,140 @@ +/** @SoCLib.c
- SoC specific Library for LS1043A SoC, containing functions to initialize various SoC components
- Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#include <Base.h> +#include <PiPei.h> +#include <Uefi.h> +#include <Library/BaseLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/PrePiLib.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/DebugAgentLib.h> +#include <Library/IoLib.h> +#include <Library/PrintLib.h>
+#include <Library/PlatformLib.h> +#include <Library/SocLib.h> +#include <Library/CpldLib.h>
+VOID +GetSysInfo (
- OUT struct SysInfo *PtrSysInfo
- )
+{
struct CcsrGur *GurBase = (void *)(LS1043A_FSL_GUTS_ADDR);struct CcsrClk *ClkBase = (void *)(LS1043A_FSL_CLK_ADDR);UINTN CpuIndex;UINT32 TempRcw;const UINT8 CoreCplxPll[8] = {[0] = 0, /* CC1 PPL / 1 */[1] = 0, /* CC1 PPL / 2 */[4] = 1, /* CC2 PPL / 1 */[5] = 1, /* CC2 PPL / 2 */};const UINT8 CoreCplxPllDivisor[8] = {[0] = 1, /* CC1 PPL / 1 */[1] = 2, /* CC1 PPL / 2 */[4] = 1, /* CC2 PPL / 1 */[5] = 2, /* CC2 PPL / 2 */};
please make these STATIC CONST and move out of the function
UINTN PllCount;UINTN FreqCPll[LS1043A_FSL_NUM_CC_PLLS];UINTN PllRatio[LS1043A_FSL_NUM_CC_PLLS];UINTN SysClk = LS1043A_CLK_FREQ;PtrSysInfo->FreqSystemBus = SysClk;PtrSysInfo->FreqDdrBus = SysClk;PtrSysInfo->FreqSystemBus *= (MmioReadBe32((UINTN)&GurBase->rcwsr[0]) >>FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;PtrSysInfo->FreqDdrBus *= (MmioReadBe32((UINTN)&GurBase->rcwsr[0]) >>FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;for (PllCount = 0; PllCount < LS1043A_FSL_NUM_CC_PLLS; PllCount++) {PllRatio[PllCount] = (MmioReadBe32((UINTN)&ClkBase->pllcgsr[PllCount].pllcngsr) >> 1) & 0xff;if (PllRatio[PllCount] > 4)FreqCPll[PllCount] = SysClk * PllRatio[PllCount];elseFreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];}for (CpuIndex = 0; CpuIndex < LS1043A_MAX_CPUS; CpuIndex++) {UINT32 c_pll_sel = (MmioReadBe32((UINTN)&ClkBase->clkcsr[CpuIndex].clkcncsr) >> 27)& 0xf;UINT32 cplx_pll = CoreCplxPll[c_pll_sel];PtrSysInfo->FreqProcessor[CpuIndex] =FreqCPll[cplx_pll] / CoreCplxPllDivisor[c_pll_sel];}TempRcw = MmioReadBe32((UINTN)&GurBase->rcwsr[7]);switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {case 2:PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;break;case 3:PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;break;case 6:PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;break;case 7:PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;break;default:DEBUG((EFI_D_WARN, "Error: Unknown FMan1 clock select!\n"));break;}TempRcw = MmioReadBe32((UINTN)&GurBase->rcwsr[15]);TempRcw = (TempRcw & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;PtrSysInfo->FreqSdhc = FreqCPll[1] / TempRcw;PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus / 2;+}
+UINT32 +CalculateBaudDivisor (
- OUT UINT64 *BaudRate
- )
+{
struct SysInfo SocSysInfo;UINTN DUartClk;GetSysInfo(&SocSysInfo);DUartClk = SocSysInfo.FreqSystemBus;return ((DUartClk)/(*BaudRate * 16));+}
+UINT32 +CalculateI2cClockRate(
VOID)+{
struct SysInfo SocSysInfo;GetSysInfo(&SocSysInfo);return SocSysInfo.FreqSystemBus;+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.inf b/Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.inf new file mode 100644 index 0000000..322fe34 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aSocLib/LS1043aSocLib.inf @@ -0,0 +1,40 @@ +#/* @SoCLib.inf +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/
+[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = LS1043aSocLib
- FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
Use a fresh GUID
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SocLib
+[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec
- OpenPlatformPkg/Chips/Nxp/QoriqLs/NxpQoriqLs.dec
+[LibraryClasses]
- BaseLib
- CpldLib
- DebugLib
- DebugAgentLib
- IoLib
- ArmLib
+[Sources.common]
- LS1043aSocLib.c
-- 1.9.1