在 8/4/2018 5:34 PM, Leif Lindholm 写道:
On Tue, Jul 24, 2018 at 03:09:10PM +0800, Ming Huang wrote:
From: Sun Yuanchen sunyuanchen@huawei.com
Move some RAS macros definition to PlatformArch.h for unifying D0x
Minor comments below. However, I would still prefer for this to be split up into a refactoring patch for d03/d05, and then simpley introduced when the d06 files are added.
OK, do it in v2.
/ Leif
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sun Yuanchen sunyuanchen@huawei.com Signed-off-by: Ming Huang ming.huang@linaro.org Signed-off-by: Heyi Guo heyi.guo@linaro.org
Silicon/Hisilicon/Hi1610/Include/PlatformArch.h | 7 +++++-- Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 4 ++++ Silicon/Hisilicon/Hi1620/Include/PlatformArch.h | 8 ++++++-- 3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h index 4843b60536..5198e3efff 100644 --- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h @@ -1,7 +1,7 @@ /** @file
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
@@ -38,6 +38,9 @@ #define S1_BASE 0x40000000000 +#define RASC_BASE (0x5000) +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) /* RASC_CFG_INFOIDX??RASC?Ķ?ȡRankͳ????Ϣ???üĴ??? */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) /* RASC_CFG_SPLVL??RASC??Sparingˮ?????üĴ??? */
Character encoding issues in comment.
// // ACPI table information used to initialize tables. diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h index 49618f6559..5124714cb5 100644 --- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h @@ -30,6 +30,10 @@ // Max NUMA node number for each node type #define MAX_NUM_PER_TYPE 8 +#define RASC_BASE (0x5000) +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) /* RASC_CFG_INFOIDX??RASC?Ķ?ȡRankͳ????Ϣ???üĴ??? */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) /* RASC_CFG_SPLVL??RASC??Sparingˮ?????üĴ??? */
Character encoding issues in comment.
// for acpi #define NODE_IN_SOCKET 2 #define CORE_NUM_PER_SOCKET 32 diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h index 2626751a0d..f2491315a8 100644 --- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h @@ -1,7 +1,7 @@ /** @file
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
@@ -31,6 +31,10 @@ #define MAX_NUM_PER_TYPE 8 +#define RASC_BASE (0x1800) +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x58) /* configuration register for Rank statistical information */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xD4) /* configuration register for Sparing level */
Much nicer comments.
// for acpi #define NODE_IN_SOCKET 2
#define CORE_NUM_PER_SOCKET 48
2.17.0