From: Heyi Guo heyi.guo@linaro.org
This patch is for https://bugs.linaro.org/show_bug.cgi?id=2711.
When there is no optical module plugged in XGE port, the interfaces (ethX) will show up/down information on console, such as below:
[root@localhost ~]# [ 676.034368] hns-nic HISI00C2:03 eth3: link up [ 676.038840] IPv6: ADDRCONF(NETDEV_CHANGE): eth3: link becomes ready [ 677.058362] hns-nic HISI00C2:03 eth3: link down [ 692.418366] hns-nic HISI00C2:03 eth3: link up [ 693.442359] hns-nic HISI00C2:03 eth3: link down [ 748.738365] hns-nic HISI00C2:03 eth3: link up [ 749.762363] hns-nic HISI00C2:03 eth3: link down
This patch adds a logic to check whether the optical module is absent or not, if absent, means the interface is down, otherwise check the mac link status.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daode Huang huangdaode@hisilicon.com --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 14a905d..11c28ba 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -174,6 +174,15 @@ Scope(_SB) H3L3, 16, // port5 , 16, //RESERVED } + OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100) + Field(HSFP, ByteAcc, NoLock, Preserve) { + Offset (0x2), + HSF0, 1, // port0 + , 7, //RESERVED + Offset (0x6), + HSF1, 1, // port1 + , 7, //RESERVED + } Name (_HID, "HISI00B2") Name (_CCA, 1) // Cache-coherent controller Name (_CRS, ResourceTemplate (){ @@ -520,7 +529,21 @@ Scope(_SB) //Get sfp status case (0x5) { + Store (1, Local1) //set no sfp default + Store (DeRefOf (Index (Arg3, 0)), Local0) + If (LEqual (Local0, 0)) + { + // port 0: + Store (HSF0, Local1) + } + ElseIf (LEqual (Local0, 1)) + { + // port 1 + Store (HSF1, Local1) + }
+ XOr (Local1, 1, local1) + Return (Local1) } } }
From: Heyi Guo heyi.guo@linaro.org
the interrupt 74 was omited and 160 was added by mistake. correct this error.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiaofei Tan tanxiaofei@huawei.com Revied-by: John Garry john.garry@huawei.com --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 72 +++++++++++----------- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 72 +++++++++++----------- 2 files changed, 72 insertions(+), 72 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 7265ac8..46b8db0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -48,24 +48,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, }
Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) @@ -238,24 +238,24 @@ Name(_PRS, ResourceTemplate() { { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, }
Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index 9944a50..7b5d4de 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -25,24 +25,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" ) @@ -140,24 +140,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, }
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1")
On Wed, Dec 28, 2016 at 04:42:50PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
the interrupt 74 was omited and 160 was added by mistake. correct this error.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiaofei Tan tanxiaofei@huawei.com Revied-by: John Garry john.garry@huawei.com
This looks like an obvious typo fix to me.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 72 +++++++++++----------- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 72 +++++++++++----------- 2 files changed, 72 insertions(+), 72 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 7265ac8..46b8db0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -48,24 +48,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) @@ -238,24 +238,24 @@ Name(_PRS, ResourceTemplate() { { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index 9944a50..7b5d4de 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -25,24 +25,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" ) @@ -140,24 +140,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") -- 1.9.1
Hi Leif,
Could you help to review this path? if it is ok please help to push it. Thanks.
The commit also could be found in http://git.linaro.org/uefi/OpenPlatformPkg.git (rp-16.12-04-all)
Thanks and Regards, Heyi.
在 2017/1/5 18:18, graeme.gregory@linaro.org 写道:
On Wed, Dec 28, 2016 at 04:42:50PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
the interrupt 74 was omited and 160 was added by mistake. correct this error.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiaofei Tan tanxiaofei@huawei.com Revied-by: John Garry john.garry@huawei.com
This looks like an obvious typo fix to me.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 72 +++++++++++----------- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 72 +++++++++++----------- 2 files changed, 72 insertions(+), 72 deletions(-)
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 7265ac8..46b8db0 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -48,24 +48,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) @@ -238,24 +238,24 @@ Name(_PRS, ResourceTemplate() { { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index 9944a50..7b5d4de 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -25,24 +25,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI6" ) @@ -140,24 +140,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73,
75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,
74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, }Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\_SB.MBI1") -- 1.9.1
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } Device (ETH3) { Name(_HID, "HISI00C2") @@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } }
Device (ROCE) { @@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } Device (ETH7) { Name(_HID, "HISI00C2") @@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } }
}
Hi Leif,
Refine this path according you and Graeme's comments,
please help to review, thanks.
Thanks and Regards,
Heyi
在 2016/12/28 16:42, Chenhui Sun 写道:
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH3) { Name(_HID, "HISI00C2")
@@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } }
Device (ROCE) { @@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH7) { Name(_HID, "HISI00C2")
@@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } }
}
On Wed, Dec 28, 2016 at 04:47:55PM +0800, Heyi Guo wrote:
Hi Leif,
Refine this path according you and Graeme's comments,
please help to review, thanks.
Thanks and Regards,
Heyi
在 2016/12/28 16:42, Chenhui Sun 写道:
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } })
I think you misunderstood what I meant.
I meant something like (untested)
Name (NICE, 0)
Method (_STA, 0x0, NotSerialized) { Return (NICE); }
Then if my thinking is correct a later SSDT loaded when the extender is present could then
Store (\_SB.XXXX.NICE, 1)
To change the status.
Otherwise if this does not work how I think it should this patch is fine for me.
Thanks
Graeme
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH3) { Name(_HID, "HISI00C2")
@@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ROCE) {
@@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH7) { Name(_HID, "HISI00C2")
@@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } }
On 01/04/2017 04:49 AM, graeme.gregory@linaro.org wrote:
On Wed, Dec 28, 2016 at 04:47:55PM +0800, Heyi Guo wrote:
Hi Leif,
Refine this path according you and Graeme's comments,
please help to review, thanks.
Thanks and Regards,
Heyi
在 2016/12/28 16:42, Chenhui Sun 写道:
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } })
I think you misunderstood what I meant.
I meant something like (untested)
Name (NICE, 0)
Method (_STA, 0x0, NotSerialized) { Return (NICE); }
Then if my thinking is correct a later SSDT loaded when the extender is present could then
Store (\_SB.XXXX.NICE, 1)
To change the status.
Otherwise if this does not work how I think it should this patch is fine for me.
Thanks
Graeme
The only caution with this I would provide is that all object definitions in an SSDT that is dynamically loaded by default *replace* any existing object definitions with the same name. So, while I quite like the use of Name(NICE,0) as suggested, that would only work if the SSDT being loaded does *not* contain Device definitions for the ports.
I think you have several options here.
Let's assume you have Device ETH0-3 that are the devices always present, and devices ETH4-7 that are the ones being dynamically added. In all cases, I would define ETH0-3 in the DSDT since they will always be present.
Option 1: define ETH4-7 in the DSDT *and* a dynamically loaded SSDT
In this case, the DSDT might contain something like:
Device (ETH4) { ... Method (_STA, 0x0, NotSerialized) { Return (0) } ... }
and the SSDT that is loaded later on might look like this:
Device (ETH4) { ... Method (_STA, 0x0, NotSerialized) { Return (1) } ... }
When the SSDT is loaded, the definitions of ETH4-7 are replaced and the new _STA method is used.
Option 2: only define ETH4-7 in a dynamically loaded SSDT
For this case, there would be no definition of ETH4-7 in the DSDT. They would not exist at all since there is nothing to be enumerated in the ASL namespace.
In the SSDT that gets loaded, each device would look something like this:
Device (ETH4) { Name (_HID, xxxxxxxx) .... }
An _STA method could be added to Return(1) but would not be required since the ACPI interpreter will create it by default when Device(ETH4) is created in the namespace. I personally would include just so I could put comments around it and explain what's happening.
Option 3: define ETH0-7 in the DSDT, add a dummy device in the SSDT
In this case, we're using the Name(NICE) idea above. The DSDT would contain a bit mask of define ETHx devices, and the _STA methods would test for their value. Something like this:
Scope (_SB) { Name (MASK, 0x0f) /* Defines only ETH0-3 as active */ ... Device (ETH0) { ... Method (_STA, 0x0, NotSerialized) { If (And (_SB.MASK, 0x1)) { Return (0x1) } Return (0x0) } ... } ...
Device (ETH1) { ... Method (_STA, 0x0, NotSerialized) { If (And (_SB.MASK, 0x2)) { Return (0x1) } Return (0x0) } ... } ... Device (ETH7) { ... Method (_STA, 0x0, NotSerialized) { If (And (_SB.MASK, 0x80)) { Return (0x1) } Return (0x0) } ... } In the SSDT, some new dummy device would have to be defined, and that might look like this:
... Device (DUMY) { ... Method (_INI, 0x0, Serialized) { Store(_SB.MASK, 0xff) /* Enable all ETHx */ } ... }
When the SSDT gets loaded, the bit mask gets changed and the next time the _STA values are checked, the devices will be enabled. You will have to force the device drivers to enable the new ports somehow (perhaps check the value of the _SB.MASK object after the SSDT is loaded...).
Or, finally, Option 4: provide a simple status register somewhere
This is essentially the same as Option 3. The difference is that instead of defining Name(_SB.MASK) as a variable, it's a hardware register in some OperationRegion. If there is no expander, this read-only register returns 0x0f; if there is an expander, it returns 0xff. The DSDT _STA methods would simply test the register (the ASL might even be identical). If the expander can only be added with power off, there would be no need to load an SSDT.
Of all these, Option 2 is simplest, but could allow the firmware to lie; if the SSDT is loaded without the expander card being present, it is now incorrect.
Option 4 is probably optimal; the firmware and hardware can always be in sync and consistent. If you can't do Option 4, Option 3 is probably the most flexible and maintainable over time, but could also cause problems if somehow the SSDT is loaded without the expander being present.
- Method (_STA, 0x0, NotSerialized) + { + Return (0) + }
} Device (ETH3) { Name(_HID, "HISI00C2") @@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } Device (ROCE) { @@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } Device (ETH7) { Name(_HID, "HISI00C2") @@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } }
_______________________________________________ Linaro-uefi mailing list Linaro-uefi@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-uefi
On Wed, Jan 04, 2017 at 04:17:13PM -0700, Al Stone wrote:
On 01/04/2017 04:49 AM, graeme.gregory@linaro.org wrote:
On Wed, Dec 28, 2016 at 04:47:55PM +0800, Heyi Guo wrote:
Hi Leif,
Refine this path according you and Graeme's comments,
please help to review, thanks.
Thanks and Regards,
Heyi
在 2016/12/28 16:42, Chenhui Sun 写道:
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } })
I think you misunderstood what I meant.
I meant something like (untested)
Name (NICE, 0)
Method (_STA, 0x0, NotSerialized) { Return (NICE); }
Then if my thinking is correct a later SSDT loaded when the extender is present could then
Store (\_SB.XXXX.NICE, 1)
To change the status.
Otherwise if this does not work how I think it should this patch is fine for me.
Thanks
Graeme
The only caution with this I would provide is that all object definitions in an SSDT that is dynamically loaded by default *replace* any existing object definitions with the same name. So, while I quite like the use of Name(NICE,0) as suggested, that would only work if the SSDT being loaded does *not* contain Device definitions for the ports.
I think you have several options here.
Let's assume you have Device ETH0-3 that are the devices always present, and devices ETH4-7 that are the ones being dynamically added. In all cases, I would define ETH0-3 in the DSDT since they will always be present.
Option 1: define ETH4-7 in the DSDT *and* a dynamically loaded SSDT
In this case, the DSDT might contain something like:
Device (ETH4) { ... Method (_STA, 0x0, NotSerialized) { Return (0) } ... }
and the SSDT that is loaded later on might look like this:
Device (ETH4) { ... Method (_STA, 0x0, NotSerialized) { Return (1) } ... }
When the SSDT is loaded, the definitions of ETH4-7 are replaced and the new _STA method is used.
And this is why I ask experts, I had totally forgotten about that, and in fact if Heyi wants to use Option 1: this file already does that!
Graeme
Option 2: only define ETH4-7 in a dynamically loaded SSDT
For this case, there would be no definition of ETH4-7 in the DSDT. They would not exist at all since there is nothing to be enumerated in the ASL namespace.
In the SSDT that gets loaded, each device would look something like this:
Device (ETH4) { Name (_HID, xxxxxxxx) .... }
An _STA method could be added to Return(1) but would not be required since the ACPI interpreter will create it by default when Device(ETH4) is created in the namespace. I personally would include just so I could put comments around it and explain what's happening.
Option 3: define ETH0-7 in the DSDT, add a dummy device in the SSDT
In this case, we're using the Name(NICE) idea above. The DSDT would contain a bit mask of define ETHx devices, and the _STA methods would test for their value. Something like this:
Scope (_SB) { Name (MASK, 0x0f) /* Defines only ETH0-3 as active */ ... Device (ETH0) { ... Method (_STA, 0x0, NotSerialized) { If (And (_SB.MASK, 0x1)) { Return (0x1) } Return (0x0) } ... } ...
Device (ETH1) { ... Method (_STA, 0x0, NotSerialized) { If (And (\_SB.MASK, 0x2)) { Return (0x1) } Return (0x0) } ... } ...Device (ETH7) { ... Method (_STA, 0x0, NotSerialized) { If (And (_SB.MASK, 0x80)) { Return (0x1) } Return (0x0) } ... } In the SSDT, some new dummy device would have to be defined, and that might look like this:
... Device (DUMY) { ... Method (_INI, 0x0, Serialized) { Store(_SB.MASK, 0xff) /* Enable all ETHx */ } ... }
When the SSDT gets loaded, the bit mask gets changed and the next time the _STA values are checked, the devices will be enabled. You will have to force the device drivers to enable the new ports somehow (perhaps check the value of the _SB.MASK object after the SSDT is loaded...).
Or, finally, Option 4: provide a simple status register somewhere
This is essentially the same as Option 3. The difference is that instead of defining Name(_SB.MASK) as a variable, it's a hardware register in some OperationRegion. If there is no expander, this read-only register returns 0x0f; if there is an expander, it returns 0xff. The DSDT _STA methods would simply test the register (the ASL might even be identical). If the expander can only be added with power off, there would be no need to load an SSDT.
Of all these, Option 2 is simplest, but could allow the firmware to lie; if the SSDT is loaded without the expander card being present, it is now incorrect.
Option 4 is probably optimal; the firmware and hardware can always be in sync and consistent. If you can't do Option 4, Option 3 is probably the most flexible and maintainable over time, but could also cause problems if somehow the SSDT is loaded without the expander being present.
- Method (_STA, 0x0, NotSerialized) + { + Return (0) + }
} Device (ETH3) { Name(_HID, "HISI00C2") @@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } Device (ROCE) { @@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } Device (ETH7) { Name(_HID, "HISI00C2") @@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } }) + Method (_STA, 0x0, NotSerialized) + { + Return (0) + } } }
_______________________________________________ Linaro-uefi mailing list Linaro-uefi@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-uefi
-- ciao, al
Al Stone Software Engineer Linaro Enterprise Group al.stone@linaro.org
On Wed, Dec 28, 2016 at 04:42:51PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Given Als detailed email and the ability of Option 1 in that which I had forgotten about then this is fine with me.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH3) { Name(_HID, "HISI00C2")
@@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } }
Device (ROCE) { @@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH7) { Name(_HID, "HISI00C2")
@@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } }
} -- 1.9.1
Hi Leif,
Could you help to review this path? if it is ok please help to push it. Thanks. The commit also could be found in http://git.linaro.org/uefi/OpenPlatformPkg.git (rp-16.12-04-all)
Thanks and Regards, Heyi.
在 2017/1/5 18:19, graeme.gregory@linaro.org 写道:
On Wed, Dec 28, 2016 at 04:42:51PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Given Als detailed email and the ability of Option 1 in that which I had forgotten about then this is fine with me.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH3) { Name(_HID, "HISI00C2")
@@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } }
Device (ROCE) { @@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH7) { Name(_HID, "HISI00C2")
@@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } }
} -- 1.9.1
sorry, correct the path to http://git.linaro.org/people/heyi.guo/OpenPlatformPkg.git
在 2017/1/9 15:23, Heyi Guo 写道:
Hi Leif,
Could you help to review this path? if it is ok please help to push it. Thanks. The commit also could be found in http://git.linaro.org/uefi/OpenPlatformPkg.git (rp-16.12-04-all)
Thanks and Regards, Heyi.
在 2017/1/5 18:19, graeme.gregory@linaro.org 写道:
On Wed, Dec 28, 2016 at 04:42:51PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
D05 has 4 physical NIC ports, which can be extended to 8 ports using an expansion card. However, the existing ACPI tables unconditionally describes the potential maximum of 8.
This patch add _STA method to the extra 4 ports from ACPI. The _STA will return the actual value when code has been added to dynamically detect whether they are present.
This patch resolves https://bugs.linaro.org/show_bug.cgi?id=2714.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo heyi.guo@linaro.org
Given Als detailed email and the ability of Option 1 in that which I had forgotten about then this is fine with me.
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..14a905d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -662,6 +662,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 2}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH3) { Name(_HID, "HISI00C2")
@@ -674,6 +678,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 3}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ROCE) {
@@ -1216,6 +1224,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 0}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } Device (ETH7) { Name(_HID, "HISI00C2")
@@ -1228,6 +1240,10 @@ Scope(_SB) Package () {"port-idx-in-ae", 1}, } })
- Method (_STA, 0x0, NotSerialized)
- {
Return (0)- } } }
-- 1.9.1
On Wed, Dec 28, 2016 at 04:42:49PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
This patch is for https://bugs.linaro.org/show_bug.cgi?id=2711.
When there is no optical module plugged in XGE port, the interfaces (ethX) will show up/down information on console, such as below:
[root@localhost ~]# [ 676.034368] hns-nic HISI00C2:03 eth3: link up [ 676.038840] IPv6: ADDRCONF(NETDEV_CHANGE): eth3: link becomes ready [ 677.058362] hns-nic HISI00C2:03 eth3: link down [ 692.418366] hns-nic HISI00C2:03 eth3: link up [ 693.442359] hns-nic HISI00C2:03 eth3: link down [ 748.738365] hns-nic HISI00C2:03 eth3: link up [ 749.762363] hns-nic HISI00C2:03 eth3: link down
This patch adds a logic to check whether the optical module is absent or not, if absent, means the interface is down, otherwise check the mac link status.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daode Huang huangdaode@hisilicon.com
This looks fine to me
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 14a905d..11c28ba 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -174,6 +174,15 @@ Scope(_SB) H3L3, 16, // port5 , 16, //RESERVED }
- OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100)
- Field(HSFP, ByteAcc, NoLock, Preserve) {
Offset (0x2),HSF0, 1, // port0, 7, //RESERVEDOffset (0x6),HSF1, 1, // port1, 7, //RESERVED- } Name (_HID, "HISI00B2") Name (_CCA, 1) // Cache-coherent controller Name (_CRS, ResourceTemplate (){
@@ -520,7 +529,21 @@ Scope(_SB) //Get sfp status case (0x5) {
Store (1, Local1) //set no sfp defaultStore (DeRefOf (Index (Arg3, 0)), Local0)If (LEqual (Local0, 0)){// port 0:Store (HSF0, Local1)}ElseIf (LEqual (Local0, 1)){// port 1Store (HSF1, Local1)}
XOr (Local1, 1, local1)Return (Local1) } } }-- 1.9.1
Hi Leif,
Could you help to review this path? if it is ok please help to push it. Thanks.
The commit also could be found in http://git.linaro.org/uefi/OpenPlatformPkg.git (rp-16.12-04-all)
Thanks and Regards, Heyi.
在 2017/1/5 18:20, graeme.gregory@linaro.org 写道:
On Wed, Dec 28, 2016 at 04:42:49PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
This patch is for https://bugs.linaro.org/show_bug.cgi?id=2711.
When there is no optical module plugged in XGE port, the interfaces (ethX) will show up/down information on console, such as below:
[root@localhost ~]# [ 676.034368] hns-nic HISI00C2:03 eth3: link up [ 676.038840] IPv6: ADDRCONF(NETDEV_CHANGE): eth3: link becomes ready [ 677.058362] hns-nic HISI00C2:03 eth3: link down [ 692.418366] hns-nic HISI00C2:03 eth3: link up [ 693.442359] hns-nic HISI00C2:03 eth3: link down [ 748.738365] hns-nic HISI00C2:03 eth3: link up [ 749.762363] hns-nic HISI00C2:03 eth3: link down
This patch adds a logic to check whether the optical module is absent or not, if absent, means the interface is down, otherwise check the mac link status.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daode Huang huangdaode@hisilicon.com
This looks fine to me
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 14a905d..11c28ba 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -174,6 +174,15 @@ Scope(_SB) H3L3, 16, // port5 , 16, //RESERVED }
- OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100)
- Field(HSFP, ByteAcc, NoLock, Preserve) {
Offset (0x2),HSF0, 1, // port0, 7, //RESERVEDOffset (0x6),HSF1, 1, // port1, 7, //RESERVED- } Name (_HID, "HISI00B2") Name (_CCA, 1) // Cache-coherent controller Name (_CRS, ResourceTemplate (){
@@ -520,7 +529,21 @@ Scope(_SB) //Get sfp status case (0x5) {
Store (1, Local1) //set no sfp defaultStore (DeRefOf (Index (Arg3, 0)), Local0)If (LEqual (Local0, 0)){// port 0:Store (HSF0, Local1)}ElseIf (LEqual (Local0, 1)){// port 1Store (HSF1, Local1)}
XOr (Local1, 1, local1)Return (Local1) } } }-- 1.9.1
Hi Heyi,
I've pushed 1-4 of the top 5 patches from your branch.
Regards,
Leif
On Mon, Jan 09, 2017 at 02:52:39PM +0800, Heyi Guo wrote:
Hi Leif,
Could you help to review this path? if it is ok please help to push it. Thanks.
The commit also could be found in http://git.linaro.org/uefi/OpenPlatformPkg.git (rp-16.12-04-all)
Thanks and Regards, Heyi.
在 2017/1/5 18:20, graeme.gregory@linaro.org 写道:
On Wed, Dec 28, 2016 at 04:42:49PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
This patch is for https://bugs.linaro.org/show_bug.cgi?id=2711.
When there is no optical module plugged in XGE port, the interfaces (ethX) will show up/down information on console, such as below:
[root@localhost ~]# [ 676.034368] hns-nic HISI00C2:03 eth3: link up [ 676.038840] IPv6: ADDRCONF(NETDEV_CHANGE): eth3: link becomes ready [ 677.058362] hns-nic HISI00C2:03 eth3: link down [ 692.418366] hns-nic HISI00C2:03 eth3: link up [ 693.442359] hns-nic HISI00C2:03 eth3: link down [ 748.738365] hns-nic HISI00C2:03 eth3: link up [ 749.762363] hns-nic HISI00C2:03 eth3: link down
This patch adds a logic to check whether the optical module is absent or not, if absent, means the interface is down, otherwise check the mac link status.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daode Huang huangdaode@hisilicon.com
This looks fine to me
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 14a905d..11c28ba 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -174,6 +174,15 @@ Scope(_SB) H3L3, 16, // port5 , 16, //RESERVED }
- OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100)
- Field(HSFP, ByteAcc, NoLock, Preserve) {
Offset (0x2),HSF0, 1, // port0, 7, //RESERVEDOffset (0x6),HSF1, 1, // port1, 7, //RESERVED- } Name (_HID, "HISI00B2") Name (_CCA, 1) // Cache-coherent controller Name (_CRS, ResourceTemplate (){
@@ -520,7 +529,21 @@ Scope(_SB) //Get sfp status case (0x5) {
Store (1, Local1) //set no sfp defaultStore (DeRefOf (Index (Arg3, 0)), Local0)If (LEqual (Local0, 0)){// port 0:Store (HSF0, Local1)}ElseIf (LEqual (Local0, 1)){// port 1Store (HSF1, Local1)}XOr (Local1, 1, local1)Return (Local1) } } }-- 1.9.1
Hi Leif,
Got it, Thanks:)
Regards,
Heyi
在 2017/1/10 3:17, Leif Lindholm 写道:
Hi Heyi,
I've pushed 1-4 of the top 5 patches from your branch.
Regards,
Leif
On Mon, Jan 09, 2017 at 02:52:39PM +0800, Heyi Guo wrote:
Hi Leif,
Could you help to review this path? if it is ok please help to push it. Thanks.
The commit also could be found in http://git.linaro.org/uefi/OpenPlatformPkg.git (rp-16.12-04-all)
Thanks and Regards, Heyi.
在 2017/1/5 18:20, graeme.gregory@linaro.org 写道:
On Wed, Dec 28, 2016 at 04:42:49PM +0800, Chenhui Sun wrote:
From: Heyi Guo heyi.guo@linaro.org
This patch is for https://bugs.linaro.org/show_bug.cgi?id=2711.
When there is no optical module plugged in XGE port, the interfaces (ethX) will show up/down information on console, such as below:
[root@localhost ~]# [ 676.034368] hns-nic HISI00C2:03 eth3: link up [ 676.038840] IPv6: ADDRCONF(NETDEV_CHANGE): eth3: link becomes ready [ 677.058362] hns-nic HISI00C2:03 eth3: link down [ 692.418366] hns-nic HISI00C2:03 eth3: link up [ 693.442359] hns-nic HISI00C2:03 eth3: link down [ 748.738365] hns-nic HISI00C2:03 eth3: link up [ 749.762363] hns-nic HISI00C2:03 eth3: link down
This patch adds a logic to check whether the optical module is absent or not, if absent, means the interface is down, otherwise check the mac link status.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daode Huang huangdaode@hisilicon.com
This looks fine to me
Reviewed-by: Graeme Gregory graeme.gregory@linaro.org
.../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 14a905d..11c28ba 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -174,6 +174,15 @@ Scope(_SB) H3L3, 16, // port5 , 16, //RESERVED }
- OperationRegion(HSFP, SystemMemory, 0x78000010, 0x100)
- Field(HSFP, ByteAcc, NoLock, Preserve) {
Offset (0x2),HSF0, 1, // port0, 7, //RESERVEDOffset (0x6),HSF1, 1, // port1, 7, //RESERVED- } Name (_HID, "HISI00B2") Name (_CCA, 1) // Cache-coherent controller Name (_CRS, ResourceTemplate (){
@@ -520,7 +529,21 @@ Scope(_SB) //Get sfp status case (0x5) {
Store (1, Local1) //set no sfp defaultStore (DeRefOf (Index (Arg3, 0)), Local0)If (LEqual (Local0, 0)){// port 0:Store (HSF0, Local1)}ElseIf (LEqual (Local0, 1)){// port 1Store (HSF1, Local1)}XOr (Local1, 1, local1)Return (Local1) } } }-- 1.9.1
-
Al Stone -
Chenhui Sun -
graeme.gregory＠linaro.org -
Heyi Guo
-
Leif Lindholm