On Mon, Mar 10, 2025 at 11:44 PM Deepak Gupta debug@rivosinc.com wrote:
This patch creates a config for shadow stack support and landing pad instr support. Shadow stack support and landing instr support can be enabled by selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires up path to enumerate CPU support and if cpu support exists, kernel will support cpu assisted user mode cfi.
If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`, `ARCH_HAS_USER_SHADOW_STACK` and DYNAMIC_SIGFRAME for riscv.
Signed-off-by: Deepak Gupta debug@rivosinc.com
arch/riscv/Kconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7612c52e9b1e..0a2e50f056e8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -250,6 +250,26 @@ config ARCH_HAS_BROKEN_DWARF5 # https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471... depends on LD_IS_LLD && LLD_VERSION < 180000
+config RISCV_USER_CFI
def_bool y
bool "riscv userspace control flow integrity"
depends on 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicfiss)
depends on RISCV_ALTERNATIVE
select ARCH_HAS_USER_SHADOW_STACK
select ARCH_USES_HIGH_VMA_FLAGS
select DYNAMIC_SIGFRAME
help
Provides CPU assisted control flow integrity to userspace tasks.
Control flow integrity is provided by implementing shadow stack for
backward edge and indirect branch tracking for forward edge in program.
Shadow stack protection is a hardware feature that detects function
return address corruption. This helps mitigate ROP attacks.
Indirect branch tracking enforces that all indirect branches must land
on a landing pad instruction else CPU will fault. This mitigates against
JOP / COP attacks. Applications must be enabled to use it, and old user-
space does not get protection "for free".
default y
config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT default 8
LGTM.
Reviewed-by: Zong Li zong.li@sifive.com
-- 2.34.1
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