On 05-05-2025 19:48, Jason Gunthorpe wrote:
- /*
* AMD's IOMMU can flush as many pages as necessary in a single flush.* Unless we run in a virtual machine, which can be inferred according* to whether "non-present cache" is on, it is probably best to prefer* (potentially) too extensive TLB flushing (i.e., more misses) over* mutliple TLB flushes (i.e., more flushes). For virtual machines the
old typo mutliple -> multiple
* hypervisor needs to synchronize the host IOMMU PTEs with those of* the guest, and the trade-off is different: unnecessary TLB flushes* should be avoided.*/
Thanks, Alok