On Wed, 24 Aug 2022 00:19:04 +0100, Peter Xu peterx@redhat.com wrote:
On Tue, Aug 23, 2022 at 11:47:03PM +0100, Marc Zyngier wrote:
On Tue, 23 Aug 2022 22:20:32 +0100, Peter Xu peterx@redhat.com wrote:
On Tue, Aug 23, 2022 at 08:17:03PM +0100, Marc Zyngier wrote:
I don't think we really need this check on the hot path. All we need is to make the request sticky until userspace gets their act together and consumes elements in the ring. Something like:
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 986cee6fbc7f..e8ed5e1af159 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -747,6 +747,14 @@ static int check_vcpu_requests(struct kvm_vcpu *vcpu) if (kvm_check_request(KVM_REQ_SUSPEND, vcpu)) return kvm_vcpu_suspend(vcpu);
if (kvm_check_request(KVM_REQ_RING_SOFT_FULL, vcpu) &&kvm_dirty_ring_soft_full(vcpu)) {kvm_make_request(KVM_REQ_RING_SOFT_FULL, vcpu);vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;trace_kvm_dirty_ring_exit(vcpu);return 0;}return 1;
Right, this seems working. We can also use kvm_test_request() here.
However, I'm a bit concerned by the reset side of things. It iterates over the vcpus and expects the view of each ring to be consistent, even if userspace is hacking at it from another CPU. For example, I can't see what guarantees that the kernel observes the writes from userspace in the order they are being performed (the documentation provides no requirements other than "it must collect the dirty GFNs in sequence", which doesn't mean much from an ordering perspective).
I can see that working on a strongly ordered architecture, but on something as relaxed as ARM, the CPUs may^Wwill aggressively reorder stuff that isn't explicitly ordered. I have the feeling that a CAS operation on both sides would be enough, but someone who actually understands how this works should have a look...
I definitely don't think I 100% understand all the ordering things since they're complicated.. but my understanding is that the reset procedure didn't need memory barrier (unlike pushing, where we have explicit wmb), because we assumed the userapp is not hostile so logically it should only modify the flags which is a 32bit field, assuming atomicity guaranteed.
Atomicity doesn't guarantee ordering, unfortunately.
Right, sorry to be misleading. The "atomicity" part I was trying to say the kernel will always see consistent update on the fields.
The ordering should also be guaranteed, because things must happen with below sequence:
(1) kernel publish dirty GFN data (slot, offset) (2) kernel publish dirty GFN flag (set to DIRTY) (3) user sees DIRTY, collects (slots, offset) (4) user sets it to RESET (5) kernel reads RESET
Maybe. Maybe not. The reset could well be sitting in the CPU write buffer for as long as it wants and not be seen by the kernel if the read occurs on another CPU. And that's the crucial bit: single-CPU is fine, but cross CPU isn't. Unfortunately, the userspace API is per-CPU on collection, and global on reset (this seems like a bad decision, but it is too late to fix this).
So the ordering of single-entry is guaranteed in that when (5) happens it must be after stablized (1+2).
Take the following example: CPU0 is changing a bunch of flags for GFNs A, B, C, D that exist in the ring in that order, and CPU1 performs an ioctl to reset the page state.
CPU0: write_flag(A, KVM_DIRTY_GFN_F_RESET) write_flag(B, KVM_DIRTY_GFN_F_RESET) write_flag(C, KVM_DIRTY_GFN_F_RESET) write_flag(D, KVM_DIRTY_GFN_F_RESET) [...]
CPU1: ioctl(KVM_RESET_DIRTY_RINGS)
Since CPU0 writes do not have any ordering, CPU1 can observe the writes in a sequence that have nothing to do with program order, and could for example observe that GFN A and D have been reset, but not B and C. This in turn breaks the logic in the reset code (B, C, and D don't get reset), despite userspace having followed the spec to the letter. If each was a store-release (which is the case on x86), it wouldn't be a problem, but nothing calls it in the documentation.
Maybe that's not a big deal if it is expected that each CPU will issue a KVM_RESET_DIRTY_RINGS itself, ensuring that it observe its own writes. But expecting this to work across CPUs without any barrier is wishful thinking.
I see what you meant...
Firstly I'm actually curious whether that'll really happen if the gfns are collected in something like a for loop:
for(i = 0; i < N; i++) collect_dirty_gfn(ring, i);
Because since all the gfps to be read will depend on variable "i", IIUC no reordering should happen, but I'm not really sure, so more of a pure question.
'i' has no influence on the write ordering. Each write targets a different address, there is no inter-write dependencies (this concept doesn't exist other than for writes to the same address), so they can be reordered at will.
If you want a proof of this, head to http://diy.inria.fr/www/ and run the MP.litmus test (which conveniently gives you a reduction of this problem) on both the x86 and AArch64 models. You will see that the reordering isn't allowed on x86, but definitely allowed on arm64.
Besides, the other thing to mention is that I think it is fine the RESET ioctl didn't recycle all the gfns got set to reset state. Taking above example of GFNs A-D, if when reaching the RESET ioctl only A & D's flags are updated, the ioctl will recycle gfn A but stop at gfn B assuming B-D are not reset. But IMHO it's okay because it means we reset partial of the gfns not all of them, and it's safe to do so. It means the next ring full event can come earlier because we recycled less, but that's functionally safe to me.
It may be safe, but it isn't what the userspace API promises. In other words, without further straightening of the API, this doesn't work as expected on relaxed memory architectures. So before this gets enabled on arm64, this whole ordering issue must be addressed.
Thanks,
M.