On Wed, Sep 06, 2023 at 06:33:15PM +0000, Puranjay Mohan wrote:
The cpuv4 added a new BPF_MOVSX instruction that sign extends the src before moving it to the destination.
BPF_ALU | BPF_MOVSX sign extends 8-bit and 16-bit operands into 32-bit operands, and zeroes the remaining upper 32 bits.
BPF_ALU64 | BPF_MOVSX sign extends 8-bit, 16-bit, and 32-bit operands into 64-bit operands.
The offset field of the instruction is used to tell the number of bit to use for sign-extension. BPF_MOV and BPF_MOVSX have the same code but the former sets offset to 0 and the later one sets the offset to 8, 16 or 32
The behaviour of this instruction is dst = (s8,s16,s32)src
On ARM32 the implementation uses LSH and ARSH to extend the 8/16 bits to a 32-bit register and then it is sign extended to the upper 32-bit register using ARSH. For 32-bit we just move it to the destination register and use ARSH to extend it to the upper 32-bit register.
Signed-off-by: Puranjay Mohan puranjay12@gmail.com
Reviewed-by: Russell King (Oracle) rmk+kernel@armlinux.org.uk
Thanks!