On Sat, May 4, 2024 at 3:33 AM Charlie Jenkins charlie@rivosinc.com wrote:
From: Conor Dooley conor.dooley@microchip.com
Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, reading the th.vlenb CSR may produce an illegal instruction trap, so this property is required on such systems.
Signed-off-by: Conor Dooley conor.dooley@microchip.com Signed-off-by: Charlie Jenkins charlie@rivosinc.com
Reviewed-by: Andy Chiu andy.chiu@sifive.com
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..edcb6a7d9319 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -94,6 +94,12 @@ properties: description: The blocksize in bytes for the Zicboz cache operations.
- riscv,vlenb:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
VLEN/8, the vector register length in bytes. This property is required insystems where the vector register length is not identical on all harts.- # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false
-- 2.44.0
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