Hi Shaoqin,
On 11/29/23 08:27, Shaoqin Huang wrote:
In general, the set/clr registers should always be used in their write form, never in a RMW form (imagine an interrupt disabling a counter between the read and the write...).
The current implementation of [enable|disable]_counter both use the RMW form, fix them by directly write to the set/clr registers.
At the same time, it also fix the buggy disable_counter() which would end up disabling all the counters.
Signed-off-by: Shaoqin Huang shahuang@redhat.com
Reviewed-by: Eric Auger eric.auger@redhat.com
Eric
tools/testing/selftests/kvm/include/aarch64/vpmu.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tools/testing/selftests/kvm/include/aarch64/vpmu.h b/tools/testing/selftests/kvm/include/aarch64/vpmu.h index e0cc1ca1c4b7..644dae3814b5 100644 --- a/tools/testing/selftests/kvm/include/aarch64/vpmu.h +++ b/tools/testing/selftests/kvm/include/aarch64/vpmu.h @@ -78,17 +78,13 @@ static inline void write_sel_evtyper(int sel, unsigned long val) static inline void enable_counter(int idx) {
- uint64_t v = read_sysreg(pmcntenset_el0);
- write_sysreg(BIT(idx) | v, pmcntenset_el0);
- write_sysreg(BIT(idx), pmcntenset_el0); isb();
} static inline void disable_counter(int idx) {
- uint64_t v = read_sysreg(pmcntenset_el0);
- write_sysreg(BIT(idx) | v, pmcntenclr_el0);
- write_sysreg(BIT(idx), pmcntenclr_el0); isb();
}