29 May
2023
29 May
'23
7:53 p.m.
On Thu, May 11, 2023 at 07:51:01AM -0700, Yi Liu wrote:
This adds IOMMU_HWPT_TYPE_VTD_S1 for stage-1 hw_pagetable of Intel VT-d +/**
- struct iommu_hwpt_intel_vtd - Intel VT-d specific user-managed
stage-1 page table info
- @flags: Combination of enum iommu_hwpt_intel_vtd_flags
- @pgtbl_addr: The base address of the user-managed stage-1 page table.
- @pat: Page attribute table data to compute effective memory type
- @emt: Extended memory type
- @addr_width: The address width of the untranslated addresses that are
subjected to the user-managed stage-1 page table.
- @__reserved: Must be 0
- The Intel VT-d specific data for creating hw_pagetable to represent
- the user-managed stage-1 page table that is used in nested translation.
- In nested translation, the stage-1 page table locates in the address
- space that defined by the corresponding stage-2 page table. Hence the
- stage-1 page table base address value should not be higher than the
- maximum untranslated address of stage-2 page table.
- The paging level of the stage-1 page table should be compatible with
- the hardware iommu. Otherwise, the allocation would be failed.
- */
+struct iommu_hwpt_intel_vtd {
- __u64 flags;
- __u64 pgtbl_addr;
__aligned_u64
- __u32 pat;
- __u32 emt;
- __u32 addr_width;
- __u32 __reserved;
}; /** @@ -391,6 +446,8 @@ enum iommu_hwpt_type {
- +------------------------------+-------------------------------------+-----------+
- | IOMMU_HWPT_TYPE_DEFAULT | N/A | IOAS |
- +------------------------------+-------------------------------------+-----------+
- | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_intel_vtd | HWPT |
- +------------------------------+-------------------------------------+-----------+
Please don't make ascii art tables.
Note beside the struct what enum it is for
Jason