On Thu, Mar 07, 2024, Sean Christopherson wrote:
On Thu, Mar 07, 2024, Manali Shukla wrote: From: Manali Shukla Manali.Shukla@amd.com
- xapic_enable();
- icr_val = (APIC_DEST_SELF | APIC_INT_ASSERT | VINTR_VECTOR);
- for (i = 0; i < NUM_ITERATIONS; i++) {
xapic_write_reg(APIC_ICR, icr_val);
asm volatile("sti; hlt; cli");
Please add safe_halt() and cli() helpers in processor.h. And then do:
Doh, saw something shiny and forgot to finish my though. For safe_halt(), copy the thing verbatim from KVM-Unit-Tests, as not everyone is familiar with the sti=>hlt trick.
/* * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, * except for a few oddballs that KVM is unlikely to run on, block IRQs for one * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. */ static inline void safe_halt(void) { asm volatile("sti; hlt"); }