With support for context switching SME state in place allow access to SME in nested guests.
The SME floating point state is handled along with all the other floating point state, SME specific floating point exceptions are directed into the same handlers as other floating point exceptions with NV specific handling for the vector lengths already in place.
TPIDR2_EL0 is context switched along with the other TPIDRs as part of the main guest register context switch.
SME priority support is currently masked from all guests including nested ones.
Signed-off-by: Mark Brown broonie@kernel.org --- arch/arm64/kvm/nested.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 0c9387d2f50708565b5aac1fc0f86fefffd94ea1..58324806c8d588b0a77c835bafc89236a1ad52d1 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -840,10 +840,11 @@ static void limit_nv_id_regs(struct kvm *kvm) val |= FIELD_PREP(NV_FTR(PFR0, EL3), 0b0001); kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR0_EL1, val);
- /* Only support BTI, SSBS, CSV2_frac */ + /* Only support BTI, SSBS, CSV2_frac and SME */ val = kvm_read_vm_id_reg(kvm, SYS_ID_AA64PFR1_EL1); val &= (NV_FTR(PFR1, BT) | NV_FTR(PFR1, SSBS) | + NV_FTR(PFR1, SME) | NV_FTR(PFR1, CSV2_frac)); kvm_set_vm_id_reg(kvm, SYS_ID_AA64PFR1_EL1, val);