On Thu, Aug 22, 2024 at 02:15:21AM +0100, Mark Brown wrote:
+static void noinstr el0_gcs(struct pt_regs *regs, unsigned long esr) +{
- enter_from_user_mode(regs);
- local_daif_restore(DAIF_PROCCTX);
- do_el0_gcs(regs, esr);
- exit_to_user_mode(regs);
+}
static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr) { enter_from_user_mode(regs); @@ -766,6 +786,9 @@ asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs) case ESR_ELx_EC_MOPS: el0_mops(regs, esr); break;
- case ESR_ELx_EC_GCS:
el0_gcs(regs, esr);break;diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 9e22683aa921..d410dcc12ed8 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -500,6 +500,16 @@ void do_el1_bti(struct pt_regs *regs, unsigned long esr) die("Oops - BTI", regs, esr); } +void do_el0_gcs(struct pt_regs *regs, unsigned long esr) +{
- force_signal_inject(SIGSEGV, SEGV_CPERR, regs->pc, 0);
+}
Just double checking: a GCSPOPM (for example, it can be a RET) from a non-GCS page would generate a classic permission fault with ISS2.GCS set rather than a GCS exception. That's my reading from the Arm ARM pseudocode, the text isn't clear to me.