On Fri, 29 Mar 2024 00:13:43 +0000, Mark Brown broonie@kernel.org wrote:
The 2023 architecture extensions have allocated some new ID registers, add them to the KVM system register descriptions so that they are visible to guests.
We make the newly introduced dpISA features writeable, as well as allowing writes to ID_AA64ISAR3_EL1.CPA for FEAT_CPA which only introduces straigforward new instructions with no additional architectural state or traps.
FPMR actively gets trapped by HCRX_EL2.
Signed-off-by: Mark Brown broonie@kernel.org
arch/arm64/kvm/sys_regs.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c9f4f387155f..a3c20d1a36aa 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2293,12 +2293,15 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64PFR0_EL1_AdvSIMD | ID_AA64PFR0_EL1_FP), }, ID_SANITISED(ID_AA64PFR1_EL1),
- ID_UNALLOCATED(4,2),
- ID_WRITABLE(ID_AA64PFR2_EL1, ~(ID_AA64PFR2_EL1_RES0 |
ID_AA64PFR2_EL1_MTEFAR |ID_AA64PFR2_EL1_MTESTOREONLY |ID_AA64PFR2_EL1_MTEPERM)),
- ID_UNALLOCATED(4,7),
- ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0),
/* CRm=5 */ { SYS_DESC(SYS_ID_AA64DFR0_EL1), @@ -2325,7 +2328,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | ID_AA64ISAR2_EL1_APA3 | ID_AA64ISAR2_EL1_GPA3)),
- ID_UNALLOCATED(6,3),
- ID_WRITABLE(ID_AA64ISAR3_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
ID_AA64ISAR3_EL1_PACM |ID_AA64ISAR3_EL1_TLBIW)),
Where is the code that enforces the lack of support for MTEFAR, MTESTOREONLY, and MTEPERM for SCTLR_ELx, EnPACM and EnFPM in HCRX_EL2? And I haven't checked whether TLBI VMALLWS2 can be trapped.
M.