Re: [PATCH v10 01/14] dt-bindings: riscv: Add xtheadvector ISA extension description

Charlie Jenkins charlie@rivosinc.com 於 2024年9月12日 週四 下午1:57寫道：

The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9.

Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c... [1]

Signed-off-by: Charlie Jenkins charlie@rivosinc.com Reviewed-by: Conor Dooley conor.dooley@microchip.com

Reviewed-by: Andy Chiu andybnac@gmail.com

---

Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b4928..1a3d01aedde6 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -556,6 +556,10 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.

•    # vendor extensions, each extension sorted alphanumerically under the
  

•    # vendor they belong to. Vendors are sorted alphanumerically as well.
  

•    # Andes
     - const: xandespmu
       description:
         The Andes Technology performance monitor extension for counter overflow
  

@@ -563,6 +567,12 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet....

•    # T-HEAD
  

•    - const: xtheadvector
  

•      description:
  

•        The T-HEAD specific 0.7.1 vector implementation as written in
  

•        https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
  

• allOf: # Zcb depends on Zca - if:

-- 2.45.0

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